UP6161 [ETC]
up6161S14;
ETC 
www.datasheet4u.com
Preliminary
Single 12V Input Supply Dual Regulator -
Synchronous-Buck-PWM and Linear-Regulator Controller
uP6161
Features
General Description
The uP6161 integrates a high performance synchronous- Operate with Single 12V Supply
rectified buck controller and a linear-regulator controller.
This part works with a single +12V supply voltage and
delivers two high quality output voltages for both processing
Self-Regulated 9V Drive Voltage
Integrated Boot Diode
Provide Two Regulated Voltages
unit and memory unit. An internal linear regulator provides
optimum 9V drive voltage for efficiency and thermal
management.
One Synchronous-Rectified Buck Controller
One Linear Controller
Both Controllers Drive N-Channel MOSFETs
Smaller Converter Size
The buck controller features internal MOSFET drivers that
supports bootstrapped voltage for high efficiency power
conversion. The bootstrap diode is built-in to simplify the
circuit design and minimize external part count. It
incorporates simple, single feedback loop, voltage-control
with fast transient response.
Excellent Output Voltage Regulation
1.5% for Buck Controller
2% for Linear Controller
Simple Single-Loop Control Design
Voltage-Mode PWM Control
The linear controller drives an externalN-Channel MOSFET
with under voltage protection during both soft start and
normal operation.
Fast Transient Response
High-Bandwidth Error Amplifier
Lossless, Programmable Overcurrent Protection
Uses Lower MOSFET RDS(ON)
Other features include adjustable operation frequency,
internal soft start, under voltage protection, adjustable over
current protection and shutdown function. With the above
function, this part provides customers a compact, well
protected and cost-effective solution. This part is available
in SOP-14 and QFN3x3 -16L packages.
Adjustable Frequency from 150kHz to 1MHz
Internal Soft Start for Both Outputs
Under Voltage Protection for Both Outputs
including Soft Start Cycle
Applications
SOP-14 and QFN3x3-16 packages
Power Supplies for Microprocessors or
RoHS Compliant and 100% Lead Free
Subsystem Power Supplies
Ordering Information
Cable Modems, Set Top Boxes, and DSL
Modems
Order Number Package Type
Remark
Industrial Power Supplies; General Purpose
uP6161S14
uP6161Q
SOP - 14
Supplies
QFN3x3 - 16
12V Input DC-DC Regulators
Low-Voltage Distributed Power Supplies
Note: uPI products are compatible with the current IPC/
JEDEC J-STD-020 and RoHS requirements. They are 100%
matte tin (Sn) plating and suitable for use in SnPb or Pb-
free soldering processes.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
www.datasheet4u.com
Preliminary
uP6161
Pin Configuration
BOOT
RT/DIS
COMP
FB
1
2
3
4
5
6
7
14
13
12
11
10
9
UGATE
PHASE
COMP
FB
PGND
LGATE
PVCC9
VCC9
1
2
3
4
12
11
10
9
PGND
LGATE
PVCC9
VCC9
PGND
LDRV
LFB
LDRV
LFB
AGND
8
VCC12
SOP-14
QFN3x3 – 16L
Typical Application Circuit
+12V
VIN1
VCC12
1
8
PVCC9
BOOT
10
9
UGATE
PHASE
VCC9
14
13
VOUT1
VIN2
LGATE
11
LDRV
LFB
5
6
VOUT2
PGND
FB
13
4
R1
RT/DIS#
GND
2
7
Disable
COMP
Enable
R2
3
2
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
www.datasheet4u.com
Preliminary
uP6161
Functional Block Diagram
VCC9
VCC12
SS3
SS2
SS1
VCC5
Soft
Start
POR &
Reference
Internal
Regulator
Internal
PVCC9
Regulator
0.6V
VOCP
BOOT
Enable &
Protection
Logic
UGATE
0.6V
0.4V
SS1
FB
Gate
Control
Logic
0.8V
SS2
PHASE
LGATE
PVCC9
LFB
0.8V
SS3
Oscillator
LDRV
COMP
RT/DIS
GND
PGND
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
www.datasheet4u.com
Preliminary
uP6161
Functional Pin Description
Pin No.
Pin
Name
Pin Function
SOP QFN
Bootstrap Supply for the floating upper gate driver. Connect the bootstrap capacitor CBOOT
between BOOT pin and the PHASE pin to form a bootstrap circuit. The bootstrap capacitor
provides the charge to turn on the upper MOSFET. Typical values for CBOOT range from 0.1uF
to 0.47uF. Ensure that CBOOT is placed near the IC.
1
15
BOOT
Frequency Setting and Chip Disable. A resistor to GND sets the operation frequency of
for the buck converter. Pulling this pin to GND disables both buck and linear regulators.
2
3
16
1
RT/DIS
Error Amplifier Output. This is the output of the error amplifier (EA) and the non-inverting
COMP input of the PWM comparator. Use this pin in combination with the FB pin to compensate the
voltage-control feedback loop of the buck converter.
Feedback Voltage for Buck Converter. This pin is the inverting input to the error amplifier.
A resistor divider from the output to GND is used to set the regulation voltage. Use this pin in
combination with the COMP pin to compensate the voltage control feedback loop of the
converter.
4
5
2
3
FB
Driver Output for Linear Regulator. This pinprovides the gate voltage for the linear regulator
LDRV pass transistor. Connect this pin to the gate of an external N-Channel MOSFET to form a linear
regulator.
Feedback Voltage for Linear Regulator. This pin is the inverting input to the error amplifier.
A resistor divider from the output to GND is used to set the regulation voltage.
6
7
4
5
LFB
Signal Ground for the IC. All voltages levels are measured with respect to this pin. Tie this
AGND
pin to the ground island/plane through the lowest impedance connection available.
Supply Voltage. This is the power supply pin for the IC; it sources the internal 9V regulator
8
9
7, 8 VCC12 used to the gate drivers. A minimum 1uF ceramic capacitor is required for locally bypassing
the input voltage.
VCC9. This pin supplies bias current for the IC. A minimum 1uF ceramic capacitor physically
9
VCC9
near the IC is required for locally bypassing the input voltage.
Power PVCC9. This is the output of the internal 9V linear regulator. It provides current required
10
10 PVCC9 for driving N-Channel MOSFETs of buck converter. A minimum 1uF ceramic capacitor
physically near the IC is required for locally bypassing the input voltage.
Lower Gate Driver Output. Connect this pin to the gate of lower MOSFET. This pin is
11 LGATE monitored by the adaptive shoot-through protection circuitry to determine when the lower
MOSFET has turn off.
11
Power Ground for the IC.
12 6, 12 PGND
PHASE Switch Node. Connect this pin to the source of the upper MOSFET and the drain of
the lower MOSFET. This pin is used as the sink for the UGATE driver, and to monitor the
voltage drop across the lower MOSFET for over current protection. This pin is also monitored
by the adaptive shoot-through protection circuitry to determine when the upper MOSFET has
turned off. A Schottky diode between this pin and ground is recommended to reduce negative
transient voltage which is common in a power supply system.
13
14
13 PHASE
Upper Gate Driver Output. Connect this pin to the gate of upper MOSFET. This pin is
14 UGATE monitored by the adaptive shoot-through protection circuitry to determine when the upper
MOSFET has turned off.
Power Ground for the IC. For QFN package only. This exposed pad should be well soldered
to PCB for effective heat conduction. Connect the exposed pad the ground.
Exposed Pad
4
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
www.datasheet4u.com
Preliminary
uP6161
Functional Description
The uP6161 integrates a high performance synchronous- power on reset with typical rising threshold level as 7.5V.
rectified buck controller and a linear-regulator controller. All the three supply inputs require minimum 1uF ceramic
This part works with a single +12V supply voltage and capacitors for local bypassing. Place the bypass capacitors
delivers two high quality output voltages for both processing physically near the IC. No external bypass capacitor is
unit and memory unit. An internal linear regulator provides required for filtering the VCC5 voltage.
optimum 9V drive voltage for efficiency and thermal
management.
Bootstrap Circuitry
The uP6161 integrates MOSFET gate drives that are
The buck controller features internal MOSFET drivers that
supports 12V + 12V bootstrapped voltage for high efficiency
power conversion. The bootstrap diode is built-in to simplify
the circuit design and minimize external part count. It
incorporates simple, single feedback loop, voltage-control
with fast transient response.
powered from the PVCC9 pin and support 12V+12V driving
capability.Abootstrap diode is embedded to facilitates PCB
design and reduce the total BOM cost. Connect a ceramic
bootstrap diode between BOOT and PHASE pins to form a
bootstrap circuit for providing charge to turn on/off the upper
MOSFET. No external Schottky diode is required.
Converters that consist of uP6161 feature high efficiency
without special consideration on the selection of
MOSFETs.
The linear controller drives an externalN-Channel MOSFET
with undervoltage protection during both softstart and normal
operation.
Chip Enable and Frequency Setting
Other features include adjustable operation frequency,
internal softstart, undervoltage protection, adjustable
overcurrent protection and shutdown function.
The RT/DIS is a multifunctional pin: chip shutdown and
frequency setting. Pulling low this pin to GND by an open
drain/collector transistor shuts down the uP6161 and
disables both buck and linear controllers.
Supply Voltage
The uP6161 is designed to work with a single supply rail.
It integrates two linear regulators providing optimal supply
voltages for gate drivers and control circuitry respectively
as shown in Figure 1. The 9V linear regulator generates
9V PVCC9 for gate drives achieving optimum balance
between efficiency and thermal management. The 5V linear
regulator works with VCC9 input generates VCC5 for
internal control circuitry. If 12V driving voltage is preferred,
simply connect +12V to the PVCC9 pin and let VCC12
open.
The switching frequency is set by a resistor connecting to
the RT/DIS pin as:
23500000
fOSC
=
+ 74000
(Hz)
RRT
Figure 2 shows the dependence between the resistor
chosen and the resulting switching frequency.
1000
+12V
VCC12
9V
Linear
uP6161
Regulator
PVCC9
VCC9
Gate
Drivers
POR
Monitoring
100
5V
10
100
1000
Linear
Regulator
RRT (kohm)
Control
Circuitry
Figure 2. Switching Frequency vs. RRT
Soft Start
Once POR is acknowledged and RT/DIS pin is released,
Figure 1. Supply Voltage Configuration
Both PVCC9 and VCC9 are continuously monitored for
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
www.datasheet4u.com
Preliminary
uP6161
Functional Description
the uP6161 initiates its digital soft start cycle to prevent ramping up to 5VDD. Another softstart is initiated after SS
surge current from power supply input during turn on ramps up to 5VDD. The hiccup period is about 8ms. Figure
(referring to the Functional Block Diagram). The error 4 shows the start up interval where VIN does not present
amplifiers are three-input devices. Reference voltage VREF initially.
or the internal soft start voltage SS2/SS3 whichever is
smaller dominates the behavior of the non-inverting inputs
of the error amplifiers. SS2/SS3 internally ramps up to 0.8V
in 4096 cycles of the internal oscillator frequency after the
after the softstart cycle is initiated. Take 600kHz switching
frequency for example (1.67us per cycle), the ramp-up time
is about 6.8ms.Accordingly, the output voltages follow the
soft start signals SS2/SS3 and linearly ramp up to their
final level, resulting minimum inrush current from input
SVO
(0.5V/Div)
VIN
(5V/Div)
LVO
(0.5V/Div)
voltage.
The SS2/SS3 signals keep ramping up after it exceeds
the internal 0.8V reference voltages. However, the internal
0.8V reference voltages takes over the behavior of error
LGATE
(10V/Div)
amplifier after SS > VREF. When the SS2/SS3 signal climb
to its ceiling voltage (5V), the uP6161 claims the end of
softstart cycle and enable the under voltage protection of
the output voltages.
Time (5ms/Div)
Figure 4. Softstart where VIN does not Present Initially.
Output Voltage Selection
Figure 3 shows a typical start up interval for uP6161 where
the RT/DIS pin has been released from a grounded (system
shutdown) state. Note the LDO output voltage (LVO)
starts ramping up only after the PWM output voltage
(SVO) is within regulation.
The output voltage can be programmed to any level between
the 0.8V internal reference, up to the 80% of VIN supply.
The lower limitation of output voltage is caused by the
internal reference. The upper limitation of the output voltage
is caused by the maximum available duty cycle (80%
typical). This is to leave enough time for overcurrent
detection. Output voltage out of this range is not allowed.
Avoltage divider sets the output voltage (refer to the Typical
Application Circuit on page 1 for detail). In real applications,
choose R2 in 100Ω ~ 10kΩ range and choose appropriate
R1 according to the desired output voltage.
RT/DIS
(1V/Div)
SVO
(0.5V/Div)
LVO
(0.5V/Div)
R1+ R2
R2
R1+R2
R2
VOUT = VREF
×
= 0.8V×
Overcurrent Protection (OCP)
PHASE
(10V/Div)
The uP6161 detects voltage drop across the lower MOSFET
(VPHASE) for overcurrent protection when it is turned on. If
VPHASE is lower than the user-programmable voltage VOCP
,
Time (5ms/Div)
the uP6161 asserts OCP and shuts down the converter.
The OCP level can be calculated according the on-
resistance of the lower MOSFET used.
Figure 3. Softstart Behavior.
Power Input Detection
The uP6161 detects PHASE voltage for the present of power
input when the UGATE turns on the first time. If the PHASE
voltage does not exceed 2.0V when the UGATE turns on,
the uP6161 asserts that power input in not ready and stops
the softstart cycle. However, the internal SS continues
VOCP
IOCP = −
(A)
RDS(ON)
Connecting a resistance from LGATE to GND selects the
6
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
www.datasheet4u.com
Preliminary
uP6161
Functional Description
appropriate VOCP as shown in Table 1. Also shown in Table
1 is OCP level if a lower MOSFET with 10mΩ RDS(ON) is
used.
When programming the OCP level, take into consideration
the conditions that affect RDS(ON) of the lower MOSFET,
including operation junction temperature, gate driving voltage
and distribution. Consider the RDS(ON) at maximum operation
temperature and lowest gate driving voltage.
Table 1. OCP Level Selection
ROCP (Ω)
OCP (mV)
OCP (A)
open
-375
37.5
42k
-300
25
24k
-225
22.5
10k
-150
15
V
I
Another factor should taken into consideration is the ripple
of the inductor current. The current near the valley of the
ripple current is used for OCP, resulting the averaged OCP
level a little higher than the calculated value.
Output Under Voltage Protection of Linear Regulator
The LDRV and LFB voltages are monitored during both
softstart and normal operation for output under voltage
protection. The uP6161 asserts UVP if the error amplifier
saturates, LDRV goes to ceiling high and LFB voltage is
lower than 0.6V for 10us. This demands VCC12 > (VOUT
+
VTH + 1V) where VTH is the threshold voltage of the external
N-Channel MOSFET. This is to ensure that the output
voltage can follow the softstart signal and will not saturate
the error amplifier. That means a low threshold voltage
MOSFET is required for low VCC12 applications. This also
demands that VIN2 should be ready before the soft start
cycle is initiated.
The uP6161 disables the output voltages upon the triggering
of UVP. The uP6161 repeats the softstart cycle if the output
under voltage is not removed.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
www.datasheet4u.com
Preliminary
uP6161
Absolute Maximum Rating
Supply Input Voltage, VCC12 (Note 1) -------------------------------------------------------------------------------------------- -0.3V to +15V
PHASE to GND
DC ------------------------------------------------------------------------------------------------------------------------------------- -1V to 15V
< 200ns ---------------------------------------------------------------------------------------------------------------------------- -3V to 30V
BOOT to PHASE ---------------------------------------------------------------------------------------------------------------------------- -0.3V to +15V
UGATE to PHASE ------------------------------------------------------------------------------------------------ -0.3V to (BOOT- PHASE +0.3V)
PVCC9, VCC9, LDRV ----------------------------------------------------------------------------------------------------- -0.3V to VCC12 + 0.3V
LGATE ------------------------------------------------------------------------------------------------------------------------ -0.3V to + (PVCC9 + 0.3V)
Other Pins -------------------------------------------------------------------------------------------------------------------------------------- -0.3V to +6V
StorageTemperature Range ------------------------------------------------------------------------------------------------------------- -65OC to +150OC
JunctionTemperature ------------------------------------------------------------------------------------------------------------------------------------ 150OC
LeadTemperature (Soldering, 10 sec) ------------------------------------------------------------------------------------------------------------ 260OC
ESD Rating (Note 2)
HBM (Human Body Mode) --------------------------------------------------------------------------------------------------------------------- 2kV
MM (Machine Mode) ----------------------------------------------------------------------------------------------------------------------------- 200V
Thermal Information
Package Thermal Resistance (Note 3)
θJA SOP-14 ------------------------------------------------------------------------------------------------------------------------------ 120°C/W
θJC QFN3x3-16 ----------------------------------------------------------------------------------------------------------------------------- 5OC/W
θJA QFN3x3-16 ---------------------------------------------------------------------------------------------------------------------------- 68OC/W
PowerDissipation, PD @ TA = 25°C
SOP-14 ----------------------------------------------------------------------------------------------------------------------------------------------- 0.83W
QFN3x3-16 ------------------------------------------------------------------------------------------------------------------------------------------ 1.47W
Recommended Operation Conditions
Operating Junction Temperature Range (Note 4) ------------------------------------------------------------------------ -40°C to +125°C
OperatingAmbient Temperature Range -------------------------------------------------------------------------------------- -40°C to +85°C
Supply InputVoltage,VCC12 ----------------------------------------------------------------------------------------------------------- +10.8V to 13.2V
Electrical Characteristics
(VCC12 = 12V, TA = 25OC, unless otherwise specified)
Parameter
Symbol Test Conditions
Min
Typ
Max Units
Supply Input
Supply Voltage
VCC12
10.8
--
--
4
3
13.2
--
V
UGATE and LGATE Open; VCC12 = 12V,
Switching
Supply Current
ICC12
mA
Quiescent Supply Current
Power Input Voltage
Power On Reset
ICC12_Q VFB = VREF + 0.1V, No Switching
VIN1
--
--
mA
V
3.0
13.2
VCC12 POR Threshold
VCC12RTH
--
--
--
8.7
7.5
0.8
--
8
V
V
V
PVCC9 POR Threshold
POR Hysteresis
VVCC9RTH PVCC9 = VCC9 rising
VCC9HYS PVCC9 = VCC9 falling
--
8
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
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Preliminary
uP6161
Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Typ Max Units
PVCC9 LDO
PVCC9 Output Voltage
Oscillator and Soft Start
Switching Frequency
Sawtooth Amplitude
Soft Start Interval
PVCC9 VCC12 = 12V
--
9.0
--
V
fOSC
ΔVOSC
TSS
RRT = 45.3kΩ
540
--
620
4
700
--
kHz
V
fOSC = 620kHz
--
6.8
--
ms
Reference Voltage
Reference Voltage for PWM
Reference Voltage for LDO
VREF
VREF
0.788 0.8 0.812
0.784 0.8 0.816
V
V
Error Amplifier for Buck Controller
Open Loop DC Gain
AO
Guaranteed by Design
55
--
70
10
6
--
--
dB
MHz
V/us
V
Gain-Bandwidth Product
Slew Rate
GBWP Guaranteed by Design
SR
Guaranteed by Design
4
--
COMP High Output Voltage
COMP Low Output Voltage
COMP High Source Current
Undervoltage Level (VFB/VREF
Buck Controller Gate Drivers
UGATE Source Current
VCOMP_H
VCOMP_L
ICOMP_H
VUVP
--
4.7
0.6
-2.8
75
--
--
--
V
--
--
mA
%
)
70
80
IUG_SRC
RUG_SNK
ILG_SRC
PVCC = 9V, VBOOT - VUG = 8V
PVCC = 9V, IUG = 100mA
PVCC = 9V, VLG = 1V
--
--
-1.5
2
--
4
A
Ω
A
UGATE Sink Output Impedance
LGATE Source Current
--
-1.5
2
--
LGATE Sink Output Impedance
Maximum Duty Cycle
RLG_SNK
PVCC = 9V, ILG = 100mA
--
4
Ω
%
70
75
80
Linear-Regulator Controller
Open Loop DC Gain
Gain-Bandwidth Product
Slew Rate
AO
Guaranteed by Design
55
--
70
2
--
--
dB
MHz
V/us
uA
GBWP Guaranteed by Design
SR
IFB
Guaranteed by Design
VFB = 0.8V
2
4
--
FB Bias Current
--
0.01
8.5
0.0
--
1
LDRV High Output Voltage
LDRV Low Output Voltage
LDRV High Source Current
LDRV Low Sink Current
VLDRV_H PVCC = 9V
VLDRV_L PVCC = 9V
ILDRV_H
--
9.0
0.5
--
V
--
V
5
mA
mA
%
ILDRV_L
5
--
--
Undervoltage Level (VLFB/VREF
)
VUVP
Percent of Nominal
70
75
80
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
w w w . d a t a s h e e t
Preliminary
uP6161
Electrical Characteristics
Parameter
Symbol
Test Conditions
Min
Typ Max Units
Protection
Over Current Threshold
Enable Threshold
VPHASE RLGATE = open
VRT/DIS
--
-375
0.4
--
mV
V
0.3
0.5
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device.
These are for stress ratings. Functional operation of the device at these or any other conditions beyond those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may remain possibility to affect device reliability.
Note 2. Devices are ESDsensitive. Handling precaution recommended.
Note 3. θJA is measured in the natural convection at TA = 25°C on a low effective thermal conductivity test board of
JEDEC 51-3 thermal measurement standard.
Note 4. The device is not guaranteed to function outside its operating conditions.
10
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
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Preliminary
uP6161
Typical Operation Characteristics
Turn On Waveforms
Power On Waveforms
SVOUT
(0.5V/Div)
VCC12
(5V/Div)
LVOUT
PVCC9
(0.5V/Div)
(5V/Div)
SVOUT
(0.5V/Div)
RT/DIS
(0.5V/Div)
LVOUT
(0.5V/Div)
PHASE
(10V/Div)
2.5ms/Div
5ms/Div
Gate Waveforms
Gate Waveforms
UGATE
(5V/Div)
UGATE
(5V/Div)
PHASE
(5V/Div)
PHASE
(5V/Div)
LGATE
(5V/Div)
LGATE
(5V/Div)
UGATE-PHASE
(5V/Div)
UGATE-PHASE
(5V/Div)
25ns/Div
25ns/Div
Over Current Protection
Trun Off Waveforms
RT/DIS
(1V/Div)
SVOUT
(0.5V/Div)
LDRV
(2V/Div)
PHASE
(10V/Div)
PHASE
(10V/Div)
IOUT
(10A/Div)
10ms/Div
5us/Div
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
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Preliminary
uP6161
Typical Operation Characteristics
PVCC9 Voltage vs. VCC12 Voltage
Switching Frequency vs. RRT
10
9.5
9
1000
8.5
8
7.5
7
100
8
10
12
14
150
150
10
100
RRT (kΩ)
1000
VCC12 Voltage (V)
PVCC9 Voltage vs. Temperature
DC/DC Output Voltage vs. Temperature
9.07
9.06
9.05
9.04
9.03
9.02
9.01
9
0.5
0.2
-0.1
-0.4
-0.7
-1
-50
0
50
100
-50
0
50
100
150
Junction Temperature (OC)
VCC12 = 12V
Junction Temperature (OC)
Switching Frequency vs. Temperature
LDO Output Voltage vs. Temperature
2
1
0.5
0.3
0.1
-0.1
-0.3
-0.5
-0.7
-0.9
-1.1
-1.3
-1.5
0
-1
-2
-3
-4
-50
0
50
100
-50
0
50
100
150
Junction Temperature (OC)
Junction Temperature (OC)
12
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
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Preliminary
uP6161
Application Information
This page is intentionally left blank and will be updated when the silicon data is available.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
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Preliminary
uP6161
Package Information
SOP-14 Package
0.76 REF
1.27 REF
8.50 - 8.75
1.27 BSC
0.32 - 0.52
Recommended Solder Pad Layout
1.45 - 1.60
0.20 BSC
0.18 - 0.25
1.75 MAX
0.10 - 0.25
0.41 - 0.89
7.62 BSC
Note
1.Package Outline UnitDescription:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.
14
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
www.datasheet4u.com
Preliminary
uP6161
Package Information
QFN3x3 - 16L Package
0.35 - 0.45
1.50 - 1.75
9
13
Pin 1 mark
(Note 6)
5
1
2.90 - 3.10
0.18 - 0.30
0.50 BSC
Bottom View - Exposed Pad
0.80 - 1.00
0.20 - REF
0.00 - 0.05
0.20 - 0.30
0.50 BSC
Recommended Solder Pitch and Dimensions
Note
1.Package Outline UnitDescription:
BSC: Basic. Represents theoretical exact dimension or dimension target
MIN: Minimum dimension specified.
MAX: Maximum dimension specified.
REF: Reference. Represents dimension for reference use only. This value is not a device specification.
TYP. Typical. Provided as a general value. This value is not a device specification.
2.Dimensions in Millimeters.
3.Drawing not to scale.
4.These dimensions no not include mold flash or protrusions. Mold flash or protrusions shell not exceed 0.15mm.
uPI Semiconductor Corp., http://www.upi-semi.com
Rev. P00, File Name: uP6161-DS-P0001
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