UPD4382162GF-A75 [ETC]
x16 Fast Synchronous SRAM ; X16高速同步SRAM\n
| 型号： | UPD4382162GF-A75 |
| 厂家： | 
ETC |
| 描述： | x16 Fast Synchronous SRAM
|
| 文件： | 总24页 (文件大小：211K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µ
PD4382162, 4382182, 4382322, 4382362
8M-BIT CMOS SYNCHRONOUS FAST SRAM
PIPELINED OPERATION
SINGLE CYCLE DESELECT
Description
The µPD4382162 is a 524,288-word by 16-bit, the µPD4382182 is a 524,288-word by 18-bit, µPD4382322 is a 262,144-
word by 32-bit and the µPD4382362 is a 262,144-word by 36-bit synchronous static RAM fabricated with advanced CMOS
technology using N-channel four-transistor memory cell.
The µPD4382162, µPD4382182, µPD4382322 and µPD4382362 integrates unique synchronous peripheral circuitry, 2-
bit burst counter and output buffer as well as SRAM core. All input registers are controlled by a positive edge of the single
clock input (CLK).
The µPD4382162, µPD4382182, µPD4382322 and µPD4382362 are suitable for applications which require synchronous
operation, high speed, low voltage, high density and wide bit configuration, such as cache and buffer memory.
ZZ has to be set LOW at the normal operation. When ZZ is set HIGH, the SRAM enters Power Down State (“Sleep”). In
the “Sleep” state, the SRAM internal state is preserved. When ZZ is set LOW again, the SRAM resumes normal operation.
The µPD4382162, µPD4382182, µPD4382322 and µPD4382362 are packaged in 100-pin plastic LQFP with a 1.4 mm
package thickness for high density and low capacitive loading.
Features
• 3.3 V (Chip) / 3.3 V or 2.5 V (I/O) Supply
• Synchronous operation
• Internally self-timed write control
• Burst read / write : Interleaved burst and linear burst sequence
• Fully registered inputs and outputs for pipelined operation
• Single-Cycle deselect timing
• All registers triggered off positive clock edge
• 3.3 V or 2.5 V LVTTL Compatible : All inputs and outputs
• Fast clock access time :
★
3.8 ns (150 MHz), 4.0 ns (133 MHz) (µPD4382322, µPD4382362), 4.0 ns (133 MHz) (µPD4382162, µPD4382182)
• Asynchronous output enable : /G
• Burst sequence selectable : MODE
• Sleep mode : ZZ (ZZ = Open or Low : Normal operation)
• Separate byte write enable :
/BW1 - /BW4 (µPD4382322, µPD4382362), /BW1 - /BW2 (µPD4382162, µPD4382182), /BWE
Global write enable : /GW
• Three chip enables for easy depth expansion
• Common I/O using three state outputs
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for
availability and additional information.
Document No. M14020EJ5V0DS00 (5th edition)
Date Published January 2000 NS CP(K)
Printed in Japan
The mark shows major revised points.
★
1999
©
µPD4382162, 4382182, 4382322, 4382362
Ordering Information
★
Package
Notes
Part number
Access
Clock
Frequency
MHz
Core Supply
Voltage
V
I/O
Interface
V
Time
ns
1
2
µPD4382162GF-A75
µPD4382182GF-A75
µPD4382322GF-A67
µPD4382322GF-A75
µPD4382362GF-A67
µPD4382362GF-A75
4.0
4.0
3.8
4.0
3.8
4.0
133
133
150
133
150
133
3.3 ± 0.165
3.3 or 2.5
LVTTL
100-PIN PLASTIC LQFP (14 x 20)
the
Notes 1. Grade A75 is available in
µPD4382162GF and µPD4382182GF.
µPD4382322GF and µPD4382362GF.
2. Grade A67 and A75 are available in the
Data Sheet M14020EJ5V0DS00
2
µPD4382162, 4382182, 4382322, 4382362
Pin Configurations (Marking Side)
/××× indicates active low signal.
100-PIN PLASTIC LQFP (14 x 20)
[µPD4382162GF, µPD4382182GF]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
A18
NC
NC
2
3
V
DD
Q
Q
4
VDDQ
V
SS
5
V
SS
Q
NC
NC
6
NC
7
I/OP1, NC
I/O8
I/O9
8
I/O10
9
I/O7
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
V
V
SS
Q
V
DD
DD
Q
I/O11
I/O12
NC
I/O6
I/O5
V
SS
VDD
NC
NC
VDD
V
SS
I/O13
I/O14
ZZ
I/O4
I/O3
V
DD
Q
Q
VDDQ
V
SS
V
SS
Q
I/O15
I/O16
I/O2
I/O1
NC
I/OP2, NC
NC
NC
V
SS
Q
Q
V
V
SS
Q
V
DD
DD
Q
NC
NC
NC
NC
NC
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawing for 1-pin index mark.
Data Sheet M14020EJ5V0DS00
3
µPD4382162, 4382182, 4382322, 4382362
Pin Identification (µPD4382162GF, µPD4382182GF)
Symbol Pin No.
Description
A0 - A18
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45, 46, 47,
48, 49, 50, 43, 80
Synchronous Address Input
I/O1 - I/O16
58, 59, 62, 63, 68, 69, 72, 73, 8, 9, 12, 13, 18, 19, 22,
23
Synchronous Data In,
Synchronous / Asynchronous Data Out
Synchronous Data In (Parity),
I/OP1, NCNote
I/OP2, NCNote
/ADV
74
24
Synchronous / Asynchronous Data Out (Parity)
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
83
/AP
84
/AC
85
/CE,CE2, /CE2
98, 97, 92
/BW1, /BW2, /BWE 93, 94, 87
/GW
/G
88
86
89
31
CLK
MODE
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
Asynchronous Power Down State Input
Power Supply
ZZ
64
VDD
VSS
15, 41, 65, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
Output Buffer Power Supply
Output Buffer Ground
1, 2, 3, 6, 7, 14, 16, 25, 28, 29, 30, 38, 39, 42, 51, 52,
53, 56, 57, 66, 75, 78, 79, 95, 96
No Connection
Note NC (No Connection) is used in the µPD4382162GF. I/OP1 - I/OP2 is used in the µPD4382182GF.
Data Sheet M14020EJ5V0DS00
4
µPD4382162, 4382182, 4382322, 4382362
100-PIN PLASTIC LQFP (14 x 20)
[µPD4382322GF, µPD4382362GF]
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
I/OP2, NC
I/O16
I/OP3, NC
I/O17
1
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
2
I/O15
I/O18
3
VDDQ
V
DD
Q
Q
4
V
SS
Q
V
SS
5
I/O14
I/O13
I/O12
I/O11
I/O19
I/O20
I/O21
I/O22
6
7
8
9
V
V
SS
Q
V
SS
Q
Q
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
DD
Q
VDD
I/O10
I/O9
I/O23
I/O24
NC
V
SS
NC
VDD
VDD
NC
ZZ
V
SS
I/O25
I/O26
I/O8
I/O7
VDDQ
V
DD
Q
Q
V
SS
Q
V
SS
I/O6
I/O5
I/O4
I/O3
I/O27
I/O28
I/O29
I/O30
V
V
SS
Q
V
SS
Q
Q
DD
Q
VDD
I/O2
I/O31
I/O32
I/O1
I/OP1, NC
I/OP4, NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
Remark Refer to Package Drawing for 1-pin index mark.
Data Sheet M14020EJ5V0DS00
5
µPD4382162, 4382182, 4382322, 4382362
Pin Identification (µPD4382322GF, µPD4382362GF)
Symbol Pin No.
A0 - A17
Description
37, 36, 35, 34, 33, 32, 100, 99, 82, 81, 44, 45,
46, 47, 48, 49, 50, 43
Synchronous Address Input
I/O1 - I/O32
52, 53, 56, 57, 58, 59, 62, 63, 68, 69, 72, 73, 74, Synchronous Data In,
75, 78, 79, 2, 3, 6, 7, 8, 9, 12, 13, 18, 19, 22, 23,
24, 25, 28, 29
Synchronous / Asynchronous Data Out
I/OP1, NCNote
I/OP2, NCNote
I/OP3, NCNote
I/OP4, NCNote
/ADV
51
Synchronous Data In (Parity),
80
Synchronous / Asynchronous Data Out (Parity)
1
30
83
Synchronous Burst Address Advance Input
Synchronous Address Status Processor Input
Synchronous Address Status Controller Input
Synchronous Chip Enable Input
Synchronous Byte Write Enable Input
Synchronous Global Write Input
Asynchronous Output Enable Input
Clock Input
/AP
84
/AC
85
/CE, CE2, /CE2
98, 97, 92
/BWE1 - /BWE4, /BWE 93, 94, 95, 96, 87
/GW
/G
88
86
89
31
CLK
MODE
Asynchronous Burst Sequence Select Input
Do not change state during normal operation
Asynchronous Power Down State Input
Power Supply
ZZ
64
VDD
VSS
15, 41, 65, 91
17, 40, 67, 90
Ground
VDDQ
VSSQ
NC
4, 11, 20, 27, 54, 61, 70, 77
5, 10, 21, 26, 55, 60, 71, 76
14, 16, 38, 39, 42, 66
Output Buffer Power Supply
Output Buffer Ground
No Connection
Note NC (No Connection) is used in the µPD4382322GF. I/OP1 - I/OP4 is used in the µPD4382362GF.
Data Sheet M14020EJ5V0DS00
6
µPD4382162, 4382182, 4382322, 4382362
Block Diagrams
[µPD4382162, µPD4382182]
19
17
19
Address
A0 - A18
Registers
A0, A1
A1’
MODE
/ADV
CLK
Q1
Binary
Counter
and Logic
A0’
/AC
/AP
Row and Column
Decoders
CLR
Q0
8/9
8/9
Memory Matrix
1,024 rows
Byte 1
Byte 1
/BW1
/BW2
Write Register
Write Driver
Byte 2
Write Register
Byte 2
Write Driver
512 × 16 columns
(8,388,608 bits)
512 × 18 columns
(9,437,184 bits)
/BWE
16/18
/GW
/CE
16/18
Enable
Register
Output
Registers Buffers
Output
CE2
/CE2
Enable Delay
Register
/G
Input
Registers
2
16/18
I/O1 - I/O16
I/OP1 - I/OP2
Power Down Control
ZZ
Burst Sequence
[µPD4382162, µPD4382182]
Interleaved Burst Sequence Table (MODE = Open or VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A18 - A2, A1, A0
A18 - A2, A1, /A0
A18 - A2, /A1, A0
A18 - A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A18 - A2, 0, 0
A18 - A2, 0, 1
A18 - A2, 1, 0
A18 - A2, 1, 1
A18 - A2, 0, 1
A18 - A2, 1, 0
A18 - A2, 1, 1
A18 - A2, 0, 0
A18 - A2, 1, 0
A18 - A2, 1, 1
A18 - A2, 0, 0
A18 - A2, 0, 1
A18 - A2, 1, 1
A18 - A2, 0, 0
A18 - A2, 0, 1
A18 - A2, 1, 0
Data Sheet M14020EJ5V0DS00
7
µPD4382162, 4382182, 4382322, 4382362
[ PD4382322, PD4382362]
µ
µ
18
16
18
Address
A0 - A17
Registers
A0, A1
A1’
MODE
/ADV
CLK
Q1
Binary
Counter
and Logic
A0’
/AC
/AP
Row and Column
Decoders
CLR
Q0
8/9
8/9
8/9
8/9
Byte 1
Byte 1
Memory Matrix
1,024 rows
/BW1
/BW2
/BW3
Write Register
Write Driver
Byte 2
Write Register
Byte 2
Write Driver
256 × 32 columns
(8,388,608 bits)
Byte 3
Write Register
Byte 3
Write Driver
256 × 36 columns
(9,437,184 bits)
Byte 4
Write Register
Byte 4
Write Driver
/BW4
/BWE
32/36
32/36
Output
Registers Buffers
Output
/GW
/CE
Enable
Register
CE2
/CE2
Enable delay
Register
Input
Registers
/G
4
32/36
I/O1 - I/O32
I/OP1 - I/OP4
Power Down Control
ZZ
[µPD4382322, µPD4382362]
Interleaved Burst Sequence Table (MODE = Open or VDD)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A17 - A2, A1, A0
A17 - A2, A1, /A0
A17 - A2, /A1, A0
A17 - A2, /A1, /A0
Linear Burst Sequence Table (MODE = VSS)
External Address
1st Burst Address
2nd Burst Address
3rd Burst Address
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 1
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 1, 0
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 1
A17 - A2, 0, 0
A17 - A2, 0, 1
A17 - A2, 1, 0
Data Sheet M14020EJ5V0DS00
8
µPD4382162, 4382182, 4382322, 4382362
Asynchronous Truth Table
Operation
Read Cycle
Read Cycle
Write Cycle
Deselected
/G
L
I/O
Dout
H
×
Hi-Z
Hi-Z, Din
Hi-Z
×
Remark × : don’t care
Synchronous Truth Table
Operation
★
/CE
H
L
CE2
×
/CE2
×
/AP
×
/AC
L
/ADV
×
/WRITE
CLK
Address
None
Deselected Note
×
×
×
×
×
×
H
×
×
×
×
L
×
×
×
×
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
L → H
Deselected Note
L
×
L
×
×
None
Deselected Note
L
×
H
×
L
×
×
None
Deselected Note
L
L
H
H
L
L
×
None
Deselected Note
L
×
H
L
L
×
None
Read Cycle / Begin Burst
Read Cycle / Begin Burst
Read Cycle / Continue Burst
Read Cycle / Continue Burst
Read Cycle / Suspend Burst
Read Cycle / Suspend Burst
Write Cycle / Begin Burst
Write Cycle / Continue Burst
Write Cycle / Continue Burst
Write Cycle / Suspend Burst
Write Cycle / Suspend Burst
L
H
H
×
×
×
External
External
Next
L
L
H
H
×
L
×
×
×
H
H
H
H
L
L
H
×
×
×
L
Next
×
×
H
×
H
H
×
Current
Current
External
Next
H
L
×
×
H
×
L
H
H
×
×
×
H
H
H
H
L
H
×
×
×
L
Next
×
×
H
×
H
H
Current
Current
H
×
×
Note Deselect status is held until new “Begin Burst” entry.
Remarks 1. × : don’t care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are
LOW or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2 and /GW are HIGH, and /BWE is LOW. [µPD4382162, µPD4382182]
/BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW. [µPD4382322, µPD4382362]
Data Sheet M14020EJ5V0DS00
9
µPD4382162, 4382182, 4382322, 4382362
Partial Truth Table for Write Enables
[ PD4382162, PD4382182]
µ
µ
Operation
/GW
H
/BWE
/BW1
/BW2
Read Cycle
Read Cycle
H
L
L
L
×
×
H
L
L
×
×
H
H
L
H
Write Cycle / Byte 1 Only
Write Cycle / All Bytes
Write Cycle / All Bytes
H
H
L
×
Remark × : don’t care
[ PD4382322, PD4382362]
µ
µ
Operation
/GW
H
/BWE
/BW1
/BW2
/BW3
/BW4
Read Cycle
Read Cycle
H
L
L
L
×
×
H
L
L
×
×
H
H
L
×
H
H
L
×
H
H
L
H
Write Cycle / Byte 1 Only
Write Cycle / All Bytes
Write Cycle / All Bytes
H
H
L
×
×
×
Remark × : don’t care
Pass-Through Truth Table
Previous Cycle
Present Cycle
Add /CEs /WRITE /G
Next Cycle
Operation
Operation
Add /WRITE
Ak
I/O
Operation
I/O
Write Cycle
L
Dn(Ak) Read Cycle
(Begin Burst)
Am
L
H
L
Q1(Ak)
Read Q1(Am)
Deselected
-
H
×
×
Hi-Z
No Carry Over from
Previous Cycle
Remarks 1. × : don’t care
2. /WRITE = L means any one or more byte write enables (/BW1, /BW2, /BW3 or /BW4) and /BWE are
LOW or /GW is LOW.
/WRITE = H means the following two cases.
(1) /BWE and /GW are HIGH.
(2) /BW1, /BW2 and /GW are HIGH, and /BWE is LOW. [µPD4382162, µPD4382182]
/BW1, /BW2, /BW3, /BW4 and /GW are HIGH, and /BWE is LOW. [µPD4382322, µPD4382362]
/CEs = L means /CE is LOW, /CE2 is LOW and CE2 is HIGH.
/CEs = H means /CE is HIGH or /CE2 is HIGH or CE2 is LOW.
ZZ (Sleep) Truth Table
ZZ
Chip Status
Active
≤ 0.2 V
Open
Active
DD 0.2 V
Sleep
≥ V
−
Data Sheet M14020EJ5V0DS00
10
µPD4382162, 4382182, 4382322, 4382362
Electrical Specifications
Absolute Maximum Ratings
Parameter
Symbol
VDD
VDDQ
VIN
Conditions
MIN.
–0.5
–0.5
–0.5
–0.5
0
TYP.
MAX.
+4.0
Unit
V
Note
Supply voltage
Output supply voltage
Input voltage
VDD
V
VDD + 0.5
VDDQ + 0.5
70
V
1, 2
1, 2
Input / Output voltage
Operating ambient temperature
Storage temperature
VI/O
V
TA
°C
°C
Tstg
–55
+125
Notes 1. –2.0 V (MIN.) (Pulse width : 2 ns)
DD
2. V Q + 2.3 V (MAX.) (Pulse width : 2 ns)
Caution
Exposing the device to stress above those listed in Absolute Maximum Ratings could cause
permanent damage. The device is not meant to be operated under conditions outside the limits
described in the operational section of this specification. Exposure to Absolute Maximum Rating
conditions for extended periods may affect device reliability.
Recommended DC Operating Conditions (TA = 0 to 70 °C)
Parameter
Supply voltage
Symbol
VDD
Conditions
MIN.
TYP.
3.3
MAX.
3.465
Unit
V
3.135
2.5 V LVTTL Interface
Output supply voltage
High level input voltage
Low level input voltage
3.3 V LVTTL Interface
Output supply voltage
High level input voltage
Low level input voltage
VDDQ
VIH
2.375
1.7
2.5
2.9
VDDQ + 0.3
+0.7
V
V
V
VIL
–0.3 Note
VDDQ
VIH
3.135
2.0
3.3
3.465
VDDQ + 0.3
+0.8
V
V
V
VIL
–0.3 Note
Note –0.8 V (MIN.) (Pulse Width : 2 ns)
Capacitance (TA = 25 °C, f = 1MHz)
Parameter
Input capacitance
Symbol
Test conditions
MIN.
TYP.
MAX.
Unit
pF
CIN
CI/O
Cclk
VIN = 0 V
4
7
4
Input / Output capacitance
Clock Input capacitance
VI/O = 0 V
Vclk = 0 V
pF
pF
Remark These parameters are periodically sampled and not 100% tested.
Data Sheet M14020EJ5V0DS00
11
µPD4382162, 4382182, 4382322, 4382362
DC Characteristics (TA = 0 to 70°C, VDD = 3.3 ± 0.165 V)
Parameter
Input leakage current
I/O leakage current
Symbol
ILI
Test condition
MIN.
–2
TYP.
MAX.
+2
Unit
µA
Note
VIN(except ZZ, MODE) = 0 V to VDD
VI/O = 0 V to VDDQ, Outputs are disabled
ILO
–2
+2
µA
★
Operating supply current
IDD
Device selected,
Cycle = MAX.
µPD4382162-A75
µPD4382182-A75
300
mA
VIN ≤ VIL or VIN ≥ VIH, µPD4382322-A67
440
400
170
II/O = 0 mA
µPD4382362-A67
µPD4382322-A75
µPD4382362-A75
IDD1
Suspend cycle, Cycle = MAX.
/AC, /AP, /ADV, /GW, /BWEs ≥ VIH,
VIN ≤ VIL or VIN ≥ VIH, II/O = 0 mA
Device deselected, Cycle = 0 MHz
VIN ≤ VIL or VIN ≥ VIH, All inputs are static
Device deselected, Cycle = 0 MHz
VIN ≤ 0.2 V or VIN ≥ VDD – 0.2 V,
VI/O ≤ 0.2 V, All inputs are static
Device deselected, Cycle = MAX.
VIN ≤ VIL or VIN ≥ VIH
Standby supply current
ISB
30
10
mA
ISB1
ISB2
ISBZZ
VOH
VOL
180
10
Power down supply current
2.5 V LVTTL Interface
High level output voltage
ZZ ≥ VDD – 0.2 V, VI/O ≤ VDDQ + 0.2 V
mA
V
IOH = –2.0 mA
IOH = –1.0 mA
IOL = +2.0 mA
IOL = +1.0 mA
1.7
2.1
Low level output voltage
0.7
0.4
V
3.3 V LVTTL Interface
High level output voltage
Low level output voltage
VOH
VOL
IOH = –4.0 mA
IOL = +8.0 mA
2.4
V
V
0.4
Data Sheet M14020EJ5V0DS00
12
µPD4382162, 4382182, 4382322, 4382362
AC Characteristics (TA = 0 to 70 °C, VDD = 3.3 ± 0.165 V)
AC Test Conditions
2.5 V LVTTL Interface
Input waveform (Rise / Fall time ≤ 2.4 ns)
2.4 V
1.2 V
Test points
1.2 V
V
SS
Output waveform
1.2 V
Test points
1.2 V
3.3 V LVTTL Interface
Input waveform (Rise / Fall time ≤ 3.0 ns)
3.0 V
1.5 V
Test ponts
1.5 V
V
SS
Output waveform
1.5 V
Test points
1.5 V
Output load condition
CL : 30 pF
5 pF (TKHQX1, TKHQX2, TGLQX, TGHQZ, TKHQZ)
External load at test
VT = +1.2 V / +1.5 V
50 Ω
ZO = 50 Ω
I/O (Output)
CL
Remark CL includes capacitances of the probe and jig, and stray capacitances.
Data Sheet M14020EJ5V0DS00
13
µPD4382162, 4382182, 4382322, 4382362
Read and Write Cycle
Parameter
Symbol
-A67
-A75
Unit
Note
(150 MHz)
(133 MHz)
Standard
Alias
TCYC
TCD
TOE
TDC1
TDC2
TOLZ
TOHZ
TCZ
TCH
TCL
MIN.
MAX.
–
MIN.
7.5
–
MAX.
Cycle time
TKHKH
TKHQV
TGLQV
TKHQX1
TKHQX2
TGLQX
TGHQZ
TKHQZ
TKHKL
6.66
–
–
4.0
4.0
–
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock access time
3.8
3.8
–
Output enable access time
Clock high to output active
Clock high to output change
Output enable to output active
Output disable to output high-Z
Clock high to output high-Z
Clock high pulse width
Clock low pulse width
Setup times Address
Address status
–
–
0
0
1.5
0
–
1.5
0
–
–
–
0
3.5
3.8
–
0
3.5
4.0
–
1.5
2.0
2.0
2.0
1.5
2.0
2.0
2.0
TKLKH
–
–
TAVKH
TADSVKH
TDVKH
TWVKH
TAS
TSS
TDS
TWS
–
–
–
Data in
Write enable
Address advance TADVVKH
Chip enable
Address
TEVKH
TKHAX
–
Hold times
TAH
TSH
TDH
TWH
–
0.5
–
0.5
–
ns
Address status
Data in
TKHADSX
TKHDX
Write enable
TKHWX
Address advance TKHADVX
Chip enable
TKHEX
TZZES
TZZEH
TZZRS
TZZRH
–
Power down entry setup
Power down entry hold
TZZES
TZZEH
TZZRS
TZZRH
5.0
1.0
6.0
0
–
–
–
–
5.0
1.0
6.0
0
–
–
–
–
ns
ns
ns
ns
1
1
1
1
Power down recovery setup
Power down recovery hold
Note 1. Although ZZ signal input is asynchronous, the signal must meet specified setup and hold times in order to be
recognized.
Data Sheet M14020EJ5V0DS00
14
★
READ CYCLE
TKHKH
CLK
/AP
/AC
TKHKL
TKLKH
TADSVKH
TKHADSX
TADSVKH
TKHADSX
TAVKH
TKHAX
A1
A2
TADVVKH
Address
/ADV
A3
TKHADVX
TWVKH
TKHWX
TKHWX
/BWE
/BWs
TWVKH
µ
µ
/GW
TEVKH
TKHEX
/CEs Note1
/G
TGLQV
Data In
TKHQV
Q2(A2)
TGHQZ
TKHQX2
Note2
TKHQZ
Q1(A2)
TGLQX
Hi-Z
Q1(A1)
Q1(A2)
Q3(A2)
Q4(A2)
Data Out
Notes 1. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
2. Outputs are disabled within one clock cycle after deselect.
Remark Qn(A2) refers to output from address A2. Q1-Q4 refer to outputs according to burst sequence.
★
WRITE CYCLE
TKHKH
CLK
/AP
TADSVKH TKHADSX
TKHKL
TKLKH
TADSVKH TKHADSX
/AC
Address
/ADV
TAVKH
TKHAX
A1
A2
A3
TADVVKH
TKHADVX
TWVKH
TKHWX
/BWENote1
/BWs
µ
µ
TWVKH
TEVKH
TKHWX
TKHEX
/GWNote1
/CEsNote2
/G
TDVKH
TKHDX
Data In
D1(A1)
D2(A1)
D1(A2)
D2(A2)
D2(A2)
D3(A2)
D4(A2)
D1(A3)
D2(A3)
D3(A3)
TGHQZ
Hi-Z
Data Out
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
1.
2.
Notes
★
READ / WRITE CYCLE
TKHKH
CLK
TKLKH
TKHKL
TKHADSX
TADSVKH
TADSVKH
/AP
/AC
TKHADSX
TAVKH
TKHAX
A1
A2
A3
TADVVKH
Address
/ADV
TKHADVX
TWVKH
TWVKH
TKHWX
/BWENote1
/BWs
µ
µ
TKHWX
/GWNote1
TEVKH
TKHEX
/CEsNote2
/G
TDVKH
TGHQZ
TKHDX
D1(A2)
Data In
TKHQV
TKHQX1
TGLQX
Q1(A2)
Hi-Z
Q1(A1)
Data Out
Q1(A3) Q2(A3)
Q3(A3)
Q4(A3)
Notes 1. All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW.
2. /CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
★
SINGLE READ / WRITE CYCLE
TKHKH
CLK
TKLKH
TKHKL
TKHADSX
TADSVKH
/AC
TAVKH TKHAX
A2
A3
TWVKH
A4
TKHWX
Address
A9
A10
A1
A5
A6
A7
A8
/BWE Note1
/BWs
TKHWX
TWVKH
/GW Note1
TEVKH
TKHEX
µ
µ
/CEs Note2
/G
TDVKH TKHDX
D1(A5) D1(A6)
TGHQZ
Data In
D1(A7)
D1(A10)
TGLQV
TGLQX
Q1(A1)
TKHQZ
TKHQV
Q1(A7)
Note3
Hi-Z
Data Out
Q1(A8)
Q1(A2) Q1(A3)
All bytes WRITE can be initiated by /GW LOW or /GW HIGH and /BWE, /BW1-/BW4 LOW.
/CEs refers to /CE, CE2 and /CE2. When /CEs is LOW, /CE and /CE2 are LOW and CE2 is HIGH.
When /CEs is HIGH, /CE and /CE2 are HIGH and CE2 is LOW.
1.
2.
Notes
Outputs are disabled within one clock cycle after deselect.
3.
/AP is HIGH and /ADV is don't care.
Remark
★
POWER DOWN (ZZ) CYCLE
TKHKH
CLK
TKHKL
TKLKH
/AP
/AC
Address
A1
A2
/ADV
µ
µ
/BWE
/BWs
/GW
/CEs
/G
Hi-Z
Q1(A1)
Q1(A2)
Data Out
TZZEH TZZES
TZZRH TZZRS
ZZ
Power Down (ISBZZ) State
STOP CLOCK CYCLE
★
TKHKH
CLK
TKHKL
TKLKH
/AP
/AC
Address
A1
A2
/ADV
/BWE
/BWs
µ
µ
/GW
/CEs
/G
Data In
Hi-Z
Q1(A1)
Q1(A2)
Data Out
Note
Power Down State (ISB1
)
Note VIN ≤ 0.2 V or VIN ≥ VDD − 0.2 V, VI/O ≤ 0.2 V
µPD4382162, 4382182, 4382322, 4382362
Package Drawing
100-PIN PLASTIC LQFP (14x20)
A
B
80
81
51
50
detail of lead end
S
C
D
R
Q
31
30
100
1
F
M
G
J
H
I
K
P
S
N
S
L
M
NOTE
ITEM MILLIMETERS
Each lead centerline is located within 0.13 mm of
its true position (T.P.) at maximum material condition.
A
B
C
D
F
22.0±0.2
20.0±0.2
14.0±0.2
16.0±0.2
0.825
G
0.575
+0.08
0.32
H
−0.07
I
J
0.13
0.65 (T.P.)
1.0±0.2
0.5±0.2
K
L
+0.06
0.17
M
−0.05
N
P
Q
0.10
1.4
0.125±0.075
+7°
3°
R
S
−3°
1.7 MAX.
S100GF-65-8ET-1
Data Sheet M14020EJ5V0DS00
21
µPD4382162, 4382182, 4382322, 4382362
Recommended Soldering Condition
Please consult with our sales offices for soldering conditions of the µPD4382162, 4382182, 4382322 and 4382362.
Types of Surface Mount Devices
µPD4382162GF : 100-PIN PLASTIC LQFP (14 x 20)
µPD4382182GF : 100-PIN PLASTIC LQFP (14 x 20)
µPD4382322GF : 100-PIN PLASTIC LQFP (14 x 20)
µPD4382362GF : 100-PIN PLASTIC LQFP (14 x 20)
Data Sheet M14020EJ5V0DS00
22
µPD4382162, 4382182, 4382322, 4382362
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
Data Sheet M14020EJ5V0DS00
23
µPD4382162, 4382182, 4382322, 4382362
[MEMO]
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
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rights of third parties by or arising from use of a device described herein or any other liability arising from use
of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other
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• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated "quality assurance program" for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98. 8
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