UPD703003AGC-33-XXX-8E [ETC]
32-Bit Microcontroller ; 32位微控制器\n
| 型号： | UPD703003AGC-33-XXX-8E |
| 厂家： | 
ETC |
| 描述： | 32-Bit Microcontroller
|
| 文件： | 总82页 (文件大小：442K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD703003A,703004A,703025A
V853TM
32/16-BIT SINGLE-CHIP MICROCONTROLLER
The µPD703003A, 703004A, 703025A are members of the V850 FamilyTM of 32-bit single-chip microcontrollers
designed for real-time control operations. These microcontrollers provide on-chip features, including a 32-bit CPU
core, ROM, RAM, interrupt controller, real-time pulse unit, a serial interface, an A/D converter, a D/A converter, and
PWM signal units.
Detailed function descriptions are provided in the following user’s manuals. Be sure to read them before
designing.
V853 User’s Manual, Hardware:
U10913E
V850 Family User’s Manual, Architecture: U10243E
FEATURES
•
•
•
•
•
Number of instructions: 74
Minimum instruction execution time: 30 ns (@ 33-MHz operation)
General-purpose registers: 32 bits × 32 registers
Instruction set optimized for control applications
On-chip memory
ROM: 256 Kbytes (µPD703025A)
128 Kbytes (µPD703003A)
96 Kbytes (µPD703004A)
RAM: 8 Kbytes (µPD703025A)
4 Kbytes (µPD703003A, 703004A)
•
•
•
•
•
•
•
•
Advanced on-chip interrupt controller
Real-time pulse unit suitable for control operations
Powerful serial interface (on-chip dedicated baud rate generator)
On-chip clock generator
10-bit resolution A/D converter: 8 channels
8-bit resolution D/A converter: 2 channels
8/9/10/12-bit resolution PWM: 2 channels
Power saving functions
APPLICATIONS
•
•
•
•
AV: Camcorders, VCRs, etc.
Office equipment: PPCs, LBPs, printers, etc.
Industrial equipment: Motor controllers, NC machine tools, etc.
Communications equipment: Mobile telephones, etc.
The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability
and additional information.
Document No. U13188EJ2V0DS00 (2nd edition)
Date Published August 1999 N CP(K)
Printed in Japan
The mark
shows major revised points.
1998
©
µPD703003A, 703004A, 703025A
ORDERING INFORMATION
Part Number
Package
Maximum
Operating
Internal Internal
ROM RAM
Frequency (MHz) (bytes) (bytes)
µPD703003AGC-25-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
µPD703003AGC-33-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
µPD703004AGC-25-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
µPD703004AGC-33-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
µPD703025AGC-25-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
µPD703025AGC-33-xxx-8EU 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
25
33
25
33
25
33
128 K
128 K
96 K
4 K
4 K
4 K
4 K
8 K
8 K
96 K
256 K
256 K
Remark xxx indicates ROM code suffix.
PIN CONFIGURATION
•
100-Pin Plastic LQFP (fine pitch) (14 × 14 mm)
µPD703003AGC-xx-xxx-8EU
µPD703004AGC-xx-xxx-8EU
µPD703025AGC-xx-xxx-8EU
P31/TO131
P32/TCLR13
P33/TI13
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
P75/ANI5
2
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
ANO0
3
P34/INTP130
P35/INTP131/SO3
P36/INTP132/SI3
P37/INTP133/SCK3
P63/A19
4
5
6
7
8
ANO1
P62/A18
9
AVREF2
P61/A17
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
AVREF3
P60/A16
P07/INTP113/ADTRG
P06/INTP112
P05/INTP111
P04/INTP110
P03/TI11
V
SS
V
DD
P57/AD15
P56/AD14
P55/AD13
P54/AD12
P53/AD11
P52/AD10
P51/AD9
P50/AD8
P47/AD7
P46/AD6
P45/AD5
P44/AD4
P02/TCLR11
P01/TO111
P00/TO110
P117/INTP143
P116/INTP142
P115/INTP141
P114/INTP140
P113/TI14
P112/TCLR14
P111/TO141
Caution Connect the IC (Internally Connected) pin directly to VSS.
2
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
PIN NAMES
A16 to A19:
AD0 to AD15:
ADTRG:
ANI0 to ANI7:
ANO0, ANO1:
ASTB:
Address Bus
P30 to P37:
P40 to P47:
P50 to P57:
P60 to P63:
P70 to P77:
P90 to P96:
P110 to P117:
PWM0, PWM1:
RESET:
Port3
Address/Data Bus
AD Trigger Input
Analog Input
Port4
Port5
Port6
Analog Output
Port7
Address Strobe
Port9
AVDD:
Analog Power Supply
Analog Reference Voltage
Analog Ground
Port11
AVREF1 to AVREF3:
AVSS:
Pulse Width Modulation
Reset
CVDD:
Power Supply for Clock Generator
Ground for Clock Generator
Clock Select
R/W:
Read/Write Status
Receive Data
Serial Clock
Serial Input
Serial Output
Timer Output
CVSS:
RXD0, RXD1:
SCK0 to SCK3:
SI0 to SI3:
CKSEL:
CLKOUT:
DSTB:
Clock Output
Data Strobe
SO0 to SO3:
TO110, TO111,:
TO120, TO121,
TO130, TO131,
TO140, TO141
HLDAK:
Hold Acknowledge
Hold Request
HLDRQ:
IC:
Internally Connected
INTP110 to INTP113,: Interrupt Request from Peripherals
INTP120 to INTP123,
TCLR11 to TCLR14: Timer Clear
INTP130 to INTP133,
TI11 to TI14:
TXD0, TXD1:
UBEN:
Timer Input
Transmit Data
Upper Byte Enable
Wait
INTP140 to INTP143
LBEN:
Lower Byte Enable
MODE:
Mode
WAIT:
NMI:
Non-maskable Interrupt Request
X1, X2:
VDD:
Crystal
P00 to P07:
P10 to P17:
P20 to P27:
Port0
Port1
Port2
Power Supply
Ground
VSS:
Data Sheet U13188EJ2V0DS00
3
µPD703003A, 703004A, 703025A
INTERNAL BLOCK DIAGRAM
Mask ROM
CPU
ASTB
NMI
Instruction
DSTB
queue
PC
INTC
RPU
INTP110 to INTP113
INTP120 to INTP123
INTP130 to INTP133
INTP140 to INTP143
R/W
UBEN
LBEN
Note 1
32-bit
barrel shifter
Multiplier
WAIT
16 × 16 → 32
A16 to A19
BCU
System
register
AD0 to AD15
TO110, TO111
TO120, TO121
TO130, TO131
TO140, TO141
HLDRQ
HLDAK
RAM
General
register
32 bits × 32
ALU
TCLR11 to TCLR14
TI11 to TI14
Note 2
SIO
SO0/TXD0
SI0/RXD0
SCK0
UART0/CSI0
BRG0
UART1/CSI1
BRG1
SO1/TXD1
SI1/RXD1
SCK1
CKSEL
Port
A/D
D/A
CG
CLKOUT
converter converter
X1
X2
SO2
SI2
SCK2
MODE
RESET
CSI2
BRG2
V
V
DD
SS
SO3
SI3
SCK3
CVDD
CVSS
CSI3
PWM0, PWM1
PWM
Notes 1. µPD703003A:
µPD703004A:
128 Kbytes
96 Kbytes
µPD703025A:
256 Kbytes
2. µPD703003A, 703004A: 4 Kbytes
µPD703025A: 8 Kbytes
4
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
CONTENTS
1. DIFFERENCES AMONG PRODUCTS ............................................................................................
2. PIN FUNCTIONS..............................................................................................................................
6
7
7
9
2.1
2.2
2.3
Port Pins ................................................................................................................................................
Non-port Pins ........................................................................................................................................
Pin I/O Circuits and Recommended Connection of Unused Pins .................................................... 11
3. FUNCTION BLOCKS ....................................................................................................................... 14
3.1
Internal Units ......................................................................................................................................... 14
4. CPU FUNCTIONS ............................................................................................................................ 16
5. BUS CONTROL FUNCTIONS ......................................................................................................... 17
6. INTERRUPT/EXCEPTION HANDLING FUNCTION........................................................................ 18
7. CLOCK GENERATION FUNCTION ................................................................................................ 21
8. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT) ........................................................ 22
9. SERIAL INTERFACE FUNCTIONS (SIO) ....................................................................................... 24
9.1
9.2
9.3
Asynchronous Serial Interfaces 0, 1 (UART0, UART1)...................................................................... 24
Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3) .................................................................................. 26
Baud Rate Generators 0 to 2 (BRG0 to BRG2) ................................................................................... 28
10. PWM UNIT ....................................................................................................................................... 29
11. A/D CONVERTER ............................................................................................................................ 30
12. D/A CONVERTER ............................................................................................................................ 31
13. PORT FUNCTIONS.......................................................................................................................... 32
14. RESET FUNCTION .......................................................................................................................... 45
15. INSTRUCTION SET ......................................................................................................................... 46
16. ELECTRICAL SPECIFICATIONS.................................................................................................... 53
17. PACKAGE DRAWINGS................................................................................................................... 77
18. RECOMMENDED SOLDERING CONDITIONS............................................................................... 78
Data Sheet U13188EJ2V0DS00
5
µPD703003A, 703004A, 703025A
1. DIFFERENCES AMONG PRODUCTS
Item
µPD703003 µPD703003A µPD703004A µPD703025A µPD70F3003 µPD70F3003A µPD70F3025A
Internal ROM
Internal RAM
Mask ROM
128 Kbytes
Flash memory
96 Kbytes 256 Kbytes 128 Kbytes
256 Kbytes
8 Kbytes
4 Kbytes
8 Kbytes
4 Kbytes
Operation Normal
Single-chip Implemented
mode
operation mode
mode
ROM-less Implemented Not implemented
mode
Implemented Not implemented
Implemented
Flash memory
Not implemented
programming mode
VPP pin
Not implemented
Implemented
Value of CKC register when reset 00H
MODE = 0: 03H
MODE = 1: 00H
00H
MODE = 0: 03H
MODE = 1: 00H
Electrical specifications
Others
Power consumption levels vary (see specific product’s data sheet).
Depending on the products, noise tolerance and noise emission will vary due to the
differences in circuit scale and mask layout.
6
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
2. PIN FUNCTIONS
2.1 Port Pins
(1/2)
Pin Name
P00
I/O
I/O
Function
Alternate Function
TO110
Port 0
8-bit input/output port
Input/output can be specified in 1-bit units
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P30
P31
P32
P33
P34
P35
P36
P37
P40 to P47
TO111
TCLR11
TI11
INTP110
INTP111
INTP112
INTP113/ADTRG
TO120
I/O
I/O
I/O
Port 1
8-bit input/output port
Input/output can be specified in 1-bit units
TO121
TCLR12
TI12
INTP120
INTP121/SO2
INTP122/SI2
INTP123/SCK2
PWM0
Port 2
8-bit input/output port
Input/output can be specified in 1-bit units
PWM1
TXD0/SO0
RXD0/SI0
SCK0
TXD1/SO1
RXD1/SI1
SCK1
Port 3
TO130
8-bit input/output port
Input/output can be specified in 1-bit units
TO131
TCLR13
TI13
INTP130
INTP131/SO3
INTP132/SI3
INTP133/SCK3
AD0 to AD7
I/O
I/O
Port 4
8-bit input/output port
Input/output can be specified in 1-bit units
P50 to P57
Port 5
AD8 to AD15
8-bit input/output port
Input/output can be specified in 1-bit units
Data Sheet U13188EJ2V0DS00
7
µPD703003A, 703004A, 703025A
(2/2)
Alternate Function
A16 to A19
Pin Name
I/O
I/O
Function
P60 to P63
Port 6
4-bit input/output port
Input/output can be specified in 1-bit units
P70 to P77
Input
I/O
Port 7
ANI0 to ANI7
8-bit input port
P90
Port 9
LBEN
7-bit input/output port
Input/output can be specified in 1-bit units
P91
UBEN
P92
R/W
P93
DSTB
P94
ASTB
P95
HLDAK
HLDRQ
TO140
TO141
TCLR14
TI14
P96
P110
P111
P112
P113
P114
P115
P116
P117
I/O
Port 11
8-bit input/output port
Input/output can be specified in 1-bit units
INTP140
INTP141
INTP142
INTP143
8
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
2.2 Non-port Pins
(1/2)
Pin Name
TO110
I/O
Function
Alternate Function
P00
Output
Pulse signal output from timers 11 to 14
TO111
TO120
TO121
TO130
TO131
TO140
TO141
TCLR11
TCLR12
TCLR13
TCLR14
TI11
P01
P10
P11
P30
P31
P110
P111
Input
Input
Input
Input
Input
Input
Output
Input
External clear signal input for timers 11 to 14
External count clock input for timers 11 to 14
P02
P12
P32
P112
P03
TI12
P13
TI13
P33
TI14
P113
INTP110
INTP111
INTP112
INTP113
INTP120
INTP121
INTP122
INTP123
INTP130
INTP131
INTP132
INTP133
INTP140
INTP141
INTP142
INTP143
SO0
External maskable interrupt request input, also used as external capture
trigger input for timer 11
P04
P05
P06
P07/ADTRG
P14
External maskable interrupt request input, also used as external capture
trigger input for timer 12
P15/SO2
P16/SI2
P17/SCK2
P34
External maskable interrupt request input, also used as external capture
trigger input for timer 13
P35/SO3
P36/SI3
P37/SCK3
P114
External maskable interrupt request input, also used as external capture
trigger input for timer 14
P115
P116
P117
Serial transmit data output (3-wire) for CSI0 to CSI3
Serial receive data input (3-wire) for CSI0 to CSI3
P22/TXD0
P25/TXD1
P15/INTP121
P35/INTP131
P23/RXD0
P26/RXD1
P16/INTP122
P36/INTP132
SO1
SO2
SO3
SI0
SI1
SI2
SI3
Data Sheet U13188EJ2V0DS00
9
µPD703003A, 703004A, 703025A
(2/2)
Alternate Function
P24
Pin Name
SCK0
I/O
I/O
Function
Serial clock I/O (3-wire) for CSI0 to CSI3
SCK1
P27
SCK2
P17/INTP123
P37/INTP133
SCK3
TXD0
Output
Input
Output
I/O
Serial transmit data output for UART0 and UART1
Serial receive data input for UART0 and UART1
PWM pulse signal output
P22/SO0
TXD1
P25/SO1
RXD0
P23/SI0
RXD1
P26/SI1
PWM0
PWM1
AD0 to AD7
AD8 to AD15
A16 to A19
LBEN
P20
P21
16-bit multiplexed address/data bus for external memory expansion
P40 to P47
P50 to P57
Output
Output
High-order address bus used for external memory expansion
External data bus’s low-order byte enable signal output
External data bus’s high-order byte enable signal output
External read/write status output
P60 to P63
P90
UBEN
R/W
P91
Output
P92
DSTB
External data strobe signal output
P93
ASTB
External address strobe signal output
Bus hold acknowledge output
P94
HLDAK
HLDRQ
ANI0 to ANI7
ANO0, ANO1
NMI
Output
Input
Input
Output
Input
Output
Input
Input
Input
Input
Input
—
P95
Bus hold request input
P96
Analog input to A/D converter
P70 to P77
Analog output to D/A converter
—
Non-maskable interrupt request input
System clock output
—
CLKOUT
CKSEL
WAIT
—
Input for specifying clock generator’s operation mode
Control signal input for inserting wait in bus cycle
Operation mode specification
CVDD
—
MODE
RESET
X1
—
System reset input
—
Resonator connection for system clock. Input is via X1 when using an
external clock.
—
X2
—
ADTRG
AVREF1
AVREF2
AVREF3
AVDD
Input
Input
Input
A/D converter external trigger input
P07/INTP113
Reference voltage input for A/D converter
Reference voltage input for D/A converter
—
—
—
—
—
—
—
—
—
—
Positive power supply for A/D converter
Ground potential for A/D converter
Positive power supply for on-chip clock generator
Ground potential for on-chip clock generator
Positive power supply
—
AVSS
—
CVDD
CKSEL
—
CVSS
VDD
—
VSS
Ground potential
—
IC
Internally connected pin. Connect directly to VSS.
—
10
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
The input/output circuit type of each pin and recommended connection of unused pins are shown in Table 2-1.
Figure 2-1 illustrates the various circuit types using partially abridged diagrams.
When connecting to VDD or VSS via a resistor, a resistance value in the range of 1 to 10 kΩ is recommended.
Table 2-1. Types of Pin Input/Output Circuits (1/2)
Pin Name
Input/Output Circuit Type
Recommended Connection of Unused Pins
P00/TO110, P01/TO111
5
8
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P02/TCLR11, P03/TI11,
P04/INTP110 to P07/INTP113/ADTRG
P10/TO120, P11/TO121
5
8
P12/TCLR12, P13/TI12
P14/INTP120
P15/INTP121/SO2
P16/INTP122/SI2
P17/INTP123/SCK2
P20/PWM0, P21/PWM1
P22/TXD0/SO0
5
P23/RXD0/SI0, P24/SCK0
P25/TXD1/SO1
8
5
8
5
8
P26/RXD1/SI1, P27/SCK1
P30/TO130, P31/TO131
P32/TCLR13, P33/TI13
P34/INTP130
P35/INTP131/SO3
P36/INTP132/SI3
P37/INTP133/SCK3
10-A
5
P40/AD0 to P47/AD7
P50/AD8 to P57/AD15
P60/A16 to P63/A19
P70/ANI0 to P77/ANI7
P90/LBEN
9
5
Connect directly to VSS.
Input: Independently connect to VDD or VSS via a resistor.
Output: Leave open.
P91/UBEN
P92/R/W
P93/DSTB
P94/ASTB
P95/HLDAK
P96/HLDRQ
P110/TO140, P111/TO141
P112/TCLR14, P113/TI14
8
P114/INTP140 to P117/INTP143
ANO0, ANO1
NMI
12
2
Leave open.
Connect directly to VSS.
Data Sheet U13188EJ2V0DS00
11
µPD703003A, 703004A, 703025A
Table 2-1. Types of Pin Input/Output Circuits (2/2)
Pin Name
Input/Output Circuit Type
Recommended Connection of Unused Pins
Leave open.
CLKOUT
WAIT
3
1
2
Connect directly to VDD.
MODE
—
RESET
CVDD/CKSEL
AVREF1 to AVREF3, AVSS
—
—
—
Connect directly to VSS.
Connect directly to VDD.
Connect directly to VSS.
AVDD
IC
12
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Figure 2-1. Pin Input/Output Circuits
Type 1
Type 8
VDD
P-ch
VDD
Data
IN/OUT
P-ch
Output
disable
IN
N-ch
N-ch
Type 2
Type 9
P-ch
N-ch
Comparator
+
–
IN
IN
VREF (threshold voltage)
Input enable
Schmitt-triggered input with hysteresis characteristics
Type 3
Type 10-A
VDD
VDD
Pull-up
P-ch
enable
VDD
P-ch
OUT
Data
P-ch
IN/OUT
N-ch
Open-drain
N-ch
output disable
Type 5
Type 12
VDD
P-ch
Data
IN/OUT
P-ch
N-ch
Analog output voltage
Output
disable
OUT
N-ch
Input
enable
Data Sheet U13188EJ2V0DS00
13
µPD703003A, 703004A, 703025A
3. FUNCTION BLOCKS
3.1 Internal Units
3.1.1 CPU
The CPU uses five-stage pipeline control to enable single-clock execution of address calculations, arithmetic logic
operations, data transfers, and almost all other instruction processing.
Other dedicated on-chip hardware, such as a multiplier (16 bits × 16 bits) and a barrel shifter (32 bits) help accelerate
processing of complex instructions.
3.1.2 Bus control unit (BCU)
The BCU starts the required bus cycle based on the physical address obtained by the CPU. When an instruction
is fetched from external memory area and the CPU does not send a bus cycle start request, the BCU generates a
prefetch address and prefetches the instruction code. The prefetched instruction code is stored in an internal
instruction queue.
3.1.3 ROM
ROM is mapped to the address space starting at 00000000H. The MODE pin can be used to select an access
enable/disable setting. ROM can be accessed by the CPU in one clock cycle when an instruction is fetched.
3.1.4 RAM
RAM is mapped to the address space starting at FFFFE000H. RAM can be accessed by the CPU in one clock
cycle when data accessed.
3.1.5 Ports
Various port pin and control pin functions can be selected for the 75 pins (port 0 to port 11) comprising I/O ports
(of which eight pins comprise an input-only port).
3.1.6 Interrupt controller (INTC)
This controller handles hardware interrupt requests (NMI, INTP110 to INTP113, INTP120 to INTP123, INTP130
to INTP133, and INTP140 to INTP143) from on-chip peripheral hardware and external hardware. Eight interrupt
priority levels can be specified for these interrupt requests, and multiplexed servicing control can be performed for
interrupt sources.
3.1.7 Clock generator (CG)
An on-chip PLL enables the CPU operating clock to be supplied to resonators connected to pins X1 and X2 at 5×
frequency, 1× frequency, and 1/2× frequency. It can also be connected to an external clock instead of to a resonator.
3.1.8 Real-time pulse unit (RPU)
The RPU includes a four-channel 16-bit timer/event counter and a one-channel 16-bit interval timer, which enables
measurement of pulse intervals and frequency as well as programmable pulse output.
14
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
3.1.9 Serial interface (SIO)
Four channels comprise two kinds of serial interfaces: an asynchronous serial interface (UART) and a clocked
serial interface (CSI). Two of these four channels are switchable between the UART and CSI and the other two
channels are fixed as CSI.
For UART, data is transferred via the TXD and RXD pins. The baud rate is determined by the on-chip baud rate
generator. For CSI, data is transferred via the SO, SI, and SCK pins. The baud rate can be determined by the on-
chip baud rate generator or it can be supplied from an external source.
One of the two CSI-fixed channels is used as the serial clock output, and serial output is sent via an N-ch open
drain output.
3.1.10 Pulse width modulation (PWM)
There are two channels of selectable 8/9/10/12-bit resolution PWM signal outputs. When a low pass filter is
externally connected, PWM output can be used as D/A converter output. This is suitable for actuator control
applications, such as in motors.
3.1.11 A/D converter (ADC)
This is a high-speed, high-resolution 10-bit A/D converter that includes eight analog input pins. It converts using
the successive approximation method.
3.1.12 D/A converter (DAC)
This is an 8-bit resolution D/A converter that includes two channels. It converts using the R-2R conversion method.
Data Sheet U13188EJ2V0DS00
15
µPD703003A, 703004A, 703025A
4. CPU FUNCTIONS
The CPU employs a RISC-based architecture and uses five-stage pipeline control to enable single-clock execution
of almost all instructions.
The features of the CPU functions are shown below.
•
Minimum instruction execution time
30 ns (@ internal 33-MHz operation)
Address space: 16-Mbyte linear
General registers: 32 bits × 32 registers
Internal 32-bit architecture
•
•
•
•
•
•
•
•
•
5-stage pipeline control
Multiply/divide instructions
Saturated operation instructions
32-bit shift instruction: 1 clock
Long/short format
Four types of bit manipulation instructions
•
•
•
•
Set
Clear
Not
Test
16
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
5. BUS CONTROL FUNCTIONS
The features of the bus control functions are shown below.
•
•
Shared as port pins, connectable to external device
Wait functions
•
•
Programmable wait function for up to three states per two blocks
External wait function using WAIT pin
•
•
•
Idle state insertion function
Bus mastering arbitration function
Bus hold function
Data Sheet U13188EJ2V0DS00
17
µPD703003A, 703004A, 703025A
6. INTERRUPT/EXCEPTION HANDLING FUNCTION
The features of the interrupt/exception handling function are shown below.
•
Interrupts
•
•
•
•
•
•
Non-maskable interrupt: 1 source
Maskable interrupt: 32 sources
8-level programmable priority control
Multiple interrupt control based on priority levels
Mask specification for each maskable interrupt request
Noise elimination, edge detection, and valid edge specification for external interrupt requests
•
Exceptions
•
•
Software exceptions: 32 sources
Exception trap: 1 source (invalid instruction code exception)
The configuration of the interrupt/exception handling function is shown below.
Figure 6-1. Block Diagram of Maskable Interrupt
Internal bus
7
0
ISPR
XXMKn (interrupt mask flag)
INTOV11
OVIF11
INTOV12
INTOV13
INTOV14
OVIF12
OVIF13
OVIF14
P11IF0
INTP110/INTCC110
INTP111/INTCC111
Handler
address
generator
RPU
P11IF1
P11IF2
P11IF3
P12IF0
P12IF1
P12IF2
P12IF3
P13IF0
P13IF1
P13IF2
P13IF3
P14IF0
P14IF1
P14IF2
P14IF3
INTP112/INTCC112
INTP113/INTCC113
INTP120/INTCC120
INTP121/INTCC121
INTP122/INTCC122
INTP123/INTCC123
INTP130/INTCC130
INTP131/INTCC131
INTP132/INTCC132
INTP133/INTCC133
INTP140/INTCC140
INTP141/INTCC141
INTP142/INTCC142
INTP143/INTCC143
INTCM4
INTP110
INTP111
INTP112
INTP113
INTP120
INTP121
INTP122
INTP123
INTP130
INTP131
INTP132
INTP133
INTP140
INTP141
INTP142
INTP143
INTM1
INTM2
INTM3
INTM4
Interrupt
request
CPU
CMIF4
CSIF0
CSIF1
CSIF2
CSIF3
SEIF0
SRIF0
STIF0
SEIF1
SRIF1
STIF1
ADIF
INTCSI0
INTCSI1
INTCSI2
INTCSI3
INTSER0
INTSR0
INTST0
INTSER1
INTSR1
INTST1
Interrupt
request
acknowledge
PSW
ID
HALT mode
release signal
SIO
INTAD
A/D converter
XX: Name of peripheral unit (OV, P11 to P14, CM, CS, SE, SR, ST, AD)
n: Peripheral unit number (none, or 0 to 4, 11 to 14)
18
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Interrupt/exception sources are shown in Table 6-1.
Table 6-1. List of Interrupts (1/2)
Interrupt/Exception Source
Default Exception Handler Restored
Priority Code Address PC
Type
Category
Name
Control
Trigger Source
Unit
Register
Reset
Interrupt RESET
—
—
—
—
—
Reset input
—
—
—
—
—
—
—
—
—
—
0
0000H
0010H
00000000H Undefined
00000010H nextPC
Non-maskable Interrupt NMI
NMI input
Software
exception
Exception TRAP0nNote
Exception TRAP1nNote
TRAP instruction
TRAP instruction
Invalid instruction code
004nHNote 00000040H nextPC
005nHNote 00000050H nextPC
Exception trap Exception ILGOP
0060H
0080H
0090H
00A0H
00B0H
00C0H
00D0H
00E0H
00F0H
0100H
0110H
0120H
0130H
0140H
0150H
0160H
0170H
0180H
0190H
01A0H
01B0H
01C0H
01D0H
01E0H
00000060H nextPC
00000080H nextPC
00000090H nextPC
000000A0H nextPC
000000B0H nextPC
000000C0H nextPC
000000D0H nextPC
000000E0H nextPC
000000F0H nextPC
00000100H nextPC
00000110H nextPC
00000120H nextPC
00000130H nextPC
00000140H nextPC
00000150H nextPC
00000160H nextPC
00000170H nextPC
00000180H nextPC
00000190H nextPC
000001A0H nextPC
000001B0H nextPC
000001C0H nextPC
000001D0H nextPC
000001E0H nextPC
Maskable
Interrupt INTOV11
Interrupt INTOV12
Interrupt INTOV13
Interrupt INTOV14
OVIC11 Timer 11 overflow
OVIC12 Timer 12 overflow
OVIC13 Timer 13 overflow
OVIC14 Timer 14 overflow
RPU
RPU
1
RPU
2
RPU
3
Interrupt INTP110/INTCC110 P11IC0 Match between INTP110 and CC110
Interrupt INTP111/INTCC111 P11IC1 Match between INTP111 and CC111
Interrupt INTP112/INTCC112 P11IC2 Match between INTP112 and CC112
Interrupt INTP113/INTCC113 P11IC3 Match between INTP113 and CC113
Interrupt INTP120/INTCC120 P12IC0 Match between INTP120 and CC120
Interrupt INTP121/INTCC121 P12IC1 Match between INTP121 and CC121
Interrupt INTP122/INTCC122 P12IC2 Match between INTP122 and CC122
Interrupt INTP123/INTCC123 P12IC3 Match between INTP123 and CC123
Interrupt INTP130/INTCC130 P13IC0 Match between INTP130 and CC130
Interrupt INTP131/INTCC131 P13IC1 Match between INTP131 and CC131
Interrupt INTP132/INTCC132 P13IC2 Match between INTP132 and CC132
Interrupt INTP133/INTCC133 P13IC3 Match between INTP133 and CC133
Interrupt INTP140/INTCC140 P14IC0 Match between INTP140 and CC140
Interrupt INTP141/INTCC141 P14IC1 Match between INTP141 and CC141
Interrupt INTP142/INTCC142 P14IC2 Match between INTP142 and CC142
Interrupt INTP143/INTCC143 P14IC3 Match between INTP143 and CC143
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
Pin/RPU
RPU
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
Interrupt INTCM4
Interrupt INTCSI0
Interrupt INTCSI1
CMIC4 Signal matches CM4
CSIC0
CSIC1
CSI0 transmission/reception completion SIO
CSI1 transmission/reception completion SIO
Note n = 0 to FH.
Remarks 1. Default priority: Default priority is the priority order when several maskable interrupt requests
are generated at the same time. The highest priority is 0.
Restored PC: This is the PC value that is saved to EIPC or FEPC when interrupt or exception
handling is started. However, if an interrupt occurs during execution of the DIVH
(divide) instruction, the restored PC value is the PC value of the current instruction
(DIVH).
2. The invalid instruction execution address can be obtained using restored PC-4 when an invalid
instruction code exception occurs.
Data Sheet U13188EJ2V0DS00
19
µPD703003A, 703004A, 703025A
Table 6-1. List of Interrupts (2/2)
Interrupt/Exception Source
Default Exception Handler Restored
Priority Code Address PC
Type
Category
Name
Control
Trigger Source
Unit
Register
Maskable
Interrupt INTCSI2
Interrupt INTCSI3
Interrupt INTSER0
Interrupt INTSR0
Interrupt INTST0
Interrupt INTSER1
Interrupt INTSR1
Interrupt INTST1
Interrupt INTAD
CSIC2
CSIC3
SEIC0
SRIC0
STIC0
SEIC1
SRIC1
STIC1
ADIC
CSI2 transmission/reception completion
CSI3 transmission/reception completion
UART0 reception error
SIO
SIO
SIO
SIO
SIO
SIO
SIO
SIO
ADC
23
24
25
26
27
28
29
30
31
01F0H
0200H
0210H
0220H
0230H
0240H
0250H
0260H
0270H
000001F0H nextPC
00000200H nextPC
00000210H nextPC
00000220H nextPC
00000230H nextPC
00000240H nextPC
00000250H nextPC
00000260H nextPC
00000270H nextPC
UART0 reception completion
UART0 transmission completion
UART1 reception error
UART1 reception completion
UART1 transmission completion
A/D conversion completion
Remarks 1. Default priority: Default priority is the priority order when several maskable interrupt requests
are generated at the same time. The highest priority is 0.
Restored PC: This is the PC value that is saved to EIPC or FEPC when interrupt or exception
handling is started. However, if an interrupt occurs during execution of the DIVH
(divide) instruction, the restored PC value is the PC value of the current instruction
(DIVH).
2. The invalid instruction execution address can be obtained using restored PC-4 when an invalid
instruction code exception occurs.
20
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
7. CLOCK GENERATION FUNCTION
The features of the clock generation function are shown below.
•
•
Multiplier function using PLL clock synthesizer
Clock sources
•
•
•
Oscillation via resonator connection (PLL mode): fXX = φ, 2 × φ, φ/5
External clock (PLL mode): fXX = φ, 2 × φ, φ/5
External clock (direct mode): fXX = 2 × φ
•
Power saving control
•
•
•
•
HALT mode
IDLE mode
Software STOP mode
Clock output inhibit mode
The configuration of the clock generation function is shown below.
Figure 7-1. Block Diagram of Clock Generation Function
φ
X1
(fXX
CPU, internal peripheral I/O
CLKOUT
)
Clock generator
X2
CKSEL
Remark φ: Internal system clock frequency
fXX: Frequency of external oscillator or external clock
Data Sheet U13188EJ2V0DS00
21
µPD703003A, 703004A, 703025A
8. TIMER/COUNTER FUNCTIONS (REAL-TIME PULSE UNIT)
The features of the timer/counter functions are shown below.
•
•
Measurement of pulse interval and frequency, programmable pulse output
•
•
16-bit measurements enabled
Generates a variety of pulse patterns (interval pulse, one-shot pulse, etc.)
Timer 1
•
•
•
•
•
•
16-bit timer/event counter
Count clock sources: two types (selection of an internal system clock division, external pulse input)
Capture/compare (shared) registers: 16
Count clear pins: TCLR11 to TCLR14
Interrupt sources: 20 types
External pulse outputs: 8
•
Timer 4
•
•
•
•
16-bit interval timer
Count clock: selectable from an internal system clock division
Compare register: 1
Interrupt source: 1
22
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
The configurations of the respective timer/counter functions are shown below.
Figure 8-1. Block Diagram of Timer 1 (16-bit timer/event counter)
Edge
detection
Clear and
start
TCLR1n
Clear and start
φ m
Note 1
φ m/4
φ m/8
φ /2 φ m
φ /4
INTOV1n
TM1n (16 bits)
φ
m/32
Note 2
Edge detection
TI1n
INTCC1n0
INTCC1n1
INTP1n0
INTP1n1
INTP1n2
INTP1n3
S
CC1n0
CC1n1
CC1n2
CC1n3
Edge detection
Edge detection
Edge detection
Edge detection
Q
Q
TO1n0
TO1n1
RNote3
S
Q
Q
RNote3
INTCC1n2
INTCC1n3
Notes 1. Internal count clock
2. External count clock
3. Priority to reset
Remark φ: Internal system clock
n = 1 to 4
Figure 8-2. Block Diagram of Timer 4 (16-bit interval timer)
φ /2
Note
φ /4 φ m
φ /16
φ m
φ m/32
TM4 (16-bit)
φ /32
Clear and start
INTCM4
CM4
Note Internal count clock
Remark φ: Internal system clock
Data Sheet U13188EJ2V0DS00
23
µPD703003A, 703004A, 703025A
9. SERIAL INTERFACE FUNCTIONS (SIO)
Two types and six channels of serial interfaces are provided.
Up to four channels may be used at the same time.
(1) Asynchronous serial interfaces 0, 1 (UART0, UART1): 2 channels
(2) Clocked serial interfaces 0 to 3 (CSI0 to CSI3): 4 channels
Caution UART0 and CSI0 use the same alternate function pin, as do UART1 and CSI1. Either one can be
selected via a register (ASIM00, ASIM10).
9.1 Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
The features of asynchronous serial interfaces 0, 1 (UART0, UART1) are shown below.
•
Transfer rate
150 bps to 76800 bps (with φ = 33-MHz operation, using baud rate generator)
110 bps to 307200 bps (with φ = 20-MHz operation, using baud rate generator)
Maximum 1031 Kbps (with φ = 33-MHz operation, using φ/2)
Full duplex communications: Receive buffer (RXBn) incorporated
Two-pin configuration
•
•
TXDn: output pin for transmit data
RXDn: input pin for receive data
•
•
Reception error detection function
•
•
•
Parity error
Framing error
Overrun error
Three types of interrupt sources
•
•
•
Reception error interrupt (INTSERn)
Reception completion interrupt (INTSRn)
Transmission completion interrupt (INTSTn)
•
•
•
•
•
The character length of transmit and receive data is specified via the ASIMn0, ASIMn1 registers
Character length: 7 or 8 bits, or 9 bits (if using expansion bit)
Parity function: even, odd, zero, or no parity
Transmission stop bits: 1 or 2 bits
On-chip baud rate generator
Remark n = 0, 1
φ: Internal system clock
24
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
The configuration of asynchronous serial interfaces 0, 1 (UART0, UART1) is shown below.
Figure 9-1. Block Diagram of Asynchronous Serial Interfaces 0, 1 (UART0, UART1)
Internal bus
8
8
16/8
ASIMn0
ASIMn1
16/8
RXBn
Receive
buffer
EBSn
TXEn RXEn PSn1 PSn0 CLn SLn SCLSn
8
RXBnL
ASISn
TXSn
Receive
shift register
Transmit
shift register
RXDn
TXDn
PEn FEn OVEn SOTn
TXSnL
Reception
control
parity check
Transmission
control parity
attachment
INTSERn
INTSTn
INTSRn
1
1
16
16
φ
1
2
Baud rate generator
Remark n = 0, 1
φ: Internal system clock
Data Sheet U13188EJ2V0DS00
25
µPD703003A, 703004A, 703025A
9.2 Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3)
The features of clocked serial interfaces 0 to 3 (CSI0 to CSI3) are shown below.
•
•
Number of channels: 4 (CSIn)
High-speed transfer
MAX 8.25 Mbps (with φ = 33-MHz operation)
Half-duplex communications
Character length: 8-bit units
•
•
•
•
•
Switchable byte ordering (MSB first or LSB first)
Selectable external serial clock input/internal serial clock output
3-wire type
SOn: Serial data output
SIn: Serial data input
SCKn: Serial clock I/O
•
Interrupt source: 1 type
•
Transmission/reception completion interrupt (INTCSIn)
Remark n = 0 to 3
φ: Internal system clock
26
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
The configuration of clocked serial interfaces 0 to 3 (CSI0 to CSI3) is shown below.
Figure 9-2. Block Diagram of Clocked Serial Interfaces 0 to 3 (CSI0 to CSI3)
Internal bus
CSIMn
CTXEn CRXEn CSOTn MODn
CLSn1 CLSn0
SO latch
SIn
D
Q
Shift register (SIOn)
SOn
Note
Note
Baud rate generator
Serial clock
control circuit
1
2
φ
φ
/2
SCKn
Serial clock
counter
Interrupt
control circuit
INTCSIn
Note SO0 to SO2, SCK0 to SCK2: CMOS outputs
SO3, SCK3:
N-ch open-drain outputs
Remark n = 0 to 3
φ: Internal system clock
Data Sheet U13188EJ2V0DS00
27
µPD703003A, 703004A, 703025A
9.3 Baud Rate Generators 0 to 2 (BRG0 to BRG2)
The features of baud rate generators 0 to 2 (BRG0 to BRG2) are shown below.
•
•
Serial clock can be selected from baud rate generator output or φ (internal system clock)
Identical baud rates during transmission and reception
The configuration of baud rate generators 0 to 2 (BRG0 to BRG2) is shown below.
Figure 9-3. Block Diagram of Baud Rate Generators 0 to 2 (BRG0 to BRG2)
Baud rate generator 0
BPRM0
BRG0
Match
UART0
CSI0
φ
Clear
1
2
TMBRG0
Prescaler
UART1
CSI1
Baud rate generator 1
CSI2
CSI3
Baud rate generator 2
28
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
10. PWM UNIT
The features of the PWM unit are shown below.
•
•
•
•
PWMn: 2 channels
Selectable active level for PWMn output pulse
Operating clock selectable as φ, φ/2, φ/4, φ/8, or φ/16 (φ: Internal system clock)
PWMn output resolution selectable as 8, 9, 10, or 12 bits
Remark n = 0, 1
The configuration of the PWM unit is shown below.
Figure 10-1. Block Diagram of PWM Unit
7
8
φ
φ
φ
φ
φ
9
Overflow
/2
/4
/8
/16
11
TMPn (12 bits)
Comparator
ALVn
0-7
0-8
0-9
0-11
S
Q
PWMn
Match
RNote
CMPn (12 bits)
PWMn (12 bits)
Note Priority at reset
Remark n = 0, 1
φ: Internal system clock
Data Sheet U13188EJ2V0DS00
29
µPD703003A, 703004A, 703025A
11. A/D CONVERTER
The features of the A/D converter are shown below.
•
•
•
Analog inputs: 8 channels
On-chip 10-bit A/D converter
On-chip A/D conversion result registers (ADCR0 to ADCR7)
10 bits × 8 registers
•
A/D conversion trigger modes
A/D trigger mode
Timer trigger mode
External trigger mode
•
Sequential conversion method
The configuration of the A/D converter is shown below.
Figure 11-1. Block Diagram of A/D Converter
Series resistor string
ANI0
Sample & hold circuit
AVREF1
R/2
R
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
R/2
AVSS
AVDD
Voltage comparator
9
9
0
SAR (10)
10
10
INTAD
0
ADCR0
ADCR1
ADCR2
ADCR3
ADCR4
ADCR5
ADCR6
ADCR7
INTCC110
INTCC111
Controller
INTCC112
INTCC113
ADTRG
Noise
Edge
elimination detection
7
0
7
0
ADM0 (8)
8
ADM1 (8)
8
10
Internal bus
30
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
12. D/A CONVERTER
The features of the D/A converter are shown below.
•
•
8-bit resolution D/A converter: 2 channels
R-2R conversion method
The configuration of the D/A converter is shown below.
Figure 12-1. Block Diagram of D/A Converter
2R
2R
AVREF2
ANOn
R
Selector
R
2R
2R
AVREF3
DACSn
DACEn
Internal bus
Remark n = 0, 1
Data Sheet U13188EJ2V0DS00
31
µPD703003A, 703004A, 703025A
13. PORT FUNCTIONS
The features of the port functions are shown below.
•
Number of ports
Input-only ports:
I/O ports:
8
67
•
•
•
•
Alternated as I/O pins for other peripheral functions
Input/output can be specified in 1-bit units
Noise elimination
Edge detection
The configurations of the respective port functions are shown below.
Figure 13-1. Block Diagram of P00 and P01 (Port 0)
WRPMC
PMC0n
WRPM
PM0n
WRPORT
TO11n
P0n
P0n
RDIN
Address
Remark n = 0, 1
32
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Figure 13-2. Block Diagram of P02 to P07 (Port 0)
WRPMC
PMC0n
PM0n
WRPM
WRPORT
P0n
P0n
Address
RDIN
INTP110 to INTP112,
INTP113/ADTRG,
TCLR11, TI11
Noise elimination
Edge detection
Remark n = 2 to 7
Figure 13-3. Block Diagram of P10 and P11 (Port 1)
WRPMC
PMC1n
WRPM
PM1n
TO12n
WRPORT
P1n
P1n
Address
RDIN
Remark n = 0, 1
Data Sheet U13188EJ2V0DS00
33
µPD703003A, 703004A, 703025A
Figure 13-4. Block Diagram of P12 to P14 (Port 1)
WRPMC
WRPM
PMC1n
PM1n
WRPORT
P1n
P1n
Address
RDIN
Noise elimination
Edge detection
TCLR12, TI12
INTP120
Remark n = 2 to 4
Figure 13-5. Block Diagram of P15 (Port 1)
PCM1
WRPMC
PMC15
WRPM
PM15
WRPORT
SO2
P15
P15
Address
RDIN
Noise elimination
Edge detection
INTP121
PCM1
34
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Figure 13-6. Block Diagram of P16 (Port 1)
WRPMC
WRPM
PMC16
PM16
WRPORT
P16
P16
Address
RDIN
Noise elimination
Edge detection
INTP122
SI2
PCM1
Figure 13-7. Block Diagram of P17 (Port 1)
SCK2 I/O
switch
PCM1
WRPMC
WRPM
PMC17
PM17
WRPORT
SCK2 output
P17
P17
Address
RDIN
Noise elimination
Edge detection
INTP123
SCK2 input
PCM1
Data Sheet U13188EJ2V0DS00
35
µPD703003A, 703004A, 703025A
Figure 13-8. Block Diagram of P20 and P21 (Port 2)
WRPMC
PMC2n
PM2n
WRPM
WRPORT
PWM0, PWM1
P2n
P2n
RDIN
Address
Remark n = 0, 1
Figure 13-9. Block Diagram of P22 and P25 (Port 2)
SO0, SO1 output
enable
WRPMC
WRPM
PMC2n
PM2n
TXD0/SO0
TXD1/SO1
WRPORT
P2n
P2n
RDIN
Address
Remark n = 2, 5
36
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Figure 13-10. Block Diagram of P23 and P26 (Port 2)
WRPMC
WRPM
PMC2n
PM2n
WRPORT
P2n
P2n
Address
RXD0/SI0
RXD1/SI1
RDIN
Remark n = 3, 6
Figure 13-11. Block Diagram of P24 and P27 (Port 2)
SCK0, SCK1
I/O switch
WRPMC
PMC2n
WRPM
PM2n
SCK0 output
SCK1 output
WRPORT
P2n
P2n
Address
SCK0 input
RDIN
SCK1 input
Remark n = 4, 7
Data Sheet U13188EJ2V0DS00
37
µPD703003A, 703004A, 703025A
Figure 13-12. Block Diagram of P30 and P31 (Port 3)
WRPMC
PMC3n
PM3n
WRPM
WRPORT
TO13n
P3n
P3n
RDIN
Address
Remark n = 0, 1
Figure 13-13. Block Diagram of P32 to P34 (Port 3)
WRPMC
PMC3n
WRPM
PM3n
WRPORT
P3n
P3n
Address
RDIN
Noise elimination
Edge detection
TCLR13, TI13
INTP130
Remark n = 2 to 4
38
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Figure 13-14. Block Diagram of P35 (Port 3)
SO3 output
enable
PCM3
PUO3
WRPMC
PMC35
PM35
V
DD
WRPM
P
WRPORT
P
N
SO3
P35
P35
Address
RDIN
Noise elimination
Edge detection
INTP131
PCM3
Figure 13-15. Block Diagram of P36 (Port 3)
WRPMC
PUO3
PMC36
VDD
WRPM
P
PM36
P36
WRPORT
P
N
P36
Address
RDIN
Noise elimination
Edge detection
INTP132
SI3
PCM3
Data Sheet U13188EJ2V0DS00
39
µPD703003A, 703004A, 703025A
Figure 13-16. Block Diagram of P37 (Port 3)
SCK3 I/O
switch
WRPMC
PCM3
PUO3
PMC37
PM37
V
DD
WRPM
P
WRPORT
P
N
SCK3 output
P37
P37
Address
RDIN
Noise elimination
Edge detection
INTP133
SCK3 input
PCM3
Figure 13-17. Block Diagram of P40 to P47 (Port 4)
MODE
MM0 to MM2
I/O control circuit
WRPM
PM4n
WRPORT
AD0 to AD7 output
P4n
P4n
Address
RDIN
AD0 to AD7 input
Remark n = 0 to 7
40
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Figure 13-18. Block Diagram of P50 to P57 (Port 5)
MODE
MM0 to MM2
I/O control circuit
WRPM
PM5n
WRPORT
AD8 to AD15 output
P5n
P5n
Address
RDIN
AD8 to AD15 input
Remark n = 0 to 7
Figure 13-19. Block Diagram of P60 to P63 (Port 6)
MODE
MM0 to MM2
I/O control circuit
WRPM
PM6n
WRPORT
A16 to A19 output
P6n
P6n
Address
RDIN
Remark n = 0 to 3
Data Sheet U13188EJ2V0DS00
41
µPD703003A, 703004A, 703025A
Figure 13-20. Block Diagram of P70 to P77 (Port 7)
P7n
ANI0 to ANI7
Sample & hold
circuit
RDIN
Remark n = 0 to 7
Figure 13-21. Block Diagram of P90 to P95 (Port 9)
MODE MM0 to MM3
I/O control circuit
WRPM
PM9n
LBEN, UBEN, R/W,
DSTB, ASTB, HLDAK
WRPORT
P9n
P9n
Address
RDIN
Remark n = 0 to 5
42
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Figure 13-22. Block Diagram of P96 (Port 9)
MM3
I/O control circuit
WRPM
PM96
P96
WRPORT
P96
Address
RDIN
HLDRQ
Figure 13-23. Block Diagram of P110 and P111 (Port 11)
WRPMC
PMC11n
WRPM
PM11n
WRPORT
TO14n
P11n
P11n
RDIN
Address
Remark n = 0, 1
Data Sheet U13188EJ2V0DS00
43
µPD703003A, 703004A, 703025A
Figure 13-24. Block Diagram of P112 to P117 (Port 11)
WRPMC
PMC11n
PM11n
WRPM
WRPORT
P11n
P11n
Address
RDIN
Noise elimination
Edge detection
TCLR14, TI14
INTP140 to INTP143
Remark n = 2 to 7
44
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
14. RESET FUNCTION
When low-level input occurs at the RESET pin, a system reset is performed and the various on-chip hardware
devices are reset to their initial settings.
When the input at the RESET pin changes from low level to high level, the reset status is canceled and the CPU
resumes program execution. The contents of the various registers should be initialized within the program as
necessary.
The reset function has the following feature.
•
On-chip noise elimination circuit which uses analog delay ( 60 ns) for the reset pin
Data Sheet U13188EJ2V0DS00
45
µPD703003A, 703004A, 703025A
15. INSTRUCTION SET
•
How to read instruction set tables
Indicates the instruction group. Instructions are listed in these tables according to their respective groups.
Indicates the mnemonic abbreviation for the instruction.
Indicates the instruction's operands (see Table 15-1).
Indicates the instruction binary code. The binary codes for 32-bit
instructions are shown in two levels (see Table 15-2).
Indicates instruction operation (see Table 15-3).
Indicates flag operations
(see Table 15-4).
Flags
Mnemonic
Operand
Opcode
Operation
CY
OV
S
Z
SAT
Table 15-1. Symbols Used to Indicate Operands
Symbol
Description
reg1
reg2
ep
General registers (r0 to r31): used as source registers
General registers (r0 to r31): mainly used as destination registers
Element pointer (r30)
bit#3
3-bit data used to specify bit number
X bits immediate
immX
dispX
regID
vector
cccc
X bits displaced
System register number
5-bit data used to specify trap vector (00H to 1FH)
4-bit data used to indicate condition code
46
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Table 15-2. Symbols Used to Indicate Opcodes
Symbol
Description
R
1-bit data of code specifying reg1 or regID
1-bit data of code specifying reg2
1 bit of displaced data
r
d
i
1 bit of immediate data
cccc
bbb
4-bit data used to indicate condition code
3-bit data used to specify bit number
Table 15-3. Symbols Used to Indicate Operations
Symbol
Description
←
Assign
GR [ ]
SR [ ]
General register
System register
zero-extend (n)
Zero-extend n up until word length
Sign-extend n up until word length
Read data having size b from address a
Replace data b at address a with data having size c
Read bit b from address a
sign-extend (n)
load-memory (a, b)
store-memory (a, b, c)
load-memory-bit (a, b)
store-memory-bit (a, b, c)
saturated (n)
Write c to bit b from address a
Execute saturation processing for n (n = complement to 2)
Calculation of n:
When n ≥ 7FFFFFFFH, result is 7FFFFFFFH.
When n ≤ 80000000H, result is 80000000H.
result
Result is indicated by flag operations
Byte (8 bits)
Byte
Halfword
Half word (16 bits)
Word (32 bits)
Add
Word
+
–
Subtract
||
Bit linkage
×
Multiply
÷
Divide
AND
Logical AND
OR
Logical OR
XOR
Exclusive OR
Logical NOT
NOT
logically shift left by
logically shift right by
arithmetically shift right by
Logical shift left
Logical shift right
Arithmetic shift right
Data Sheet U13188EJ2V0DS00
47
µPD703003A, 703004A, 703025A
Table 15-4. Flag Operations
Identifier
Description
(Blank)
No change
0
×
Clear to zero
Set or clear according to result
Restore previously saved value(s)
R
Table 15-5. Condition Codes
Condition Name (cond) Condition Code (cccc)
Conditional Expression
OV = 1
Description
V
0000
1000
0001
Overflow
No overflow
Carry
NV
OV = 0
CY = 1
C/L
Lower (Less than)
NC/NL
Z/E
1001
0010
1010
CY = 0
Z = 1
No carry
No lower (Greater than or equal)
Zero
Equal
NZ/NE
Z = 0
Not zero
Not equal
NH
H
0011
1011
0100
1100
0101
1101
0110
1110
0111
1111
(CY OR Z) = 1
(CY OR Z) = 0
S = 1
Not higher (Less than or equal)
Higher (Greater than)
Negative
N
P
S = 0
Positive
T
–
Always (unconditional)
Saturated
SA
LT
GE
LE
GT
SAT = 1
(S XOR OV) = 1
(S XOR OV) = 0
((S XOR OV) OR Z) = 1
((S XOR OV) OR Z) = 0
Less than signed
Greater than or equal signed
Less than or equal signed
Greater than signed
48
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Instruction Set List
Instruction Mnemonic
Group
Operand
Opcode
Operation
Flags
CY OV
S
Z
SAT
Load/store SLD.B
instructions
disp7[ep], reg2
disp8[ep], reg2
disp8[ep], reg2
r r r r r 0 1 1 0 d d d d d d d adr ← ep + zero-extend (disp7)
GR[reg2] ← sign-extend (Load-memory (adr, Byte))
SLD.H
SLD.W
LD.B
r r r r r 1 0 0 0 d d d d d d d adr ← ep + zero-extend (disp8)
Note 1 GR[reg2] ← sign-extend (Load-memory (adr, Halfword))
r r r r r 1 0 1 0 d d d d d d 0 adr ← ep + zero-extend (disp8)
Note 2 GR[reg2] ← Load-memory (adr, Word)
disp16[reg1], reg2 r r r r r 1 1 1 0 0 0RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d d GR[reg2] ← sign-extend (Load-memory (adr, Byte))
LD.H
disp16[reg1], reg2 r r r r r 1 1 1 0 0 1RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d 0 GR[reg2] ← sign-extend (Load-memory (adr, Halfword))
Note 3
LD.W
disp16[reg1], reg2 r r r r r 1 1 1 0 0 1RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d 1 GR[reg2] ← Load-memory (adr, Word)
Note 3
SST.B
SST.H
SST.W
ST.B
reg2, disp7[ep]
reg2, disp8[ep]
reg2, disp8[ep]
r r r r r 0 1 1 1 d d d d d d d adr ← ep + zero-extend (disp7)
Store-memory (adr, GR[reg2], Byte)
r r r r r 1 0 0 1 d d d d d d d adr ← ep + zero-extend (disp8)
Note 1 Store-memory (adr, GR[reg2], Halfword)
r r r r r 1 0 1 0 d d d d d d 1 adr ← ep + zero-extend (disp8)
Note 2 Store-memory (adr, GR[reg2], Word)
reg2, disp16[reg1] r r r r r 1 1 1 0 1 0RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d d Store-memory (adr, GR[reg2], Byte)
ST.H
reg2, disp16[reg1] r r r r r 1 1 1 0 1 1RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d 0 Store-memory (adr, GR[reg2], Halfword)
Note 3
ST.W
reg2, disp16[reg1] r r r r r 1 1 1 0 1 1RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d 1 Store-memory (adr, GR[reg2], Word)
Note 3
Arithmetic MOV
reg1, reg2
imm5, reg2
r r r r r 0 0 0 0 0 0RRRRR GR[reg2] ← GR[reg1]
operation
MOV
r r r r r 0 1 0 0 0 0 i i i i i GR[reg2] ← sign-extend (imm5)
instructions
MOVHI
imm16, reg1, reg2 r r r r r 1 1 0 0 1 0RRRRR GR[reg2] ← GR[reg1] + (imm16 || 016
)
i i i i i i i i i i i i i i i i
MOVEA imm16, reg1, reg2 r r r r r 1 1 0 0 0 1RRRRR GR[reg2] ← GR[reg1] + sign-extend (imm16)
i i i i i i i i i i i i i i i i
ADD
ADD
ADDI
reg1, reg2
imm5, reg2
r r r r r 0 0 1 1 1 0RRRRR GR[reg2] ← GR[reg2] + GR[reg1]
×
×
×
×
×
×
×
×
×
×
×
×
r r r r r 0 1 0 0 1 0 i i i i i GR[reg2] ← GR[reg2] + sign-extend (imm5)
imm16, reg1, reg2 r r r r r 1 1 0 0 0 0RRRRR GR[reg2] ← GR[reg1] + sign-extend (imm16)
i i i i i i i i i i i i i i i i
SUB
reg1, reg2
reg1, reg2
r r r r r 0 0 1 1 0 1RRRRR GR[reg2] ← GR[reg2] – GR[reg1]
r r r r r 0 0 1 1 0 0RRRRR GR[reg2] ← GR[reg1] – GR[reg2]
×
×
×
×
×
×
×
×
SUBR
Notes 1. ddddddd = high-order 7 bits of disp8
2. dddddd = high-order 6 bits of disp8
3. ddddddddddddddd = high-order 15 bits of disp16
Data Sheet U13188EJ2V0DS00
49
µPD703003A, 703004A, 703025A
Instruction Mnemonic
Group
Operand
Opcode
Operation
Flags
CY OV
S
Z
SAT
Arithmetic MULH
operation
reg1, reg2
r r r r r 0 0 0 1 1 1RRRRR GR[reg2] ← GR[reg2]Note × GR[reg1]Note
(signed multiplication)
instructions
MULH
imm5, reg2
r r r r r 0 1 0 1 1 1 i i i i i GR[reg2] ← GR[reg2]Note × sign-extend (imm5)
(signed multiplication)
MULHI
imm16, reg1, reg2 r r r r r 1 1 0 1 1 1RRRRR GR[reg2] ← GR[reg1]Note × imm16
i i i i i i i i i i i i i i i i
(signed multiplication)
Note
DIVH
CMP
CMP
SETF
reg1, reg2
reg1, reg2
imm5, reg2
cccc, reg2
r r r r r 0 0 0 0 1 0RRRRR GR[reg2] ← GR[reg2] ÷ GR[reg1]
r r r r r 0 0 1 1 1 1RRRRR result ← GR[reg2] – GR[reg1]
(signed division)
×
×
×
×
×
×
×
×
×
×
×
r r r r r 0 1 0 0 1 1 i i i i i result ← GR[reg2] – sign-extend (imm5)
r r r r r 1 1 1 1 1 1 0 c c c c if conditions are satisfied
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
then GR[reg2] ← 00000001H
else GR[reg2] ← 00000000H
Saturated SATADD reg1, reg2
r r r r r 0 0 0 1 1 0RRRRR GR[reg2] ← saturated (GR[reg2] + GR[reg1])
r r r r r 0 1 0 0 0 1 i i i i i GR[reg2] ← saturated (GR[reg2] + sign-extend (imm5))
r r r r r 0 0 0 1 0 1RRRRR GR[reg2] ← saturated (GR[reg2] – GR[reg1])
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
operation
SATADD imm5, reg2
instructions
SATSUB reg1, reg2
SATSUBI imm16, reg1, reg2 r r r r r 1 1 0 0 1 1RRRRR GR[reg2] ← saturated (GR[reg1] – sign-extend (imm16))
i i i i i i i i i i i i i i i i
SATSUBR reg1, reg2
r r r r r 0 0 0 1 0 0RRRRR GR[reg2] ← saturated (GR[reg1] – GR[reg2])
r r r r r 0 0 1 0 1 1RRRRR result ← GR[reg2]AND GR[reg1]
r r r r r 0 0 1 0 0 0RRRRR GR[reg2] ← GR[reg2]OR GR[reg1]
×
×
0
0
0
×
×
×
×
×
×
×
×
×
Logical
TST
OR
reg1, reg2
reg1, reg2
operation
instruction
ORI
imm16, reg1, reg2 r r r r r 1 1 0 1 0 0RRRRR GR[reg2] ← GR[reg1]OR zero-extend (imm16)
i i i i i i i i i i i i i i i i
AND
reg1, reg2
r r r r r 0 0 1 0 1 0RRRRR GR[reg2] ← GR[reg2]AND GR[reg1]
0
0
×
×
×
ANDI
imm16, reg1, reg2 r r r r r 1 1 0 1 1 0RRRRR GR[reg2] ← GR[reg1]AND zero-extend (imm16)
0
i i i i i i i i i i i i i i i i
XOR
reg1, reg2
r r r r r 0 0 1 0 0 1RRRRR GR[reg2] ← GR[reg2]XOR GR[reg1]
0
0
×
×
×
×
XORI
imm16, reg1, reg2 r r r r r 1 1 0 1 0 1RRRRR GR[reg2] ← GR[reg1]XOR zero-extend (imm16)
i i i i i i i i i i i i i i i i
NOT
SHL
reg1, reg2
reg1, reg2
r r r r r 0 0 0 0 1RRRRR
GR[reg2] ← NOT (GR[reg1])
0
0
×
×
×
×
r r r r r 1 1 1 1 1 1RRRRR GR[reg2] ← GR[reg2]logically shift left by GR[reg1]
×
×
×
×
×
×
0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0
SHL
SHR
SHR
SAR
SAR
imm5, reg2
reg1, reg2
imm5, reg2
reg1, reg2
imm5, reg2
r r r r r 0 1 0 1 1 0 i i i i i GR[reg2] ← GR[reg2]logically shift left by
0
0
0
0
0
×
×
×
×
×
×
×
×
×
×
zero-extend (imm5)
r r r r r 1 1 1 1 1 1RRRRR GR[reg2] ← GR[reg2]logically shift right by GR[reg1]
0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
r r r r r 0 1 0 1 0 0 i i i i i GR[reg2] ← GR[reg2]logically shift right by
zero-extend (imm5)
r r r r r 1 1 1 1 1 1RRRRR GR[reg2] ← GR[reg2]arithmetically shift right by
0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0
GR[reg1]
r r r r r 0 1 0 1 0 1 i i i i i GR[reg2] ← GR[reg2]arithmetically shift right by
zero-extend (imm5)
Note Only the low-order half word is valid.
50
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Instruction Mnemonic
Group
Operand
Opcode
Operation
Flags
CY OV
S
Z
SAT
Branch
JMP
JR
[reg1]
0 0 0 0 0 0 0 0 0 1 1RRRRR PC ← GR[reg1]
instructions
disp22
0 0 0 0 0 1 1 1 1 0 d d d d d d PC ← PC + sign-extend (disp22)
d d d d d d d d d d d d d d d 0
Note 1
JARL
disp22, reg2
disp9
r r r r r 1 1 1 1 0 d d d d d d GR[reg2] ← PC + 4
d d d d d d d d d d d d d d d 0 PC ← PC + sign-extend (disp22)
Note 1
Bcond
SET1
d d d d d 1 0 1 1 d d d c c c c if conditions are satisfied
Note 2 then PC ← PC + sign-extend (disp9)
Bit
bit#3, disp16[reg1] 0 0 b b b 1 1 1 1 1 0RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d d Z flag ← Not (Load-memory-bit (adr, bit#3))
Store-memory-bit (adr, bit#3, 1)
×
×
×
×
manipulation
instructions
CLR1
NOT1
TST1
bit#3, disp16[reg1] 1 0 b b b 1 1 1 1 1 0RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d d Z flag ← Not (Load-memory-bit (adr, bit#3))
Store-memory-bit (adr, bit#3, 0)
bit#3, disp16[reg1] 0 1 b b b 1 1 1 1 1 0RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d d Z flag ← Not (Load-memory-bit (adr, bit#3))
Store-memory-bit (adr, bit#3, Z flag)
bit#3, disp16[reg1] 1 1 b b b 1 1 1 1 1 0RRRRR adr ← GR[reg1] + sign-extend (disp16)
d d d d d d d d d d d d d d d d Z flag ← Not (Load-memory-bit (adr, bit#3))
Notes 1. ddddddddddddddddddddd = high-order 21 bits of disp22
2. dddddddd = high-order 8 bits of disp9
Data Sheet U13188EJ2V0DS00
51
µPD703003A, 703004A, 703025A
Instruction Mnemonic
Group
Operand
Opcode
Operation
Flags
CY OV
S
Z
SAT
Special
LDSR
reg2, regID
r r r r r 1 1 1 1 1 1RRRRR SR[regID] ← GR[reg2] regID = EIPC, FEPC
0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0
instructions
regID = EIPSW, FEPSW
Note
regID = PSW
×
×
×
×
×
STSR
TRAP
regID, reg2
vector
r r r r r 1 1 1 1 1 1RRRRR GR[reg2] ← SR[regID]
0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0
0 0 0 0 0 1 1 1 1 1 1 i i i i i EIPC ← PC + 4 (restored PC)
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 EIPSW ← PSW
ECR.EICC ← Interrupt code
PSW.EP ← 1
PSW.ID ← 1
PC ← 00000040H (when vector is 00H to 0FH)
00000050H (when vector is 10H to 1FH)
RETI
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 if PSW.EP = 1
R
R
R
R
R
0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0
then PC ← EIPC
PSW ← EIPSW
else if PSW.NP = 1
then PC ← FEPC
PSW ← FEPSW
else PC ← EIPC
PSW ← EIPSW
HALT
DI
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 Stops
0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0
0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID ← 1
0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 (maskable interrupt prohibit)
EI
1 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 PSW.ID ← 0
0 0 0 0 0 0 0 1 0 1 1 0 0 0 0 0 (maskable interrupt enable)
NOP
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 No operation, uses at least one clock
Note In this instruction, “reg2” is the mnemonic abbreviation for the source register, but the reg1 field is used for
the opcode. Consequently, this instruction differs from other instructions in the way the registers are
specified in the mnemonic description and opcode.
rrrrr = regID specification
RRRRR = reg2 specification
52
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
16. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25°C)
Parameter
Symbol
VDD
Conditions
Rating
–0.5 to +7.0
–0.5 to VDD + 0.3
–0.5 to +0.5
–0.5 to VDD + 0.3
–0.5 to +0.5
–0.5 to VDD + 0.3
–0.5 to VDD + 1.0
4.0
Unit
V
Power supply voltage
VDD pin
CVDD
CVSS
AVDD
AVSS
VI1
CVDD pin
CVSS pin
AVDD pin
AVSS pin
V
V
V
V
Input voltage
Note, VDD = 5.0 V±10%
X1 pin, VDD = 5.0 V±10%
Per pin
V
Clock input voltage
Output current, low
VK
V
IOL
mA
mA
mA
mA
V
Total for all pins
Per pin
100
Output current, high
IOH
–4.0
Total for all pins
VDD = 5.0 V±10%
P70/ANI0 to P77/ANI7
–100
Output voltage
VO
–0.5 to VDD + 0.3
–0.5 to VDD + 0.3
–0.5 to AVDD + 0.3
–0.5 to VDD + 0.3
–0.5 to AVDD + 0.3
–40 to +85
Analog input voltage
VIAN
AVDD > VDD
VDD ≥ AVDD
AVDD > VDD
VDD ≥ AVDD
V
V
Analog reference input voltage
AVREF
AVREF1 to AVREF3
V
V
Operating ambient temperature
Storage temperature
TA
°C
°C
Tstg
–65 to +150
Note X1, P70/ANI0 to P77/ANI7, and AVREF1 to AVREF3 are excluded.
Cautions 1. Be sure to avoid direct connections among the IC device output (or I/O) pins and between
VDD or VCC and GND. However, open-drain pins and open collector pins can be directly
connected. A direct connection to an external circuit can be made to avoid conflicting output
from high-impedance pins if the external circuit is designed for the correct timing.
2. Product quality may suffer if the absolute maximum rating is exceeded even momentarily for
any parameter. That is, the absolute maximum ratings are rated values at which the product
is on the verge of suffering physical damage, and therefore the product must be used under
conditions that ensure that the absolute maximum ratings are not exceeded.
The ratings and conditions shown below for DC characteristics and AC characteristics are
within the range for normal operation and quality assurance.
Capacitance (TA = 25°C, VDD = VSS = 0 V)
Parameter
Input capacitance
Symbol
CI
Condition
MIN.
TYP. MAX.
Unit
pF
fC = 1 MHz
Unmeasured pins returned to 0 V.
15
15
15
I/O capacitance
CIO
pF
Output capacitance
CO
pF
Data Sheet U13188EJ2V0DS00
53
µPD703003A, 703004A, 703025A
Recommended Operating Conditions
Operation Mode
Internal Operating
Operating Ambient
Temperature (TA)
Power Supply
Voltage (VDD)
Clock Frequency (φ)
Note 1
Direct mode
0 to 33 MHz
–40 to +85°C
–40 to +85°C
–40 to +85°C
5.0 V ±10%
5.0 V ±10%
5.0 V ±10%
Note 2
5 to 33 MHz
PLL mode
Free-running oscillation frequency to 33 MHz
Notes 1. When not using A/D converter
2. When using A/D converter
Remark The range of internal operating clock frequency in PLL mode is the assured range of function operation.
PLL locked frequency is specified by tCYX.
54
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Recommended Oscillator
(1) µPD703003A, 703004A
(a) Ceramic resonator connection (TA = –40 to +85°C)
X1
X2
Rd
C2
C1
Manufacturer
Part Number
Oscillation
Frequency
fXX (MHz)
Recommended
Circuit Constant
Oscillation
Oscillation
Voltage Range
Stabilization Time
(MAX.) TOST (ms)
C1 (pF) C2 (pF)
Rd (Ω) MIN. (V) MAX. (V)
Kyocera
KBR-3.0MS
3.0
3.2
5.0
5.0
5.0
5.0
5.0
5.0
6.6
6.6
6.6
6.6
6.6
6.6
5.0
5.0
6.6
3.2
3.2
5.0
5.0
6.6
6.6
82
82
33
82
82
33
—
—
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
4.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
0.24
0.24
0.14
0.14
0.14
0.14
0.14
0.14
0.10
0.10
0.10
0.10
0.10
0.10
0.18
0.16
0.17
0.27
0.27
0.31
0.31
0.30
0.30
Corporation
KBR-3.2MS
KBR-5.0MSA/MSB
KBR-5.0MKC
KBR-5.0MKD
KBR-5.0MKS
PBRC5.00A
680
680
680
680
680
680
—
On-chip On-chip
On-chip On-chip
On-chip On-chip
33
On-chip On-chip
33 33
33
PBRC5.00B
KBR-6.6MSA/MSB
KBR-6.6MKC
KBR-6.6MKD
KBR-6.6MKS
PBRC6.60A
On-chip On-chip
On-chip On-chip
On-chip On-chip
—
—
—
33
33
—
PBRC6.60B
On-chip On-chip
On-chip On-chip
On-chip On-chip
On-chip On-chip
—
TDK
CCR5.0MC3
—
FCR5.0MC5
—
CCR6.6MC3
—
Murata Mfg.
Co., Ltd.
CSA3.20MG040
CST3.20MGW040
CSA5.00MG040
CST5.00MGW040
CSA6.60MTZ040
CST6.60MTW040
100
On-chip On-chip
100 100
On-chip On-chip
100 100
On-chip On-chip
100
—
—
—
—
—
—
Cautions 1. Put the oscillator as close to the X1 and X2 pins as possible.
2. Do not cross the wiring with the other signal lines in the broken-line area.
3. Sufficiently evaluate the matching between the µPD703003A, 703004A and the resonator.
Data Sheet U13188EJ2V0DS00
55
µPD703003A, 703004A, 703025A
(b) External clock input
X1
X2
Open
High-speed CMOS inverter
External clock
Cautions 1. Put the high-speed CMOS inverter as close to the X1 pin as possible.
2. Sufficiently evaluate the matching between the µPD703003A, 703004A and the high-
speed CMOS inverter.
(2) µPD703025A
Undefined
56
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)
(1/2)
Parameter
Input voltage, high
Symbol
Conditions
MIN.
2.2
TYP.
MAX.
VDD + 0.3
VDD + 0.3
+0.8
Unit
V
VIH
Except for X1 and pins listed in Note
Note
0.8VDD
–0.5
V
Input voltage, low
VIL
Except for X1 and pins listed in Note
V
Note
–0.5
0.2VDD
VDD + 0.5
+0.6
V
Clock input voltage, high
Clock input voltage, low
VXH
VXL
X1
0.8VDD
–0.5
V
X1
V
+
Schmitt-triggered input
Threshold voltage
VT
Note, rising edge
Note, falling edge
Note
3.0
2.0
V
–
VT
V
+
–
Schmitt-triggered input hysteresis width VT – VT
0.5
V
Output voltage, high
VOH
IOH = –2.5 mA
IOH = –100 µA
IOL = 2.5 mA
VI = VDD
0.7VDD
V
VDD – 0.4
V
Output voltage, low
VOL
ILIH
ILIL
0.45
10
V
Input leakage current, high
Input leakage current, low
Output leakage current, high
Output leakage current, low
Software pull-up resistor
µA
µA
µA
µA
kΩ
VI = 0 V
–10
10
ILOH
ILOL
R
VO = VDD
VO = 0 V
–10
90
P35/INTP131/SO3,
P36/INTP132/SI3,
P37/INTP133/SCK3
15
40
Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/
INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/
SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3,
P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE
Remarks 1. TYP. values are reference values for when TA = 25°C and VDD = 5.0 V.
2. φ = Internal system clock frequency
Data Sheet U13188EJ2V0DS00
57
µPD703003A, 703004A, 703025A
DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)
(2/2)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Note
Power µPD703003A, When
IDD1
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
1.9 × φ + 5 2.1 × φ + 17 mA
2.0 × φ + 7 2.2 × φ + 20 mA
1.2 × φ + 5 1.3 × φ + 13 mA
1.3 × φ + 7 1.4 × φ + 15 mA
703004A
operating
supply
current
Note
Note
In
IDD2
IDD3
IDD4
IDD1
IDD2
IDD3
IDD4
HALT mode
In
8 × φ + 300 10 × φ + 500
0.1 × φ + 2 0.2 × φ + 3
µA
mA
µA
IDLE mode
In
2
50
STOP mode
Note
Note
Note
µPD703025A, When
operating
Direct mode
PLL mode
Direct mode
PLL mode
Direct mode
PLL mode
2.5 × φ + 2 2.8 × φ + 16.5 mA
2.6 × φ + 4 2.9 × φ +19.5 mA
1.3 × φ + 5 1.4 × φ + 13 mA
1.3 × φ + 10 1.4 × φ + 18 mA
8 × φ + 300 10 × φ + 500 µA
In
HALT mode
In
IDLE mode
0.1 × φ + 2 0.2 × φ + 3
mA
In
2
50
µA
STOP mode
Note When using A/D converter: φ = 5 to 33 MHz
When not using A/D converter: φ = 0 to 33 MHz
Remarks 1. TYP. values are reference values for when TA = 25°C and VDD = 5.0 V. The power supply current
does not include AVREF1 to AVREF3 or the current that flows across a software pull-up resistor.
2. φ = Internal system clock frequency
58
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Data Retention Characteristics (TA = –40 to +85°C)
Parameter
Data retention voltage
Data retention current
Symbol
VDDDR
IDDDR
Conditions
MIN.
1.5
TYP.
MAX.
5.5
Unit
V
STOP mode
VDD = VDDDR
–40°C ≤ TA ≤ +50°C
50°C < TA ≤ 85°C
0.2VDDDR
0.2VDDDR
50
µA
µA
µs
200
Power supply voltage rise time
Power supply voltage fall time
tRVD
tFVD
tHVD
200
200
0
µs
Power supply voltage hold time
(vs. STOP mode setting)
ms
STOP mode release signal input time tDREL
Data retention high-level input voltage
Data retention low-level input voltage VILDR
Note
Note
0
0.9VDDDR
0
ns
V
VIHDR
VDDDR
0.1VDDDR
V
Note P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/
INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/
SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3,
P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1
Remark TYP. values are reference values for when TA = 25°C and VDD = 5.0 V.
STOP mode setting (fifth clock after PSC register is set)
V
DD
V
DD
V
DD
V
DDDR
t
DREL
t
HVD
t
FVD
t
RVD
RESET (input)
V
V
IHDR
NMI (input)
(Released at falling edge)
IHDR
NMI (input)
(Released at rising edge)
V
ILDR
Data Sheet U13188EJ2V0DS00
59
µPD703003A, 703004A, 703025A
AC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V)
AC test input waveform
(a) P02/TCLR11, P03/TI11, P04/INTP110toP07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/INTP121/
SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/SCK1, P32/
TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/SCK3, P112/TCLR14,
P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE, X1
VDD
0.8VDD
0.2VDD
0.8VDD
0.2VDD
Test points
0 V
(b) Pins other than those listed in (a) above
2.4 V
2.2 V
2.2 V
0.8 V
Test points
0.8 V
0.4 V
AC test output test points
2.2 V
0.8 V
2.2 V
0.8 V
Test points
Load condition
DUT
(Device under testing)
CL = 50 pF
Caution In cases where the load capacitance is greater than 50 pF due to the circuit configuration, insert
a buffer or other element to reduce the device’s load capacitance to below 50 pF.
60
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
(1) Clock timing
Parameter
Symbol
<1> tCYX
<2> tWXH
<3> tWXL
<4> tXR
<5> tXF
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
20
200
7
MAX.
Note 1
315
MIN.
15
151
6
MAX.
Note 1
334
X1 input cycle
Direct mode
ns
ns
PLL mode (PLL locked)
Direct mode
PLL mode
X1 input high-level width
X1 input low-level width
X1 input rise time
ns
80
7
60
6
ns
Direct mode
PLL mode
ns
80
60
ns
Direct mode
PLL mode
7
15
7
10
ns
ns
X1 input fall time
Direct mode
PLL mode
7
7
ns
15
10
ns
CPU operating frequency
—
φ
Direct mode
PLL mode
Note 2
Note 3
40
25
Note 2
Note 3
30
33
MHz
MHz
ns
25
33
CLKOUT output cycle
<6> tCYK
<7> tWKH
<8> tWKL
<9> tKR
Note 4
Note 4
CLKOUT input high-level width
CLKOUT input low-level width
CLKOUT input rise time
0.5T – 5
0.5T – 5
0.5T – 5
0.5T – 5
ns
ns
5
5
5
5
ns
CLKOUT input fall time
<10> tKF
<11> tDXK
ns
X1 ↓ → CLKOUT delay time
Direct mode
3
17
3
17
ns
Notes 1. When using A/D converter: 100 ns
When not using A/D converter: DC
2. When using A/D converter: 5 MHz
When not using A/D converter: 0 MHz
3. Free-running oscillation frequency
4. When using A/D converter: 200 ns
When not using A/D converter: DC
Remark T = tCYK
Parameter
Symbol
Conditions
PLL mode
TYP.
Unit
Free-running oscillation frequency
—
φP
1
MHz
<1>
<2>
<3>
X1 (input)
<4>
<11>
<5>
<6>
<11>
<7>
<8>
CLKOUT (output)
<9>
<10>
Data Sheet U13188EJ2V0DS00
61
µPD703003A, 703004A, 703025A
(2) Input waveform
(a) P02/TCLR11, P03/TI11, P04/INTP110 to P07/INTP113, P12/TCLR12, P13/TI12, P14/INTP120, P15/
INTP121/SO2, P16/INTP122/SI2, P17/INTP123/SCK2, P23/RXD0/SI0, P24/SCK0, P26/RXD1/SI1, P27/
SCK1, P32/TCLR32, P33/TI13, P34/INTP130, P35/INTP131/SO3, P36/INTP132/SI3, P37/INTP133/
SCK3, P112/TCLR14, P113/TI14, P114/INTP140 to P117/INTP143, RESET, NMI, MODE
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
MAX.
20
MIN.
MAX.
20
Input rise time
Input fall time
<12> tIR2
<13> tIF2
ns
ns
20
20
VDD
0.8VDD
0.8VDD
Input signal
0.2VDD
<13>
0.2VDD
0 V
<12>
(b) Pins other than those listed in (a) above
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
MAX.
10
MIN.
MAX.
10
Input rise time
Input fall time
<14> tIR1
<15> tIF1
ns
ns
10
10
2.4 V
0.4 V
2.2 V
2.2 V
Input signal
0.8 V
<15>
0.8 V
<14>
62
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
(3) Output waveform (other than CLKOUT)
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
MAX.
10
MIN.
MAX.
10
Output rise time
Output fall time
<16> tOR
<17> tOF
ns
ns
10
10
2.2 V
2.2 V
Output signal
0.8 V
0.8 V
<16>
<17>
(4) Reset timing
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
500
MAX.
MIN.
500
MAX.
RESET high-level width
RESET low-level width
<18> tWRSH
<19> tWRSL
ns
ns
When power supply is ON
and STOP mode has been
released
500 + TOST
500 + TOST
Other than when power
supply is ON and STOP
mode has been released
500
500
ns
Remark TOST: Oscillation stabilization time
<18>
<19>
RESET (input)
Data Sheet U13188EJ2V0DS00
63
µPD703003A, 703004A, 703025A
(5) Read timing (1/2)
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
MAX.
20
MIN.
MAX.
20
Address delay time from CLKOUT↑ <20> tDKA
R/W, UBEN, LBEN delay time from CLKOUT↑ <78> tDKA2
Address float delay time from CLKOUT↑ <21> tFKA
ASTB delay time from CLKOUT↓ <22> tDKST
DSTB delay time from CLKOUT↑ <23> tDKD
Data input setup time (to CLKOUT↑) <24> tSIDK
Data input hold time (from CLKOUT↑) <25> tHKID
WAIT setup time (to CLKOUT↓) <26> tSWTK
WAIT hold time (from CLKOUT↓) <27> tHKWT
Address hold time (from CLKOUT↑) <28> tHKA
Address setup time (to ASTB↓) <29> tSAST
3
3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
–2
13
–2
13
3
15
3
15
3
15
3
15
3
15
3
15
5
5
5
5
5
5
5
5
0
0
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
0.5T – 10
0.5T – 12
0.5T – 10
0.5T – 10
0.5T – 12
0.5T – 10
Address hold time (from ASTB↓) <30> tHSTA
Address float delay time from DSTB↓ <31> tFDA
Data input setup time (to address) <32> tSAID
0
0
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
(2 + n)T – 22
(2 + n)T – 25
(1 + n)T – 20
(1 + n)T – 24
(2 + n)T – 22
(2 + n)T – 25
(1 + n)T – 20
(1 + n)T – 24
Data input setup time (to DSTB↓) <33> tSDID
DSTB↓ delay time from ASTB↓ <34> tDSTD
Data input hold time (from DSTB↑) <35> tHDID
Address output delay time from DSTB↑ <36> tDDA
ASTB↑ delay time from DSTB↑ <37> tDDSTH
ASTB↓ delay time from DSTB↑ <38> tDDSTL
0.5T – 10
0
0.5T – 10
0
(1 + i)T
0.5T – 10
(1.5 + i)T – 10
(1 + n)T – 10
(1 + n)T – 13
T – 10
(1 + i)T
0.5T – 10
(1.5 + i)T – 10
(1 + n)T – 10
(1 + n)T – 13
T – 10
DSTB low-level width
<39> tWDL
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
ASTB high-level width
<40> tWSTH
<41> tSAWT1
WAIT setup time (to address)
n ≥ 1, –40°C ≤ TA ≤ +70°C
n ≥ 1, 70°C < TA ≤ 85°C
n ≥ 1, –40°C ≤ TA ≤ +70°C
n ≥ 1, 70°C < TA ≤ 85°C
n ≥ 1
1.5T – 20
1.5T – 24
(1.5 + n)T – 20
(1.5 + n)T – 24
1.5T – 20
1.5T – 24
(1.5 + n)T – 20
(1.5 + n)T – 24
<42> tSAWT2
WAIT hold time (from address) <43> tHAWT1
<44> tHAWT2
(0.5 + n)T
(1.5 + n)T
(0.5 + n)T
(1.5 + n)T
n ≥ 1
WAIT setup time (to ASTB↓)
<45> tSSTWT1
n ≥ 1, –40°C ≤ TA ≤ +70°C
n ≥ 1, 70°C < TA ≤ 85°C
n ≥ 1
T – 18
T – 20
T – 18
T – 20
<46> tSSTWT2
<47> tHSTWT1
<48> tHSTWT2
(1 + n)T – 15
(1 + n)T – 15
WAIT hold time (from ASTB↓)
Remarks 1. T = tCYK
n ≥ 1
nT
nT
n ≥ 1
(1 + n)T
(1 + n)T
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
3. i indicates the number of idle states (0 or 1) that are inserted after a read cycle.
4. Maintain at least one of the two data input hold times, either tHKID (<25>) or tHDID (<35>).
64
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
(5) Read timing (2/2): 1 wait
T1
T2
TW
T3
CLKOUT (output)
<20>
<28>
A16 to A19 (output)
<78>
R/W (output)
UBEN (output)
LBEN (output)
<32>
<21>
<24>
<25>
AD0 to AD15 (I/O)
A0 to A15 (output)
D0 to D15 (input)
<35>
<22>
<29>
<30>
<22>
ASTB (output)
DSTB (output)
<37>
<36>
<40>
<34> <31>
<23>
<23>
<33>
<38>
<39>
<45> <26>
<47>
<27>
<26>
<27>
<46>
<48>
WAIT (input)
<41>
<43>
<42>
<44>
Remark Broken lines indicate high impedance.
Data Sheet U13188EJ2V0DS00
65
µPD703003A, 703004A, 703025A
(6) Write timing (1/2)
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
MAX.
20
MIN.
MAX.
20
Address delay time from CLKOUT↑ <20> tDKA
R/W, UBEN, LBEN delay time from CLKOUT↑ <78> tDKA2
ASTB delay time from CLKOUT↓ <22> tDKST
DSTB delay time from CLKOUT↑ <23> tDKD
WAIT setup time (to CLKOUT↓) <26> tSWTK
WAIT hold time (from CLKOUT↓) <27> tHKWT
Address hold time (from CLKOUT↑) <28> tHKA
Address setup time (to ASTB↓) <29> tSAST
3
–2
3
–2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
13
13
3
15
3
15
3
15
3
15
5
5
5
5
0
0
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
0.5T – 10
0.5T – 12
0.5T – 10
0.5T – 10
0.5T – 10
(1 + n)T – 10
(1 + n)T – 13
T – 10
0.5T – 10
0.5T – 12
0.5T – 10
0.5T – 10
0.5T – 10
(1 + n)T – 10
(1 + n)T – 13
T – 10
Address hold time (from ASTB↓) <30> tHSTA
DSTB↓ delay time from ASTB↓ <34> tDSTD
ASTB↑ delay time from DSTB↑ <37> tDDSTH
DSTB low-level width
<39> tWDL
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
ASTB high-level width
<40> tWSTH
<41> tSAWT1
WAIT setup time (to address)
n ≥ 1, –40°C ≤ TA ≤ +70°C
n ≥ 1, 70°C < TA ≤ 85°C
n ≥ 1, –40°C ≤ TA ≤ +70°C
n ≥ 1, 70°C < TA ≤ 85°C
n ≥ 1
1.5T – 20
1.5T – 24
(1.5 + n)T – 20
(1.5 + n)T – 24
1.5T – 20
1.5T – 24
(1.5 + n)T – 20
(1.5 + n)T – 24
<42> tSAWT2
WAIT hold time (from address) <43> tHAWT1
<44> tHAWT2
(0.5 + n)T
(1.5 + n)T
(0.5 + n)T
(1.5 + n)T
n ≥ 1
WAIT setup time (to ASTB↓)
<45> tSSTWT1
n ≥ 1, –40°C ≤ TA ≤ +70°C
n ≥ 1, 70°C < TA ≤ 85°C
n ≥ 1
T – 18
T – 20
T – 18
T – 20
<46> tSSTWT2
<47> tHSTWT1
<48> tHSTWT2
<49> tDKOD
(1 + n)T – 15
(1 + n)T – 15
WAIT hold time (from ASTB↓)
n ≥ 1
nT
nT
n ≥ 1
(1 + n)T
(1 + n)T
Data output delay time from
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
20
23
10
20
23
10
CLKOUT↑
Data output delay time from DSTB↓ <50> tDDOD
Data output hold time (from CLKOUT↑) <51> tHKOD
Data output setup time (to DSTB↑) <52> tSODD
Data output hold time (from DSTB↑) <53> tHDOD
0
0
(1 + n)T – 15
T – 10
(1 + n)T – 15
T – 10
Remarks 1. T = tCYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
66
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
(6) Write timing (2/2): 1 wait
T1
T2
TW
T3
CLKOUT (output)
<20>
<28>
A16 to A19 (output)
<78>
R/W (output)
UBEN (output)
LBEN (output)
<49>
<51>
AD0 to AD15 (I/O)
A0 to A15 (output)
D0 to D15 (output)
<22>
<29>
<30>
<22>
ASTB (output)
<23>
<37>
<53>
<23>
<50>
<40>
<34>
<52>
DSTB (output)
<39>
<45> <26>
<47>
<46>
<48>
<27>
<26>
<27>
WAIT (input)
<41>
<43>
<42>
<44>
Remark Broken lines indicate high impedance.
Data Sheet U13188EJ2V0DS00
67
µPD703003A, 703004A, 703025A
(7) Bus hold timing (1/2)
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Units
MIN.
MAX.
MIN.
MAX.
HLDRQ setup time (to CLKOUT↓) <54> tSHQK
HLDRQ hold time (from CLKOUT↓) <55> tHKHQ
HLDAK delay time from CLKOUT↑ <56> tDKHA
5
5
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
20
20
HLDRQ high-level width
HLDAK low-level width
<57> tWHQH
<58> tWHAL
T + 10
T – 10
T – 12
T + 10
T – 10
T – 12
–40°C ≤ TA ≤ +70°C
70°C < TA ≤ 85°C
Bus float delay time from CLKOUT↑ <59> tDKF
Bus output delay time from HLDAK↑ <60> tDHAC
HLDAK↓ delay time from HLDRQ↓ <61> tDHQHA1
HLDAK↑ delay time from HLDRQ↑ <62> tDHQHA2
20
20
–3
–3
(2n + 7.5)T + 20
(2n + 7.5)T + 20
0.5T 1.5T + 20 0.5T 1.5T + 20
Remarks 1. T = tCYK
2. n indicates the number of wait clocks that are inserted during a bus cycle. The sampling timing may
vary when using the programmable wait insertion function.
68
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
(7) Bus hold timing (2/2)
TH
TH
TH
TH
TI
CLKOUT (output)
<54>
<54><55>
<57>
HLDRQ (input)
<56>
<56>
<61>
<62>
HLDAK (output)
<58>
<60>
<59>
A16 to A19 (output)Note
D0 to D15
(input or output)
AD0 to AD15 (I/O)
ASTB (output)
DSTB (output)
R/W (output)
Note UBEN (output), LBEN (output)
Remark Broken lines indicate high impedance.
Data Sheet U13188EJ2V0DS00
69
µPD703003A, 703004A, 703025A
(8) Interrupt timing
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
500
500
MAX.
MIN.
500
MAX.
NMI high-level width
NMI low-level width
INTPn high-level width
<63> tWNIH
<64> tWNIL
<65> tWITH
ns
ns
ns
500
n = 110 to 113, 120 to 123, 3T + 10
130 to 133, 140 to 143
3T + 10
INTPn low-level width
<66> tWITL
n = 110 to 113, 120 to 123, 3T + 10
130 to 133, 140 to 143
3T + 10
ns
Remark T = tCYK
<63>
<64>
NMI (input)
<65>
<66>
INTPn (input)
Remark n = 110 to 113, 120 to 123, 130 to 133, 140 to 143
70
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
[MEMO]
Data Sheet U13188EJ2V0DS00
71
µPD703003A, 703004A, 703025A
(9) CSI timing (1/2)
(a) Master mode
(i) Timing of CSI0 to CSI2
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
160
MAX.
MIN.
120
MAX.
SCKn cycle
<67> tCYSK1
<68> tWSKH1
<69> tWSKL1
<70> tSSISK1
<71> tHSKSI1
Output
Output
Output
ns
ns
ns
ns
ns
ns
ns
SCKn high-level width
0.5tCYSK1 – 20
0.5tCYSK1 – 20
30
0.5tCYSK1 – 20
0.5tCYSK1 – 20
30
SCKn low-level width
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↑)
0
0
SOn output delay time (from SCKn↓) <72> tDSKSO1
SOn output hold time (from SCKn↑) <73> tHSKSO1
18
18
0.5tCYSK1 – 5
0.5tCYSK1 – 5
Remark n = 0 to 2
(ii) Timing of CSI3
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
500
MAX.
MIN.
500
MAX.
SCK3 cycle
<67> tCYSK3
<68> tWSKH3
<69> tWSKL3
<70> tSSISK3
<71> tHSKSI3
Output
Output
Output
RL = 1.5 kΩ
CL = 50 pF
ns
ns
ns
ns
ns
ns
ns
SCK3 high-level width
0.5tCYSK3 – 70
0.5tCYSK3 – 70
100
0.5tCYSK3 – 70
0.5tCYSK3 – 70
100
SCK3 low-level width
SI3 setup time (to SCK3↑)
SI3 hold time (from SCK3↑)
50
50
SO3 output delay time (from SCK3↓) <72> tDSKSO3
SO3 output hold time (from SCK3↑) <73> tHSKSO3
RL = 1.5 kΩ
150
150
CL = 50 pF
0.5tCYSK3 – 5
0.5tCYSK3 – 5
Remark RL is the load resistance and CL is the load capacitance of the output line for SCK3 and SO3.
(b) Slave mode
(i) Timing of CSI0 to CSI2
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
160
50
MAX.
MIN.
120
30
MAX.
SCKn cycle
<67> tCYSK2
<68> tWSKH2
<69> tWSKL2
<70> tSSISK2
<71> tHSKSI2
Input
Input
Input
ns
ns
ns
ns
ns
ns
ns
SCKn high-level width
SCKn low-level width
50
30
SIn setup time (to SCKn↑)
SIn hold time (from SCKn↑)
10
10
10
10
SOn output delay time (from SCKn↓) <72> tDSKSO2
SOn output hold time (from SCKn↑) <73> tHSKSO2
30
30
tWSKH2
tWSKH2
Remark n = 0 to 2
72
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
(9) CSI timing (2/2)
(b) Slave mode
(ii) Timing of CSI3
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
500
180
180
100
50
MAX.
MIN.
500
180
180
100
50
MAX.
SCK3 cycle
<67> tCYSK4
<68> tWSKH4
<69> tWSKL4
<70> tSSISK4
<71> tHSKSI4
Input
Input
Input
ns
ns
ns
ns
ns
ns
ns
SCK3 high-level width
SCK3 low-level width
SI3 setup time (to SCK3↑)
SI3 hold time (from SCK3↑)
SO3 output delay time (from SCK3↓) <72> tDSKSO4
SO3 output hold time (from SCK3↑) <73> tHSKSO4
RL = 1.5 kΩ
150
150
CL = 50 pF
tWSKH4
tWSKH4
Remark RL is the load resistance and CL is the load capacitance of the output line for SCK3 and SO3.
<67>
<69>
<68>
SCKn (I/O)
<70>
<71>
SIn (Input)
Input data
<72>
<73>
SOn (output)
Output data
Remarks 1. Broken lines indicate high impedance.
2. n = 0 to 3
Data Sheet U13188EJ2V0DS00
73
µPD703003A, 703004A, 703025A
(10) RPU timing
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
MAX.
MIN.
MAX.
TI1n high-level width
TI1n low-level width
<74> tWTIH
<75> tWTIL
<76> tWTCH
<77> tWTCL
3T + 10
3T + 10
3T + 10
3T + 10
3T + 10
3T + 10
3T + 10
3T + 10
ns
ns
ns
ns
TCLR1n high-level width
TCLR1n low-level width
Remark T = tCYK
<74>
<75>
TI1n (input)
<76>
<77>
TCLR1n (input)
Remark n = 1 to 4
74
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
Resolution
—
—
10
10
bit
Note 1
Total error
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
±0.4
±0.7
±1/2
±0.4 %FSR
±0.7 %FSR
—
Quantization error
Conversion time
—
±1/2
LSB
tCYK
tCYK
tCYK
tCYK
LSB
LSB
LSB
LSB
LSB
LSB
V
tCONV
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
4.5 V ≤ AVREF1 ≤ AVDD
3.5 V ≤ AVREF1 ≤ AVDD
48
48
8
60
60
10
10
Sampling time
tSAMP
8
Note 1
Zero scale error
—
—
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±3.5
±4.5
±2.5
±4.5
±2.5
±4.5
±1.5
±1.5
±1.5
±1.5
±1.5
±1.5
±3.5
±4.5
±2.5
±4.5
±2.5
±4.5
Note 1
Full scale error
Nonlinearity error
Analog input
—
—
Note 1
—
—
VIAN
–0.3
3.5
AVDD
–0.3
3.5
AVDD
Note 2
voltage
+0.3
+0.3
Reference voltage
AVREF1 current
AVREF1
AIREF1
AIDD
AVDD
3.0
AVDD
3.0
V
1.2
2.3
1.2
2.3
mA
mA
AVDD power supply
current
6.0
6.0
Notes 1. Exclude quantization error.
2. When VIAN = 0, the conversion result becomes 000H.
When 0 < VIAN < AVREF1, conversion has 10-bit resolution.
When AVREF1 ≤ VIAN ≤ AVDD, the conversion result becomes 3FFH.
Data Sheet U13188EJ2V0DS00
75
µPD703003A, 703004A, 703025A
D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)
Parameter
Symbol
Conditions
25-MHz Version
33-MHz Version
Unit
MIN.
TYP.
MAX.
MIN.
TYP.
MAX.
Resolution
—
—
8
8
bit
%
Total error
Load condition: 2 MΩ, 30 pF
AVREF2 = VDD
0.8
0.8
AVREF3 = 0
—
—
—
Load condition: 2 MΩ, 30 pF
AVREF2 = 0.75VDD
1.0
0.6
0.8
10
1.0
0.6
0.8
10
%
%
%
AVREF3 = 0.25VDD
Load condition: 4 MΩ, 30 pF
AVREF2 = VDD
AVREF3 = 0
Load condition: 4 MΩ, 30 pF
AVREF2 = 0.75VDD
AVREF3 = 0.25VDD
Settling time
—
Load condition: 2 MΩ, 30 pF
µs
kΩ
V
Output resistance
AVREF2 input voltage
AVREF3 input voltage
RO
8
4
8
4
AVREF2
AVREF3
0.75VDD
VDD
0.75VDD
VDD
0
2
0.25VDD
0
2
0.25VDD
V
AVREF2 to AVREF3
resistance value
RAIREF DACS0, DACS1 = 55H
kΩ
76
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
17. PACKAGE DRAWINGS
100 PIN PLASTIC LQFP (FINE PITCH) (14×14)
A
B
75
76
51
50
detail of lead end
S
C
D
R
Q
100
1
26
25
F
M
H
I
J
G
K
L
P
M
N
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.08 mm (0.003 inch) of
its true position (T.P.) at maximum material condition.
A
B
16.00±0.20
14.00±0.20
0.630±0.008
+0.009
0.551
–0.008
+0.009
0.551
C
D
14.00±0.20
16.00±0.20
–0.008
0.630±0.008
F
1.00
1.00
0.039
0.039
G
+0.05
0.22
H
0.009±0.002
–0.04
I
0.08
0.003
J
0.50 (T.P.)
0.020 (T.P.)
+0.009
0.039
K
L
1.00±0.20
0.50±0.20
–0.008
+0.008
0.020
–0.009
+0.03
0.17
+0.001
0.007
M
–0.07
–0.003
N
P
Q
0.08
0.003
1.40±0.05
0.10±0.05
0.055±0.002
0.004±0.002
+7°
3°
+7°
3°
R
S
–3°
–3°
1.60 MAX.
0.063 MAX.
S100GC-50-8EU
Data Sheet U13188EJ2V0DS00
77
µPD703003A, 703004A, 703025A
18. RECOMMENDED SOLDERING CONDITIONS
The µPD703003A, 703004A, and 703025A should be soldered and mounted under the following recommended
conditions.
For the details of the recommended soldering conditions, refer to the document Semiconductor Device Mounting
Technology Manual (C10535E).
For soldering methods and conditions other than those recommended below, contact your NEC sales represen-
tatives.
Table 18-1. Soldering Conditions
(1) µPD703003AGC-xx-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
µPD703004AGC-xx-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
Soldering Method
Soldering Conditions
Recommended
Condition Symbol
Package peak temperature: 235°C, Time: 30 sec. Max. (at 210°C or higher),
Infrared reflow
IR35-107-2
VP15-107-2
—
Note
Count: two times or less, Exposure limit: 7 days
(after that, prebake at
125°C for 10 hours)
Package peak temperature: 215°C, Time: 40 sec. Max. (at 200°C or higher),
VPS
Note
Count: two times or less, Exposure limit: 7 days
(after that, prebake at
125°C for 10 hours)
Pin temperature: 300°C Max., Time 3 sec. Max. (per pin row)
Partial heating
Note After opening a dry pack, store it at 25°C or less and 65% RH or less for the allowable storage period.
Caution Do not use different soldering methods together (except for partial heating).
(2) µPD703025AGC-xx-xxx-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14 mm)
Undefined
78
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
[MEMO]
Data Sheet U13188EJ2V0DS00
79
µPD703003A, 703004A, 703025A
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
80
Data Sheet U13188EJ2V0DS00
µPD703003A, 703004A, 703025A
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 65-253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
NEC Electronics (Germany) GmbH
Scandinavia Office
Tel: 02-66 75 41
Fax: 02-2719-5951
Taeby, Sweden
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Fax: 08-63 80 388
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 55-11-6465-6810
Fax: 55-11-6465-6829
J99.1
Data Sheet U13188EJ2V0DS00
81
µPD703003A, 703004A, 703025A
RELATED DOCUMENTS µPD703003 Data Sheet (U12261E)
µPD70F3003 Data Sheet (U12036E)
µPD70F3003A, 70F3025A Data Sheet (U13189E)
V850 Family Instruction Table (U10229J)Note
Note Japanese version
The related documents indicated in this publication may include preliminary versions. However, preliminary versions
are not marked as such.
V850 Family and V853 are trademarks of NEC Corporation.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
• The information in this document is subject to change without notice. Before using this document, please
confirm that this is the latest version.
• No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in
this document.
• NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights
or other intellectual property rights of NEC Corporation or others.
• Descriptions of circuits, software, and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these circuits,
software, and information in the design of the customer's equipment shall be done under the full responsibility
of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third
parties arising from the use of these circuits, software, and information.
• While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
• NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a
customer designated “quality assurance program“ for a specific application. The recommended applications of
a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device
before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support
systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
M7 98.8
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