UPD703032BY [ETC]
V850 Series Pamphlet | Pamphlet[02/2002] ; V850系列小册子|小册子08/2004 ]
| 型号： | UPD703032BY |
| 厂家： | 
ETC |
| 描述： | V850 Series Pamphlet | Pamphlet[02/2002]
|
| 文件： | 总64页 (文件大小：5537K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
•
2002 February
Inverter-type air conditioners
The V850 SeriesTM of embedded microcontrollers
answers diversified needs in all kinds of application
systems. It realizes lower power consumption and
noise while achieving higher performance and
multiple functions. Consisting of a rich lineup, the
V850 Series offers optimum solutions for next-
generation embedded systems.
Digital video cameras
Automotive electronics
DVD players
Digital still cameras
Storage devices
Fax machines
Cellular phones
Pamphlet U15412EJ1V0PF
2
Single-lens reflex cameras
Network modems
Microwave ranges
PDA
Washing machines
Digital video recorders
Printers
Home audio
Vending machines
Electronic music instruments
Car audio
Car AV centers
Pamphlet U15412EJ1V0PF
3
V850 POSITION
NEC Microcontroller Lineup
V
SeriesTM
R
64-bit MIPS RISC Microprocessors
V
R
4x00 / 5x00
V
R
1x000
V850E/Mxx
high-end lineup
V850 Series
32-bit RISC microcontrollers
V850, V850ES, V850E
ASSP lineup
V850ES, V850/Sxx
low-end lineup
Data processing
78K Series
8/16-bit microcontrollers
System control
78K4
Mid-range
78K0
16-bit
microcontrollers
High-End
8-bit
78K0S
microcontrollers
Low-End
75X/XL
17K
8-bit
16-bit
32-bit
Price
V850 ROADMAP
V850E2 core 200 to 266 MHz @ 0.13 µm or lower
V850E2/xxx
External 32-bit bus
80 to 100 MHz
High-end lineup
SDRAM compatible
40 to 50 MHz
V850E/Mxx
V850E1 core
124 MIPS
/100 MHz
Enhanced MEMC
33 to 40 MHz
V850E/MAx
@ 0.35 µm or lower
V850E/MSx
33 MHz with
on-chip flash memory
V853TM
V850
V850E
ASSP lineup
ASSP lineup
V850/Sxx
low-power lineup
V850ES
low-power lineup
V850 core
38 MIPS
/33 MHz
@ 0.8 µm or lower
Low-end lineup
: Under development
Pamphlet U15412EJ1V0PF
4
INDEX
5KEYS V850
06
1 8
27
32
36
38
42
53
61
Architecture
Variety of Peripheral Functions
Low Power & Low Noise
Middleware
Flash Memory Microcontrollers
Functional Outline
Comfortable Development Environment
Information
Pamphlet U15412EJ1V0PF
5
5KEYS V850
Processor products
Data processing
V850E2
High Performance
100MHz
50MHz
Applicable down to
middle-range models
32-bit
microcontrollers of
other companies
V850E1
Scalable coverage of 20 MHz to over 100 MHz
ꢀ 3 to 4 times higher performance at same frequency
compared to 16-bit microcontrollers
33MHz
V850
ꢀ V850, V850ES, and V850E1 cores are upward
compatible at object level.
3-4 times higher
performance Applicable
up to high-end models
ꢀ V850 Series covers a broad range from middle to
high-end market with a single instruction set
16-bit
microcontrollers of
other companies
20MHz
V850ES
V850
System control
: Under development
V850E/Mxx
Automotive
OA
High-end lineup
Sophisticated
memory I/F
Extensive Product
Lineup
V850E/xxx
V850E1 core
V850ES core
V850ES/xxx
Industrial
Communications
V850/xxx
On-chip
dedicated
hardware
From low-end/high-end general-purpose
products all the way to ASSP lineup
ASSP lineup
V850 core
ꢀ
ꢀ
ꢀ
Low-end lineup designed for 8/16-bit market
(V850ES, V850/Sxx)
Low power,
low noise,
expanded
internal memory
High-end lineup with on-chip MEMC, DMA,
that pursues high performance (V850E)
ASSP lineup with on-chip dedicated hardware
optimized for various fields (V850E, V850ES, V850/Sxx)
Information
appliances
V850ES/xxx
V850/Sxx
Low-end lineup
Consumer
electronics
Amusement machines
FAX
Portable terminals
Electronic dictionaries
DSC
Additional Functions
Handwriting
recognition
JBIG
ADPCM
MH/MR/MMR
TTS
Toys
Car audio
Video processing
JPEG
Human interface
Enriched middleware lineup
ꢀ Rich lineup of middleware related to video, audio,
networks, etc., optimized for the V850
Speech
recognition
Middleware
Home appliances
AV equipment
Phones
ꢀ Realization of peripheral functions through V850 +
middleware combination
Browser
TCP/IP
Network
Java
Shorter development time, lower system cost
Pamphlet U15412EJ1V0PF
6
System
Process
Design environment
System Integration
CPU DSP
Analog
IP
Memory Flash
Logic
DRAM
High-performance CPU cores
ꢀ By meeting the five conditions consisting of
leading-edge process technology,
middleware
Middleware
IP cores
high-performance CPU cores, a rich lineup of IP cores,
a top-down design environment, and a flexible application
environment, the V850 Series offers optimum
system-on-chip solutions.
CPU Core Lineup
700
V850E3
500
0.1µm
process
V850E3/xxx
V850E3/xxx
Nx85E3
350MHz
xxx
300
200
V850E2
Nx85E2
260MHz
0.13µm
process
Nx85E2
200MHz
V850E2/xxx
V850E2/xxx
xxx
V850E1
Nx85E
100
66
100MHz
0.25µm
process
V850E/MAx
Nx85E
66MHz
V850E/MA1TM MA2TM
0.35µm
process
V850E/IA1TM
IA2TM
33
V850
2000
2005
Utilization of
existing functions
Improved operability
78K Development
Environment
V850 Development
Environment
Accessible Development
PM
PM
Project Manager
Project Manager
Enviroment
V850 products
Realize
a sophisticated
and powerful
development
environment
through:
Higher versatility
CC (Compiler)
CA (Compiler)
Rich lineup and high operability
ꢀ Inherits operability of 78K Series.
ꢀ Shorter software development TAT through
superior operability and sophisticated development
environment
RX (Real-time OS)
RX (Real-time OS)
Higher performance
Debugging support
+ RD (Task debugger)
+ AZ (Analyzer)
•High performance
•General-purpose
registers
•Large-capacity
memory
Debugging support
Improved operability
SM (Simulator)
ID (Debugger)
SM (Simulator)
ID (Debugger)
ꢀ Easy C-language support through
high-performance CPUs and real-time OS
embedding possible
IE
IE
Support of high speed
(In-circuit emulator)
(In-circuit emulator)
Pamphlet U15412EJ1V0PF
7
V850E Product Development Concept
Pursuit of high performance
High-performance CPU using V850E core
ꢀ10% higher performance than V850 CPU at same frequency
ꢀ10% to 20% higher code efficiency than V850 CPU through addition of C-compatible instructions
ꢀUpward compatibility at object level with V850 CPU cores
Enhanced external bus performance
On-chip direct interface for various memories
ꢀSRAM, page ROM, EDO DRAM, synchronous DRAM, etc.
On-chip DMA controller
ꢀRealization of voluminous data processing and high-performance control on one chip
In mass production
[Low Voltage]
External 32-bit bus
Under development
In planning
Higher performance
More compact
V850E/Mxx
80 to 100MHz
144-pin LQFP/161-pin FBGA
V850E/MA1
On-chip SDRAM controller
ROMless/4 KB to 256 KB/10 KB
On-chip 256 KB flash memory
50 MHz @ 3.0 to 3.6 V
100-pin LQFP
Higher
performance
V850E/MA2
(5 V tolerance)
On-chip SDRAM controller
ROMless/4 KB
40 MHz @ 3.0 to 3.6 V
144-pin LQFP/157-pin FBGA (3.3 V only)
V850E/MS1TM(3.3V)
[
]
5 V
144-pin LQFP
100-pin LQFP
V850E/MS1(5V)
On-chip DRAM controller
ROMless/4 KB to 128 KB/4 KB
On-chip 128 KB flash memory
33 MHz @ 3.0 to 3.6 V
33 MHz @ 3.0 to 3.6 V/
V850E/IA1
On-chip inverter and timer
256 KB/10 KB
On-chip 256 KB flash memory
50 MHz @ 3.0 to 3.6 V/
4.5 to 5.5 V (external)
More compact
V850E/IA2
On-chip inverter and timer
128KB/6KB
On-chip 128 KB flash memory
40 MHz @4.5 to 5.5V
Higher performance
Enhanced
peripheral
functions
4.5 to 5.5 V (external) 100-pin LQFP
V850E/MS2TM
ROMless/4 KB
33 MHz @ 3.0 to 3.6 V/
4.5 to 5.5 V (external)
Higher performance
Enhanced peripheral functions
100-pin LQFP
Higher
performance
V853
96KB/4KB to 256KB/8KB
On-chip 128 KB, 256 KB flash memory
33 MHz @4.5 to 5.5V
Higher
performance
16-bit V SeriesTM
78K/III
Pamphlet U15412EJ1V0PF
8
V850E Product Features
V850E/MS1
Performance of 43 MIPS @ 33 MHz
ꢀ
ꢀ
ꢀ
On-chip memory controllers for EDO DRAM, etc.
Lineup of products for 5 V systems and 3.3 V systems
V850E/MS2
Support of 5 V interface enables connection of existing external I/Os
ꢀ
Contributes to higher cost performance of sets through use of V850E CPU architecture
ꢀ
V850E/MA1
High performance of 62 MIPS @ 50 MHz
ꢀ
ꢀ
ꢀ
On-chip memory controllers for SDRAM, etc.
Various peripheral functions such as timer, serial interface, and A/D converter
V850E/MA2
On-chip SDRAM controller
ꢀ
Contributes to smaller applications, lighter weight, and higher cost performance through
ꢀ
use of 14 × 14 mm, 100-pin package
V850E/IA1
On-chip 3-phase sine wave PWM timer, 2-phase encoder input up/down counter,
ꢀ
A/D converter, 2-system motor driving enabled through inverter control
6-system serial I/F including FCAN for automotive LAN (Ver. 2.0 Part B compliant)
V850E/IA2
2-system motor driving enabled through on-chip peripheral functions almost the
ꢀ
same as those of V850E/IA1
System can be configured with single 5 V power supply thanks to on-chip regulator
ꢀ
Pamphlet U15412EJ1V0PF
9
V850E Product Application Examples
System bus
Optical system
V850E/MS1
Document
Image processing
Motor
driver
ROM:
128 KB
S/H
A/D
RPU
PORT
INTC
DMA
SIO
Shading
Compensation/
binarization
CCD
RAM
4 KB
MH/MR/MMR
JBIG
Motor
Memory
Operation
panel
SDRM
CPU
ROM
RAM
Communication
For storing image data
system
F A X
Telephone network
AFE
NCU
Application example using V850E/MS1
Printing system Paper
Watch
Image
processing
Printer
engine
Real-time
clock
Program ROM
Font ROM
DRAM
SRAM
ASIC
ASIC
CR motor
PF motor
IEEE1284
IEEE1394
USB
Engine
controller
Interface
controller
V850E/MA1
Printer
Color head
Black head
Application example using V850E/MA1
LAN
Operation panel
AC-3
2ch
decoder
DAC
Pick up
Speech
output
DRAM
DRAM
RF-Amp
Driver
ADC
NTSC/PAL
Stream
management
A/V
separation
MPEG2
decoder
Video
encoder
Error
correction
3ch
DAC
Servo processor
CPUI/F
Image
output
GUI
D V D P l a y e r
Mechanical control
microcontroller
Application example using V850E/MA2
Display
Key input
System control microcontroller V850E/MA2
Pamphlet U15412EJ1V0PF
10
V850ES, V850/Sxx Product Development Concept
High Performance
3 to 4 times higher performance compared to 16-bit CISC microcontrollers
Middleware support (JPEG, speech recognition, etc.)
ꢁ
ꢁ
Low noise & low power
Optimum design for maximum operating frequency of 20 MHz
Thorough EMI noise countermeasures
ꢁ
ꢁ
Low-voltage support
Realization of 2.2 V low voltage operation (V850ES/SA2, SA3)
ꢁ
Variation in memory and I/O
Various memory capacities (ROM: 64 KB to 512 KB, RAM: 4 KB to 24 KB)
Various ASSPs (automotive bus support (IEBusTM, CAN), servo timer, etc.)
Various packages (100-pin to 180-pin)
ꢁ
ꢁ
ꢁ
Peripheral functions inherited from 78K Series
Standard peripheral functions of 78K Series (timer, serial interface, etc.)
Pursuit of high cost performance
Designed for 8/16-bit application market
ꢁ
ꢁ
ꢁ
[Low Voltage]
176-pin LQFP/180-pin FBGA
[5 V]
In mass
production
144-pin LQFP
V850/SV1TM
Under
development
V850/SC1,2,3TM
On-chip servo timer
192 KB/8 KB to 384 KB/16 KB
On-chip 256 KB, 384 KB flash memory
16 MHz @2.7 to 3.6 V
Enhanced
peripheral
functions
Enhanced
peripheral
functions
On-chip IEBus (SC2), on-chip FCAN (SC3)
256 KB/20 KB to 512 KB/24 KB
On-chip 512 KB flash memory
20 MHz@4.5 to 5.5V
20 MHz @3.1 to 3.6 V
100-pin QFP/LQFP
100-pin LQFP/121-pin FBGA
Enhanced peripheral functions
100-pin LQFP
V850/SB1,2TM
V850/SA1TM
Support of low voltage
100-pin LQFP/121-pin FBGA
On-chip IEBus (SB2)
64 KB/4 KB to 256 KB/8 KB
On-chip 128 KB, 256 KB flash memory
17 MHz @2.7 to 3.6 V
128 KB/12 KB to 512 KB/24 KB
On-chip 256 KB, 512 KB flash memory
20 MHz@4.5 to 5.5V
20 MHz @3.0 to 3.6 V
V850/SF1TM
V850ES/SA2,3TM
On-chip FCAN
256 KB/16 KB
256 KB/16 KB
On-chip 256 KB flash memory
13.5 MHz @2.2 to 2.7 V
17 MHz @2.3 to 2.7 V
On-chip 256 KB flash memory
16 MHz@4.5 to 5.5V
Higher
3 V performance
78K/IV
5 V higher performance
78K/0
Pamphlet U15412EJ1V0PF
11
V850ES, V850/Sxx Product Features
V850ES/SA2, SA3
Ultra-low power consumption/high-speed operation (30 mW @ 2.5 V, 17 MHz)
Low-voltage operation of 2.2 V Min. (1.8 V under planning)
On-chip single power supply flash memory
ꢀ
ꢀ
ꢀ
ꢀ
On-chip V850ES core
V850/SA1
Ultra-low power consumption (66 mW (20 MHz @ 3.3 V, mask ROM version, Typ.))
Rich memory lineup (ROM 64 KB to 256 KB/RAM 4 KB to 8 KB)
Support of CSP package (121-pin FBGA)
ꢀ
ꢀ
ꢀ
V850/SV1
Various on-chip peripheral functions including servo timer
Rich memory lineup (ROM 192 KB to 384 KB/RAM 8 KB to 16 KB)
Support of high-pin-count CSP package (180-pin FBGA)
ASSP lineup for DVC
ꢀ
ꢀ
ꢀ
ꢀ
V850/SB1, SB2
Low EMI noise
On-chip large-capacity memory (512 KB/24 KB Max.)
Rich memory lineup (ROM 128 KB to 512 KB/RAM 12 KB to 24 KB)
Automotive bus support (V850/SB2 only)
ꢀ
ꢀ
ꢀ
ꢀ
V850/SF1
Low EMI noise
On-chip FCAN controller (2 ch Max.)
ASSP lineup for car audio
ꢀ
ꢀ
ꢀ
V850/SC1, SC2, SC3
Low EMI noise
ꢀ
Enhanced peripheral functions for V850/SB1, SB2 (100-pin 144-pin)
Automotive bus support (IEBus, FCAN)
ꢀ
ꢀ
Pamphlet U15412EJ1V0PF
12
V850ES, V850/Sxx Product Features
ꢂ V850ES, V850/Sxx Series power performance ꢂ
mA/MIPS
10
9.2mA/MIPS
8-bit CISC
Low current consumption: 1/5th that of
16-bit CISC with equivalent performance
7.3mA/MIPS
16-bit CISC
5
1.1mA/MIPS
V850/SV1
1.1mA/MIPS
V850/SB1
V850/SA1
0.9mA/MIPS
V850ES/SA2, 3*
0.7mA/MIPS
0
:Under development
ꢂ Smooth transition from CISC to RISC ꢂ
CISC-like use enabled
• Bit manipulation instructions
(SET1, CLR1, NOT1, TST1)
• Multi-status flags
On-chip standard peripheral
functions of 78K Series
• Timers (8-bit, 16-bit)
• Serial interface (3-wire CSI, UART)
• Watchdog timer, etc.
High code efficiency
• Equals CISC code efficiency (1.0 to 1.2)
• High-level language (C language)
programming supported
• 32-bit barrel shifter
ꢂ Comparison of peripheral functions of 78K Series and V850/Sxx products ꢂ
78K/IV Series
PD78421x
V850 Series
V850/SV1
78K/0 Series
PD78003x
V850/SA1
V850/SB1,2
V850/SF1
V850/SC1,2,3
16-bit timer
TM0
8-bit timer
TM5
Serial interface (CSI)
Serial interface (UART)
I2C interface
SIO3
UART0
IIC0
UART3
AD converter
ADCTL0
Real-time output
Watchdog timer
Watch timer
RT00
WDT
WT
Separate specifications WDT
WTN0
KR0
Key return function
Separate specifications
:Listed on left
:Not provided
Pamphlet U15412EJ1V0PF
13
V850 ASSP Lineup
Inverter Control
DVC
V850E/IA1
High performance
V850E/IA2
For general use
V850/SAx
For camera control
V850/SV1
For servo control
Car Audio
Automotive Electronics
V850/Sxx
Standard product
V850/SB2, SC2
IEBus
V850/SF1, SC3
CAN bus
V850/xxx
ABS
V850/xxx
Air bag
V850/xxx
Dashboard
ꢁV850/SV1 System Block Diagram (DVC)
ꢁV850E/IA2 inverter air conditioner application example
Power supply
Indoor unit
V850E/IA2
Sensors
block
LCD
signal
CDS
+AGC
10-bit
ADC
Field
memory
3CCD
Finder
Head
DRAM
processing
Error
correction
(modem)
Camera
signal
control
Video
Memory
control
Head
amp
compression/
decompression
OSD
Vertical
drive
Drive SG
Sync SG
Power module
Power module
Motor
drive
Motor
drive
V850/SV1
ADC
Display
key
operation
Error
correction
Microphone
Mic/amp
Compressor
motor
Fan
motor
ꢁV850/SB2 System Block Diagram (Car Audio)
FM/AM tuner block
MD deck block
CD deck block
Changer connector
IEBus
AUX connector
Audio switch
PLL
AMP
DSP
Power supply block
Front panel block
V850/SB2
FLT driver
Display block VFD
FCAN driver
Key microcontroller
Key matrix
Remote control receiver
Pamphlet U15412EJ1V0PF
14
Memory Lineup
Mask products
Flash memory products
ROM Size
(Bytes)
V850/SC3
V850/SC3
V850/SC2
V850/SC2
V850/SC1
V850/SC1
V850/SB2
V850/SB2
V850/SB1
V850/SB1
512K
V850/SV1
V850/SV1
V850/SB2
*
*
V850/SB2
*
384K
V850/SB1
V850/SB1
*
V850ES/SA3*
V850ES/SA3*
V850ES/SA2*
V850ES/SA2*
V850/SV1
V850/SV1
V850/SF1
256K
V853
V850/SF1
V853
V850E/IA1
V850E/IA1
V850E/MA1
V850E/MA1
V850/SB2
V850/SB2
V850/SB1
V850/SB1
V850/SV1
V850/SA1
V850/SA1
V850/SV1
192K
128K
V853
V853
V850/SA1
V850/SA1
V850E/MA1
V850E/MS1
V850E/MS1
V850E/IA2
V850E/IA2
V850/SB2
*
V850/SB2
*
V850/SB1
*
V850E/MA1
V850/SB1
*
V853
96K
64K
V850E/MS1
V850/SA1
V850E/MS1
V850E/MS2
V850E/MA1
V850E/MA2
ROMless
4K
6K
8K
10K
12K
16K
20K
24K
RAM Size (Bytes)
*
: Under development
Pamphlet U15412EJ1V0PF
15
Package Lineup
Package Name
Applicable Products
100-pin plastic QFP (14 × 20 mm)
100-pin plastic LQFP (14 × 14 mm)
144-pin plastic LQFP (20 × 20 mm)
176-pin plastic LQFP (24 × 24 mm)
121-pin plastic FBGA (12 × 12 mm)
157-pin plastic FBGA (14 × 14 mm)
161-pin plastic FBGA (13 × 13 mm)
180-pin plastic FBGA (13 × 13 mm)
V850/SB1, SB2, SF1
V850E/MA2, MS2, IA2, V850ES/SA2, V850/SA1, SB1, SB2, SF1, V853
V850E/MA1, IA1, MS1, V850/SC1, SC2, SC3
V850/SV1
V850ES/SA3, V850/SA1
V850E/MS1
V850E/MA1
V850/SV1
QFP package photos
ꢀ
100-pin plastic QFP
100-pin plastic LQFP
144-pin plastic LQFP
176-pin plastic LQFP
0.65 mm pitch, 14 × 20 mm, 3.0 mm thick
0.5 mm pitch, 14 × 14 mm, 1.4 mm thick
0.5 mm pitch, 20 × 20 mm, 1.4 mm thick
0.5 mm pitch, 24 × 24 mm, 1.4 mm thick
FBGA package photos
ꢀ
161-pin plastic FBGA
121-pin plastic FBGA
157-pin plastic FBGA
180-pin plastic FBGA
0.8 mm pitch, 13 × 13 mm, 1.48 mm thick
0.8 mm pitch, 12 × 12 mm, 1.48 mm thick
0.8 mm pitch, 14 × 14 mm, 1.31 mm thick
0.8 mm pitch, 13 × 13 mm, 1.48 mm thick
The Eco Symbol mark is applied to products that comply with NEC’s environmental standard, which is one of the world’s
toughest. Such products are antimony-free and use smaller amounts of halogen, and are subject to product assessment
and green procurement.
Pamphlet U15412EJ1V0PF
16
Pamphlet U15412EJ1V0PF
17
Architecture
V850 Common Architecture
The V850 Series, which consists of single-chip RISC microcontrollers that use an architecture optimized for embedding, has the following features.
5-stage pipeline processing
Support of CISC-like instructions
Harvard architecture
Multi-status flags
32 general-purpose registers
DSP function
Simple addressing
32-bit barrel shifter
2-byte basic instruction set
ꢁ5-stage pipeline processing
The V850 Series uses a 5-stage pipeline structure (5 stages from instruction fetch to writeback) that supports simultaneous processing of 5 instructions,
thus enabling the execution of almost all instructions in just one clock.
Internal system clock
Instruction 1
Instruction 2
Instruction 3
Instruction 4
Instruction 5
Instruction 6
IF
ID
IF
EX
ID
IF
MEM
EX
ID
WB
MEM
EX
WB
MEM
EX
WB
MEM
EX
IF
ID
WB
MEM
EX
IF
ID
WB
IF
ID
MEM
WB
IF
ID
: Instruction fetch
: Instruction decode
Instruction 1
end
Instruction 2
end
Instruction 3
end
Instruction 4
end
Instruction 5 Instruction 6
end end
EX : Instruction execution
MEM : Memory access to target address
WB : Write execution result to register
An instruction is executed each clock
ꢁHarvard architecture
The V850 Series uses the Harvard architecture, which is designed so that the instruction bus and data bus can operate completely independently
from each other, thereby preventing pipeline operation problems and ensuring efficient instruction execution.
In the case of an architecture other than the Harvard architecture, the MEM stage of
instruction 1 and the IF stage of instruction 4, and the MEM stage of instruction 2
and the IF stage of instruction 5 conflict, causing bus waits. This in turn causes the
pipeline operation to become disordered and lowers the instruction execution speed.
CPU
BCU
Instruction bus
Instruction
fetch
Pipeline Operation of Non-Harvard Architecture
Internal
ROM
Instruction1
Instruction2
IF
ID
IF
EX
ID
IF
MEM WB
EX
ID
IF
MEM WB
External
memory
EX
ID
IF
MEM WB
Instruction 3
Instruction 4
Data bus
Operand
data
access
On-chip
peripheral
I/O
EX
ID
MEM WB
EX MEM WB
Internal
RAM
Instruction 5
: Idles inserted due to bus wait
Pamphlet U15412EJ1V0PF
18
ꢁ32 general-purpose registers
The V850 Series provides 32 general-purpose registers. Along with a hardware environment that is ideal for program execution, the development
environment, including compilers, exploits these 32 registers to achieve program generation with superior code efficiency and execution performance.
Comparison of Performance/Object Efficiency According to Number of Registers
Execution time (s)
Byte count (bytes)
4000
For example, looking at the program execution time and
code size changes when the number of registers used
by the compiler is changed using the servo control
module, we can see that the larger the number of
registers, the better the program execution speed and
the smaller the code size. However, from about 26
registers, the improvement in terms of execution speed
and code size becomes smaller, and in the
neighborhood of 32 registers, there are no more
changes. This is why the V850 Series has been provided
with 32 registers as the strict minimum requirement.
12
3000
2000
9
6
1000
0
3
0
16
18
20
22
24
26
28
30
32
Used C program: Servo control module
Byte count
Execution time
Number of registers
ꢁSoftware register bank
The number of registers can be selected from among 22, 26, and 32 as a compiler option to efficiently execute application programs. Unused registers
can be used as a software register bank for which save and restore processing is not required during interrupt servicing or task switching, which
increases the processing speed.
Register bank
interrupt
Program
execution
Interrupt servicing
instruction execution
Program
execution
Save the program counter, etc., to a save register.
Execute the interrupt restore instruction. Restore
the program counter value, etc., from the save
register.
Actual interrupt
servicing time
Save general-purpose registers to stacks.
Restore general-purpose registers from stacks.
Program
execution
Interrupt servicing
instruction execution
Program
execution
Normal
interrupt
Actual interrupt
servicing time
User interrupt servicing routine execution time
Total interrupt servicing time
ꢁGeneral-purpose register configuration
ꢁSystem register configuration
31
r0
r1
r2
r3
r4
r5
r6
r7
0
Zero Register
Reserved for Address Generation
Operand
Name
Application
Operation
System
Register Name
Specification
Application
No.
r0
Zero register
Always holds "0"
Stack Pointer(SP)
Global Pointer(GP)
Text Pointer(TP)
LDSR STSR
r1
Assembler
reservation
Used as working register for
address generation
0
1
EIPC
Register for saving status
during interrupt
EIPSW
FEPC
FEPSW
ECR
r8
r9
r2
Address/data variable register
(If real-time OS being used does not use r2)
r10
r11
r12
r13
r14
r15
r16
r17
r18
r19
r20
r21
r22
r23
r24
r25
r26
r27
r28
r29
2
Register for saving status
during NMI
3
r3
Stack pointer
Used for stack frame
generation during function call
4
×
Interrupt source register
Program status word
5
PSW
r4
r5
Global pointer
Text pointer
Used when accessing global
variables in the data area
16
17
18
19
20
CTPC
CTPSW
DBPC
DBPSW
CTBP
Register for saving status
during CALLT execution
Used as register
for specifying
the beginning of the text area
(program code allocation)
Only supported by
V850E1 CPU
core products
supported
Register for saving status
during exception/debug trap
r6-r29 Address/data variable register
CALLT base pointer
r30 Element Pointer(EP)
r31 Link Pointer(LP)
31
PC Program Counter
r30
Element pointer Used as base pointer
for address
6-15, 21-31 Reserved
×
×
0
generation during memory
access
× : Access prohibited LDSR: Instruction to load general-purpose register
contents to system register
r31
PC
Link pointer
Used during function
call by compiler
: Access enabled
STSR: Instruction to store system register contents to
general-purpose register
Program counter Holds instruction addresses
during program execution
Pamphlet U15412EJ1V0PF
19
ꢁSimple addressing
The increased amount of address calculations in the CPU in the case of complex addressing causes disturbances in the pipeline operation. As a
result, address calculation becomes a bottleneck for pipeline processing and raising the frequency to increase the performance becomes difficult. The
V850 Series avoids this problem by supporting only simple addressing.
Pipeline Processing Time and CPU Operating Frequency
In case of excessive addressing
In case of simple addressing
Pipeline processing sequence
Instruction fetch
Address calculation
Execution
All processing is standardized and efficient
Operating frequency
held back by slow
processing
Memory access
Writeback
Processing time
Processing time
ꢁAddressing mode
ꢀInstruction addresses
ꢀOperand addresses
•Relative addressing (PC dependent)
•Register addressing
Addressing that accesses the general-purpose register specified by the general-purpose specification
Add 9 signed bits or 22 signed bits of data of the instruction code to the program counter.
field or a system register as an operand.
Example: 22-bit data
31
26 25
0
0
PC
•Immediate addressing
Addressing of 5-bit data or 16-bit data for manipulation in the instruction code.
31
31
22 21
0
Signed extension
disp22
PC
•Based addressing
31
31
0
0
Addressing that accesses
memory, with the sum of the
contents of the general-
purpose register (reg1) and
16-bit displacement (disp16)
as the operand address.
reg1
26 25
0
0
16 15
Memory subject to
manipulation
Signed extension
disp16
Memory subject to
manipulation
•Register addressing (register indirect)
Transfer the contents of the general-purpose register specified by the instruction (reg1) to the program counter (PC).
•Bit addressing
31
31
0
0
Addressing that accesses 1
bit of 1 byte of the memory
space, with the sum of the
contents of the general-
purpose register (reg1) and
16-bit displacement (disp16)
that has been sign extended
to word length as the
operand address.
reg1
31
26 25
0
reg1
16 15
Signed extension
disp16
31
26 25
0
Memory subject to
manipulation
0
PC
Memory subject to
manipulation
ꢁ2-byte basic instruction set
The V850 Series employs a 2-byte instruction code to perform basic processing to enable compact program development equivalent to 16-bit CISC
microcontrollers.
Object Code Size Comparison
(Dhrystone 1.1/Large model)
•Improved object efficiency through ROMization programming
Application of 2-byte instructions to all basic processing, consisting of load, store, arithmetic/
logic operations, and branching.
1.00
1.03
16-bitV(CISC)
78K/IV(CISC)
•To realize ease of use, restrictions on 16-bit fixed-length instructions are partially
removed through incorporation of 32-bit instructions.
•Bit manipulation instructions, etc.
1.02
V850(RISC)
1.48
V
R
/MIPS32(RISC)
Pamphlet U15412EJ1V0PF
20
ꢁ CISC-like instructions for embedding (bit manipulation instructions)
The V850 Series supports bit manipulation instructions suitable for flag manipulation on I/O registers, which play a large role in embedding control.
• Improvement of operability of memory mapped I/
Os for control purposes
Example: Setting (1) bit 6 of ASIM00 register
Bit Manipulation
Instruction
When Used
6, ASIM00[r0]
When Used
Item
• Manipulation of any 1 bit of byte data in the
memory space
set1
ld.b
ori
st.b
ASIM00[r0], r20
0x0040, r20, r20
r20, ASIM00[r0]
add
st.w
ld.b
ori
st.b
ld.w
add
-4, sp
r20, 0[sp]
ASIM00[r0], r20
0x0040, r20, r20
r20, ASIM00[r0]
0[sp], r20
Coding example
Save r20
• Provision of test (tst1)/set (set1)/clear (clr1)/invert
(not1)
Restore r20
• Effective for reducing object size and execution
time since flags can be manipulated in 1-bit units
with 1 instruction
4, sp
Object size
4 bytes
12 bytes
4 clocks
24 bytes
8 clocks
Execution time
4 clocks
ꢁ Multi-status flags
In the V850 Series, calculation results are reflected in registers as status flags. As a result, delay branching such as can be seen in the RISC
microcontrollers of other manufacturers does not occur and programs can be coded with the same feel as CISC microcontrollers.
Example: Program that branches to positive/negative/zero according to register contents
• Easy recording with assembler
CISC Microcontroller
cmp ax, 0
V850
0, r10
ZERO
PLUS
MINUS
Other Manufacturer's RISC Microcontroller
• Improved object efficiency and execution speed
cmp
bz
bgt
br
cmp/eq
bt
cmp/pl
bt
#0, r10
ZERO
r10
PLUS
MINUS
jz
ZERO
PLUS
MINUS
jgt
jmp
ZERO : Zero processing
bra
PLUS : Positive processing
MINUS : Negative processing
nop
;For delay branching
ꢁ DSP function
The V850 Series provides a DSP function for executing high-speed calculations and product-sum operations indispensable for digital signal processing
such as image and speech processing.
V850
CPU+DSP
• Direct data handling via general-purpose registers
• Realization of digital signal processing through general-
purpose CPU
CPU
General-purpose register
DSP
CPU
INT
SAT
flag
MUL
• High-speed 16-bit (V850 CPU), 32-bit (V850E1 CPU)
multiply/sum-of-products
ALU
MUL
(Multiply: 1 to 2 clocks, sum-of-products: 3 clocks)
• Effective for filter operations and matrix operations for
feedback calculations in speed, position, and other servo
control.
ALU
Memory
ꢁ 32-bit barrel shifter
V850 Series can realize bit manipulations frequently used during signed data and image data processing in 1 instruction per clock.
Example: 27-bit logical right shift
• Shifting of any number of bits (0 to 31) executable in 1 instruction per clock
Improved execution speed/object efficiency
Other manufacturer's
RISC microcontroller
V850
Effective for extracting arbitrary bit lengths of image data and signed data
(extracting code during MH/MR/MMR encoding, etc.)
Processing sequence
SHR16
SHR8
SHR2
SHR
Rn
Rn
Rn
Rn
SHR 27, Rn
4
4
Number of instructions
1
1
Number of execution clocks
Pamphlet U15412EJ1V0PF
21
Strengths of V850E1 and V850ES Cores
The V850E1 and V850ES cores are CPU cores that enhance the functions of the V850 core.
ꢁ V850E1 core
ꢀHigher performance and improved operating frequency of 50 to 100 MHz
ꢀImproved external memory access function
ꢀImproved code efficiency (10 to 15% higher than V850 core)
•Addition of C language compatible instructions (Switch instruction, CALLT instruction, etc.)
ꢀHigh performance high-end lineup (V850E products), system-on-chip core lineup
ꢁ V850ES core
ꢀNext-generation CPU core of low-end lineup
ꢀSupport of lower voltage for V850/Sxx products
ꢀImproved code efficiency through use of same architecture as V850E1
(10 to 15% higher than V850 core)
CPU Core
V850
V850ES
V850E1
Function
Maximum operating frequency
20/33 MHz
16 MB
20 MHz
16 MB
50 100MHz
Maximum program memory space
64 MB
Maximum data memory space
Higher performance
16 MB
16 MB
256 MB
Use of 5-stage pipeline
Use of Harvard architecture
Improvement of pipeline
• Non-blocking load/store
Parallel execution of instructions (during instruction execution in
internal ROM)
• Addition of branch/load pipes
• Shift to 3-operand manipulations in 1 slot
Higher code efficiency
Use of 2-byte instructions
Use of CISC instructions
Addition of C language compatible instructions
(Addition of Switch instruction, Callt instruction, data conversion
instruction, Prepare/Dispose instruction)
Multiplier
16 × 16 bit 32 bit
16 × 16 bit 32 bit
32 × 32 bit 64 bit
(32-bit multiply instruction support)
Interrupt responsiveness
11 to 18 clocks
4 to 10 clocks
Pamphlet U15412EJ1V0PF
22
Employment as ASIC CPU Cores
ꢂ Smooth transition to ASIC microcontroller development using V850E1 CPU cores
1. Introduction to market with short TAT through use of standard V850E1 products
2. Optimization of system through switch to ASIC
ꢂ Easy securing of compatibility from traditional systems made into ASICs through use of same device development methods
for both standard products and ASIC microcontrollers
ꢂ Development of CPU cores bearing in mind shift to ASIC
Software debugging support
Release of CPU core that supports on-chip debugging through full-function in-circuit emulator, JTAG method (N-Wire ICE) and on-chip debugging
with trace function
Internal system bus configuration
Independent high-speed 32-bit synchronous system bus and 16-bit asynchronous bus for low-speed peripheral function macro connection, realizing
both high-speed processing, low-power consumption and easy design
Provision of large assortment of peripheral function macros
Cache memory, memory controller, ROM/RAM, USB, etc.
ꢂ Covering required performance and power consumption through support of a large variety of processes
Process
0.35µm
0.25µm
0.13µm
Cell-based IC family
CB-9VX
CB-10VX
CB-12
ꢁV850E1 core
ꢀ Realization of excellent performance/power ratio of 827 MIPS/W for 100 MHz Max. (at 2.5 V operation)
ꢀ Improved object efficiency
ꢀ A flexible and high-performance bus system can be configured through independent buses such as a high-speed system bus that enables 400 MB/s
data transfer and a low-speed peripheral macro connection bus.
ꢀ Support of on-chip debugging function
ꢁV850E1 core
ꢁV850E/MA1 block configuration
V850E1Core
Timer
UART
CSI
INT(64ch)
INT
RCU
RCU
INTC
INTC
Peripheral
Bus
(16bit/asynchronous)
BBR
BBR
ROM
(256KB)
iROM I/F
(32bit/1clk)
Peripheral Bus
System Bus
CPU
32x32
MUL
CPU
32 × 32
MUL
PWM
A/D
iRAM I/F
(32bit/1clk)
System
Bus
(32bit/1clk)
RAM
(10KB)
BCU
TEST
Ctrl
BCU
DMA
TEST
Ctrl
DMA
PORT
MEMC
Pamphlet U15412EJ1V0PF
23
ꢁV850E1, V850ES architecture
The V850E1 and V850ES cores achieve high performance and higher code efficiency through the implementation of the following improvements to
the V850 CPU core.
Non-blocking load/store
Addition of branch/load pipes
Shift to 3-operand manipulations in 1 slot
Addition of high-level language-compatible instructions
• Improved bus use efficiency
• Shorter interrupt insensitivity period
• 2-clock branching
• Parallel execution of instructions
• Improved absolute performance
• Example: Synchronous processing
of mov + add
• Improved code efficiency
•
10 to 15% improvement in object
efficiency mainly when C compiler used
ꢀPipeline configuration
ꢀNon-blocking load/store
Master Pipeline
(V850 CPU compatible)
Conventional (V850 CPU) Pipeline is stopped until MEM stage complete
MEM (external memory)
Load
instruction
IF
ID
IF
EX
ID
IF
WB
(MEM)
EX
ID
EX
DF
WB
T1
T2
T3
ADD
instruction
EX
WB
IF
Async WB Pipeline
br/sld
Pipeline
ID
Address
calculation stage
Next
instruction
ID
MEM
WB
MEM
WB
Load, store buffer
(1 stage each)
Effective pipeline processing that uses the Async WB Pipeline when
appropriate, according to the instruction.
V850E1 CPU
Load
instruction
MEM (external memory)
IF (instruction fetch)
ID (Instruction decode)
: Fetches instructions and increments the fetch pointer.
: Decodes instructions, creates immediate data,
and reads registers.
IF
ID
IF
EX
ID
IF
WB
WB
T1
T2
ADD
instruction
EX
DF
EX (ALU, multiplier, barrel shifter execution)
MEM (Memory access)
WB (Writeback)
: Executes decoded instructions.
: Accesses memory of corresponding addresses.
: Writes execution results to registers.
: Transfers execution data to WB stage.
Next
instruction
ID
EX
WB
MEM
DF (data fetch)
ꢀAddition of branch/load pipes
•Pipeline operation with branch instruction
•Parallel instruction execution (when executed by internal ROM)
Conventional (V850 CPU)
Conventional (V850 CPU)
Branch destination determined in EX stage
ADD instruction
(16-bit length)
IF
ID
EX
ID
(MEM)
EX
WB
Branch
instruction
IF
ID
EX
MEM
IF
WB
ID
Branch instruction
(16-bit length)
MEM
IF
WB
ID
Branch destination
instruction
EX
MEM
WB
Next instruction
V850E1 CPU
EX
MEM
Branch destination determined in ID stage
1-clock reduction
2-clock reduction
WB
V850E1 CPU
ADD instruction
Branch instruction
Next instruction
IF
ID
ID
EX
MEM
IF
DF
WB
ID
Branch
instruction
IF
ID
MEM
WB
Branch destination
instruction
IF
ID
EX
MEM
WB
EX
MEM
WB
* The next branch instruction code is also fetched due to the internal 32-bit bus.
ꢀShift to 3-operand manipulations in 1 slot
Conventional
(V850 CPU)
•
Sequence from mov to arithmetic
instruction is detected in the ID
stage, and if dst is the same, the
next manipulation is performed.
mov r20(src2),
add r22(src2),
r21(dst)
r21(dst)
src1 : Replace with src2 of mov
src2 : src2 of arithmetic instruction
dst
: As is
• mov + add instructions executable in
1 clock
V850E1 CPU
add r22(src2), r20(src1), r21(dst)
Pamphlet U15412EJ1V0PF
24
ꢀ Addition of high-level language compatible instructions
The V850E1 and V850ES cores have enhanced the instruction set of the V850 core as follows.
ꢂ switch (2 bytes)
ꢂ unsigned Load
• C language switch statement processing converted into instruction
ꢂ callt (2 bytes)/ctret (4 bytes)
• Reduction of unsigned manipulation code
ꢂ mov imm32, reg (6 bytes/2 clocks)
• Reduction of address setting code
ꢂ mul/mulu (4 bytes)
• Table-reference branching
• Reducing size of call code that frequently appears
ꢂ Data conversion instructions (2 bytes)
• char, short type cast executed with 1 instruction
• sxh, sxb, zxb, and zxh instructions
• Reduction of array address calculation
• Improvement of sum-of-products performance
ꢂ Other
ꢂ prepare/dispose (4 bytes)
• Bit manipulation (register indirect bit specification)
• cmov (Conditional Move), divide (div/divu/divhu)
• sasf, endian conversion
• Function start/end processing executed in 1 instruction
callt N (Table-reference subroutine calling)
switch R (table-reference branching)
<1> Transfers the restored PC and PSW values to CTPC
<1> Adds the table start address and double the register value.
PC
CTBP
15
0
15
0
and CTPSW.
<2> Sign extends halfword entry data indicated by the address
generated in <1> to word length, doubles it, and adds the
table start address to generate a 32-bit address.
<2> Adds the CTBP value and 2N to generate a 32-bit table
entry address.
<3> Loads the halfword of the address generated in <2> and
adds the CTBP value to the value 0 extended to word
length to generate the 32-bit target address.
<4> Branches to the address generated in <3>.
entry 0
entry 1
entry 2
switch R
entry 0
entry 1
entry 2
PC+2
2n
<3> Branches to target address generated in <2>.
2N
<2>
CTBP+2N
<1>
PC+2+2n
entry N
Target
<3>
<1>
<1>
entry n
Target
PC
CTPC
CTBP+(unsigned(entry data))
<2>
CPU
V850E1
switch r10
V850
Item
PC+2+2y
Coding example
movhi
movea
shl
hi (L267), zero, r9
lo (L267), r9, r9
1, r10
<4>
PSW
CTPSW
<3>
add
r9, r10
PC
PSW
: Program counter
: Program status word
ld.h
add
0[r10], r10
r9, r10
PC : Program counter
: General-purpose register
: General-purpose register
(R) value
: signed(entry data)
CTPC : Register to save status during
CALLT execution
jmp
[r10]
R
n
CTPSW : Register to save status during
CALLT execution
22 bytes
Object size
2 bytes
CTBP
N
: CALLT base pointer
: 0 to 63
y
Execution time
9 clocks
5 clocks
V850E1 Core and V850ES Core vs. V850 Core Code Size Comparison
Interrupt Response Time
Bytes
600
Internal
system clock
Interrupt
request
500
400
300
200
100
0
IF
ID
EX
MEM WB
Instruction 1
Instruction 2
IFx
IDx
Interrupt
acknowledgement
operation
INT1 INT2 INT3 INT4
4 system clocks
IF
ID
EX MEM WB
Interrupt
servicing routine
System registers for saving the PC and PSW are provided and high-speed branching
to the interrupt program is performed, except under the following conditions.
• In IDLE/STOP mode • In case of consecutive interrupt request non-sample instructions
• During external bus access • During access to the interrupt control register
A
B
C
D
E
F
G
H
I
J
K
Remark INT1 to INT4 : Interrupt acknowledgement processing
Measurement program
V850 core
V850E1 core, V850ES core
IFx
IDx
: Invalid instruction fetch
: Invalid instruction decode
Pamphlet U15412EJ1V0PF
25
Middleware Performance
ꢁMeasurement conditions
ꢀCommon
ꢀMH/MR/MMR
• Internal ROM
CPU
: V850 core (33 MHz)
: Program
Measurement results are frequency-converted values (50 MHz).
: 16 bits
• External memory (SRAM) : Encoding/decoding table, change point table,
Bus width
stacks (including I/O parameters)
Number of waits : 1
(The basic bus cycle is 3 clocks, so 1 bus cycle = 4 clocks.)
ꢀJBIG
• Internal ROM
• External memory (SRAM) : Learning table, stacks (including I/O parameters)
:
Program (including probability assumption table (1 KB))
Compiler
Tool
: CA850
: V850 in-circuit emulator (IE) (product of NEC)
V850 MH Method — A4 100 dpi
V850 MR (K = 4) Method — A4 100 dpi
chart1
0.07s
0.07s
chart2
0.06s
0.06s
chart3
0.10s
0.10s
chart4
0.17s
0.16s
chart5
0.11s
0.10s
chart6
0.09s
0.08s
chart7
0.18s
0.15s
chart8
0.11s
0.08s
chart1
0.06s
0.06s
chart2
0.06s
0.05s
chart3
0.09s
0.08s
chart4
0.14s
0.12s
chart5
0.09s
0.08s
chart6
0.08s
0.07s
chart7
0.15s
0.11s
chart8
0.10s
0.07s
Compression
Decompression
Compression
Decompression
Compression
Decompression
Seconds
Seconds
0.20
0.20
Compression
Decompression
Seconds
0.16
Seconds
0.18
0.16
0.18
0.16
0.16
0.14
0.12
0.14
0.12
0.14
0.12
0.14
0.12
0.10
0.10
0.10
0.10
0.08
0.06
0.08
0.06
0.08
0.06
0.08
0.06
0.04
0.02
0.04
0.02
0.04
0.02
0.04
0.02
0.00
0.00
0.00
1
0.00
1
2
3
4
5
6
7
8
chart
1
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8
chart
2
3
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5
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7
8
chart
1
2
3
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5
6
7
8
chart
V850 MMR Method — A4 100 dpi
V850 JBIG Method — A4 100 dpi
(Layer=Lowest, TPBON=ON, AT=default)
chart1
Compression LRLTWO=OFF 0.41s
LRLTWO=ON 0.38s
LRLTWO=OFF 0.46s
LRLTWO=ON 0.43s
chart2
0.52s
0.48s
0.59s
0.57s
chart3
0.63s
0.58s
0.73s
0.68s
chart4
0.84s
0.76s
0.96s
0.89s
chart5
0.62s
0.57s
0.72s
0.68s
chart6
0.57s
0.52s
0.67s
0.63s
chart7
0.85s
0.78s
1.02s
0.93s
chart8
0.90s
0.83s
1.04s
0.97s
chart1
0.07s
0.07s
chart2
0.06s
0.05s
chart3
0.11s
0.10s
chart4
0.18s
0.17s
chart5
0.11s
0.10s
chart6
0.09s
0.07s
chart7
0.18s
0.16s
chart8
0.11s
0.08s
Compression
Decompression
Decompression
Seconds
0.20
Compression
Seconds
Decompression
Decompression
Seconds
1.00
Compression
Seconds
0.20
1.00
0.80
0.60
0.18
0.16
0.18
0.16
0.80
0.60
0.14
0.12
0.14
0.12
0.10
0.10
0.40
0.40
0.08
0.06
0.08
0.06
0.20
0.00
0.20
0.00
0.04
0.02
0.04
0.02
1
2
3
4
5
6
7
8
chart
1
2
3
4
5
6
7
8
chart
0.00
1
0.00
2
3
4
5
6
7
8
chart
1
2
3
4
5
6
7
8
chart
LRLTWO=OFF
LRLTWO=ON
LRLTWO=OFF
LRLTWO=ON
ꢀJPEG
Internal ROM
Internal RAM
: Program
: Stack, work area (one part)
V850 JPEG Method
Processing Time
QVGA(320×240×24) VGA(640×480×24)
Compression Decompression Compression Decompression
External memory (SRAM) : Data and remaining work area
Data I/O : RGB
Sample ratio
4 : 1 : 1
(Quality75)
0.27s
0.21s
1.09s
0.85s
4 : 2 : 2
(Quality75)
0.33s
0.26s
1.33s
1.04s
Pamphlet U15412EJ1V0PF
26
Variety of Peripheral Functions
Memory Access Functions
ꢁSDRAM controller
ꢁDRAM controller
Products: V850E/MA1, MA2
Products: V850E/MS1, MS2, MA1
ꢂ SDRAM connectable without external circuit
ꢂ CAS latency: 2, 3 supported
ꢂ EDO DRAM directly connectable without external circuit
ꢂ 2CAS type DRAM supported
ꢂ CBR refresh, CBR self refresh supported
ꢂ CBR refresh, CBR self refresh supported
A1 to A12
A21, A22Note
D0 to D15
SDCLK
A0 to A11
A12, A13
DQ0 to DQ15
CLK
A1 to A12
D0 to D15
RASn
LCAS
UCAS
WE
A0 to A11
I/O1 to I/O16
RAS
SDCKE
CSn
CKE
CS
LCAS
SDRAS
SDCAS
LDQM
RAS
UCAS
WE
CAS
LDQM
UDQM
WE
OE
OE
UDQM
V850E/MA1
64 Mb DRAM
(4 Mword × 16 bits)
WE
V850E/MA1
64 Mb SDRAM
(1 Mword × 16 bits × 4 banks)
Note The address signal used differs depending on the SDRAM product.
ꢁDMA controller (provided in V850E products)
ꢁDMA controller (provided in V850/Sxx products)
Products: V850E/MA1, MA2, MS1, MS2, IA1, IA2
ꢂ Transfer targets: Memory-peripheral I/O, memory-memory
ꢂ Single, single step, block transfer
Products: V850/SA1, SB1, SB2, SV1, SF1, SC1, SC2, SC3
ꢂTransfer targets: Internal RAM-on-chip peripheral I/O
ꢂSingle transfer
ꢂ 8-/16-bit data units
ꢂ 8-/16-bit data units
ꢂ Transfer type: 1-cycle transfer, 2-cycle transfer
ꢂ Number of transfers: 65,536 Max.
ꢂTransfer clock: 4 clocks Min.
ꢂNumber of transfers: 256 Max.
Internal RAM
CPU core
CPU core
On-chip peripheral I/O
External I/O
DMA
Data control
Internal
RAM
DMA
External RAM
On-chip
8/16bit-data
8-/16-bit
bus
Address control
Count control
peripheral
I/O
Transfer source address
Transfer destination address
Number of transfers
External ROM
Channel control
Pamphlet U15412EJ1V0PF
27
A/D Converters
ꢁScan mode
ꢁMulti-stage buffer type
Products: V853, V850/SV1, V850E/MA1, IA1, IA2, MS1
ꢂ Conversion can be started by both software and hardware
ꢂ Eight conversion result registers are incorporated
ꢂ Select/scan modes can be switched
ANI0 (Input)
ANI1 (Input)
Data
1
Data
6
Data
5
ANI0
Data
7
Data
2
AVREF
ANI2 (Input)
ANI3 (Input)
Data
3
ANIn
AVSS
Successive approximation register
Data
4
ADTRG
INTAD
Conversion controller
Data 1 Data 2 Data 3 Data 4 Data 5
Data 6 Data 7
(ANI0) (ANI1)
A/D conversion
(ANI0) (ANI1) (ANI2) (ANI3)
(ANI0)
Conversion result register 0
Conversion result register 1
Data 1 Data 2 Data 3
(ANI0) (ANI1) (ANI2)
Conversion Conversion Conversion
Data 4
(ANI3)
Data 6
(ANI0)
Conversion
result
Conversion result register 2
Conversion result register 3
Conversion
result registers
Conversion
result
result
result
result
register 0 register 1 register 2
register 3
register 0
Conversion result register 4
Conversion result register 5
Conversion result register 6
Conversion result register 7
INTAD interrupt
Conversion start
(Control register setting)
Conversion start
(Control register setting)
ꢁSelect mode operation
Analog input
Conversion result registers
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
Conversion result register 0
Conversion result register 1
Conversion result register 2
Conversion result register 3
Conversion result register 4
Conversion result register 5
Conversion result register 6
Conversion result register 7
Data 4
ANI1 (Input)
Data 5
Data 1 Data 2 Data 3
Data 6
Data 7
Data
1
Data
2
Data
3
Data
4
Data
5
Data
6
Data 7
(ANI1)
A/D conversion
(ANI1)
(ANI1)
(ANI1)
(ANI1)
(ANI1)
(ANI1)
A/D converter
Data 1 Data 2 Data 3
(ANI1) (ANI1) (ANI1)
Data 4
(ANI1)
Data 6
(ANI1)
Conversion
result registers
INTAD interrupt
Conversion start Control bit Control bit Control bit Control bit Conversion start Control bit
(Conversion result
register setting)
(Conversion result
register setting)
set
set
set
set
set
Analog input
Conversion result registers
ANI0
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
Conversion result register 0
Conversion result register 1
Conversion result register 2
Conversion result register 3
Conversion result register 4
Conversion result register 5
Conversion result register 6
Conversion result register 7
A/D converter
Pamphlet U15412EJ1V0PF
28
Timer/Counter Functions
ꢁ24-bit servo timer
Product: V850/SV1
ꢁPWM
Product: V850/SV1
ꢂ 24-bit timer unit for servo control
ꢂ Capture registers: 4
ꢂ 12- to 16-bit PWM output
ꢂ Main pulse + additional pulse configuration
Main pulse: 4/5/6/7/8 bits
Compare registers: 2
ꢂ External input detector with 1-64/1-128 divider
Additional pulse: 8 bits
ꢂ Active level of PWM output pulse selectable
Clear count
control
INTOVm
INTTIm
Tim
Selector
24-bit timer
Count
clock
PWM module register PWM module register
(higher 8 bits)
(lower 8 bits)
OVFn
Reload
controller
Capture register 0
Capture register 1
INTCPn
0
INTCPn1
1-64 division
1-128 division
m bit down counter
(m = 4 to 8)
Count
clock
PWM pulse
generator
Vsync
Output
controller
PWMn
INTCPn2
Capture register 2
Capture register 3
Compare register 1
Compare register 2
1-64 division
1/2m
8-bit counter
INTCPn3
INTCMm0
RTP
INTCMm1
INTCPm0-9
ꢁ3-phase inverter control timer
Products: V850E/IA1, IA2
ꢁUp/down counter
Products: V850E/IA1, IA2
ꢂ 3-phase PWM output function
ꢂ 16-bit 2-phase encoder input supported
ꢂ Compare registers: 2
Symmetric triangular wave, asymmetric triangular wave, sawtooth wave
ꢂ Interrupt culling function
ꢂ Capture/compare registers: 2
Culling rate: 1/1, 1/2, 1/3, 1/4, 1/8, 1/16
ꢂ 3-phase PWM forcible output stop function
ꢂ Real-time output function
Count clock
Compare buffer
register
Compare
register 3
Compare capture
register
Output
controller
INTCC
0
16-bit timer
Compare capture
register
Deadtime
timer
TCLR
TCUD
INTCC1
Compare buffer
register
CLR
circuit
TO0
TO1
16-bit up/down
counter timer
Compare
register 0
Deadtime
generator
Selector
Output
control
TO
Compare buffer
register
Compare
register
TO2
TO3
Compare
register 1
Deadtime
generator
INTCM
0
TIUD
Compare
register
INTCM1
Compare buffer
register
TO4
TO5
Compare
register 2
Deadtime
generator
Pamphlet U15412EJ1V0PF
29
Serial Interface
ꢁVariable-length serial interface
Products: V850/SB1, SB2, SV1, SF1, SC1, SC2, SC3
ꢂ 3-wire serial I/O
ꢁ8-/16-bit serial interface
Products: V850/SC1, SC2, SC3, V850E/IA1, IA2
ꢂ 3-wire serial I/O
ꢂ Data length switchable between 8 bits and 16 bits
ꢂ Start bit switchable between MSB and LSB
ꢂ Data length switchable between 8 bits and 16 bits
ꢂ Start bit switchable between MSB and LSB
MSB/LSB controller
Counter
clock
SCKn
SIn
8-/16-bit variable-length shift register
Serial clock
Selector
Interrupt
controller
controller
INTCSIn
BRG
SOn
SCKn
8-bit
shift register L
8-bit
shift register H
SIn
Serial clock counter
(8/16 counting switchable)
Interrupt
controller
INTCSIn
SCKn
SOn
Selector
Serial clock controller
BRG
ꢁIEBus controller
Products: V850/SB2, SC2
ꢁCAN
Products: V850E/IA1, V850/SF1, SC3
ꢂ Supports communication mode 1
ꢂ CAN protocol Ver. 2.0 Part B
ꢂ Maximum number of transfer bytes: 32 bytes/frame
ꢂ Maximum transfer speed: Approx. 17 Kbps
(Transmission/reception of standard and extended frames)
ꢂ Maximum transfer rate: 1 Mbps
ꢂ 32 message buffers
Register block
CANTX1
CANRX1
CANTX2
CANRX2
CAN
CAN
receiver 1
module 1
Transmission
block
IETX
MAC
(Memory Access
Controller)
Interrupt
request
Controller
Reception
block
IERX
CAN
receiver 2
CAN
module 2
Bit
Field
controller
controller
CAN RAM
Message buffer 0
Message buffer 31
Control block
Interrupt request
Note The number of channels differs depending on the product.
Pamphlet U15412EJ1V0PF
30
Distinctive Peripheral Functions of V850
ꢁWatch timer
ꢁHsync/Vsync separator
Product: V850/SV1
Products: V850/SB1, SB2, SV1, SC1, SC2, SC3
ꢂ 0.5-second interrupt generation using watch timer function
ꢂ Interval timer supported
ꢂ Separation of Vsync (vertical) signal and Hsync (horizontal) signal from
decoding sync signal of VCR
ꢂ Odd/even field discrimination
Hsync mask signal
HSOUT0
(Detected Hsync)
IHsync↑ detection
Edge
switching
HSOUT1
(Compensated Hsync)
fxx
CSYNCIN
Hsync
separator
INTWTN
INTWTNI
5-bit counter
(main clock)
11-bit prescaler
fxt
Vsync
separator
(subclock)
Odd/even field
discrimination flag
Count
clock
Selector
VSOUT(Vsync)
Division
by 2
ꢁROM correction function
ꢁROM correction operation
Products: V850/SB1, SB2, SV1, SF1, SC1, SC2, SC3
ꢂ Substitutes JMP r0 instruction for instruction of address to be corrected and
branches to 0000H
ꢂ Program can be modified following creation of mask ROM
ꢂ Correction addresses: 4 points
RESET
Internal ROM
Normal flow
no
ROM correction
request flag = 0?
ROM correction flow
Instruction address bus
Clear ROM
correction request flag
Yes
ROM correction
address register
Initialization
Jump to
correction program
Internal RAM
Download
correction program
Internal ROM
(Max. 1 MB space)
Download
correction program
Write correction
program to RAM
Correction program
execution
External ROM
Comparator
EEPROMTM, etc.
JMP r0 instruction generator
Correction address = XXXX
ROM correction
enable flag = 1
Setting correction
address and enabling ROM
correction
Return to internal ROM
Correction
address enable
setting information
Output trigger
Instruction replacement block
controller
Replace with JMP[r0] instruction
Correction point
Next processing...
Main routine
Instruction data bus
Pamphlet U15412EJ1V0PF
31
Low Power & Low Noise
Low Power Consumption Measures
Low-power-consuming, high-speed microcontrollers are required for portable devices and battery-operated devices such as DVCs and cellular phones.
The V850 Series incorporates various functions to lower the power consumption.
ꢁSuperior power performance
The V850ES and V850/Sxx products feature a thorough power-saving design that realizes a superb power/performance ratio of 1.1 to 0.7 mA/MIPS.
As a result, these products realize a low consumption current only one fifth that of a 16-bit CISC microcontroller of comparable performance. By
featuring such extremely high power performance, these products enable the simultaneous realization of lower power consumption and more
sophisticated functions in various systems.
mA/MIPS
10
Low power consumption 1/5 that of
16-bit CISC of comparable performance
8-bit CISC
16-bit CISC
9.2mA/MIPS
7.3mA/MIPS
5
1.1mA/MIPS
0.9mA/MIPS
V850/SA1
V850/SV1
V850/SB1
1.1mA/MIPS
0.7mA/MIPS
V850ES/SA2, 3*
0
*: Under development
ꢁClock gear function
ꢁStandby mode
The V850/Sxx products come with two oscillators: a main clock and a
subclock. 1/1/, 1/2, 1/4, or 1/8 of the main clock or the subclockNote can
be selected as the CPU operating clock, making it possible to minimize
the power consumption according to the system’s operating status.
Note Not selectable in V850/SV1
An efficient low-power-consumption system can be realized by using
the three standby modes, STOP, IDLE, and HALT, according to the
usage purpose.
Operation modes
Operation status of each mode
Current
consumption
Oscillator
Main Sub
clock clock
Peripheral Watch
functions timer
CPU
Approx. 70% reduction
through clock gear
Normal
operation
mode
Current
Further reduction to
HALT
mode
Approx. 1/2
consumption
1/20 through subclock
reduced to
1/100 or
lower!
operation
Approx. 1/10
IDLE
mode
Approx. 1/100
STOP
mode
Operating
clock
f
xx
f
xx/8
f t
x
Current consumption
(20MHz)
(32.768kHz)
Operating
Stopped
ꢁFunction to cut voltage between A/D converter VREF and
resistor string
AVDD
Voltage application to the A/D converter’s resistor string can be switched
ON/OFF
on and off. The power consumption can be minimized by switching off
ANI0
voltage application to the resistor string when the A/D converter is not
AVREF
AVSS
used.
• Main products:
V850/SB1, SB2, SC1, SC2, SC3, SF1
ANIn
Successive
approximation register
ADTRG
INTAD
Conversion controller
Conversion result register
Pamphlet U15412EJ1V0PF
32
EMI Countermeasures
Minimizing the influence of electromagnetic interference (EMI) from the microcontroller in AV equipment such as car audio systems is a major requirement,
making the reduction of EMI one of the highest technological priorities for microcontroller manufacturers. Various EMI countermeasures are implemented
in the V850 Series.
ꢁEMI countermeasures for individual chip
Noise reduction measures focussing on the following
Example for V850/SB1, 2, SF1, SC1, 2, 3
Phase 1
V850/SB1
1st Ver.
Phase 2
V850/SB1
A products
Phase 3
V850/SB2
A products
Phase4
V850/SF1
Phase5
V850/SBx B products
V850/SCx
three points are implemented as noise countermeasures
in individual V850 Series chips.
ꢂ Reduction of noise generation
Decoupling capacitor
Increased on-chip capacitance
600pF 6000pF
• Use of low-voltage internal logic power supply
• Optimization of oscillator
Noise
(dBm)
ꢂ Reduction of noise propagation
• Separation of internal logic sound source and power supply
of pins
Separation of power supply and GND for port controller
Separation of power supply and GND for oscillator
Elimination of VDD protection element
10 dBm reduction
• Reduction of cross talk between different power supply
wires
5 dBm reduction
Optimization of output buffer
Change of regulator voltage
(3.3V 3.0V)
ꢂ Confining of noise inside
10 dBm reduction
• On-chip decoupling capacitor between power supply
and GND inside microcontroller
Insertion of bypass capacitor
• Separation of power supply and GND for oscillator
Optimization of operating frequency
Internal regulator operation
Separation of power supply circuit
ꢁStandardization of evaluation methods (1/2)
There are no rules regarding the EMI measurement testing method for individual microcontrollers. NEC aims to standardize evaluation circuit constants
through the use of a standalone EMI evaluation board and evaluate products in a measuring environment that uses a shielded room and power supply
filters. This approach enables the evaluation of different products (8-bit and 16-bit NEC CISC microcontrollers, etc.) in the same environment.
ꢀStandalone EMI evaluation board
ꢀStandalone EMI evaluation board measurement environment
Shielded room
Spectrum analyzer
Evaluation
points
Probe
Power supply
Evaluation board
+
-
Filter
+
-
+
-
Pamphlet U15412EJ1V0PF
33
ꢁStandardization of evaluation methods (2/2)
ꢀEMI evaluation results
A comparison of the EMI evaluation results for Phase 2 products (V850/SB1 A products) and Phase 4 products (V850/SF1) is shown below.
Product Name
Measurement Point
Phase 2
(V850/SB1 A Products)
Phase 4
(V850/SF1)
V
DD
10dB
10dB
70
75
80
85
90
95
100
105
110
115
120
70
75
80
85
90
95
100
105
110
115
120
Frequency [MHz]
Frequency [MHz]
Port
10dB
10dB
70
75
80
85
90
95
100
105
110
115
120
70
75
80
85
90
95
100
105
110
115
120
Frequency [MHz]
Frequency [MHz]
Remark Oscillation frequency = 16 MHz
ꢁEvaluation of characteristics using radio system board (1/2)
In addition to EMI measurement using a standalone EMI evaluation board, NEC has also established an evaluation method employing set evaluation
criteria using a radio system board. Since the evaluation results obtained with the radio evaluation board match the evaluation method established by
the customer, the influence of EMI can be judged directly.
ꢀRadio system board
ꢀRadio system board measurement environment
Audio analyzer
Power supply
Signal generator
Tuner pack
Antenna
Audio output
Electronic
volume
+
Audio amp
12 V power supply
CPU board
Coaxial cable
Output
Antenna
Frequency to be modulated : 400 Hz
Frequency deviation
RF signal output level
Output impedance
: 30% (22.5 kHz)
Dummy load
: 60 dB
V
(4Ω)
: 75Ω
LCD & key panel
Audio output level : 0.5 W
Radio system board
Pamphlet U15412EJ1V0PF
34
ꢁEvaluation of characteristics using radio system board (2/2)
ꢀRadio system board block diagram
Audio amp
Electronic volume
Tuner pack
0.1 F× 4
+
----
LF
L output
R output
+
RF
LR
RR
----
Tuner
9V
+
----
PLL
CE
+
----
0.027 F×2
Tuner
GND
Analog
9 V
Analog
12 V
3-wire SIO
2
I C bus
Analog
GND
Analog
GND
Digital
5V
Mute
Microcontroller
Digital
GND
LCD & keyboard
LCD panel
3-wire SIO
CPU board
Strobe
Tuner Pack Electrical Specifications
LCD driver
KEY REQ
Parameter
MIN.
51
TYP.
58
MAX.
10
Unit
dB
dB V
Digital
5V
Audio S/N ratio
Key matrix
Digital
GND
Operational sensitivity
6
ꢀCPU board block diagram
Noise-reduction element insertion location
DIP switches
Digital
5V
Digital
5V
1 kΩ×2
P40-47
P50-57
SCL0
SDA0
AVDD
Electronic volume IC
PLL IC
AVSS
BVDD
BVSS
EVDD
EVSS
SIO4
P37(CE)
V850/SBx
SIO3
P31 (Strobe)
P01 (KEY REQ)
LCD driver IC
P35 (Mute)
RESET
X2
V
DD
Audio amp IC
Reset signal
VSS
REGC
X1
Digital
GND
1 F
0.33 H
V850/SBx CPU board
ꢀResults of characteristics evaluation using radio system board
The EMI reduction efficiency can be ascertained with a radio system board in the same way as standalone microcontroller evaluation.
Phase 5
(V850/SB1 B Products)
Phase 3
(V850/SB2 A Products)
Product Name
16-Bit Microcontroller from Other Company
30
25
20
15
10
5
30
25
20
15
10
5
30
25
20
15
10
5
f
XX=12MHz
0
0
0
-5
-5
-5
85
90
95
100
105
110
85
90
95
100
105
110
85
90
95
100
105
110
Frequency [MHz]
Frequency [MHz]
Frequency [MHz]
Phase 4
(V850/SF1)
Phase 2
(V850/SB1 A Products)
Product Name
16-Bit Microcontroller from Other Company
30
25
20
15
10
5
30
25
20
15
10
5
30
25
20
15
10
5
f
XX=16MHz
0
0
0
-5
85
-5
85
-5
90
95
100
105
110
90
95
100
105
110
85
90
95
100
105
110
Frequency [MHz]
Frequency [MHz]
Frequency [MHz]
Remark fxx : Oscillation frequency
Pamphlet U15412EJ1V0PF
35
Middleware
Middleware Development System
Middleware Development
NEC is developing a range of middleware products suitable to processors for various
systems. NEC middleware is realized by original NEC technology, superior third-
party technology, and established standards.
Communications
Multimedia
MPEG7
MPEG-4 Video
JPEG2000
Standard
specifications
Original NEC
technology
Cooperation with
third parties
USB
Development support system
2001
WMA
ATRAC3
Internet
Music source for
incoming-call
melody
System proposal
Demonstration
Performance
evaluation
Security
V.90
Planning
Creation of middleware
Accumulation of solutions
MP3
XML
AMR
AAC
IrDA
Information
search
MPEG-4 CELP
TrueSpeechTM 8.5
Echo canceller
Processor lineup
WAP
Separation of
hardware/software
Feasibility study
Browser
JAVATM
Image
recognition
RISC
V850 Series
G.723/729
MH/MR/MMR
POP/SMTP
HTTP
Speech recognition (Japanese)
ADPCM
Development
completed
Human
interface
Assembly support
Customization
Next-generation processor
Development
JBIG
JPEG
PPP
TCP/IP
Handwriting recognition (Japanese)
Speech recognition (English (US))
Agent system
Text To Speech (Japanese)
Mass production
2001
Development completed
JPEG
V850 Series Speech Recognition
The V850 Series uses internal memory and peripheral I/Os to realize speech
recognition on one chip.This makes this series ideal for applications that require
speech recognition in sets with large constraints, such as games and home
appliances.
Conforms to JPEG international standard
ꢀ
ꢀ
Conforms to DCT baseline process (non-reverse coding)
Versatile compression and decompression processing
<Compression functions>
Speech recognition realized using just the internal memory and
• User-customizable VRAM input module
• User-specified Huffman and quantization tables
• APPn marker insertion
ꢀ
peripheral I/Os of V850 Series
Increased number of recognized words
ꢀ
• Compression suspend function
Number of recognized words: 30 (for V850/SA1, 20 MHz)
<Decompressing processing>
V850 Series
V850/SA1
• User-customizable VRAM output module
• Support of various JPEG markers (DRI, RSTn, DNL)
• Decompressing suspend function
Speech recognition system
configuration example
LPF
(internal 20 MHz)
Internal
ROM
Internal
RAM
Mic/amp
A/D(1ch)
JPEG Performance
Processing Time
CPU
Sample Ratio
QVGA (320×240×24)
VGA (640×480×24)
Compression
Decompression
Compression
Decompression
4:1:1
(Quality75)
V850E/MS1
(33MHz)Note
0.32s
0.24s
1.3s
0.97s
Increased number of recognized words
Memory Capacity
Note Programs are placed in internal ROM, and stack and work areas (one part) are placed in internal RAM. Data and the
Parent dictionary
Child dictionary 1
remaining work area are placed in external RAM.
ROM/RAM
Description
Program
Table
Capacity
Approx. 25 KB
Approx. 62 KB
Thomas, Richard, Harriet...
Friends
ROM
Company
Child dictionary 2
Memory
Reservations
Recognition dictionary (in case of 20 words) Approx. 0.8 KB Note1
Work area (in case of 20 words) Approx. 4.0 KB Note2
Ms. Smith, Ms. Jones, Mr. Wang...
•
•
•
ROM
Decompression
RAM
Decompression
RAM
Child dictionary 3
ANA, JAL, ticket...
Compression
10KB
Compression
5KB
Stack area
Approx. 0.4 KB
7.5KB
10KB
Notes 1. Figure using average of 5 letters per word to calculate standard dictionary size.
2. The variable work area is proportional to the number of recognized words.
Speech recognition evaluation system
ꢀ
In introducing speech recognition, NEC
has provided an environment that allows
easy evaluation.
For details about this system or how to
purchase it, contact NEC.
Pamphlet U15412EJ1V0PF
36
Handwriting Recognition (Japanese Only)
Text to Speech (TTS) (For Japanese Text)
Easy to use because of flexibility regarding stroke order and count
Pattern matching method based on “non-linear normalization matching method”
Speech synthesized from Japanese Kana and Kanji texts (SJIS
code)
ꢀ
ꢀ
Conversion of pen-drawn lines into image
Versatile speech synthesis
Synthesis of male and female voices (2 types)
ꢀ
High recognition rate, high-speed recognition
Recognition of 95% or higher in 0.1 s (V85x: 25 MHz)
ꢀ
Various parameters such as intonation and reading speed can be adjusted.
TTS rhythm data (pitch, phoneme duration) can be designed
Support of up to JIS No. 2 standard
JIS No. 1 Standard: Approx. 3,400 characters, JIS No. 2 Standard: Approx. 800
ꢀ
ꢀ
(Support of Speech Designer)
characters
TTS using natural rhythm possible (synthesis of more natural sounding speech)
Support of characters with special readings (character readings
New characters can be added (pictographs, etc., can be freely
added)
ꢀ
ꢀ
can be set using the user dictionary)
Synthesis speed (V853: 25 MHz)
A dictionary can be created from character data using a dictionary compilation
tool.
ꢀ
Speech: Between 1.9 sNote and 3 s; Text analysis: 163 ms; speech generation:
1,709 ms
Note Varies depending on the input character string.
ROM/RAM
ROM
Description
Program
Capacity
ROM/RAM
ROM
Description
Program data
Capacity
Approx. 60 KB
Approx. 450 KB
Approx. 60 KB
Approx. 32 KB
Approx. 2 KB
Approx. 103 KB
Approx. 1.2 MB
Approx. 670 KB to 1.4 MB
Approx. 160 KB
Approx. 256 KB
Approx. 8 KB × n blocks
Dictionary data (approx. 4,200 characters)
Dictionary data (approx. 80,000 words)
Phoneme data
Data
RAM
Work area
Stack area
RAM
Work area
Stack area
Speech output buffer
Middleware Product List
Middleware list
ꢀ
Category
Image
Middleware
V850 Series
MH/MR/MMR
JBIG
JPEG
Speech
Text To Speech
Speech CODEC
Speech recognition
Speech recognition
Handwriting recognition
Browser
Japanese
G.726 (ADPCM)
Recognition
Japanese (small vocabulary)
English (US) (small vocabulary)
Japanese (input frame required)
Internet
Drivers
TCP/IP
IrDA protocol stack
USB
IEEE1394
PCMCIA/CF card
PC-compatible file system
Font
Other
Remarks 1.
: Development completed;
: Under development;
: In planning
2. Third-party products included.
3. For details about middleware products, refer to the following
http://www.ic.nec.co.jp/apsoft/english/middle_top.html
Middleware performance
ꢀ
Middleware
Performance
MH Chart1 : Enc0.12s/Dec0.08s
Chart1 : Enc0.73s/Dec0.83s
QVGA × 24 : Enc0.32s/Dec0.24s
32Kbps, 16Kbps
Power(MIPS)
ROM
64 KB
RAM
200 bytes
2.6 KB
MH/MR/MMR
JBIG
----
----
----
21 KB
17.5 KB
9 KB
JPEG
15 KB
G.726(ADPCM)
Enc8/Dec8.2
19 (20 words)
63 (100 words)
14
80 bytes
3.5 KB
Speech recognition (small vocabulary)
0.4s
82 KB
(15 words)
34 KB
Handwriting recognition
(Japanese, input frame required)
IrDA protocol stack
0.1s/character
----
570 KB
60 KB
----
16 KB
Pamphlet U15412EJ1V0PF
37
Flash Memory Microcontrollers
Features
To answer the need for shorter development time and maintenance after shipping,
NEC offers microcontrollers with on-chip flash memory available in a large range of
capacities from 128 KB to 512 KB as part of the V850 Series. NEC’s flash memory
microcontrollers offer the following features.
Flash Memory Size
(Bytes)
128K
256K
10K
384K 512K
RAM Size (Bytes)
V850E/MA1
V850E/IA1
V850E/IA2
V850E/MS1
V853
4K
6K
8K
16K
16K
24K
ꢂ
ꢂ
ꢂ
Support of batch rewrite of entire memory and rewrite in area units
Flash memory programming with self-rewrite in area units
Support of on-board programming through serial communication using a
flash memory programmer
V850/SA1
V850/SV1
V850/SB1
V850/SB2
V850/SF1
V850/SC1
V850/SC2
V850/SC3
V850ES/SA2
V850ES/SA3
ꢂ
Erase/write voltage: 2.5 V, 7.8 V, 10.3 V
:
Under development
Rewrite Mode
The V850 Series supports a programmer rewrite mode that uses serial communication supporting on-board programming, as well as a self-programming mode that rewrites
flash memory with user programs, to enable continuous use from development to maintenance.
ꢁProgrammer rewrite mode
CSI communication mode
Handshake-compatible CSI communication mode
UART communication mode
V
PP
V
V
V
PP
DD
SS
V
PP
V
V
V
PP
DD
SS
V
PP
V
V
V
PP
DD
SS
VDD
V
DD
VDD
GND
RESET
SO
GND
GND
RESET
TXD
RESET
SI0
RESET
SO
RESET
SI0
RESET
RXD0
TXD0
Example:
V850/SA1
Dedicated
flash programmer
(PG-FP3, etc.)
Example:
V850/SA1
Dedicated
flash programmer
(PG-FP3, etc.)
Dedicated
flash programmer
(PG-FP3, etc.)
Example:
V850/SA1
SI
SO0
SI
SCK
HS
SO0
SCK0
P15
RXD
SCK
SCK0
ꢁSelf-Programming Mode
Normal operation mode
Flash memory
Self programming mode
Flash memory can be erased and rewritten by calling a self-
programming function (device-internal processing) using a self-
programming interface, from a program placed in an area other
than the flash memory.The self-programming function is called
by switching from the normal operation mode to the self-
programming mode using the flash programming mode control
register (FLPMC).
Flash memory
3FFFFH
3FFFFH
Erase areaNote
(128 KB)
FLPMC 02H
Self-programming
function
(on-chip erase/
write routine)
256 KB
Erase areaNote
(128 KB)
FLPMC 00H
00000H
Note Erasure is performed in area units (128 KB).
00000H
Pamphlet U15412EJ1V0PF
38
Specifications
Flash Memory
Capacity
Power Supply
Voltage
Max. Operating
Frequency
Package
Rewrite Voltage
Rewrite Mode
W/E Count
Part No.
V
DD
V
PP
256 KB
3.0 to 3.6 V
50 MHz
3.3 V
3.3 V
3.3 V
7.8 V
7.8 V
7.8 V
CSI, HS-compatible
CSI
100
V850E/MA1
V850E/IA1
V850E/MS1
144-pin LQFP (20 × 20mm)
161-pin FBGA (13 × 13mm)
144-pin LQFP (20 × 20mm)
256 KB
128 KB
128 KB
3.0 to 3.6 V
50 MHz
33 MHz
CSI, UART,
100
100
(Internal unit)
HS-compatible CSI
4.5 to 5.5 V
(External pin)
3.0 to 3.6 V
144-pin LQFP (20 × 20mm)
157-pin FBGA (14 × 14mm)
144-pin LQFP (20 × 20mm)
CSI, UART,
HS-compatible CSI
3.0 to 3.6 V
(Internal unit)
4.5 to 5.5 V
(External pin)
V853
128 KB
256 KB
128 KB
256 KB
4.5 to 5.5 V
33 MHz
20 MHz
100-pin LQFP (14 × 14mm)
100-pin LQFP (14 × 14mm)
5 V
10.3 V
7.8 V
CSI, UART,
20
HS-compatible CSI
V850/SA1
3.0 to 3.6 V
100-pin LQFP (14 × 14mm)
100-pin LQFP (14 × 14mm)
121-pin FBGA (12 × 12mm)
3.3 V
CSI, UART,
100
HS-compatible CSI
V850/SV1
V850/SB1
V850/SB2
V850/SF1
256 KB
3.1 to 3.6 V
4.0 to 5.5 V
4.0 to 5.5 V
4.0 to 5.5 V
20 MHz
20 MHz
13 MHz
16 MHz
176-pin LQFP (24 × 24mm)
180-pin FBGA (13 × 13mm)
180-pin FBGA (13 × 13mm)
3.3 V
3.3 V
3.3 V
3.3 V
7.8 V
7.8 V
7.8 V
7.8 V
CSI, UART,
100
100
100
100
HS-compatible CSI
384 KB
256 KB
100-pin LQFP (14 × 14mm)
100-pin QFP (14 × 20mm)
100-pin QFP (14 × 20mm)
CSI, UART,
HS-compatible CSI
512 KB
256 KB
100-pin LQFP (14 × 14mm)
100-pin QFP (14 × 20mm)
100-pin QFP (14 × 20mm)
CSI, UART,
HS-compatible CSI
512 KB
256 KB
100-pin LQFP (14 × 14mm)
100-pin QFP (14 × 20mm)
CSI, UART,
HS-compatible CSI
V850/SC1, SC2, SC3
V850ES/SA2*
512 KB
256 KB
4.0 to 5.5 V
2.3 to 2.7 V
20 MHz
17 MHz
144-pin LQFP (20 × 20mm)
100-pin LQFP (14 × 14mm)
3.3 V
2.5 V
7.8 V
2.5 V
CSI, UART,
100
100
HS-compatible CSI
CSI, UART
CSI, UART
V850ES/SA3*
256 KB
2.3 to 2.7 V
17 MHz
121-pin FBGA (12 × 12mm)
2.5 V
2.5 V
100
* : Under Development
Pamphlet U15412EJ1V0PF
39
Flash Memory Programmers
ꢁNEC flash memory programmer (PG-FP3)
[Features]
ꢂ Supports write to all NEC microcontrollers with dual-power supply flash memory
ꢂ Device-specific information required for writing can be automatically set with
parameter files.
ꢂ Supports both on-board writing and program adapter writing.
ꢂ Easy-to-carry A5 size
ꢂ Simple operation either on standalone basis or with a dedicated application
(Flashpro III) on WindowsTM 95, 98, 2000, or Windows NTTM Ver. 4.0
<Standalone>
Executed in one of the following modes: PROMLOAD, ERASE, PROGRAM,
VERIFY, E.P.V.
<On Windows>
Operated via GUI screen.
ꢁThird-party flash memory programmers (1/2)
ꢀProgramming system Y1000-8
[Manufacturer/Marketing] Wave Technology Co., Ltd.
[Target Devices] V850E/MA1, V850/SV1
[Features]
ꢂ
Gang programmer enabling simultaneous programming and verification of up to 8
devices
ꢂ
ꢂ
ꢂ
ꢂ
Enables reading of master data directly from floppy disk to internal memory.
Data dump display and editing functions
Master data storable on internal hard disk
Emphasizes simple and comfortable operation via touch panel and workability via
PASS/FAIL display, check-sum display, and task count display supporting sockets
[Additional information]
TEL: +81-3-5304-1885
FAX: +81-3-5304-1886
E-mail: sales@y1000.com
Website: http://www.y1000.com/en/index.html
ꢀFlashpro III FL-PR3
[Manufacturer/Marketing] Naito Densei Machida Mfg. Co., Ltd.
[Target Devices] V850 Series
[Features]
ꢂ Supports writing to all NEC microcontrollers with dual-power supply flash
memory
ꢂ Device-specific information required for writing can be automatically set with
parameter files.
ꢂ Supports both on-board writing and program adapter writing.
ꢂ Easy-to-carry A5 size
ꢂ Simple operation either on standalone basis or with a dedicated application
(Flashpro III) on Windows 95, 98, 2000, or Windows NT Ver. 4.0
[Additional Information]
FAX: +81-45-475-4091
E-mail: info@ndk-m.co.jp
Website: http://www.ndk-m.co.jp/eng/index.html
Pamphlet U15412EJ1V0PF
40
ꢁThird-party flash memory programmers (2/2)
ꢀNET IMPRESS
[Manufacturer/Marketing] Yokogawa Digital Computer Corporation
[Target Devices] V850E/IA1, V850/SB1 (µPD70F3033A)
[Features]
This in-circuit programmer for flash memory microcontrollers (NET IMPRESS) is used to program
the microcontrollers with on-chip flash memory of each company, which have various writing
specifications, while solder mounted on the user system board.
This programmer comes in four models (AF220, AF210, AF120, AF110) to be used according
to the intended application field.
ꢂ
One control module is the key to this product’s versatility.
Microcontrollers of the same family are supported by changing parameters, and
microcontrollers of different families are supported by purchasing the license for the descriptor
part.
ꢂ
ꢂ
Can be used on standalone basis as well as via a host machine.
Rich lineup of freeware
[Additional Information]
TEL : Japan
U.S.A
+81-42-333-6224
+408-244-1932
+44-1256-811998
+81-42-352-6109
+408-244-1881
+44-1256-811761
Europe
FAX : Japan
U.S.A
Europe
E-mail : info@advice.ydc.co.jp
Website : http://www.ydc.co.jp/micom/index_E.htm
Flash Memory Programmers
NEC's flash memory programmer (PG-FP3) supports all NEC microcontrollers with dual-power-supply on-chip flash memory.The PG-FP3 stores the device-specific information
required for rewriting in a parameter file and the rewriting environment for each microcontroller can be automatically set by downloading this file. After the parameter file is
downloaded, the PG-FP3 can be used on a standalone basis. Combined with a program adapter (FA series (manufactured by Naito Densei Machida Mfg. Co., Ltd.)), this
programmer can be used to write single microcontrollers. On-board writing is also possible using a target cable.
An example of the rewriting environment when using the program adapter is described below.
ꢀExample of rewriting environment
Flash memory programmer (PG-FP3)
Target system
Power supply unit
Host machine interface (RS-232-C)
To host machine
Cautions 1. Install the control software of the PG-FP3 and the
parameter file of the target device in the host
machine.
• PG-FP3 control software: Provided with PG-FP3
• Parameter files: Distributed via online delivery
2. In addition to using the program adapter, rewriting
can also be done on-board on the target system.
Pamphlet U15412EJ1V0PF
41
Functional Outline
(1/11)
V850E/MA1
PD703106A
V850E/MA2
PD703108
Item
PD703103A
V850E1
PD703105A
PD703107A
PD70F3107A
V850E1
CPU core
----
62MIPS (@ 50 MHz)
----
CPU performance (Dhrystone)
Internal ROM
128 KB
(Mask ROM)
256 KB
(mask ROM)
256 KB
(flash memory)
None
None
4 KB
10 KB
4 KB
Internal RAM
26 bits
16 bits
0 to 7
25 bits
16 bits
0 to 7
External
bus interface
Address bus
Data bus
Programmable
waits
External: 25 (17)Note
Internal: 33
External: 8 (4)Note
Internal: 23
Interrupt sources
DSP function
0.02 to 0.04µs (@ 50 MHz)
0.025 to 0.05µs
32×32 64
(@ 40 MHz)
0.06µs (@ 50 MHz)
0.075µs (@ 40 MHz)
32×32+32 32
----
----
----
----
16×16 32
16×16+32 32
16-bit timer/event counter × 4 ch
16-bit interval timer × 4 ch
16-bit timer/event
counter × 2 ch
Timer/counter (RPU)
16-bit interval
timer × 4 ch
1 ch
----
----
----
Serial interface
(SIO)
CSI
CSI/I2C
2 ch
1 ch
2 ch
----
CSI/UART
UART
3 ch
2 ch
Dedicated BRG
8 ch (10-bit resolution)
4 ch
4 ch (10-bit resolution)
4 ch
A/D converter
DMA controller
----
----
74
5
Real-time output port
Ports
106
I/O
9
Input
Memory access control function
Memory access control
function (SDRAM,
SRAM, page ROM, etc.,
directly connectable)
Other peripheral I/O functions
(SDRAM, SRAM, EDO DRAM, page ROM, etc., directly connectable)
PWM: 2 ch (8/9/10/12-bit resolution)
HALT, IDLE, STOP
4 to 50 MHz
HALT, IDLE, STOP
4 to 40 MHz
Power save function
Operating frequency
3.0 to 3.6 V
3.0 to 3.6 V
Power supply voltage
540mW (@ 3.3 V, 50 MHz)
376mW
Power consumption (Typ.)
(@ 3.3 V, 40 MHz)
144-pin plastic LQFP (20 × 20 mm)
144-pin plastic LQFP (20 × 20 mm)
161-pin plastic FGBA (13 × 13 mm)
100-pin plastic LQFP
Package
(14 × 14 mm)
Note Number of external interrupts that can be used to release STOP mode
Pamphlet U15412EJ1V0PF
42
(2/11)
V850E/IA1
V850E/IA2
Item
PD703116
PD70F3116
PD703114
PD70F3114
V850E1
V850E1
CPU core
62MIPS (@ 50 MHz)
256 KB (mask ROM)
50MIPS (@ 40 MHz)
128 KB (mask ROM)
CPU performance (Dhrystone)
Internal ROM
256 KB (flash memory)
128 KB (flash memory)
10 KB
24 bits
16 bits
0 to 7
6 KB
Internal RAM
22 bits
16 bits
0 to 7
External
bus interface
Address bus
Data bus
Programmable
waits
External: 20 (14)Note
Internal: 46
External: 16 (12)Note
External: 42
Interrupt sources
DSP function
0.02 to 0.04µs (@ 50 MHz)
0.025 to 0.05µs
32×32 64
(@ 40 MHz)
0.06µs (@ 50 MHz)
0.075µs (@ 40 MHz)
32×32+32 32
----
----
----
----
16×16 32
16×16+32 32
16-bit 3-phase sine wave PWM timer × 2 ch
16-bit encoder counter/timer × 2 ch
16-bit timer/counter × 2 ch
16-bit timer/event counter × 1 ch
16-bit interval timer × 1 ch
16-bit 3-phase sine wave PWM timer × 2 ch
16-bit encoder counter/timer × 1 ch
16-bit timer/counter × 2 ch
16-bit timer/event counter × 1 ch
16-bit interval timer × 1 ch
Timer/counter (RPU)
2 ch
----
1 ch
----
Serial interface
(SIO)
CSI
CSI/I2C
----
1 ch
1 ch
CSI/UART
UART
3 ch
4 ch
3 ch
Dedicated BRG
8 ch (10-bit resolution), 2 units
4 ch
6 ch (10-bit resolution): A/D converter 0, 8 ch (10-bit resolution): A/D converter 1
4 ch
A/D converter
DMA controller
----
----
Real-time output port
Ports
75
47
I/O
8
6
Input
Memory access control function (SRAM, ROM connectable)
Memory access control function (SRAM, ROM connectable)
Other peripheral I/O functions
HALT, IDLE, STOP
4 to 50 MHz
HALT, IDLE, STOP
4 to 40 MHz
Power save function
Operating frequency
Internal unit: 3.3 V, A/D converter: 5 V, external pin: 5 V
630 mW (For internal unit: 3.3 V, external pin: 5 V, 50 MHz)
5 V (Internal unit: 3.3 V, A/D converter: 5 V, external pin: 5 V)
(On-chip regulator)
Power supply voltage
440mW
Power consumption (Typ.)
144-pin plastic LQFP (20 × 20 mm)
100-pin plastic LQFP (14 × 14 mm)
Package
Note Number of external interrupts that can be used to release STOP mode
Pamphlet U15412EJ1V0PF
43
(3/11)
V850E/MS1
PD703100-40
PD703100-33
PD703101-33
PD703102-33
PD70F3102-33
Item
V850E
----
CPU core
43 MIPS (@ 33 MHz)
CPU performance (Dhrystone)
Internal ROM
None
96 KB
128 KB
(mask ROM)
128 KB
(flash memory)
(mask ROM)
4 KB
Internal RAM
24 bits
16 bits
0 to 7
External
bus interface
Address bus
Data bus
Programmable
waits
External: 25 (1)Note
Internal: 47
Interrupt sources
DSP function
0.03 to 0.06µs (@ 33 MHz)
0.09µs (@ 33 MHz)
0.025 to 0.05µs
32×32 64
(@ 40 MHz)
0.075µs
32×32+32 32
(@ 40 MHz)
----
----
16×16 32
16×16+32 32
16-bit timer/event counter × 6 ch
16-bit interval timer × 2 ch
Timer/counter (RPU)
2 ch
----
Serial interface
(SIO)
CSI
CSI/I2C
2 ch
----
CSI/UART
UART
3 ch
Dedicated BRG
8 ch (10-bit resolution)
4 ch
A/D converter
DMA controller
----
Real-time output port
Ports
114
I/O
9
Input
Memory access control function
Other peripheral I/O functions
(EDO DRAM, SRAM, page ROM, etc., directly connectable)
HALT, IDLE, STOP
Power save function
Operating frequency
2 to 40 MHz
2 to 33 MHz
Internal unit: 3.3 V, A/D converter: 5 V
External pin: 5 V
Power supply voltage
540mW
430mW
Power consumption (Typ.)
(@ 40 MHz)
(@ 33 MHz)
144-pin plastic LQFP (20 × 20 mm)
Package
Note Number of external interrupts that can be used to release STOP mode
Pamphlet U15412EJ1V0PF
44
(4/11)
V850E/MS1
V850E/MS2
PD703130
PD703100A-40
PD703100A-33
PD703101A-33
PD703102A-33
PD70F3102A-33
Item
V850E
V850E
CPU core
----
----
43MIPS (@ 33 MHz)
CPU performance (Dhrystone)
Internal ROM
None
None
96 KB
128 KB
(mask ROM)
128 KB
(flash memory)
(mask ROM)
4 KB
4 KB
Internal RAM
24 bits
16 bits
0 to 7
24 bits
16 bits
0 to 7
External
bus interface
Address bus
Data bus
Programmable
waits
External: 25 (1)Note
Internal: 47
External: 10 (1)Note
Internal: 35
Interrupt sources
DSP function
0.03 to 0.06µs (@ 33 MHz)
0.09µs (@ 33 MHz)
0.03 to 0.06µs
0.025 to 0.05µs
32×32 64
(@ 33 MHz)
(@ 40 MHz)
0.075µs
0.09µs
32×32+32 32
(@ 40 MHz)
(@ 33 MHz)
----
----
----
----
16×16 32
16×16+32 32
16-bit timer/event counter × 6 ch
16-bit interval timer × 2 ch
16-bit timer/
Timer/counter (RPU)
event counter
× 4 ch
16-bit interval timer
× 2 ch
2 ch
----
----
----
Serial interface
(SIO)
CSI
CSI/I2C
2 ch
----
2 ch
----
CSI/UART
UART
3 ch
2 ch
Dedicated BRG
8 ch (10-bit resolution)
4 ch
4 ch (10-bit resolution)
4 ch
A/D converter
DMA controller
----
----
76
5
Real-time output port
Ports
114
I/O
9
Input
Memory access control function
Memory access control
function (EDO DRAM,
SRAM, page ROM, etc.,
directly connectable)
Other peripheral I/O functions
(EDO DRAM, SRAM, page ROM, etc., directly connectable)
HALT, IDLE, STOP
HALT, IDLE, STOP
10 to 33MHz
Power save function
Operating frequency
2 to 40MHz
2 to 33MHz
Internal unit: 3.3 V,
A/D converter: 5 V
External pin: 5 V
Internal unit: 3.3 V, A/D converter: 3.3 V
External pin: 3.3 V
Power supply voltage
330mW
381mW
270mW
Power consumption (Typ.)
(@ 40 MHz)
(@ 33 MHz)
(@ 33 MHz)
144-pin plastic LQFP
144-pin plastic LQFP (20 × 20 mm)
157-pin plastic FBGA (14 × 14 mm)
100-pin plastic LQFP
Package
(20 × 20 mm)
(14 × 14 mm)
Note Number of external interrupts that can be used to release STOP mode
Pamphlet U15412EJ1V0PF
45
(5/11)
V850ES/SA2
V850ES/SA3
PD703201/
PD703201Y
PD70F3201/
PD70F3201Y
PD703204/
PD703204Y
PD70F3204/
PD70F3204Y
Item
V850ES
21 MIPS (@ 17 MHz)/16 MIPS (@ 13.5 MHz)
CPU core
CPU performance (Dhrystone)
Internal ROM
256 KB
256 KB
(flash memory)
256 KB
256 KB
(flash memory)
(mask ROM)
(mask ROM)
16 KB
22 bits
8/16 bits
0 to 7
Internal RAM
24 bits
External
bus interface
Address bus
Data bus
Programmable
waits
External: 8 (8)Note 1
External: 8 (8)Note 1
Interrupt sources
DSP function
Internal 30 (Y products: 31)
Internal: 31 (Y products: 32)
32×32 64
0.24 to 0.29µs (@ 17 MHz)
32×32+32 32
0.35µs (@ 17 MHz)
0.06 to 0.12µs (@ 17 MHz)
0.18µs (@ 17 MHz)
16×16 32
16×16+32 32
16-bit timer/event counter × 2 ch
Timer/counter (RPU)
8-bit timer/event counter × 4 ch (usable as 16-bit timer/event counter × 2 ch)
2 ch
1 ch
3 ch
1 ch
Serial interface
(SIO)
CSI
CSI/I2CNote 2
CSI/UART
UART
1 ch
1 ch
1 ch
1 ch
2 ch (UART-dedicated)
2 ch
Dedicated BRG
12 ch (10-bit resolution)
4 ch
16 ch (10-bit resolution)
A/D converter
DMA controller
----
68
14
Real-time output port
Ports
84
18
I/O
Input
Other peripheral I/O functions
Real-time counter (for watch): 1 ch
Watchdog timer: 1 ch
HALT, IDLE, STOP
Power save function
Operating frequency
When using main clock: 2 to 17 MHz (@ 2.4 V)/2 to 13.5 MHz (@ 2.3 V)
When using subclock: 32.768 kHz (only real-time counter operating)
2.3 to 2.7 V (@ 17 MHz)/2.2 to 2.7 V (@ 13.5 MHz)
When using main clock: 30 mW* (@ 2.5 V, 17 MHz)
Power supply voltage
Power consumption (Typ.)
100-pin plastic LQFP (14 × 14 mm)
121-pin plastic FBGA (12 × 12 mm)
Package
Notes1. Number of external interrupts that can be used to release STOP mode
2. Only Y products have an on-chip I2C bus interface.
CSI/I2C : µPD703201Y, 703204Y, 70F3201Y, 70F3204Y
CSI
: µPD703201, 703204, 70F3201, 70F3204
Remark Values with * are target values.
Pamphlet U15412EJ1V0PF
46
(6/11)
V850/SA1
PD703014A/
PD703014AY
PD703014B/
PD703014BY
PD703015A/
PD703015AY
PD70F3015B/
PD70F3015BY
PD703017A/
PD703017AY
PD70F3017A/
PD70F3017AY
PD703015B/
PD703015BY
Item
V850
CPU core
23MIPS (@ 20 MHz)/19MIPS (@ 17 MHz)
CPU performance (Dhrystone)
Internal ROM
64 KB
128 KB
(mask ROM)
128 KB
256 KB
256 KB
(mask ROM)
(flash memory)
(mask ROM)
(flash memory)
4 KB
8 KB
Internal RAM
22 bits
16 bits
External
bus interface
Address bus
Data bus
0 to 3
Programmable
waits
External: 9 (6)Note 1
Internal: 22
Interrupt sources
DSP function
----
32×32 64
----
32×32+32 32
0.05 to 0.10µs (@ 20 MHz)
16×16 32
0.15
µs (@ 20 MHz)
16×16+32 32
16-bit timer/event counter × 2 ch
Timer/counter (RPU)
8-bit timer/event counter × 4 ch (usable as 16-bit timer/event counter × 2 ch)
1 ch
Serial interface
(SIO)
CSI
CSI/I2CNote 2
CSI/UART
UART
1 ch
1 ch
1 ch
2 ch (UART-dedicated)
12 ch (10-bit resolution)
Dedicated BRG
A/D converter
DMA controller
3 ch (only for internal RAM
on-chip peripheral I/O)
8-bit × 1 ch or 4-bit × 2 ch
Real-time output port
Ports
72
13
I/O
Input
Watch timer: 1 ch
Other peripheral I/O functions
Watchdog timer: 1 ch
HALT, IDLE, STOP
Power save function
Operating frequency
Using main clock: 2 to 20 MHz (@ 3.3 V)/2 to 17 MHz (@ 3 V)
Using subclock: 32.768 kHz
3.0 to 3.6 V (@ 20 MHz)/2.7 to 3.6 V (@ 17 MHz)
Power supply voltage
Using main clock: 66 mW (@ 3.3 V, 20 MHz)/56 mW (@ 3.3 V, 17 MHz)
Using main clock:
Using main clock:
Using main clock:
Power consumption (Typ.)
105 mW(@ 3.3 V, 20 MHz)/ 66 mW (@ 3.3 V, 20 MHz)/ 105 mW (@ 3.3 V, 20 MHz)/
99 mW (@ 3.3 V, 17 MHz)
56 mW (@ 3.3 V, 17 MHz) 99 mW (@ 3.3 V, 17 MHz)
100-pin plastic LQFP (14 × 14 mm)Note 3
121-pin plastic FBGA (12 × 12 mm)Note 4
Package
Notes1. Number of external interrupts that can be used to release STOP mode
2. Only Y products have an on-chip I2C bus interface.
CSI/I2C : µPD703014AY, 703014BY, 703015AY, 703015BY, 703017AY, 70F3015BY, 70F3017AY
CSI
: µPD703014A, 703014B, 703015A, 703015B, 703017A, 70F3015B, 70F3017A
3. µPD703014B, 703014BY, 703015B, 703015BY, 703017A, 703017AY, 70F3015B, 70F3015BY, 70F3017A, 70F3017AY
4. µPD703014A, 703014AY, 703015A, 703015AY, 703017A, 703017AY, 70F3017A, 70F3017AY
Caution The maximum operating frequency of the I2C bus interface is 17 MHz.
Pamphlet U15412EJ1V0PF
47
(7/11)
V850/SV1
PD703041/
PD703041Y
PD703039/
PD703039Y
PD703040/
PD703040Y
PD70F3040/
PD70F3040Y
PD703038/
PD703038Y
PD70F3038/
PD70F3038Y
Item
CPU core
V850
23 MIPS (@ 20 MHz)/18 MIPS (@ 16 MHz)
CPU performance (Dhrystone)
Internal ROM
192 KB
256 KB
256 KB
(flash memory)
384 KB
(mask ROM)
384 KB
(flash memory)
(mask ROM)
(mask ROM)
Internal RAM
8 KB
16 KB
External
bus interface
Address bus
22 bits
16 bits
Data bus
Programmable
waits
0 to 3
Interrupt sources
DSP function
External: 9 (6)Note 1
Internal: 43 (Y products: 44)
32×32 64
----
----
32×32+32 32
16×16 32
0.05 to 0.10µs (@ 20 MHz)
0.15µs (@ 20 MHz)
16×16+32 32
Timer/counter (RPU)
24-bit timer/event counter × 2 ch
16-bit timer/event counter × 2 ch
8-bit timer/event counter × 8 ch (usable as 16-bit timer/event counter × 4 ch)
Serial interface
(SIO)
CSI
1 ch
CSI/I2CNote 2
CSI/UART
UART
2 ch
2 ch
----
Dedicated BRG
3 ch
A/D converter
DMA controller
16 ch (10-bit resolution )
6 ch (only for internal RAM
on-chip peripheral I/O)
Real-time output port
Ports
8-bit × 2 ch or 4-bit × 4 ch
I/O
135
Input
16
Vsync/Hsync separator
Other peripheral I/O functions
Watch timer: 1 ch
Watchdog timer: 1 ch
PWM: 4 ch (12 to 16-bit resolution)
HALT, IDLE, STOP
Power save function
Operating frequency
4 to 20 MHz (@ 3.3 V)/4 to 16 MHz (@ 3 V)
3.1 to 3.6 V (@ 20 MHz)/2.7 to 3.6 V (@ 16 MHz)
82 mW (@ 3.3 V, 20 MHz)/72 mW (@ 3.3 V, 16 MHz)
Power supply voltage
148 mW (@ 3.3 V, 20 MHz)/ 82 mW (@ 3.3 V, 20 MHz)
132 mW (@ 3.3 V, 16 MHz) 72 mW (@ 3.3 V. 16 MHz)
148 mW (@ 3.3 V, 20 MHz)
132 mW (@ 3.3 V, 16 MHz)
Power consumption (Typ.)
Package
176-pin plastic LQFP
176-pin plastic LQFP (24 × 24 mm)
180-pin plastic FBGA (13 × 13 mm)
180-pin plastic FBGA (13 × 13 mm)
(24 × 24 mm)
Notes1. Number of external interrupts that can be used to release STOP mode
2. Only Y products have an on-chip I2C bus interface.
CSI/I2C : µPD703038Y, 703039Y, 703040Y, 703041Y, 70F3038Y, 70F3040Y
CSI
: µPD703038, 703039, 703040, 703041, 70F3038, 70F3040
Caution The maximum operating frequency of the I2C bus interface is 17 MHz.
Pamphlet U15412EJ1V0PF
48
(8/11)
V850/SC1
V850/SC2
V850/SC3
V850/SC1, V850/SC2, V850/SC3
PD703068Y
PD703069Y
PD703088Y
PD703089Y
PD70F3089Y
Item
V850
V850
V850
V850
CPU core
23MIPS (@ 20 MHz)
21MIPS (@ 19 MHz)
18MIPS (@ 16 MHz)
23MIPS (@ 20 MHz)
CPU performance (Dhrystone)
Internal ROM
512 KB
512 KB
512 KB
512 KB
(mask ROM)
(mask ROM)
(mask ROM)
(flash memory)
24 KB
22 bits
16 bits
0 to 3
24 KB
22 bits
16 bits
0 to 3
24 KB
22 bits
16 bits
0 to 3
24 KB
22 bits
16 bits
0 to 3
Internal RAM
External
bus interface
Address bus
Data bus
Programmable
waits
External: 12 (9)Note
Internal: 39
External: 12 (9)Note
Internal: 41
External: 12 (9)Note
Internal: 43
External: 12 (9)Note
Internal: 46
External: 12 (9)Note
Internal: 46
Interrupt sources
DSP function
----
----
----
----
32×32 64
----
----
----
----
32×32+32 32
0.05 to 0.10µs (@ 20 MHz)
0.15µs (@ 20 MHz)
0.053 to 0.106µs (@ 19 MHz) 0.06 to 0.12µs (@ 16 MHz)
0.05 to 0.10µs (@ 20 MHz)
0.15µs (@ 20 MHz)
16×16 32
0.159µs (@ 19 MHz)
0.18µs (@ 16 MHz)
16×16+32 32
16-bit timer/
16-bit timer/
16-bit timer/event counter × 10 ch
16-bit timer/
Timer/counter (RPU)
event counter × 10 ch
event counter × 10 ch
event counter × 10 ch
2 ch
2 ch
2 ch
2 ch
2 ch
2 ch
2 ch
2 ch
Serial interface
(SIO)
CSI
CSI/I2C
2 ch
2 ch
2 ch
2 ch
2 ch
2 ch
2 ch
2 ch
CSI/UART
UART
5 ch
5 ch
5 ch
5 ch
Dedicated BRG
12 ch (10-bit resolution)
12 ch (10-bit resolution)
12 ch (10-bit resolution)
12 ch (10-bit resolution)
A/D converter
DMA controller
6 ch (only for internal RAM
on-chip peripheral I/O)
6 ch (only for internal RAM
on-chip peripheral I/O)
6 ch (only for internal RAM
on-chip peripheral I/O)
6 ch (only for internal RAM
on-chip peripheral I/O)
----
----
----
----
Real-time output port
Ports
112
12
112
112
112
I/O
12
12
12
Input
----
IEBus (simple version): 1 ch
FCAN : 1 ch
FCAN : 2 ch
IEBus (simple version): 1 ch/FCAN: 2 ch
Other peripheral I/O functions
Watch timer: 1 ch
Watch timer: 1 ch
Watch timer: 1 ch
Watch timer: 1 ch
Watchdog timer: 1 ch
Watchdog timer: 1 ch
Watchdog timer: 1 ch
Watchdog timer: 1 ch
HALT, IDLE, STOP
HALT, IDLE, STOP
HALT, IDLE, STOP
HALT, IDLE, STOP
Power save function
Operating frequency
Using main clock:
Using main clock:
Using main clock:
Using main clock:
4 to 20 MHz (@ 5 V)
Using subclock: 32.768 kHz
4 to 19 MHz (@ 5 V)
Using subclock: 32.768 kHz
4 to 16 MHz (@ 5 V)
Using subclock: 32.768 kHz
4 to 20 MHz (@ 5 V)
Using subclock: 32.768 kHz
3.5 to 5.5 V
3.5 to 5.5 V
3.5 to 5.5 V (A/D converter: 4.5 to 5.5 V)
4.0 to 5.5 V
Power supply voltage
(A/D converter: 4.5 to 5.5 V)
(A/D converter: 4.5 to 5.5 V)
(A/D converter: 4.5 to 5.5 V)
Using main clock:
Using main clock:
Using main clock: 110 mW* (@ 5 V, 16 MHz)
Using main clock:
Power consumption (Typ.)
125 mW* (@ 5 V, 20 MHz)
120 mW* (@ 5 V, 19 MHz)
150 mW* (@ 5 V, 20 MHz)
144-pin plastic LQFP
144-pin plastic LQFP
144-pin plastic LQFP (20 × 20 mm)
144-pin plastic LQFP
Package
(20 × 20 mm)
(20 × 20 mm)
(20 × 20 mm)
Note Number of external interrupts that can be used to release STOP mode
Remark Values with * are target values.
Pamphlet U15412EJ1V0PF
49
(9/11)
V850/SF1
V850/SB1
PD70F3033A/
PD703033AY PD70F3033AY
PD703078Y
PD703079Y
PD70F3079Y
PD703031A/
PD703031AY
PD703033A/
PD703032A/
PD703032AY
PD70F3032A/
PD70F3032AY
PD703030A/
PD703030AY
Item
CPU core
V850
V850
CPU performance (Dhrystone)
Internal ROM
18MIPS (@ 16 MHz)
23MIPS (@ 20 MHz)
128 KB 256 KB
256 KB
256 KB
256 KB
384 KB
512 KB
512 KB
(mask ROM)
(flash memory) (mask ROM)
(mask ROM)
(flash memory) (mask ROM)
(mask ROM)
(flash memory)
Internal RAM
16 KB
22 bits
16 bits
0 to 3
12 KB
22 bits
16 bits
0 to 3
16 KB
20 KB
24 KB
External
bus interface
Address bus
Data bus
Programmable
waits
Interrupt sources
DSP function
External: 9 (6)Note 1 External: 9 (6)Note 1
External: 9 (6)Note 1
Internal: 32
Internal: 35
Internal: 30 (Y products: 31)
32×32 64
----
----
32×32+32 32
----
----
16×16 32
0.06 to 0.12µs (@ 16 MHz)
0.18µs (@ 16 MHz)
0.05 to 0.10µs (@ 20 MHz)
0.15µs (@ 20 MHz)
16×16+32 32
16-bit timer/event counter × 8 ch
16-bit timer/event counter × 2 ch
Timer/counter (RPU)
8-bit timer/event counter × 4 ch (usable as 16-bit timer/event counter × 2 ch)
8-bit timer × 2 ch (usable as 16-bit timer × 1 ch)
Serial interface
(SIO)
CSI
1 ch
1 ch
CSI/I2CNote 2
CSI/UART
UART
1 ch
2 ch
2 ch
2 ch
----
----
Dedicated BRG
3 ch
3 ch
A/D converter
DMA controller
12 ch (10-bit resolution)
12 ch (10-bit resolution)
6 ch (only for internal RAM on-chip peripheral I/O) 6 ch (only for internal RAM on-chip peripheral I/O)
Real-time output port
Ports
----
8 bits × 1 or 4 bits × 2
I/O
72
71
12
----
Input
12
FCAN : 1 ch
Watch timer
FCAN : 2 ch
1 ch
Other peripheral I/O functions
:
1 ch
Watch timer: 1 ch
Watchdog timer
:
Watchdog timer: 1 ch
HALT, IDLE, STOP
HALT, IDLE, STOP
Power save function
Operating frequency
Using main clock: 4 to 16 MHz (@ 5 V)
Using subclock: 32.768 kHz
Using main clock: 2 to 20 MHz (@ 5 V)
Using subclock: 32.768 kHz
Power supply voltage
4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V)
(@ 16 MHz)
4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V)
Using main clock:
Using main clock:
165 mW
Using main clock: 75 mW (mask ROM)/
125 mW (flash memory)(@ 5 V, 16 MHz)
Using main clock:
Using main clock:
Power consumption (Typ.)
165 mW
125 mW (@ 5 V, 20 MHz)
125 mW (@ 5 V, 20 MHz)
(@ 5 V, 20 MHz)
(@ 5 V, 20 MHz)
Package
100-pin plastic LQFP (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic LQFP (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
Notes1. Number of external interrupts that can be used to release STOP mode
2. Only Y products have an on-chip I2C bus interface.
CSI/I2C : µPD703030AY, 703031AY, 703032AY, 703033AY, 703078Y, 703079Y, 70F3032AY, 70F3033AY, 70F3079Y
CSI
: µPD703030A, 703031A, 703032A, 703033A, 70F3032A, 70F3033A
Pamphlet U15412EJ1V0PF
50
(10/11)
V850/SB2
PD703034A/
PD703034AY
PD703035A/
PD703035AY
PD70F3035A/
PD70F3035AY
PD703036A/
PD703036AY
PD703037A/
PD703037AY
PD70F3037A/
PD70F3037AY
Item
CPU core
V850
CPU performance (Dhrystone)
Internal ROM
15MIPS (@ 13 MHz)
128 KB
256 KB
256 KB
(flash memory)
384 KB
512 KB
512 KB
(mask ROM)
(mask ROM)
(mask ROM)
(mask ROM)
(flash memory)
Internal RAM
12 KB
22 bits
16 bits
16 KB
20 KB
24 KB
External
bus interface
Address bus
Data bus
Programmable
waits
0 to 3
Interrupt sources
DSP function
External: 9 (6)Note 1
Internal: 32 (Y products: 33)
32×32 64
----
----
32×32+32 32
16×16 32
0.077 to 0.154µs (@ 13 MHz)
0.231µs (@ 13 MHz)
16×16+32 32
Timer/counter (RPU)
16-bit timer/event counter × 2 ch
8-bit timer/event counter × 4 ch (usable as 16-bit timer/event counter × 2 ch)
8-bit timer × 2 ch (usable as 16-bit timer × 1 ch)
Serial interface
(SIO)
CSI
1 ch
CSI/I2CNote 2
CSI/UART
UART
2 ch
2 ch
----
Dedicated BRG
3 ch
A/D converter
DMA controller
12 ch (10-bit resolution)
6 ch (only for internal RAM
on-chip peripheral I/O)
Real-time output port
Ports
8 bits × 1 or 4 bits × 2
I/O
71
Input
12
IEBus (simple version)
Other peripheral I/O functions
Watch timer: 1 ch
Watchdog timer: 1 ch
HALT, IDLE, STOP
Power save function
Operating frequency
Using main clock: 2 to 13 MHz (@ 5 V)
Using subclock: 32.768 kHz
4.0 to 5.5 V (A/D converter: 4.5 to 5.5 V)
Power supply voltage
Power consumption (Typ.)
Using main clock: 75 mW
(@ 5 V, 13 MHz)
Using main clock:
125 mW
Using main clock:
Using main clock:
125 mW
75 mW (@ 5 V, 13 MHz)
(@ 5 V, 13 MHz)
(@ 5 V, 13 MHz)
Package
100-pin plastic LQFP (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
100-pin plastic QFP (14 × 20 mm)
Notes1. Number of external interrupts that can be used to release STOP mode
2. Only Y products have an on-chip I2C bus interface.
CSI/I2C : µPD703034AY, 703035AY, 703036AY, 703037AY, 70F3035AY, 70F3037AY
CSI
: µPD703034A, 703035A, 703036A, 703037A, 70F3035A, 70F3037A
Pamphlet U15412EJ1V0PF
51
(11/11)
V853
PD703003A
PD703004A
PD703025A
PD70F3003A
PD70F3025A
Item
V850
CPU core
38MIPS (@ 33 MHz)
CPU performance (Dhrystone)
Internal ROM
128 KB
96 KB
(mask ROM)
256 KB
128 KB
256 KB
(mask ROM)
(mask ROM)
(flash memory)
(flash memory)
4 KB
8 KB
4 KB
8 KB
Internal RAM
20 bits
16 bits
External
bus interface
Address bus
Data bus
0 to 3
Programmable
waits
External: 17 (1)Note
Internal: 32
Interrupt sources
DSP function
----
32×32 64
----
32×32+32 32
0.03 to 0.06µs (@ 33 MHz)
0.09µs (@ 33 MHz)
16×16 32
16×16+32 32
16-bit timer/event counter × 4 ch
16-bit timer × 1 ch
Timer/counter (RPU)
2 ch
Serial interface
(SIO)
CSI
CSI/I2C
----
2 ch
CSI/UART
UART
----
3 ch
Dedicated BRG
8 ch (10-bit resolution)
----
A/D converter
DMA controller
----
67
8
Real-time output port
Ports
I/O
Input
PWM: 2 ch (8/9/10/12-bit resolution)
D/A converter: 2 ch
Other peripheral I/O functions
HALT, IDLE, STOP
5 to 33 MHz (@ 5 V)
Power save function
Operating frequency
4.5 to 5.5V
Power supply voltage
365 mW
450 mW
425 mW
480 mW
Power consumption (Typ.)
(@ 5 V, 33 MHz)
(@ 5V, 33 MHz)
(@ 5 V, 33 MHz)
(@ 5 V, 33 MHz)
100-pin plastic LQFP (14 × 14 mm)
Package
Note Number of external interrupts that can be used to release STOP mode
Pamphlet U15412EJ1V0PF
52
Comfortable Development Environment
Development Flow
Product planning
System design
PM
Hardware design
Software design
Coding
RX850, RX850 Pro
Fabrication
Compiling/
assembly
CA850
SM850
Standalone testing
Debugging
+RD850, +RD850 Pro
+AZ850
ID850
System debugging
System evaluation
Commercialization
IE
DF703xxx
Hardware tools
Software tools
Development Tools (1/3)
ꢁSoftware tools
Product Name
SP850
Software package
C compiler
CA850Note 1
Device file
DF703xxxNote 1
PMNotes 1, 2
ID850Note 1
Project Manager
Integrated debugger
System simulator
Real-time OS
SM850Note 1
RX850, RX850 Pro
RD850, RD850 ProNote 3
AZ850Note 1
Task debugger
System performance analyzer
Middleware
AP703000-Bxxx, AP703100-Bxxx
Notes 1. Packaged in SP850
2. Included with CA850
3. Included with RX850, RX850 Pro
Remark For details, refer to the V800 SeriesTM Development Environment Pamphlet (U10782E).
Pamphlet U15412EJ1V0PF
53
Development Tools (2/3)
ꢁHardware tools
Target Device
In-Circuit Emulator
Device Name
V850E/MA1
Package
144-pin plastic LQFP (20 × 20 mm)
Main Unit
Emulation Board
IE-703107-MC-EM1
IE-V850E-MC-A
161-pin plastic FBGA (13 × 13 mm)
100-pin plastic LQFP (14 × 14 mm)
IE-703107-MC-EM1
+
CSSOCKET161A1413N01S1 (under development)Note 1
LSPACK161A1413N01 (under development)Note 1
CSICE161A1413N02 (under development)Note 1
V850E/MA2
IE-703107-MC-EM1
+
VP-V850E/MA1-MA2 (under development)Note 2
V850E/IA1
144-pin plastic LQFP (20 × 20 mm)
100-pin plastic LQFP (14 × 14 mm)
144-pin plastic LQFP (20 × 20 mm)
144-pin plastic LQFP (20 × 20 mm)
IE-V850E-MC
IE-703102-MC
IE-703116-MC-EM1
IE-703114-MC-EM1
IE-703102-MC-EM1
IE-703102-MC-EM1-A
V850E/IA2
V850E/MS1 (5V)
V850E/MS1 (3.3V)
IE-703102-MC-EM1-A
+
CSPACK157A1614N01Note 1
CSICE157A1614N01Note 1
157-pin plastic FBGA (14 × 14 mm)
V850E/MS2 (5V)
V850/SA1
100-pin plastic LQFP (14 × 14 mm)
IE-703102-MC-EM1
+
VP-V850E/MS1-MS2Note 2
100-pin plastic LQFP (14 × 14 mm)
121-pin plastic FBGA (12 × 12 mm)
IE-703002-MC
IE-703017-MC-EM1
IE-703017-MC-EM1
+
CSPACK121A1312N02Note 1
CSICE121A1312N02Note 1
V850/SB1, V850/SB2
100-pin plastic LQFP (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
IE-703037-MC-EM1
IE-703037-MC-EM1
+
NEXB-100SD/RBNote 1
V850/SV1
176-pin plastic LQFP (24 × 24 mm)
180-pin plastic FBGA (13 × 13 mm)
IE-703040-MC-EM1
IE-703040-MC-EM1
+
CSSOCKET180A1513N01NNote 1
CSSOCKET180A1513N01S01Note 1
EXC-180A/SV1Note 1
100-pin plastic LQFP (14 × 14 mm)
100-pin plastic QFP (14 × 20 mm)
IE-703079-MC-EM1
V850/SF1
IE-703079-MC-EM1
+
SWEX100SD/GF-N17DNote 1
NQPACK100RBNote 1
YQPACK100RBNote 1
HQPACK100RBNote 1
YQSOCKET100RBNNote 1
YQGUIDENote 1
V850/SC1, V850/SC2, V850/SC3
V853
144-pin plastic LQFP (20 × 20 mm)
100-pin plastic LQFP (14 × 14 mm)
IE-703089-MC-EM1
IE-703003-MC-EM1
Notes 1. Tokyo Eletech Corp.
2. Naito Densei Machida Mfg. Co., Ltd.
Remarks 1. The following parts are required as common products.
• PC interface board
: IE-70000-PCI-IF-A or IE-70000-CD-IF-A
• Power supply
: IE-70000-MC-PS-B
2. For details, refer to the V800 SeriesTM Development Environment Pamphlet (U10782E).
Pamphlet U15412EJ1V0PF
54
Development Tools (3/3)
V850E/MA1, V850E/MA2, V850E/IA1, V850E/IA2 hardware tool configuration example
ꢀ
In-circuit emulator (main unit)
Emulation board
Power supply unit
Conversion adapter/conversion socket
To common interface block
V850E/MS1, V850E/MS2 hardware tool configuration example
ꢀ
In-circuit emulator (main unit)
Emulation board
Power supply unit
Conversion adapter/conversion socket
To common interface block
V850/SA1, V850/SB1, V850/SB2, V850/SV1, V850/SF1, V850/SC1 ,V850/SC2, V850/SC3, V853 hardware tool configuration example
ꢀ
In-circuit emulator (main unit)
Emulation board
Power supply unit
Conversion adapter/conversion socket
To common interface block
Pamphlet U15412EJ1V0PF
55
Development Environment (1/2)
ꢁ Development environment using in-circuit emulator
Debugger
Analyzer
Real-time OS
In-circuit emulator
Compiler
Task debugger
Integrated development
environment
NEC
NEC
ID850
NEC
CA850
Note
RX850
AZ850
Note The RD850, RD850 Pro, and AZ850 can be used with
NEC
RX850 Pro
ID850, MULTI, PARTNER, and WATCHPOINT.
V850 IE Series
NEC
GHS
RD850 Note
CATS
ID850
RD850 Pro Note
CCV850
CCV850E
Remarks 1. ATI
CATS
: Accelerated Technology, Inc.
: Communication And Technology
Systems, Inc.
ZIPC850
GHS
TM
ATI
Nucleus Plus
Metrowerks
Midas Lab
MULTI
®
CodeWarrior
GAIO
: Gaio Technology Co., Ltd.
: Green Hills SoftwareTM, Inc.
: Kyoto Microcomputer Corporation
: Metrowerks Corporation
: Midas Lab Co., Ltd.
RTE-V85x-IE Series
AZ850
GHS
Red Hat
GNU
Mispo
KMC
®
PARTNER
AZ850
NORTi
3
Metrowerks
Midas Lab
Mispo
GAIO
KMC
Sophia Systems
Sophia Systems
G-OS
exeGCC
: MiSPO, Inc.
WATCHPOINT TM
UniSTAC Series
Red Hat
: Red Hat Corporation
GAIO
AZ850
YDC
Sophia Systems: Sophia Systems Co., Ltd.
XCC-V
XASS-V
advice Series
YDC
YDC
: Yokogawa Digital Computer
Corporation
micro VIEW-G
GAIO
2. For details, refer to the V800 Series Development
XDDI-V
Environment Pamphlet (U10782E).
ꢁ Development environment using ROM emulator and evaluation board
Evaluation board
Low-cost evaluation board
Real-time OS
Compiler
Debugger
Analyzer
ROM emulator
(
)
limited functions
Evaluation board
Task debugger
NEC
NEC
CA850
Cosmo
RX850
RX850 Pro
CEB-V85x Series
KMC
RD850 Note
exeGCC
PARTNER
AZ850 Note
RD850 Pro Note
Note The RD850, RD850 Pro, and AZ850 can be used with
ID850, MULTI, and PARTNER.
GHS
CCV850
CCV850E
Remarks 1. ATI
Cosmo
: Accelerated Technology, Inc.
: Cosmo Co., Ltd.
GAIO
: Gaio Technology Co., Ltd.
: Green Hills SoftwareTM, Inc.
: Kyoto Microcomputer Corporation
: Lightwell Co., Ltd.
ATI
KMC
GHS
Nucleus Plus
PARTNER-ET II
GHS
Metrowerks
KMC
Midas Lab
Code Warrior
MULTI
AZ850
Lightwell
Metrowerks
Midas Lab
Midoriya
Mispo
RTE-V85x-PC/CB Series
Midoriya
: Metrowerks Corporation
: Midas Lab Co., Ltd.
EMUSE
: Midoriya Electric Co., Ltd.
: MiSPO, Inc.
Lightwell
Mispo
Red Hat
GNU
MDX700
NORTi3
Red Hat
WRS
: Red Hat Corporation
: Wind River Systems, Inc.
WRS
2. For details, refer to the V800 Series Development
TornadoTM
GNU
CrossWind
Environment Pamphlet (U10782E).
Pamphlet U15412EJ1V0PF
56
Development Environment (2/2)
ꢁ Development environment using simulator
Real-time OS
Compiler
Debugger
Simulator
Analyzer
Co-simulation tool
Task debugger
Integrated development
environment
NEC
NEC
NEC
SM850
RX850
RX850 Pro
CA850
AZ850
RD850
RD850 Pro
NEC
SM850
ZIPC850
CATS
YOKOGAWA
GHS
Virtual ICE ®
MULTI
Synopsys
Synopsys Eaglei®
GHS
Remarks 1. ATI
CATS
: Accelerated Technology, Inc.
: Communication And Technology
Systems, Inc.
CCV850
ATI
Nucleus Plus
GAIO
: Gaio Technology Co., Ltd.
: Green Hills Software, Inc.
: MiSPO, Inc.
GHS
Mispo
Mispo
NORTi3
GAIO
XCCV/XASS-V
GAIO
YOKOGAWA
Synopsys
: Yokogawa Electric Corporation
: Nihon Synopsys, Inc.
XDEB
GAIO
2. For details, refer to the V800 Series Development
G-OS
Environment Pamphlet (U10782E).
Pamphlet U15412EJ1V0PF
57
Software Package (SP850)
C Compiler (CA850)
ꢁ Product configuration
ꢁ Features
The SP850 software package consists of the following software development
•Complies with ANSI-C, a C language standard.
tools.
•Supports libraries for embedded systems
•C compiler (CA850)
•Compact code size and faster execution speed can be realized through
powerful optimization
•Project Manager (PM)
•Integrated debugger (ID850)
•System simulator (SM850)
•Utilities useful for embedded systems (ROMization processor, etc.)
•Description of embedded systems in C language (specification of memory
allocation and I/O register access) is possible.
•System performance analyzer (AZ850)
•Device file (DF703xxx)
System Simulator (SM850)
Project Manager (PM)
ꢁ Features
ꢁ Features
•Same operability as debugger
•Project management (management of target chip, source, and environment
•Target-less evaluation prior to target completion possible
•In addition to the operation of the CPU itself, target system operation
including on-chip peripheral unit and interrupt servicing can also be
simulated.
during debugging is possible.)
•Automation of series of operations consisting of edit, build, and debug
•Integration of Help function
•Included with C compiler package
•Pseudo-target system construction and I/O operation are possible through
external parts.
•Data generated by 0/1 logic and timing charts can be input to the program
being simulated.
•Larger number of events than in-circuit emulator
•Execution speed estimates can be done on the host machine to accurately
simulate pipeline operationNote
.
•Construction by user target system users is possible through user open
interface.
•A peripheral I/O register status can be specified and when this status
occurs, the system can be made to output an interrupt at the desired timing
or transfer data to memory (peripheral I/O register event & action function).
Note The pipeline mode is supported by the V853.
ꢁ Target devices
V853, V850/SA1, V850/SB1, V850/SB2, V850/SF1, V850E/MS1, V850E/
MA1, V850E/IA1
Pamphlet U15412EJ1V0PF
58
Integrated Debugger (ID850)
In-Circuit Emulator
ꢁ Features
ꢁ Features
•Supports object files
•Realization of high transparency with emulator functions concentrated in
•Debugging at source level
a dedicated chip
•Debugging using target resources
•Real-time execution on target
•Event setting according to complex software operation
•Online help function
•V850 core IE enabling easy product expansion
•V850E1 core IE enabling high-speed operation
•Connectable to various personal computers
Real-Time OSs (RX850, RX850 Pro)
Task Debuggers (RD850, RD850 Pro)
ꢁ Features
ꢁ Features
•Comply with global standard (µITRON 3.0 specifications).
•Display detailed information on OS resources such as tasks.
•Support power management function.
•Issue system calls.
•Enable embedding of required functions only (selection of system calls to
be used).
•Display source of referenced tasks.
•Included with real-time OS (RX850, RX850 Pro)
•Support sophisticated task development through task debugger (RD).
•Support application operation analysis through system performance
analyzer (AZ)
•Inherit attributes of real-time OS of 16-bit V Series and 78K Series
System Performance Analyzer (AZ850)
TCP/IP Software Library (RX-NET) for V850E Products
ꢁ Features
ꢁ Product configuration
•TCP/IP protocol stack
•Applications
•Detection of bugs through system timing errors
•Detection of bugs due to simultaneous operation of complex tasks
•Detection/analysis of real-time system execution performance
•Operation linked to various debuggers
•LAN control driver
ꢁ Features
•RFC-compliant
•Multiprotocol stack
•Support of numerous socket interfaces/libraries
•Support of applications as option products
•Simplified device driver
•Support of NEC real-time OS (RX850 Pro)
ꢁ Target devices
V850E products
Pamphlet U15412EJ1V0PF
59
OSEK/VDX Specification-Compliant OS (RX-OSEK850)
ꢁ Features
• Kernel
OSEK/VDX OS Ver. 2.0 specification-compliant
Supports four conformance classes (BCC1, BCC2, ECC1, ECC2).
• Communications
OSEK/VDX COM Ver. 2.1 Rev. 1 specification-compliant
Supports three conformance classes (CCC1, CCC2, CCC3).
• Configurator
Configurator simplifying construction of system information (OIL850)
OIL Ver. 2.0-compliant format supported for configuration files
• Task debugger (RD-OSEK850)
Task debugger effective for debugging applications that use the RX-OSEK850 included as standard.
RISC Microcontroller Reference Platform (SolutionGearTM)
ꢁ Features
• General-purpose evaluation boards available as development platforms for RISC microcontroller software
• Supported CPU: V850E/MA1
• Global and PC-compatible interfaces provided, including PCI, ISA, PCMCIA, E-IDE, EthernetTM, Serial, Parallel, PS/2, and USB
• Used combined with CPU-independent motherboard (usable in common with VR Series) and any of various CPU boards
• Real-time OS, middleware, and sample drivers are included.
• Development environment of Green Hills Software (evaluation version) provided
• MULTI/PARTNER remote monitor version can be used.
• Reference design information provided
It's actually testable
Circuit diagrams are provided
This board usable for comparison purposes
It does not work properly.
Is this a hardware or
software problem?
I want to measure
the CPU performance
Can such a performance
be realized?
This is my first device so
I want sample circuits
H/W
S/W
Board design/development
Debugging
Software design/development
Time
I want to start software
development ahead of
board development
The OS and middleware look
difficult to start up and use
I want to use OS
/middleware
The OS and
middleware are bundled.
Since various peripheral devices are
mounted,debugging can be started
from device-independent parts.
A user-own coding part matching
this board is provided as sample.
ꢃ At such times, RISC microcontroller reference platform is ideal
Cooperation with Third Parties
By strengthening its cooperation with third-party companies and creating tool groups that combine the best characteristics of NEC tools and third-party
tools, NEC provides a development environment that answers diversified user needs.
Pamphlet U15412EJ1V0PF
60
Information
V850 Series Website Introduction
For information about the V850 Series and the V850 Series
development environment, check out the NEC Microcomputer website.
http://www.ic.nec.co.jp/micro/index_e.html
Product Information
ꢀ Product information on the V850 Series, development
environments for the V850 Series, and the middleware
reference platform can be referenced.
Downloading Development Tools
ꢀ Development tools for the V850 Series can be downloaded.
Upgrade information is provided.
Downloading Documents
ꢀ Documents about the V850 Series and V850 Series
development environment can be downloaded.
FAQ
ꢀ Answer to questions about the V850 Series
development environment are introduced.
Pamphlet U15412EJ1V0PF
61
IEBus, EEPROM, Solution Gear, V Series, V800 Series, V850 Series, V830 Family, V853, V850/SA1,
V850/SB1, V850/SB2, V850/SC1, V850/SC2, V850/SC3, V850/SF1, V850/SV1, V850E/IA1, V850E/IA2,
V850E/MA1, V850E/MA2, V850E/MS1, V850E/MS2, V850ES/SA2, V850ES/SA3, and VR Series are
trademarks of NEC Corporation.
TrueSpeech is a trademark of DSP Group, Inc.
JAVA and all trademarks and logos related to JAVA are trademarks of Sun Microsystems, Inc.
Windows and Windows NT are either registered trademarks or trademarks of Microsoft Corporation in
the United States and/or other countries.
NORTi is a trademark of MiSPO, Inc.
CodeWarrior is a trademark of Metrowerks Corporation.
Green Hills Software and MULTI are trademarks of Green Hills Software, Inc.
WATCHPOINT is a trademark of Sophia Systems Co., Ltd.
Tornado is a trademark of Wind River Systems, Inc.
Virtual ICE is a trademark of Yokogawa Electric Corporation.
Synopsys Eaglei is a trademark of Synopsys, Inc.
TRON stands for The Realtime Operating system Nucleus.
ITRON is an abbreviation of Industrial TRON.
Ethernet is a trademark of Xerox Corporation.
Caution: The I2C bus interface circuit is incorporated in the µPD703014AY, 703014BY, 703015AY,
703015BY, 70F3015BY, 703017AY, 70F3017AY, 703030AY, 703031AY, 703032AY, 70F3032AY,
703033AY, 70F3033AY, 703034AY, 703035AY, 70F3035AY, 703036AY, 703037AY, 70F3037AY,
703038Y, 70F3038Y, 703039Y, 703040Y, 70F3040Y, 703041Y, 703068Y, 703069Y, 703078Y,
703079Y, 70F3079Y, 703088Y, 703089Y, 70F3089Y, 703201Y, 70F3201Y, 703204Y, 70F3204Y.
Those who use the I2C bus interface can be granted the license below by giving prior notification
before ordering the custom code.
Purchase of NEC I2C components conveys a license under the Philips I2C Patent Rights to use
these components in an I2C system, provided that the system conforms to the I2C Standard
Specification as defined by Philips.
Pamphlet U15412EJ1V0PF
62
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
•
The information in this document is current as of August, 2001. The information is subject to
change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or
data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all
products and/or types are available in every country. Please check with an NEC sales representative
for availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
Pamphlet U15412EJ1V0PF
63
For further information, please contact:
NEC Corporation
NEC Building
7-1, Shiba 5-chome, Minato-ku
Tokyo 108-8001, Japan
Tel: 03-3454-1111
http://www.ic.nec.co.jp/
[North & South America]
[Europe]
[Asia & Oceania]
NEC Electronics Hong Kong Limited
12/F., Cityplaza 4,
NEC Electronics Inc.
2880 Scott Blvd.
NEC Electronics (Europe) GmbH
Oberrather Str. 4
40472 Düsseldorf, Germany
Tel: 0211-6503-01
12 Taikoo Wan Road, Hong Kong
Tel: 2886-9318
Santa Clara, CA 95050-2554, U.S.A.
Tel: 408-588-6000
Fax: 0211-6503-327
Fax: 2886-9022/9044
800-366-9782
http://www.ee.nec.de/
Fax: 408-588-6130
800-729-9288
Seoul Branch
10F, ILSONG Bldg., 157-37,
Samsung-Dong, Kangnam-Ku
Seoul, the Republic of Korea
Tel: 02-528-0303
http://www.necel.com/
Branch The Netherlands
Boschdijk 187a
5612 HB Eindhoven,
The Netherlands
Tel: 040-2445845
Fax: 040-2444580
NEC do Brasil S.A.
Electron Devices Division
Rodovia Presidente Dutra, Km 214
07210-902-Guarulhos-SP Brasil
Tel: 011-6462-6810
Fax: 02-528-4411
NEC Electronics Taiwan Ltd.
7F, No. 363 Fu Shing North Road
Taipei, Taiwan, R. O. C.
Tel: 02-2719-2377
Fax: 011-6462-6829
Branch Sweden
P.O. Box 134
18322 Taeby, Sweden
Tel: 08-6380820
Fax: 08-6380388
Fax: 02-2719-5951
NEC Electronics Singapore Pte. Ltd.
238A Thomson Road
#12-01/10 Novena Square
Singapore 307684
Tel: 253-8311
Fax: 250-3583
NEC Electronics (UK) Limited
Cygnus House, Sunrise Parkway,
Linford Wood, Milton Keynes,
MK14 6NP, U.K.
Tel: 01908-691-133
Fax: 01908-670-290
NEC Electronics (France) S.A.
9, rue Paul Dautier-B.P. 52
78142 Velizy-Villacoublay Cédex
France
Tel: 01-3067-5800
Fax: 01-3067-5899
Madrid Office
Juan Esplandiu, 15
28007 Madrid, Spain
Tel: 091-504-2787
Fax: 091-504-2860
NEC Electronics Italiana s.r.l.
Via Fabio Filzi, 25/A,
20124 Milano, Italy
Tel: 02-667541
Fax: 02-66754299
G02. 1
Document No. U15412EJ1V0PF00 (1st edition)
Date Published February 2002 N CP(K)
Printed in Japan
© NEC Corporation 2002
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