UPD784037GC-XXX-3B9 [ETC]
MICROCONTROLLER|16-BIT|UPD78K4 CPU|CMOS|QFP|80PIN|PLASTIC ; 微控制器| 16位| UPD78K4 CPU | CMOS | QFP | 80PIN |塑料\n型号: | UPD784037GC-XXX-3B9 |
厂家: | ETC |
描述: | MICROCONTROLLER|16-BIT|UPD78K4 CPU|CMOS|QFP|80PIN|PLASTIC
|
文件: | 总98页 (文件大小:762K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
DATA SHEET
MOS INTEGRATED CIRCUIT
µPD784035, 784036, 784037, 784038
16/8-BIT SINGLE-CHIP MICROCONTROLLER
The µPD784038 is a product of the µPD784038 sub-series in the 78K/IV series. It contains various peripheral
hardware such as ROM, RAM, I/O ports, 8-bit resolution A/D and D/A converters, timers, serial interface, and interrupt
functions, as well as a high-speed, high-performance CPU.
In addition, the µPD78P4038 (one-time PROM or EPROM product), which can be operated within the same power
supply voltage ranges as masked-ROM products, and development tools are supported.
For specific functions and other detailed information, consult the following user’s manual.
This manual is required reading for design work.
µPD784038, 784038Y Sub-Series User’s Manual, Hardware : U11316E
78K/IV Series User’s Manual, Instruction
: U10905E
FEATURES
• Serial interface: 3 channels
UART/IOE (3-wire serial I/O): 2 channels
CSI (3-wire serial I/O, 2-wire serial I/O): 1 channel
• PWM outputs: 2
• Pin-compatible with the µPD78234, µPD784026, and
µPD784038Y sub-series
• Expanded internal memory spaces in the µPD78234
and µPD784026 sub-series
• Standby function
• Minimum instruction execution time: 125 ns
(at 32 MHz)
HALT/STOP/IDLE mode
• Clock frequency division function
• Watchdog timer: 1 channel
• Number of I/O ports: 64
• Timer/counters: 16-bit timer/counter × 3 units
16-bit timer × 1 unit
• Clock output function
Selectable from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16
• Supply voltage: VDD = 2.7 to 5.5 V
• A/D converter: 8-bit resolution × 8 channels
• D/A converter: 8-bit resolution × 2 channels
APPLICATIONS
LBP, automatic-focusing camera, PPC, printer, electronic typewriter, air conditioner, electronic musical instru-
ments, cellular telephone, etc.
This manual describes the µPD784038 unless otherwise specified.
The information in this document is subject to change without notice.
Document No. U10847EJ2V0DS00 (2nd edition)
Date Published February 1998 J CP(K)
Printed in Japan
The mark
shows major revised points.
1995
©
µPD784035, 784036, 784037, 784038
ORDERING INFORMATION
Part number
Package
Internal ROM
(bytes)
48K
Internal RAM
(bytes)
2,048
µPD784035GC-×××-3B9
µPD784035GC-×××-8BT
µPD784035GK-×××-BE9
µPD784036GC-×××-3B9
µPD784036GC-×××-8BT
µPD784036GK-×××-BE9
µPD784037GC-×××-3B9
µPD784037GC-×××-8BT
µPD784037GK-×××-BE9
µPD784038GC-×××-3B9
µPD784038GC-×××-8BT
µPD784038GK-×××-BE9
80-pin plastic QFP (14 × 14 × 2.7 mm)
80-pin plastic QFP (14 × 14 × 1.4 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 × 2.7 mm)
80-pin plastic QFP (14 × 14 × 1.4 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 × 2.7 mm)
80-pin plastic QFP (14 × 14 × 1.4 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin plastic QFP (14 × 14 × 2.7 mm)
80-pin plastic QFP (14 × 14 × 1.4 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
48K
2,048
48K
2,048
64K
2,048
64K
2,048
64K
2,048
96K
3,584
96K
3,584
96K
3,584
128K
128K
128K
4,352
4,352
4,352
Remark ××× is ROM code suffix.
2
µPD784035, 784036, 784037, 784038
78K/IV SERIES PRODUCT DEVELOPMENT DIAGRAM
: Under mass production
: Under development
2
2
I C bus supported
Multimaster I C bus supported
µPD784038Y
µPD784225Y
µPD784225
Standard models
µPD784038
Enhanced internal memory capacity,
80 pins,
added ROM correction
PD784026
µ
pin compatible with the PD784026
µ
Enhanced A/D,
16-bit timer,
and power
2
2
Multimaster I C bus supported
Multimaster I C bus supported
µ
PD784216Y
µPD784218Y
µPD784218
management
µPD784216
100 pins,
enhanced I/O and
internal memory capacity
Enhanced internal memory capacity,
added ROM correction
µ
PD784054
µ
PD784046
ASSP models
Equipped with 10-bit A/D
µPD784955
For DC inverter control
µPD784908
TM
Equipped with IEBus
controller
2
µ
PD78F4943
Multimaster I C bus supported
For CD-ROM
Flash memory 56K bytes
µPD784928Y
µPD784928
Enhanced function of the µPD784915
µ
PD784915
For software servo control,
equipped with analog circuit
for VCR,
enhanced timer
3
µPD784035, 784036, 784037, 784038
FUNCTIONS
Product
µPD784035
µPD784036
µPD784037
µPD784038
Item
113
Number of basic instructions
(mnemonics)
8 bits × 16 registers × 8 banks, or 16 bits × 8 registers × 8 banks (memory mapping)
General-purpose register
125 ns/250 ns/500 ns/1,000 ns (at 32 MHz)
Minimum instruction execution
time
48K bytes
64K bytes
96K bytes
128K bytes
4,352 bytes
Internal
memory
ROM
RAM
2,048 bytes
3,584 bytes
Memory space
I/O ports
Program and data: 1M byte
64
8
Total
Input
56
54
Input/output
Additional
function
pins
Pins with pull-
up resistor
Note
24
LED direct
drive outputs
8
Transistor
direct drive
Real-time output ports
Timer/counter
4 bits × 2, or 8 bits × 1
Timer/counter 0:
(16 bits)
Timer register × 1
Capture register × 1
Compare register × 2
Pulse output capability
• Toggle output
• PWM/PPG output
• One-shot pulse output
Timer/counter 1:
(8/16 bits)
Timer register × 1
Capture register × 1
Pulse output capability
• Real-time output (4 bits × 2)
Capture/compare register × 1
Compare register × 1
Timer/counter 2:
(8/16 bits)
Timer register × 1
Capture register × 1
Pulse output capability
• Toggle output
Capture/compare register × 1
Compare register × 1
• PWM/PPG output
Timer 3
:
Timer register × 1
(8/16 bits)
Compare register × 1
PWM outputs
12-bit resolution × 2 channels
Serial interface
UART/IOE (3-wire serial I/O)
: 2 channels (incorporating baud rate generator)
CSI (3-wire serial I/O, 2-wire serial I/O): 1 channel
A/D converter
D/A converter
Clock output
Watchdog timer
Standby
8-bit resolution × 8 channels
8-bit resolution × 2 channels
Selected from fCLK, fCLK/2, fCLK/4, fCLK/8, or fCLK/16 (can be used as a 1-bit output port)
1 channel
HALT/STOP/IDLE mode
Interrupt
Hardware source 23 (16 internal, 7 external (sampling clock variable input: 1))
Software source BRK instruction, BRKCS instruction, operand error
Nonmaskable
Maskable
1 internal, 1 external
15 internal, 6 external
•
•
4-level programmable priority
3 operation statuses: vectored interrupt, macro service, context switching
Supply voltage
Package
VDD = 2.7 to 5.5 V
80-pin plastic QFP (14 × 14 × 2.7 mm)
80-pin plastic QFP (14 × 14 × 1.4 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Note Additional function pins are included in the I/O pins.
4
µPD784035, 784036, 784037, 784038
CONTENTS
1. DIFFERENCES BETWEEN µPD784038 SUB-SERIES ...........................................................
7
2. MAIN DIFFERENCES BETWEEN µPD784038, µPD784038Y, µPD784026,
AND µPD78234 SUB-SERIES ...................................................................................................
8
9
3. PIN CONFIGURATION (TOP VIEW) .........................................................................................
4. SYSTEM CONFIGURATION EXAMPLE (PPC)........................................................................ 11
5. BLOCK DIAGRAM ..................................................................................................................... 12
6. PIN FUNCTIONS ........................................................................................................................ 13
6.1
6.2
6.3
Port Pins .........................................................................................................................................
Non-Port Pins .................................................................................................................................
I/O Circuits for Pins and Handling of Unused Pins ..................................................................
13
15
17
7. CPU ARCHITECTURE ............................................................................................................... 20
7.1
7.2
Memory Space................................................................................................................................
CPU Registers ................................................................................................................................
20
25
25
26
27
7.2.1
7.2.2
7.2.3
General-purpose registers............................................................................................
Control registers ............................................................................................................
Special function registers (SFRs) ...............................................................................
8. PERIPHERAL HARDWARE FUNCTIONS ................................................................................ 32
8.1
8.2
8.3
8.4
8.5
8.6
8.7
8.8
Ports ................................................................................................................................................
Clock Generator .............................................................................................................................
Real-Time Output Port ..................................................................................................................
Timers/Counters ............................................................................................................................
PWM Output (PWM0, PWM1) ........................................................................................................
A/D Converter .................................................................................................................................
D/A Converter .................................................................................................................................
Serial Interface ...............................................................................................................................
32
33
35
36
38
39
40
41
42
44
45
46
46
8.8.1
8.8.2
Asynchronous serial interface/three-wire serial I/O (UART/IOE)............................
Synchronous serial interface (CSI) .............................................................................
8.9
Clock Output Function ..................................................................................................................
8.10 Edge Detection Function ..............................................................................................................
8.11 Watchdog Timer .............................................................................................................................
9. INTERRUPT FUNCTION ............................................................................................................ 47
9.1
9.2
9.3
9.4
9.5
Interrupt Source .............................................................................................................................
Vectored Interrupt..........................................................................................................................
Context Switching .........................................................................................................................
Macro Service.................................................................................................................................
Examples of Macro Service Applications ..................................................................................
47
49
50
50
51
5
µPD784035, 784036, 784037, 784038
10. LOCAL BUS INTERFACE ......................................................................................................... 53
10.1 Memory Expansion ........................................................................................................................
10.2 Memory Space................................................................................................................................
10.3 Programmable Wait .......................................................................................................................
10.4 Pseudo-Static RAM Refresh Function ........................................................................................
10.5 Bus Hold Function.........................................................................................................................
53
54
55
55
55
11. STANDBY FUNCTION ............................................................................................................... 56
12. RESET FUNCTION..................................................................................................................... 57
13. INSTRUCTION SET.................................................................................................................... 58
14. ELECTRICAL CHARACTERISTICS ......................................................................................... 63
15. PACKAGE DRAWINGS ............................................................................................................. 84
16. RECOMMENDED SOLDERING CONDITIONS ........................................................................ 87
APPENDIX A DEVELOPMENT TOOLS.......................................................................................... 89
APPENDIX B RELATED DOCUMENTS ......................................................................................... 92
6
µPD784035, 784036, 784037, 784038
1. DIFFERENCES BETWEEN µPD784038 SUB-SERIES
The only difference between the µPD784035, µPD784036, µPD784037, and µPD784038 is their capacity of
internal memory.
The µPD78P4038 is produced by replacing the masked ROM in the µPD784035, µPD784036, µPD784037, or
µPD784038 with 128K-byte one-time PROM or EPROM. Table 1-1 shows the differences between these products.
Table 1-1. Differences between the µPD784038 Sub-Series
Product
µPD784031
µPD784035
µPD784036
µPD784037
µPD784038
µPD78P4038
Item
Internal ROM
Unavailable
48K bytes
64K bytes
96K bytes
128K bytes
128K bytes
(masked ROM) (masked ROM) (masked ROM) (masked ROM) (one-time PROM
or EPROM)
2,048 bytes
3,584 bytes
4,352 bytes
Internal RAM
Package
80-pin plastic QFP (14 × 14 × 2.7 mm)
80-pin plastic QFP (14 × 14 × 1.4 mm)
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
80-pin ceramic
WQFN
(14 × 14mm)
7
µPD784035, 784036, 784037, 784038
2. MAIN DIFFERENCES BETWEEN µPD784038, µPD784038Y, µPD784026, AND µPD78234 SUB-
SERIES
Series
µPD784038 sub-series
µPD784038Y sub-series
µPD784026 sub-series
µPD78234 sub-series
Item
Number of basic instructions
(mnemonics)
113
65
Minimum instruction execution 125 ns
160 ns
(at 25 MHz)
333 ns
time
(at 32 MHz)
(at 12 MHz)
Memory space (program/data) 1M byte in total
64K bytes/1M byte
Timer/counter
16-bit timer/counter × 1
16-bit timer/counter × 1
8-bit timer/counter × 2
8-bit timer × 1
8/16-bit timer/counter × 2
8/16-bit timer × 1
Clock output function
Watchdog timer
Available
Available
Unavailable
Unavailable
Serial interface
UART/IOE (3-wire serial I/O) UART/IOE (3-wire serial I/O) UART × 1 channel
× 2 channels
× 2 channels
CSI (3-wire serial I/O, SBI)
CSI (3-wire serial I/O, 2-wire CSI (3-wire serial I/O, SBI)
× 1 channel
2
Note
serial I/O, I C bus
)
× 1 channel
× 1 channel
Available
4 levels
Interrupt Context switching
Priority
Unavailable
2 levels
Standby function
3 modes (HALT, STOP, IDLE)
2 modes (HALT, STOP)
Fixed to fXX/2
Operation clock switching
Selectable from fXX/2, fXX/4, fXX/8, or fXX/16
Unavailable
Pin
MODE pin
TEST pin
To specify ROM-less mode
(always in the high level for
the µPD78233 or µPD78237)
functions
Pin for testing the device
Unavailable
Low level during ordinary use
Package
80-pin plastic QFP
(14 × 14 × 2.7 mm)
80-pin plastic QFP
(14 × 14 × 1.4 mm)
80-pin plastic TQFP
(fine pitch) (12 × 12 mm)
80-pin ceramic WQFN
(14 × 14 mm):
80-pin plastic QFP
80-pin plastic QFP
(14 × 14 × 2.7 mm)
94-pin plastic QFP
(20 × 20 mm)
(14 × 14 × 2.7 mm)
80-pin plastic TQFP
(fine pitch) (12 × 12 mm):
for the µPD784021 only
80-pin ceramic WQFN
(14 × 14 mm):
84-pin plastic QFJ
(1,150 ×1,150 mil)
94-pin ceramic WQFN
(20 × 20 mm):
for the µPD78P4026 only
for the µPD78P4038 and
µPD78P4038Y only
for the µPD78P238 only
Note For the µPD784038Y sub-series only.
8
µPD784035, 784036, 784037, 784038
3. PIN CONFIGURATION (TOP VIEW)
•
•
•
80-pin plastic QFP (14 × 14 × 2.7 mm)
µPD784035GC-×××-3B9, µPD784036GC-×××-3B9, µPD784037GC-×××-3B9, µPD784038GC-×××-3B9
80-pin plastic QFP (14 × 14 × 1.4 mm)
µPD784035GC-×××-8BT, µPD784036GC-×××-8BT, µPD784037GC-×××-8BT, µPD784038GC-×××-8BT
80-pin plastic TQFP (fine pitch) (12 × 12 mm)
µPD784035GK-×××-BE9, µPD784036GK-×××-BE9, µPD784037GK-×××-BE9, µPD784038GK-×××-BE9
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
P32/SCK0/SCL
P33/SO0/SDA
P34/TO0
P74/ANI4
P73/ANI3
P72/ANI2
P71/ANI1
P70/ANI0
1
2
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
3
P35/TO1
4
P36/TO2
5
P37/TO3
V
DD0
6
RESET
P17
7
V
DD1
X2
X1
P16
8
P15
9
P14/T
XD2/SO2
10
11
12
13
14
15
16
17
18
19
20
VSS1
P13/R
XD2/SI2
P00
P01
P02
P03
P04
P05
P06
P07
P12/ASCK2/SCK2
P11/PWM1
P10/PWM0
TESTNote
V
SS0
ASTB/CLKOUT
P40/AD0
P41/AD1
P67/REFRQ/HLDAK
P42/AD2
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
Note Connect the TEST pin to the VSS0 pin directly.
9
µPD784035, 784036, 784037, 784038
A8-A19
: Address bus
P60-P67
P70-P77
: Port 6
: Port 7
AD0-AD7
ANI0-ANI7
: Address/data bus
: Analog input
PWM0, PWM1 : Pulse width modulation output
ANO0, ANO1 : Analog output
RD
: Read strobe
: Refresh request
: Reset
ASCK, ASCK2 : Asynchronous serial clock
REFRQ
RESET
RxD, RxD2
SCK0-SCK2
SCL
ASTB
AVDD
: Address strobe
: Analog power supply
: Receive data
: Serial clock
: Serial clock
: Serial data
: Serial input
: Serial output
: Test
AVREF1-AVREF3 : Reference voltage
AVSS
: Analog ground
: Clock input
CI
SDA
CLKOUT
HLDAK
HLDRQ
: Clock output
: Hold acknowledge
: Hold request
SI0-SI2
SO0-SO2
TEST
INTP0-INTP5 : Interrupt from peripherals
TO0-TO3
TxD, TxD2
VDD0, VDD1
VSS0, VSS1
WAIT
: Timer output
: Transmit data
: Power supply
: Ground
NMI
: Non-maskable interrupt
: Port 0
P00-P07
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
: Port 1
: Port 2
: Wait
: Port 3
WR
: Write strobe
: Crystal
: Port 4
X1, X2
: Port 5
10
µPD784035, 784036, 784037, 784038
4. SYSTEM CONFIGURATION EXAMPLE (PPC)
µPD784038
P11
P15
P16
P17
Sensing paper presence
RxD
TxD
Sensing paper feed
Serial communi-
cation
Sensing paper ejection
Sensing the position of the scanner station
SCK1
Operator panel
SI1
Sensing paper
transport
INTP0
SO1
P04
P06
High voltage
control circuit
Charging the drum to attract
the toner on it
Fusing heater
control circuit
P07
P66
Fusing roller
Temperature
of the fusing
heater
ANI0
ANI1
Lamp for lighting the original
Lamp for discharging
Lamp regulator
Brightness of
the lamp
(DC stepping motor)
PWM0
P00-P03
M
Main motor
Lever for ad-
justing the
tone of the
copy
ANI2
ANI3
Clutch for stopping
the scanner station
SL
P33
P34
P35
P36
P37
Clutch for forward-
ing the scanner
station
SL
SL
SL
Lever for com-
pensating the
tone of the
copy
Driver
Clutch for the
resist shutter
Clutch for manual
feeding
Clutch for cassette
feeding
SL
Reset circuit
RESET
Solenoid
11
µPD784035, 784036, 784037, 784038
5. BLOCK DIAGRAM
RxD/SI1
TxD/SO1
NMI
UART/IOE2
Programmable
interrupt controller
Baud-rate
ASCK/SCK1
generator
INTP0-INTP5
RxD2/SI2
TxD2/SO2
INTP3
TO0
UART/IOE1
Timer/counter 0
(16 bits)
Baud-rate
TO1
ASCK2/SCK2
generator
SCK0/SCL
Timer/counter 1
(16 bits)
INTP0
Clocked serial
interface
SO0/SDA
SI0
INTP1
INTP2/CI
TO2
ASTB/CLKOUT
78K/IV
CPU core
Timer/counter 2
(16 bits)
Clock output
Bus interface
ROM
AD0-AD7
A8-A15
TO3
A16-A19
RD
Timer 3
(16 bits)
WR
WAIT/HLDRQ
REFRQ/HLDAK
P00-P03
P04-P07
Real-time output
port
P00-P07
P10-P17
P20-P27
P30-P37
P40-P47
P50-P57
P60-P67
Port 0
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
RAM
PWM0
PWM1
PWM
ANO0
ANO1
AVREF2
AVREF3
D/A converter
ANI0-ANI7
AVDD
AVREF1
AVSS
P70-P77
RESET
A/D converter
Watchdog timer
TEST
INTP5
System control
X1
X2
V
, V
VSDSD00, VSDSD11
Remark The internal ROM or RAM capacity differs for each product.
12
µPD784035, 784036, 784037, 784038
6. PIN FUNCTIONS
6.1 Port Pins (1/2)
Pin
I/O
I/O
Dual-function
-
Function
P00-P07
Port 0 (P0):
• 8-bit I/O port.
• Functions as a real-time output port (4 bits × 2).
• Inputs and outputs can be specified bit by bit.
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
• Can drive a transistor.
Port 1 (P1):
P10
I/O
PWM0
P11
PWM1
• 8-bit I/O port.
P12
ASCK2/SCK2
RxD2/SI2
TxD2/SO2
-
• Inputs and outputs can be specified bit by bit.
P13
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
P14
• Can drive LED.
P15-P17
P20
Input
NMI
Port 2 (P2):
P21
INTP0
• 8-bit input-only port.
• P20 does not function as a general-purpose port (nonmaskable inter-
rupt). However, the input level can be checked by an interrupt service
routine.
P22
INTP1
P23
INTP2/CI
INTP3
P24
• The use of the pull-up resistors can be specified by software for pins
P25
INTP4/ASCK/SCK1
INTP5
P22 to P27 (in units of 6 bits).
P26
• The P25/INTP4/ASCK/SCK1 pin functions as the SCK1 output pin by
CSIM1.
P27
SI0
Port 3 (P3):
P30
I/O
RxD/SI1
TxD/SO1
SCK0/SCL
SO0/SDA
TO0-TO3
AD0-AD7
• 8-bit I/O port.
P31
• Inputs and outputs can be specified bit by bit.
P32
• The use of the pull-up resistors can be specified by software for the pins
P33
in the input mode together.
P34-P37
P40-P47
Port 4 (P4):
I/O
• 8-bit I/O port.
• Inputs and outputs can be specified bit by bit.
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
• Can drive LED.
Port 5 (P5):
P50-P57
I/O
A8-A15
• 8-bit I/O port.
• Inputs and outputs can be specified bit by bit.
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
• Can drive LED.
13
µPD784035, 784036, 784037, 784038
6.1 Port Pins (2/2)
Pin
P60-P63
P64
I/O
I/O
Dual-function
A16-A19
Function
Port 6 (P6):
RD
• 8-bit I/O port.
P65
WR
• Inputs and outputs can be specified bit by bit.
P66
WAIT/HLDRQ
REFRQ/HLDAK
ANI0-ANI7
• The use of the pull-up resistors can be specified by software for the pins
in the input mode together.
P67
P70-P77
I/O
Port 7 (P7):
• 8-bit I/O port.
• Inputs and outputs can be specified bit by bit.
14
µPD784035, 784036, 784037, 784038
6.2 Non-Port Pins (1/2)
Pin
TO0-TO3
CI
I/O
Dual-function
P34-P37
Function
Timer output
Output
Input
Input
P23/INTP2
P30/SI1
Input of a count clock for timer/counter 2
Serial data input (UART0)
RXD
RXD2
TXD
P13/SI2
Serial data input (UART2)
Output
Input
P31/SO1
P14/SO2
P25/INTP4/SCK1
P12/SCK2
P33/SO0
P27
Serial data output (UART0)
TXD2
ASCK
ASCK2
SDA
Serial data output (UART2)
Baud rate clock input (UART0)
Baud rate clock input (UART2)
Serial data I/O (2-wire serial I/O)
Serial data input (3-wire serial I/O0)
Serial data input (3-wire serial I/O1)
Serial data input (3-wire serial I/O2)
Serial data output (3-wire serial I/O0)
Serial data output (3-wire serial I/O1)
Serial data output (3-wire serial I/O2)
Serial clock I/O (3-wire serial I/O0)
Serial clock I/O (3-wire serial I/O1)
Serial clock I/O (3-wire serial I/O2)
Serial clock I/O (2-wire serial I/O)
I/O
SI0
Input
SI1
P30/RXD
P13/RXD2
P33/SDA
P31/TXD
SI2
SO0
Output
I/O
SO1
SO2
P14/TXD2
P32/SCL
P25/INTP4/ASCK
P12/ASCK2
P32/SCK0
P20
SCK0
SCK1
SCK2
SCL
NMI
Input
External interrupt request
-
INTP0
P21
•
•
Input of a count clock for timer/counter 1
Capture/trigger signal for CR11 or CR12
INTP1
INTP2
INTP3
P22
•
•
Input of a count clock for timer/counter 2
Capture/trigger signal for CR22
P23/CI
P24
•
•
Input of a count clock for timer/counter 2
Capture/trigger signal for CR21
•
•
Input of a count clock for timer/counter 0
Capture/trigger signal for CR02
INTP4
INTP5
AD0-AD7
A8-A15
A16-A19
RD
P25/ASCK/SCK1
P26
-
Input of a conversion start trigger for A/D converter
I/O
P40-P47
P50-P57
P60-P63
P64
Time multiplexing address/data bus (for connecting external memory)
High-order address bus (for connecting external memory)
High-order address bus during address expansion (for connecting external memory)
Strobe signal output for reading the contents of external memory
Strobe signal output for writing on external memory
Wait signal insertion
Output
Output
Output
Output
Input
WR
P65
WAIT
P66/HLDRQ
P67/HLDAK
P66/WAIT
P67/REFRQ
CLKOUT
REFRQ
HLDRQ
HLDAK
ASTB
Output
Input
Refresh pulse output to external pseudo static memory
Input of bus hold request
Output
Output
Output of bus hold response
Latch timing output of time multiplexing address (A0-A7) (for
connecting external memory)
CLKOUT
Output
ASTB
Clock output
15
µPD784035, 784036, 784037, 784038
6.2 Non-Port Pins (2/2)
Pin
RESET
X1
I/O
Input
Input
-
Dual-function
Function
-
-
Chip reset
Crystal input for system clock oscillation (A clock pulse can also be
input to the X1 pin.)
X2
ANI0-ANI7
ANO0, ANO1
AVREF1
Input
Output
-
P70-P77
Analog voltage inputs for the A/D converter
Analog voltage inputs for the D/A converter
Application of A/D converter reference voltage
Application of D/A converter reference voltage
Positive power supply for the A/D converter
Ground for the A/D converter
-
-
AVREF2
AVDD
AVSS
, AVREF3
VDD0Note 1
VDD1Note 1
VSS0Note 2
VSS1Note 2
Positive power supply of the port part
Positive power supply except for the port part
Ground of the port part
Ground except for the port part
TEST
Directly connect to the VSS pin. (The TEST pin is for the IC test.)
Notes 1. The potential of the VDD0 pin must be equal to that of the VDD1 pin.
2. The potential of the VSS0 pin must be equal to that of the VSS1 pin.
16
µPD784035, 784036, 784037, 784038
6.3 I/O Circuits for Pins and Handling of Unused Pins
Table 6-1 describes the types of I/O circuits for pins and the handling of unused pins.
Figure 6-1 shows the configuration of these various types of I/O circuits.
Table 6-1. Types of I/O Circuits for Pins and Handling of Unused Pins (1/2)
Pin
I/O circuit type
5-H
I/O
I/O
Recommended connection method for unused pins
Input state : Connect these pins to the VDD0 pin.
Output state: Leave open.
P00-P07
P10/PWM0
P11/PWM1
P12/ASCK2/SCK2
P13/RxD2/SI2
P14/TxD2/SO2
P15-P17
8-C
5-H
P20/NMI
2
Input
Connect these pins to the VDD0 or VSS0 pin.
Connect these pins to the VDD0 pin.
P21/INTP0
P22/INTP1
2-C
P23/INTP2/CI
P24/INTP3
P25/INTP4/ASCK/SCK1 8-C
I/O
Input
I/O
Input state : Connect this pin to the VDD0 pin.
Output state: Leave open.
P26/INTP5
2-C
5-H
10-B
5-H
Connect these pins to the VDD0 pin.
P27/SI0
P30/RxD/SI1
Input state : Connect these pins to the VDD0 pin.
Output state: Leave open.
P31/TxD/SO1
P32/SCK0/SCL
P33/SO0/SDA
P34/TO0-P37/TO3
P40/AD0-P47/AD7
P50/A8-P57/A15
P60/A16-P63/A19
P64/RD
P65/WR
P66/WAIT/HLDRQ
P67/REFRQ/HLDAK
P70/ANI0-P77/ANI7
20-A
I/O
Input state : Connect this pin to the VDD0 or VSS0 pin.
Output state: Leave open.
ANO0, ANO1
12
Output
Leave open.
ASTB/CLKOUT
4-B
17
µPD784035, 784036, 784037, 784038
Table 6-1. Types of I/O Circuits for Pins and Handling of Unused Pins (2/2)
Pin
I/O circuit type
I/O
Recommended connection method for unused pins
-
RESET
TEST
2
Input
1-A
Connect this pin to the VSS0 pin directly.
Connect these pins to the VSS0 pin.
AVREF1-AVREF3
AVSS
-
AVDD
Connect this pin to the VDD0 pin.
Caution When the I/O mode of an I/O dual-function pin is unpredictable, connect the pin to VDD0 through
a resistor of 10 to 100 kilohms (particularly when the voltage of the reset input pin becomes higher
than that of the low-level input at power-on or when I/O is switched by software).
Remark Since type numbers are consistent in the 78K series, those numbers are not always serial in each product.
(Some circuits are not included.)
18
µPD784035, 784036, 784037, 784038
Figure 6-1. I/O Circuits for Pins
Type 1-A
Type 2-C
V
DD0
VDD0
P
IN
Pull-up
enable
P
N
V
SS0
IN
Type 2
Schmitt trigger input with hysteresis characteristics
Type 5-H
IN
V
DD0
Schmitt trigger input with hysteresis characteristics
Type 4-B
V
DD0
Pull-up
enable
P
V
DD0
Data
P
Data
P
OUT
IN/OUT
Output
disable
Output
disable
N
V
N
SS0
V
SS0
Input
enable
Push-pull output which can output high impedance
(both the positive and negative channels are off.)
Type 8-C
Type 12
V
DD0
Pull-up
enable
P
V
DD0
P
N
Data
Analog output
voltage
P
OUT
IN/OUT
Output
disable
N
V
SS0
Type 10-B
Type 20-A
VDD0
V
DD0
Data
P
Pull-up
enable
IN/OUT
P
Output
disable
N
V
DD0
Data
V
SS0
P
Comparator
IN/OUT
Open
P
N
drain
+
–
N
Output
disable
V
SS0
AVSS
AVREF
(Threshold voltage)
Input
enable
19
µPD784035, 784036, 784037, 784038
7. CPU ARCHITECTURE
7.1 Memory Space
A 1M-byte memory space can be accessed. By using a LOCATION instruction, the mode for mapping internal
data areas (special function registers and internal RAM) can be selected. A LOCATION instruction must always be
executed after a reset, and can be used only once.
(1) When the LOCATION 0 instruction is executed
• Internal memory
The table below indicates the internal data areas and internal ROM areas of each product.
Product name
µPD784035
Internal data area
0F700H-0FFFFH
Internal ROM area
00000H-0BFFFH
00000H-0F6FFH
µPD784036
µPD784037
0F100H-0FFFFH
0EE00H-0FFFFH
00000H-0F0FFH
10000H-17FFFH
µPD784038
00000H-0FDFFH
10000H-1FFFFH
Caution The following internal ROM areas, existing at the same addresses as the internal data areas,
cannot be used when the LOCATION 0 instruction is executed:
Product name
µPD784035
Unusable area
-
µPD784036
µPD784037
µPD784038
0F700H-0FFFFH (2,304 bytes)
0F100H-0FFFFH (3,840 bytes)
0EE00H-0FFFFH (4,608 bytes)
• External memory
External memory is accessed in external memory expansion mode.
(2) When the LOCATION 0FH instruction is executed
-
• Internal memory
The table below lists the internal data areas and internal ROM areas for each product.
Product name
µPD784035
Internal data area
FF700H-FFFFFH
Internal ROM area
00000H-0BFFFH
00000H-0FFFFH
00000H-17FFFH
00000H-1FFFFH
µPD784036
µPD784037
µPD784038
0F100H-FFFFFH
FEE00H-FFFFFH
• External memory
External memory is accessed in external memory expansion mode.
20
Figure 7-1. µPD784035 Memory Map
When the LOCATION 0
instruction is executed
When the LOCATION
0FH instruction is executed
F
FFFFH
F F F F F H
F F F D F H
F F F D 0 H
F F F 0 0 H
Special function registers (SFRs)
Note 1
(256 bytes)
0
FFEFFH
FFEFFH
FEFFH
Internal RAM
(2,048 bytes)
General-purpose
registers (128 bytes)
External memory
(960K bytes)Note 1
0
0
FFE80H
FFE7FH
FF7 00H
FF6 FFH
FE80H
FE7FH
1
0
0
0
0
0
0 0 00H
FFFFH
FFDFH
FFD0H
FF 00H
FEFFH
0
0
FFE2FH
FFE06H
FE2FH
FE06H
Macro service control
word area (42 bytes)
Special function registers (SFRs)
Note 1
(256 bytes)
Data area (512 bytes)
µ
0
0
FD00H
FCFFH
FFD00H
FFCFFH
Internal RAM
(2,048 bytes)
Program/data area
(1,536 bytes)
External memory
(997,120 bytes)Note 1
0
0
FF7 00H
F7 00H
BFFFH
0
0
F7 00H
F6 FFH
Program/data area
(48K bytes)
External memory
Note 2
(14,080 bytes)Note 1
0
0
10 00H
0FFFH
100 00H
0FFFFH
CALLF entry area
(2K bytes)
Note 2
0
0
C0 00H
BFFFH
0C0 00H
0BFFFH
0
0
08 00H
07 FFH
0
0
00 80H
00 7FH
Internal ROM
(48K bytes)
CALLT table area
(64 bytes)
Internal ROM
(48K bytes)
0
0
00 40H
00 3FH
Vector table area
(64 bytes)
0
000 00H
00 00H
0
0 0 00H
Notes 1. Accessed in external memory expansion mode.
2. Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.
Figure 7-2. µPD784036 Memory Map
When the LOCATION 0
instruction is executed
When the LOCATION 0FH
instruction is executed
F FFFFH
F F F F F H
F F F D F H
F F F D 0 H
F F F 0 0 H
Special function registers (SFRs)
Note 1
(256 bytes)
0 FEFFH
F FEFFH
F FEFFH
Internal RAM
(2,048 bytes)
General-purpose
registers (128 bytes)
External memory
(960K bytes)Note 1
0 FE80H
0 FE7FH
F FE80H
F FE7FH
F F700H
F F6FFH
1 0000H
0 FFFFH
0 FFDFH
0 FFD0H
0 FF00H
0 FEFFH
0 FE2FH
0 FE06H
F FE2FH
F FE06H
Macro service control
word area (42 bytes)
Special function registers (SFRs)
Note 1
(256 bytes)
Data area (512 bytes)
0 FD00H
0 FCFFH
F FD00H
F FCFFH
Internal RAM
(2,048 bytes)
Program/data area
(1,536 bytes)
External memory
(980,736 bytes)Note 1
0 F700H
F F700H
0 FFFFH
0 F700H
0 F6FFH
µ
Note 2
0 F6FFH
Program/data areaNote 3
0 1000H
0 0FFFH
CALLF entry
Internal ROM
area (2K bytes)
(63,232 bytes)
Note 4
1 0000H
0 FFFFH
0 0800H
0 07FFH
0 0080H
0 007FH
CALLT table area
(64 bytes)
Internal ROM
(64K bytes)
Note 4
0 0040H
0 003FH
Vector table area
(64 bytes)
0 0000H
0 0000H
0 0000H
Notes 1. Accessed in external memory expansion mode.
2. This 2,304-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.
3. When the LOCATION 0 instruction is executed : 63,232 bytes
When the LOCATION 0FH instruction is executed: 65,536 bytes
4. Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.
Figure 7-3. µPD784037 Memory Map
When the LOCATION 0
instruction is executed
When the LOCATION 0FH
instruction is executed
Special function registers (SFRs)
Note 1
F F F F F H
F F F D F H
F F F D 0 H
F F F 0 0 H
FFFFFH
(256 bytes)
FFEFFH
0 FEFFH
FFEFFH
External memory
(928K bytes)Note 1
Internal RAM
(3,584 bytes)
General-purpose
registers (128 bytes)
0 FE80H
0 FE7FH
FFE80H
FFE7FH
FF100H
FF0FFH
1 8000H
1 7FFFH
Internal ROM
(32,768 bytes)
1 0000H
0 FFFFH
0 FFDFH
0 FFD0H
0 FF00H
0 FEFFH
0 FE2FH
0 FE06H
FFE2FH
FFE06H
Macro service control
word area (42 bytes)
Special function registers (SFRs)
Note 1
(256 bytes)
Data area (512 bytes)
0 FD00H
0 FCFFH
FFD00H
FFCFFH
Internal RAM
(3,584 bytes)
µ
Program/data area
(3,072 bytes)
External memory
(946,432 bytes)Note 1
0F100H
FF100H
1 7FFFH
0F100H
0 F0FFH
1 7 F F F H
1 0 0 0 0 H
Note 2
0 F0FFH
Program/data areaNote 3
0 1000H
0 0FFFH
CALLF entry area
(2K bytes)
Internal ROM
(61,696 bytes)
Note 4
1 8000H
1 7FFFH
0 0800H
0 07FFH
0 0080H
0 007FH
CALLT table area
(64 bytes)
Internal ROM
(96K bytes)
Note 4
0 0040H
0 003FH
Vector table area
(64 bytes)
0 0000H
0 0000H
0 0000H
Notes 1. Accessed in external memory expansion mode.
2. This 3,840-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.
3. When the LOCATION 0 instruction is executed : 94,464 bytes
When the LOCATION 0FH instruction is executed: 98,304 bytes
4. Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.
Figure 7-4. µPD784038 Memory Map
When the LOCATION 0FH
instruction is executed
Special function registers (SFRs)
Note 1
When the LOCATION 0
instruction is executed
F F F F F H
F F F D F H
F F F D 0 H
F F F 0 0 H
FFFFFH
(256 bytes)
0FEFFH
FFEFFH
FFEFFH
External memory
(896K bytes)Note 1
General-purpose
registers (128 bytes)
Internal RAM
(4,352 bytes)
0FE80H
0FE7FH
FFE80H FEE00H
FFE7FH FEDFFH
20000H
1FFFFH
Internal ROM
(65,536 bytes)
10000H
0FFFFH
0FFDFH
0FFD0H
0FF00H
0FEFFH
0FE2FH
0FE06H
FFE2FH
FFE06H
Macro service control
word area (42 bytes)
Special function registers (SFRs)
Note 1
(256 bytes)
Data area (512 bytes)
0FD00H
0FCFFH
FFD00H
FFCFFH
Internal RAM
(4,352 bytes)
Program/data area
(3,840 bytes)
External memory
(912,896 bytes)Note 1
0EE00H
FEE00H
1FFFFH
0EE00H
0EDFFH
µ
1 F F F F H
1 0 0 0 0 H
Note 2
0EDFFH
Program/data areaNote 3
01000H
00FFFH
CALLF entry area
(2K bytes)
Internal ROM
(60,928 bytes)
Note 4
20000H
1FFFFH
00800H
007FFH
00080H
0007FH
CALLT table area
(64 bytes)
Internal ROM
(128K bytes)
Note 4
00040H
0003FH
Vector table area
(64 bytes)
00000H
00000H
00000H
Notes 1. Accessed in external memory expansion mode.
2. This 4,608-byte area can be used as an internal ROM area only when the LOCATION 0FH instruction is executed.
3. When the LOCATION 0 instruction is executed : 126,464 bytes
When the LOCATION 0FH instruction is executed: 131,072 bytes
4. Base area, or entry area based on a reset or interrupt. Internal RAM is excluded in the case of a reset.
µPD784035, 784036, 784037, 784038
7.2 CPU Registers
7.2.1 General-purpose registers
A set of general-purpose registers consists of sixteen general-purpose 8-bit registers. Two 8-bit general-purpose
registers can be combined to form a 16-bit general-purpose register. Moreover, four 16-bit general-purpose registers,
when combined with an 8-bit register for address extension, can be used as 24-bit address specification registers.
Eight banks of this register set are provided. The user can switch between banks by software or the context
switching function.
General-purpose registers other than the V, U, T, and W registers used for address extension are mapped onto
internal RAM.
Figure 7-5. General-Purpose Register Format
A (R1)
B (R3)
R5
X (R0)
C (R2)
R4
AX (RP0)
BC (RP1)
RP2
R7
R6
RP3
V
R9
R8
VVP (RG4)
R11
UUP (RG5)
D (R13)
TDE (RG6)
H (R15)
WHL (RG7)
VP (RP4)
UP (RP5)
DE (RP6)
HL (RP7)
U
T
R10
E (R12)
L (R14)
W
8 banks
The character strings enclosed in
parentheses represent absolute names.
Caution By setting the RSS bit of PSW to 1, R4, R5, R6, R7, RP2, and RP3 can be used as the X, A, C, B,
AX, and BC registers, respectively. However, this function must be used only when using
programs for the 78K/III series.
25
µPD784035, 784036, 784037, 784038
7.2.2 Control registers
(1) Program counter (PC)
This register is a 20-bit program counter. The program counter is automatically updated by program execution.
Figure 7-6. Format of Program Counter (PC)
19
0
PC
(2) Program Status Word (PSW)
This register holds the CPU state. The program status word is automatically updated by program execution.
Figure 7-7. Format of Program Status Word (PSW)
15
14
13
12
11
10
9
8
UF
RBS2
RBS1
RBS0
PSWH
PSWL
PSW
7
6
Z
5
4
3
2
1
0
0
S
RSSNote
AC
IE
P/V
CY
Note This flag is used to maintain compatibility with the 78K/III series. This flag must be set to 0 when programs
for the 78K/III series are being used.
(3) Stack pointer (SP)
This register is a 24-bit pointer for holding the start address of the stack. The high-order 4 bits must be set
to 0.
Figure 7-8. Format of Stack Pointer (SP)
23
20
0
0
SP
0
0
0
26
µPD784035, 784036, 784037, 784038
7.2.3 Special function registers (SFRs)
The special function registers are registers with special functions such as mode registers and control registers
for built-in peripheral hardware. The special function registers are mapped onto the 256-byte space between 0FF00H
and 0FFFFHNote
.
Note Applicable when the LOCATION 0 instruction is executed. FFF00H-FFFFFH when the LOCATION 0FH
instruction is executed.
Caution Never attempt to access addresses in this area where no SFR is allocated. Otherwise, the
µPD784038 may be placed in the deadlock state. The deadlock state can be cleared only by a
reset.
Table 7-1 lists the special function registers (SFRs). The titles of the table columns are explained below.
• Abbreviation ................... Symbol used to represent a built-in SFR. The abbreviations listed in the table are
reserved words for the NEC assembler (RA78K4). The C compiler (CC78K4) allows
the abbreviations to be used as sfr variables with the #pragma sfr command.
• R/W ................................. Indicates whether each SFR allows read and/or write operations.
R/W : Allows both read and write operations.
R
: Allows read operations only.
: Allows write operations only.
W
• Manipulatable bits .......... Indicates the maximum number of bits that can be manipulated whenever an SFR is
manipulated. An SFR that supports 16-bit manipulation can be described in the sfrp
operand. For address specification, an even-numbered address must be speci-
fied.
An SFR that supports 1-bit manipulation can be described in a bit manipulation
instruction.
• When reset ..................... Indicates the state of each register when RESET is applied.
27
µPD784035, 784036, 784037, 784038
Table 7-1. Special Function Registers (SFRs) (1/4)
Manipulatable bits
Note
Address
Special function register (SFR) name
Abbreviation R/W
When reset
Undefined
1 bit 8 bits 16 bits
0FF00H
0FF01H
0FF02H
0FF03H
0FF04H
0FF05H
0FF06H
0FF07H
0FF0EH
0FF0FH
0FF10H
0FF12H
0FF14H
0FF15H
0FF16H
0FF17H
0FF18H
0FF19H
0FF1AH
0FF1BH
0FF1CH
0FF1DH
0FF20H
0FF21H
0FF23H
0FF24H
0FF25H
0FF26H
0FF27H
0FF2EH
0FF30H
0FF31H
0FF32H
0FF33H
Port 0
P0
R/W
-
-
-
-
-
-
-
-
-
-
Port 1
Port 2
Port 3
Port 4
Port 5
Port 6
Port 7
P1
P2
R
P3
R/W
P4
P5
P6
00H
P7
Port 0 buffer register L P0L
P0H
Undefined
Port 0 buffer register H
Compare register (timer/counter 0)
Capture/compare register (timer/counter 0)
Compare register L (timer/counter 1)
Compare register H (timer/counter 1)
Capture/compare register L (timer/counter 1)
Capture/compare register H (timer/counter 1)
Compare register L (timer/counter 2)
Compare register H (timer/counter 2)
Capture/compare register L (timer/counter 2)
Capture/compare register H (timer/counter 2)
Compare register L (timer 3)
CR00
-
-
-
-
-
-
-
-
-
-
-
-
-
-
CR01
CR10 CR10W
-
-
-
-
-
-
CR11 CR11W
-
CR20 CR20W
-
CR21 CR21W
-
CR30 CR30W
-
Compare register H (timer 3)
Port 0 mode register
PM0
-
-
-
-
-
-
-
-
-
-
-
-
FFH
Port 1 mode register
PM1
Port 3 mode register
PM3
Port 4 mode register
PM4
Port 5 mode register
PM5
Port 6 mode register
PM6
Port 7 mode register
PM7
Real-time output port control register
Capture/compare control register 0
Timer output control register
RTPC
CRC0
TOC
00H
10H
00H
-
Capture/compare control register 1
Capture/compare control register 2
CRC1
CRC2
-
-
10H
Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is
executed, F0000H is added to each address.
28
µPD784035, 784036, 784037, 784038
Table 7-1. Special Function Registers (SFRs) (2/4)
Manipulatable bits
Note
Address
Special function register (SFR) name
Abbreviation R/W
When reset
0000H
1 bit 8 bits 16 bits
0FF36H
0FF38H
0FF39H
0FF3AH
0FF3BH
0FF41H
0FF43H
0FF4EH
0FF50H
0FF51H
0FF52H
0FF53H
0FF54H
0FF55H
0FF56H
0FF57H
0FF5CH
0FF5DH
0FF5EH
0FF5FH
0FF60H
0FF61H
0FF62H
0FF68H
0FF6AH
0FF70H
0FF71H
0FF72H
0FF74H
0FF7DH
0FF80H
0FF81H
0FF82H
Capture register (timer/counter 0)
Capture register L (timer/counter 1)
Capture register H (timer/counter 1)
Capture register L (timer/counter 2)
Capture register H (timer/counter 2)
Port 1 mode control register
CR02
R
-
-
-
-
-
-
-
-
CR12 CR12W
-
CR22 CR22W
-
PMC1
PMC3
PUO
TM0
R/W
R
-
-
-
00H
Port 3 mode control register
Register for optional pull-up resistor
Timer register 0
-
-
-
-
-
-
-
-
-
-
-
0000H
Timer register 1
Timer register 2
Timer register 3
TM1 TM1W
-
-
-
-
TM2 TM2W
-
TM3 TM3W
-
Prescaler mode register 0
Timer control register 0
PRM0
TMC0
PRM1
TMC1
DACS0
DACS1
DAM
R/W
-
-
-
-
-
-
-
-
-
-
-
11H
00H
11H
00H
Prescaler mode register 1
Timer control register 1
-
D/A conversion value setting register 0
D/A conversion value setting register 1
D/A converter mode register
A/D converter mode register
A/D conversion result register
PWM control register
-
-
03H
ADM
00H
ADCR
PWMC
PWPR
PWM0
PWM1
OSPC
IICC
R
-
Undefined
05H
R/W
PWM prescaler register
-
-
-
00H
PWM modulo register 0
-
-
Undefined
PWM modulo register 1
One-shot pulse output control register
-
-
-
-
00H
2
I C bus control register
Prescaler mode register for serial clock
Synchronous serial interface mode register
SPRM
CSIM
-
04H
00H
Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is
executed, F0000H is added to each address.
29
µPD784035, 784036, 784037, 784038
Table 7-1. Special Function Registers (SFRs) (3/4)
Manipulatable bits
Note 1
Address
Special function register (SFR) name
Abbreviation R/W
When reset
00H
1 bit 8 bits 16 bits
0FF84H
0FF85H
0FF86H
0FF88H
0FF89H
0FF8AH
0FF8BH
0FF8CH
Synchronous serial interface mode register 1
Synchronous serial interface mode register 2
Serial shift register
CSIM1
CSIM2
SIO
R/W
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Asynchronous serial interface mode register
ASIM
Asynchronous serial interface mode register 2 ASIM2
Asynchronous serial interface status register
ASIS
R
Asynchronous serial interface status register 2 ASIS2
Serial receive buffer: UART0
Serial transmission shift register: UART0
Serial shift register: IOE1
RXB
-
-
-
-
-
-
-
-
Undefined
TXS
W
SIO1
R/W
R
0FF8DH
Serial receive buffer: UART2
Serial transmission shift register: UART2
Serial shift register: IOE2
RXB2
TXS2
SIO2
W
R/W
0FF90H
0FF91H
0FFA0H
0FFA1H
0FFA4H
0FFA8H
0FFAAH
0FFACH
0FFADH
0FFAEH
0FFC0H
0FFC2H
0FFC4H
0FFC5H
0FFC6H
0FFC7H
0FFC8H
Baud rate generator control register
Baud rate generator control register 2
External interrupt mode register 0
External interrupt mode register 1
Sampling clock selection register
In-service priority register
BRGC
BRGC2
INTM0
INTM1
SCS0
ISPR
00H
-
R
Interrupt mode control register
Interrupt mask register 0L
IMC
R/W
80H
MK0L MK0
MK0H
MK1L
STBC
WDM
MM
FFFFH
Interrupt mask register 0H
Interrupt mask register 1L
-
-
-
-
-
-
-
FFH
30H
00H
20H
00H
Note 2
Note 2
Standby control register
-
-
Watchdog timer mode register
Memory expansion mode register
Hold mode register
HLDM
CLOM
PWC1
PWC2
Clock output mode register
Programmable wait control register 1
Programmable wait control register 2
-
-
AAH
-
AAAAH
Notes 1. Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is
executed, F0000H is added to each address.
2. A write operation can be performed only with special instructions MOV STBC,#byte and MOV
WDM,#byte. Other instructions cannot perform a write operation.
30
µPD784035, 784036, 784037, 784038
Table 7-1. Special Function Registers (SFRs) (4/4)
Manipulatable bits
Note
Address
Special function register (SFR) name
Abbreviation R/W
When reset
00H
1 bit 8 bits 16 bits
0FFCCH
0FFCDH
0FFCFH
0FFD0H-
0FFDFH
0FFE0H
0FFE1H
0FFE2H
0FFE3H
0FFE4H
0FFE5H
0FFE6H
0FFE7H
0FFE8H
0FFE9H
0FFEAH
0FFEBH
0FFECH
0FFEDH
0FFEEH
0FFEFH
Refresh mode register
RFM
RFA
R/W
-
-
Refresh area specification register
Oscillation settling time specification register
External SFR area
OSTS
-
-
-
-
-
Interrupt control register (INTP0)
Interrupt control register (INTP1)
Interrupt control register (INTP2)
Interrupt control register (INTP3)
Interrupt control register (INTC00)
Interrupt control register (INTC01)
Interrupt control register (INTC10)
Interrupt control register (INTC11)
Interrupt control register (INTC20)
Interrupt control register (INTC21)
Interrupt control register (INTC30)
Interrupt control register (INTP4)
Interrupt control register (INTP5)
Interrupt control register (INTAD)
Interrupt control register (INTSER)
Interrupt control register (INTSR)
Interrupt control register (INTCSI1)
Interrupt control register (INTST)
Interrupt control register (INTCSI)
Interrupt control register (INTSER2)
Interrupt control register (INTSR2)
Interrupt control register (INTCSI2)
Interrupt control register (INTST2)
PIC0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
43H
PIC1
PIC2
PIC3
CIC00
CIC01
CIC10
CIC11
CIC20
CIC21
CIC30
PIC4
PIC5
ADIC
SERIC
SRIC
CSIIC1
STIC
0FFF0H
0FFF1H
0FFF2H
0FFF3H
CSIIC
SERIC2
SRIC2
CSIIC2
STIC2
0FFF4H
Note Applicable when the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is
executed, F0000H is added to each address.
31
µPD784035, 784036, 784037, 784038
8. PERIPHERAL HARDWARE FUNCTIONS
8.1 Ports
The ports shown in Figure 8-1 are provided to enable the application of wide-ranging control. Table 8-1 lists the
functions of the ports. For the inputs to port 0 to port 6, a built-in pull-up resistor can be specified by software.
Figure 8-1. Port Configuration
P00
Port 0
P07
P10
Port 1
P17
P20-P27
P30
Port 2
8
Port 3
P37
P40
Port 4
P47
P50
Port 5
Port 6
Port 7
P57
P60
P67
P70
P77
32
µPD784035, 784036, 784037, 784038
Table 8-1. Port Functions
Port name
Port 0
Pin
Function
Pull-up specification by software
P00-P07
• Bit-by-bit input/output setting supported
• Operable as 4-bit real-time outputs
(P00-P03, P04-P07)
Specified as a batch for all pins placed in
input mode.
• Capable of driving transistors
Port 1
P10-P17
• Bit-by-bit input/output setting supported
• Capable of driving LEDs
Specified as a batch for all pins placed in
input mode.
Port 2
Port 3
P20-P27
P30-P37
• Input port
Specified for the 6 bits (P22-P27) as a batch.
• Bit-by-bit input/output setting supported
Specified as a batch for all pins placed in
input mode.
Port 4
Port 5
Port 6
Port 7
P40-P47
P50-P57
P60-P67
P70-P77
• Bit-by-bit input/output setting supported
• Capable of driving LEDs
Specified as a batch for all pins placed in
input mode.
• Bit-by-bit input/output setting supported
• Capable of driving LEDs
Specified as a batch for all pins placed in
input mode.
• Bit-by-bit input/output setting supported
Specified as a batch for all pins placed in
input mode.
• Bit-by-bit input/output setting supported
-
8.2 Clock Generator
A circuit for generating the clock signal required for operation is provided. The clock generator includes a frequency
divider; low current consumption can be achieved by operating at a lower internal frequency when high-speed
operation is not necessary.
Figure 8-2. Block Diagram of Clock Generator
X1
f
XX
Oscillator
1/2
1/2
1/2
1/2
X2
f
CLK
CPU
Peripheral circuits
fXX/2
UART/IOE
INTP0 noise eliminator
Oscillation settling timer
Remark fXX : Oscillator frequency or external clock input frequency
fCLK: Internal operating frequency
33
µPD784035, 784036, 784037, 784038
Figure 8-3. Examples of Using Oscillator
(1) Crystal/ceramic oscillation
µ
PD784038
V
SS1
X1
X2
(2) External clock
• When EXTC bit of OSTS = 1
• When EXTC bit of OSTS = 0
PD784038
µ
µPD784038
X1
X1
Open
X2
X2
PD74HC04, etc.
µ
Caution When using the system clock generator, run wires in the portion surrounded by broken lines
according to the following rules to avoid effects such as stray capacitance:
• Minimize the wiring.
• Never cause the wires to cross other signal lines.
• Never cause the wires to run near a line carrying a large varying current.
• Cause the grounding point of the capacitor of the oscillator circuit to have the same potential
as VSS1. Never connect the capacitor to a ground pattern carrying a large current.
• Never extract a signal from the oscillator.
34
µPD784035, 784036, 784037, 784038
8.3 Real-Time Output Port
The real-time output port outputs data stored in the buffer, synchronized with a timer/counter 1 match interrupt
or external interrupt. Thus, pulse output that is free of jitter can be obtained.
Therefore, the real-time output port is best suited to applications (such as open-loop control over stepping motors)
where an arbitrary pattern is output at arbitrary intervals.
As shown in Figure 8-4, the real-time output port is built around port 0 and the port 0 buffer register (P0H, P0L).
Figure 8-4. Block Diagram of Real-Time Output Port
Internal bus
4
4
8
Real-time output port
control register
(RTPC)
Buffer register
8
P0H
4
P0L
4
INTP0 (externally)
INTC10 (from timer/counter 1)
INTC11 (from timer/counter 1)
Output trigger
control circuit
Output latch (P0)
P00
P07
35
µPD784035, 784036, 784037, 784038
8.4 Timers/Counters
Three timer/counter units and one timer unit are incorporated.
Moreover, seven interrupt requests are supported, allowing these units to function as seven timer/counter units.
Table 8-2. Timer/Counter Operation
Name
Timer/counter 0 Timer/counter 1 Timer/counter 2
-
Timer 3
Item
Count pulse width 8 bits
16 bits
Operating mode
Interval timer
2ch
2ch
2ch
2ch
1ch
External event counter
One-shot timer
-
-
-
-
-
-
-
-
Function
Timer output
2ch
-
Toggle output
-
PWM/PPG output
One-shot pulse output
Real-time output
-
Note
-
-
-
1 input
2
-
2 inputs
2
-
Pulse width measurement
1 input
2
-
Number of interrupt requests
1
Note The one-shot pulse output function makes the level of a pulse output active by software, and makes the
level of a pulse output inactive by hardware (interrupt request signal).
Note that this function differs from the one-shot timer function of timer/counter 2.
36
µPD784035, 784036, 784037, 784038
Figure 8-5. Timer/Counter Block Diagram
Timer/counter 0
Clear information
Software trigger
OVF
Timer register 0
(TM0)
f
xx/8
Prescaler
Match
Match
Compare register
(CR00)
TO0
TO1
Compare register
(CR01)
Capture register
(CR02)
Edge
detection
INTP3
INTC00
INTC01
INTP3
Timer/counter 1
Clear information
Timer register 1
(TM1/TM1W)
f
xx/8
Prescaler
OVF
Match
Match
Event input
Compare register
(CR10/CR10W)
INTC10
To real-time
output port
INTC11
Edge
detection
Capture/compare register
(CR11/CR11W)
INTP0
INTP0
Capture register
(CR12/CR12W)
Timer/counter 2
Clear information
Timer register 2
(TM2/TM2W)
f
xx/8
Prescaler
OVF
Match
Match
Compare register
(CR20/CR20W)
TO2
TO3
Edge
detection
INTP2/C1
INTP2
Capture/compare register
(CR21/CR21W)
Capture register
(CR22/CR22W)
Edge
detection
INTP1
INTC20
INTC21
INTP1
Timer 3
Clear
Timer register 3
(TM3/TM3W)
f
xx/8
Prescaler
CSI
Match
Compare register
(CR30/CR30W)
INTC30
Remark OVF: Overflow flag
37
µPD784035, 784036, 784037, 784038
8.5 PWM Output (PWM0, PWM1)
Two channels of PWM (pulse width modulation) output circuitry with a resolution of 12 bits and a repetition
frequency of 62.5 kHz (fCLK = 16 MHz) are incorporated. Low or high active level can be selected for the PWM output
channels, independently of each other. This output is best suited to DC motor speed control.
Figure 8-6. Block Diagram of PWM Output Unit
Internal bus
16
8
PWM modulo register
PWM control register
8
7
4 3
15
0
PWMn
(PWMC)
8
4
Reload
control
Pulse control
circuit
8-bit
down-counter
Output
control
Prescaler
fCLK
PWMn (output pin)
4-bit counter
1/256
Remark n = 0, 1
38
µPD784035, 784036, 784037, 784038
8.6 A/D Converter
An analog/digital (A/D) converter having 8 multiplexed analog inputs (ANI0-ANI7) is incorporated.
The successive approximation system is used for conversion. The result of conversion is held in the 8-bit A/D
conversion result register (ADCR). Thus, speedy high-precision conversion can be achieved. (The conversion time
is about 7.5 µs at fCLK = 16 MHz.)
A/D conversion can be started in any of the following modes:
• Hardware start: Conversion is started by means of trigger input (INTP5).
• Software start : Conversion is started by means of bit setting the A/D converter mode register (ADM).
After conversion has started, one of the following modes can be selected:
• Scan mode : Multiple analog inputs are selected sequentially to obtain conversion data from all pins.
• Select mode: A single analog input is selected at all times to enable conversion data to be obtained
continuously.
ADM is used to specify the above modes, as well as the termination of conversion.
When the result of conversion is transferred to ADCR, an interrupt request (INTAD) is generated. Using this feature,
the results of conversion can be continuously transferred to memory by the macro service.
Figure 8-7. Block Diagram of A/D Converter
ANI0
Series resistor string
Sample-and-hold circuit
ANI1
ANI2
ANI3
ANI4
ANI5
ANI6
ANI7
AVREF1
R/2
R
Voltage comparator
Successive conver-
sion register (SAR)
Conversion
trigger
Edge
detector
INTAD
INTP5
Control
circuit
R/2
AVSS
Trigger enable
8
A/D converter mode
register (ADM)
A/D conversion
result register (ADCR)
8
8
Internal bus
39
µPD784035, 784036, 784037, 784038
8.7 D/A Converter
Two digital/analog (D/A) converter channels of voltage output type, having a resolution of 8 bits, are incorporated.
An R-2R resistor ladder system is used for conversion. By writing the value to be subject to D/A conversion in
the 8-bit D/A conversion value setting register (DACSn: n = 0, 1), the resulting analog value is output on ANOn
(n = 0, 1). The range of the output voltages is determined by the voltages applied to the AVREF2 and AVREF3 pins.
Because of its high output impedance, no current can be obtained from an output pin. When the load impedance
is low, insert a buffer amplifier between the load and the converter.
The impedance of the ANOn pin goes high while the RESET signal is low. DACSn is set to 0 after a reset
is released.
Figure 8-8. Block Diagram of D/A Converter
ANOn
2R
AVREF2
R
2R
Selector
R
2R
AVREF3
R
2R
DACEn
DACSn
Internal bus
Remark n = 0, 1
40
µPD784035, 784036, 784037, 784038
8.8 Serial Interface
Three independent serial interface channels are incorporated.
• Asynchronous serial interface (UART)/three-wire serial I/O (IOE) × 2
• Synchronous serial interface (CSI) × 1
• Three-wire serial I/O (IOE)
• Two-wire serial I/O (IOE)
So, communication with points external to the system and local communication within the system can be performed
at the same time. (See Figure 8-9.)
Figure 8-9. Example Serial Interfaces
UART + Three-wire serial I/O + Two-wire serial I/O
µ
PD784038 (master)
PD75108 (slave)
µ
[Three-wire serial I/O]
PD4711A
µ
SO1
SI1
SI
(UART)
SO
SCK
Port
RxD
TxD
SCK1
INTPm
Port
Note
RS-232-C
driver/receiver
Port
INT
VDD
VDD
µ
PD78014 (slave)
SDA
SCL
SB0
SCK0
Port
Note
INTPn
Port
INT
[Two-wire serial I/O]
Note Handshake line
41
µPD784035, 784036, 784037, 784038
8.8.1 Asynchronous serial interface/three-wire serial I/O (UART/IOE)
Two serial interface channels are available; for each channel, asynchronous serial interface mode or three-wire
serial I/O mode can be selected.
(1) Asynchronous serial interface mode
In this mode, 1-byte data is transferred after a start bit.
A baud rate generator is incorporated to enable communication at a wide range of baud rates.
Moreover, the frequency of a clock signal applied to the ASCK pin can be divided to define a baud rate.
With the baud rate generator, the baud rate conforming to the MIDI standard (31.25 kbps) can be obtained.
Figure 8-10. Block Diagram of Asynchronous Serial Interface Mode
Internal bus
RXB, RXB2
Receive buffer
Transmission
shift register
Receive
shift register
RxD, RxD2
TxD, TxD2
TXS, TXS2
INTSR,
Transmission
control parity
bit addition
Reception
control parity
check
INTSR2
INTSER,
INTSER2
INTST, INTST2
Baud rate generator
1/2m
1/2m
f
XX/2
1/2 n+1
ASCK, ASCK2
Remark fXX: Oscillator frequency or external clock input frequency
n = 0 to 11
m = 16 to 30
42
µPD784035, 784036, 784037, 784038
(2) Three-wire serial I/O mode
In this mode, the master device makes the serial clock active to start transmission, then transfers 1-byte data
in phase with the clock.
This mode is designed for communication with a device incorporating a conventional synchronous serial interface.
Basically, three lines are used for communication: the serial clock line (SCK) and the two serial data lines
(SI and SO).
In general, a handshake line is required to check the communication state.
Figure 8-11. Block Diagram of Three-Wire Serial I/O Mode
Internal bus
Direction control
circuit
SIO1, SIO2
Shift register
Output latch
SI1, SI2
SO1, SO2
Interrupt signal
generator
INTCSI1,
INTCSI2
SCK1, SCK2
Serial clock counter
1/2n+1
f
XX/2
1/m
Serial clock
control circuit
Remark fXX: Oscillator frequency or external clock input frequency
n = 0 to 11
m = 1, 16 to 30
43
µPD784035, 784036, 784037, 784038
8.8.2 Synchronous serial interface (CSI)
With this interface, the master device makes the serial clock active to start transmission, then transfers 1-byte data
in phase with the clock.
Figure 8-12. Block Diagram of Synchronous Serial Interface
Internal bus
Direction
control circuit
Reset
Output latch
Set
SI0
Shift register
SO0/SDA
N-ch open-drain
output enabled
(when two-wire
mode is used)
Interrupt signal
generator
Serial clock
counter
SCK0/SCL
INTCSI
Timer 3 output
Serial clock
control circuit
N-ch open-drain
output enabled
(when two-wire
mode is used)
f
XX/16
CLS0
CLS1
fXX/2
Remark fXX: Oscillator frequency or external clock input frequency
44
µPD784035, 784036, 784037, 784038
(1) Three-wire serial I/O mode
This mode is designed for communication with a device incorporating a conventional synchronous serial interface.
Basically, three lines are used for communication: the serial clock line (SCK0) and serial data lines (SI0 and SO0).
In general, a handshake line is required to check the communication state.
(2) Two-wire serial I/O mode
In this mode, 8-bit data is transferred using two lines: the serial clock line (SCL) and serial data bus (SDA).
In general, a handshake line is required to check the communication state.
8.9 Clock Output Function
The frequency of the CPU clock signal can be divided for output to a point external to the system. Moreover, the
port can be used as a 1-bit port.
The ASTB pin is also used for the CLKOUT pin, so that when this function is used, the local bus interface cannot
be used.
Figure 8-13. Block Diagram of Clock Output Function
f
f
f
CLK
CLK/2
CLK/4
Output control
CLKOUT
f
f
CLK/8
CLK/16
Enable output
Output level
45
µPD784035, 784036, 784037, 784038
8.10 Edge Detection Function
The interrupt input pins (NMI, INTP0-INTP5) are used to apply not only interrupt requests but also trigger signals
for the built-in circuits. As these pins are triggered by an edge (rising or falling) of an input signal, a function for edge
detection is incorporated. Moreover, a noise suppression function is provided to prevent erroneous edge detection
caused by noise.
Pin
Detectable edge
Noise suppression method
Analog delay
NMI
Rising edge or falling edge
Note
INTP0-INTP3
INTP4, INTP5
Rising edge or falling edge, or both edges
Clock sampling
Analog delay
Note INTP0 is used for sampling clock selection.
8.11 Watchdog Timer
A watchdog timer is incorporated for CPU runaway detection. The watchdog timer, if not cleared by software within
a specified interval, generates a nonmaskable interrupt. Furthermore, once watchdog timer operation is enabled,
it cannot be disabled by software. The user can specify whether priority is placed on an interrupt based on the
watchdog timer or on an interrupt based on the NMI pin.
Figure 8-14. Block Diagram of Watchdog Timer
f
CLK
Timer
f
CLK/221
f
CLK/220
INTWDT
f
f
CLK/219
CLK/217
Clear signal
46
µPD784035, 784036, 784037, 784038
9. INTERRUPT FUNCTION
Table 9-1 lists the interrupt request handling modes. These modes are selected by software.
Table 9-1. Interrupt Request Handling Modes
Handling mode
Handled by
Handling
PC and PSW contents
Vectored interrupt Software
Branches to a handling routine for execution
(arbitrary handling).
The PC and PSW contents are pushed
to and popped from the stack.
Context switching
Automatically selects a register bank, and
branches to a handling routine for execution
(arbitrary handling).
The PC and PSW contents are saved to
and read from a fixed area in the
register bank.
Macro service
Firmware
Performs operations such as memory-to-I/O-
device data transfer (fixed handling).
Maintained
9.1 Interrupt Source
An interrupt can be issued from any one of the interrupt sources listed in Table 9-2: execution of a BRK instruction
and BRKCS instruction, an operand error, or any of the 23 other interrupt sources.
Four levels of interrupt handling priority can be set. Priority levels can be set to nest control during interrupt handling
or to concurrently generate interrupt requests. Nested macro services, however, are performed without suspension.
When interrupt requests having the same priority level are generated, they are handled according to the default
priority (fixed). (See Table 9-2.)
47
µPD784035, 784036, 784037, 784038
Table 9-2. Interrupt Sources
Source
Trigger
Default
priority
Internal/
external
Macro
Type
service
Name
Software
-
BRK instruction
BRKCS instruction
Operand error
Instruction execution
-
-
When the MOV STBC,#byte, MOV WDM,#byte, or LOCATION
instruction is executed, exclusive OR of the byte operand and byte
does not produce FFH.
Nonmaskable
Maskable
-
NMI
Detection of edge input on the pin
Watchdog timer overflow
External
Internal
External
-
WDT
0 (highest) INTP0
Detection of edge input on the pin
Enabled
(TM1/TM1W capture trigger, TM1/TM1W event counter input)
1
2
3
INTP1
INTP2
INTP3
Detection of edge input on the pin
(TM2/TM2W capture trigger, TM2/TM2W event counter input)
Detection of edge input on the pin
(TM2/TM2W capture trigger, TM2/TM2W event counter input)
Detection of edge input on the pin
(TM0 capture trigger, TM0 event counter input)
4
5
6
INTC00
INTC01
INTC10
TM0-CR00 match signal issued
TM0-CR01 match signal issued
Internal
Enabled
TM1-CR10 match signal issued (in 8-bit operation mode)
TM1W-CR10W match signal issued (in 16-bit operation mode)
7
INTC11
INTC20
INTC21
INTC30
TM1-CR11 match signal issued (in 8-bit operation mode)
TM1W-CR11W match signal issued (in 16-bit operation mode)
8
TM2-CR20 match signal issued (in 8-bit operation mode)
TM2W-CR20W match signal issued (in 16-bit operation mode)
9
TM2-CR21 match signal issued (in 8-bit operation mode)
TM2W-CR21W match signal issued (in 16-bit operation mode)
10
TM3-CR30 match signal issued (in 8-bit operation mode)
TM3W-CR30W match signal issued (in 16-bit operation mode)
11
12
13
14
15
INTP4
Detection of edge input on the pin
External
Internal
Enabled
INTP5
Detection of edge input on the pin
INTAD
A/D converter processing completed (ADCR transfer)
ASI0 reception error
Enabled
-
INTSER
INTSR
ASI0 reception completed or CSI1 transfer completed
Enabled
INTCSI1
INTST
16
17
18
19
ASI0 transmission completed
CSI0 transfer completed
INTCSI
INTSER2
INTSR2
INTCSI2
ASI2 reception error
-
ASI2 reception completed or CSI2 transfer completed
Enabled
20 (lowest) INTST2
ASI2 transmission completed
Remark ASI: Asynchronous serial interface
CSI: Synchronous serial interface
48
µPD784035, 784036, 784037, 784038
9.2 Vectored Interrupt
When a branch to an interrupt handling routine occurs, the vector table address corresponding to the interrupt
source is used as the branch address.
Interrupt handling by the CPU consists of the following operations :
• When a branch occurs : Push the CPU status (PC and PSW contents) to the stack.
• When control is returned: Pop the CPU status (PC and PSW contents) from the stack.
To return control from the handling routine to the main routine, use the RETI instruction. The branch destination
addresses must be within the range of 0 to FFFFH.
Table 9-3. Vector Table Address
Interrupt source
BRK instruction
Vector table address
003EH
Operand error
NMI
003CH
0002H
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
0016H
0018H
001AH
001CH
001EH
0020H
0022H
0024H
WDT
INTP0
INTP1
INTP2
INTP3
INTC00
INTC01
INTC10
INTC11
INTC20
INTC21
INTC30
INTP4
INTP5
INTAD
INTSER
INTSR
INTCSI1
INTST
0026H
0028H
002AH
002CH
INTCSI
INTSER2
INTSR2
INTCSI2
INTST2
002EH
49
µPD784035, 784036, 784037, 784038
9.3 Context Switching
When an interrupt request is generated, or when the BRKCS instruction is executed, an appropriate register bank
is selected by the hardware. Then, a branch to a vector address stored in that register bank occurs. At the same
time, the contents of the current program counter (PC) and program status word (PSW) are stacked in the register
bank.
The branch address must be within the range of 0 to FFFFH.
Figure 9-1. Context Switching Caused by an Interrupt Request
0000B
7
Transfer
PC15-0
Register bank (0-7)
Register bank n (n = 0-7)
PC19-16
A
B
X
C
6
Exchange
Save
2
R5
R7
R4
R6
Save
(Bits 8 to 11 of
temporary register)
5
VP
UP
V
U
T
Switching between register banks
(RBS0-RBS2 ← n)
RSS ← 0
3
4
Temporary register
D
H
E
L
IE ← 0
W
1
Save
PSW
9.4 Macro Service
The macro service function enables data transfer between memory and special function registers (SFRs) without
requiring the intervention of the CPU. The macro service controller accesses both memory and SFRs within the same
transfer cycle to directly transfer data without having to perform data fetch.
Since the CPU status is neither saved nor restored, nor is data fetch performed, high-speed data transfer is
possible.
Figure 9-2. Macro Service
Write
Read
Read
Write
Macro service
controller
CPU
Memory
SFR
Internal bus
50
µPD784035, 784036, 784037, 784038
9.5 Examples of Macro Service Applications
(1) Serial interface transmission
Transmission data storage buffer (memory)
Data n
Data n-1
Data 2
Data 1
Internal bus
Transmission
TXS (SFR)
TxD
shift register
Transmission control
INTST
Each time macro service request (INTST) is generated, the next transmission data is transferred from memory
to TXS. When data n (last byte) has been transferred to TXS (that is, once the transmission data storage buffer
becomes empty), vectored interrupt request (INTST) is generated.
(2) Serial interface reception
Reception data storage buffer (memory)
Data n
Data n-1
Data 2
Data 1
Internal bus
Reception buffer
RXB (SFR)
Reception
shift register
RxD
Reception control
INTSR
Each time macro service request (INTSR) is generated, reception data is transferred from RXB to memory. When
data n (last byte) has been transferred to memory (that is, once the reception data storage buffer becomes full),
vectored interrupt request (INTSR) is generated.
51
µPD784035, 784036, 784037, 784038
(3) Real-time output port
INTC10 and INTC11 function as the output triggers for the real-time output ports. For these triggers, the macro
service can simultaneously set the next output pattern and interval. Therefore, INTC10 and INTC11 can be used
to independently control two stepping motors. They can also be applied to PWM and DC motor control.
Output pattern profile (memory)
Output timing profile (memory)
Pn
Tn
P
n–1
T
n–1
P
2
T
2
1
P1
T
Internal bus
Internal bus
Match
(SFR)
P0L
CR10
TM1
(SFR)
INTC10
Output latch
P00-P03
Each time macro service request (INTC10) is generated, a pattern and timing data are transferred to the buffer
register (P0L) and compare register (CR10), respectively. When the contents of timer register 1 (TM1) and CR10
match, another INTC10 is generated, and the P0L contents are transferred to the output latch. When Tn (last
byte) is transferred to CR10, vectored interrupt request (INTC10) is generated.
For INTC11, the same operation as that performed for INTC10 is performed.
52
µPD784035, 784036, 784037, 784038
10. LOCAL BUS INTERFACE
The local bus interface enables the connection of external memory and I/O devices (memory-mapped I/O). It
supports a 1M-byte memory space. (See Figure 10-1.)
Figure 10-1. Example of Local Bus Interface
PD784038
µ
A16-A19
RD
WR
Kanji character
generator
µPD24C1000
PROM
PD27C1001A
Pseudo SRAM
µ
REFRQ
Data bus
AD0-AD7
ASTB
Latch
Address bus
A8-A15
Gate array for I/O
expansion including
Centronics interface
circuit, etc.
10.1 Memory Expansion
By adding external memory, program memory or data memory can be expanded, 256 bytes at a time, to
approximately 1M byte (seven steps).
53
µPD784035, 784036, 784037, 784038
10.2 Memory Space
The 1M-byte memory space is divided into eight spaces, each having a logical address. Each of these spaces
can be controlled using the programmable wait and pseudo-static RAM refresh functions.
Figure 10-2. Memory Space
FFFFFH
512K bytes
80000H
7FFFFH
256K bytes
40000H
3FFFFH
128K bytes
20000H
1FFFFH
64K bytes
10000H
0FFFFH
16K bytes
0C000H
0BFFFH
16K bytes
08000H
07FFFH
16K bytes
04000H
03FFFH
16K bytes
00000H
54
µPD784035, 784036, 784037, 784038
10.3 Programmable Wait
When the memory space is divided into eight spaces, a wait state can be separately inserted for each memory
space while the RD or WR signal is active. This prevents the overall system efficiency from being degraded even
when memory devices having different access times are connected.
In addition, an address wait function that extends the ASTB signal active period is provided to produce a longer
address decode time. (This function is set for the entire space.)
10.4 Pseudo-Static RAM Refresh Function
Refresh is performed as follows:
• Pulse refresh
: A bus cycle is inserted where a refresh pulse is output on the REFRQ pin at regular
intervals. When the memory space is divided into eight, and a specified area
is being accessed, refresh pulses can also be output on the REFRQ pin as the
memory is being accessed. This can prevent the refresh cycle from suspending
normal memory access.
• Power-down self-refresh : In standby mode, a low-level signal is output on the REFRQ pin to maintain the
contents of pseudo-static RAM.
10.5 Bus Hold Function
A bus hold function is provided to facilitate connection to devices such as a DMA controller. Suppose that a bus
hold request signal (HLDRQ) is received from an external bus master. In this case, upon the completion of the bus
cycle being performed, the address bus, address/data bus, ASTB, RD, and WR pins are placed in the high-impedance
state, and the bus hold acknowledge signal (HLDAK) is made active to release the bus for the external bus master.
While the bus hold function is being used, the external wait and pseudo-static RAM refresh functions are disabled.
55
µPD784035, 784036, 784037, 784038
11. STANDBY FUNCTION
The standby function allows the power consumption of the chip to be reduced. The following standby modes are
supported:
• HALT mode : The CPU operation clock is stopped. By occasionally inserting the HALT mode during normal
operation, the overall average power consumption can be reduced.
• IDLE mode : The entire system is stopped, with the exception of the oscillator circuit. This mode consumes
only very little more power than STOP mode, but normal program operation can be restored in
almost as little time as that required to restore normal program operation from HALT mode.
• STOP mode : The oscillator is stopped. All operations in the chip stop, such that only leakage current flows.
These modes can be selected by software.
A macro service can be initiated in HALT mode.
Figure 11-1. Standby Mode Status Transition
Macro service request
End of one operation
End of macro service
Program
operation
Macro
service
Wait for
oscillation
settling
HALT
(standby)
IDLE
(standby)
STOP
(standby)
Request for masked interrupt
Notes 1. INTP4 and INTP5 are applied when not masked.
2. Only when the interrupt request is not masked
Remark NMI is enabled only by external input. The watchdog timer cannot be used to release one of the standby
modes (STOP or IDLE mode).
56
µPD784035, 784036, 784037, 784038
12. RESET FUNCTION
Applying a low-level signal to the RESET pin initializes the internal hardware (reset status).
When the RESET input makes a low-to-high transition, the following data is loaded into the program counter (PC):
• Eight low-order bits of the PC
: Contents of location at address 0000H
• Intermediate eight bits of the PC : Contents of location at address 0001H
• Four high-order bits of the PC : 0
The PC contents are used as a branch destination address. Program execution starts from that address. Therefore,
a reset start can be performed from an arbitrary address.
The contents of each register can be set by software, as required.
The RESET input circuit contains a noise eliminator to prevent malfunctions caused by noise. This noise eliminator
is an analog delay sampling circuit.
Figure 12-1. Accepting a Reset
Execute instruction
at reset start address
Delay
Initialize PC
Delay
Delay
RESET
(input)
Internal reset signal
Start reset
End reset
For power-on reset, the RESET signal must be held active until the oscillation settling time (approximately 40 ms)
has elapsed.
Figure 12-2. Power-On Reset
Execute instruction at
reset start address
Oscillation settling time
Delay
Initialize PC
VDD
RESET
(input)
Internal reset signal
End reset
57
µPD784035, 784036, 784037, 784038
13. INSTRUCTION SET
(1) 8-bit instructions (The instructions enclosed in parentheses are implemented by a combination of
operands, where A is described as r.)
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, MULU, DIVUW, INC, DEC, ROR, ROL, RORC,
ROLC, SHR, SHL, ROR4, ROL4, DBNZ, PUSH, POP, MOVM, XCHM, CMPME, CMPMNE, CMPMNC, CMPMC,
MOVBK, XCHBK, CMPBKE, CMPBKNE, CMPBKNC, CMPBKC, CHKL, CHKLA
Table 13-1. Instructions Implemented by 8-Bit Addressing
Note 2
2nd operand
#byte
A
r
saddr
saddr'
sfr
!addr16
mem
r3
[WHL+]
[WHL–]
n
None
r'
!!addr24 [saddrp]
[%saddrg]
PSWL
PSWH
1st operand
Note 6
A
(MOV)
(MOV)
(XCH)
MOV
(MOV)
MOV
(XCH)
(MOV)
(XCH)
MOV
XCH
MOV
(MOV)
(XCH)
Note 1
Note 6
ADD
XCH
(ADD)
(XCH)
(ADD)Notes 1, 6 (ADD)
Note 1
Note 1
Note 1
Note 1
Note 1
(ADD)
(ADD)
ADDNote 1 ADD
Note 3
ROR
r
MOV
(MOV)
(XCH)
MOV
XCH
MOV
XCH
MOV
XCH
MOV
XCH
MULU
DIVUW
INC
Note 1
ADD
Note 1
Note 1
Note 1
ADD
(ADD)
ADD
ADDNote 1
DEC
Note 6
saddr
sfr
MOV
(MOV)
MOV
MOV
XCH
INC
Note 1
Note 1
ADDNote 1 (ADD)
ADD
DEC
DBNZ
Note 1
ADD
MOV
MOV
MOV
PUSH
POP
Note 1
Note 1
ADDNote 1 (ADD)
ADD
CHKL
CHKLA
!addr16
!!addr24
MOV
(MOV)
MOV
Note 1
ADD
mem
MOV
Note 1
[saddrp]
[%saddrg]
ADD
mem3
ROR4
ROL4
r3
MOV
MOV
MOV
PSWL
PSWH
B, C
DBNZ
STBC, WDM
5
[TDE+]
[TDE–]
(MOV)
MOVBKNote
Note 1
(ADD)
Note 4
MOVM
Notes 1. ADDC, SUB, SUBC, AND, OR, XOR, and CMP are the same as ADD.
2. There is no second operand, or the second operand is not an operand address.
3. ROL, RORC, ROLC, SHR, and SHL are the same as ROR.
4. XCHM, CMPME, CMPMNE, CMPMNC, and CMPMC are the same as MOVM.
5. XCHBK, CMPBKE, CMPBKNE, CMPBKNC, and CMPBKC are the same as MOVBK.
6. When saddr is saddr2 with this combination, an instruction with a short code exists.
58
µPD784035, 784036, 784037, 784038
(2) 16-bit instructions (The instructions enclosed in parentheses are implemented by a combination of
operands, where AX is described as rp.)
MOVW, XCHW, ADDW, SUBW, CMPW, MULUW, MULW, DIVUX, INCW, DECW, SHRW, SHLW, PUSH, POP,
ADDWG, SUBWG, PUSHU, POPU, MOVTBLW, MACW, MACSW, SACW
Table 13-2. Instructions Implemented by 16-Bit Addressing
Note 2
None
2nd operand
#word
AX
rp
saddrp
saddrp'
sfrp
!addr16
mem
[WHL+]
byte
n
rp'
!!addr24 [saddrp]
[%saddrg]
1st operand
Note 3
AX
(MOVW) (MOVW) (MOVW)
(MOVW)
MOVW
(MOVW) MOVW
(MOVW)
(XCHW)
Note 1
ADDW
(XCHW) (XCHW)
(XCHW)Note 3 (XCHW) XCHW
XCHW
Note 1
Notes 1,3
(ADD)
(ADDW)Note 1 (ADDW)
(ADDW)Note 1
Note 4
MULW
rp
MOVW
(MOVW) MOVW
(XCHW) XCHW
MOVW
XCHW
MOVW
XCHW
MOVW
SHRW
SHLW
Note 1
ADDW
INCW
Note 1
Note 1
Note 1
ADDW
(ADDW)Note 1 ADDW
ADDW
DECW
saddrp
sfrp
MOVW
(MOVW)Note 3 MOVW
MOVW
Note 1
XCHW
INCW
Note 1
ADDW
(ADDW)Note 1 ADDW
DECW
Note 1
ADDW
MOVW
MOVW
MOVW
PUSH
POP
Note 1
Note 1
(ADDW)Note 1 ADDW
ADDW
!addr16
!!addr24
MOVW
(MOVW) MOVW
MOVTBLW
mem
MOVW
[saddrp]
[%saddrg]
PSW
PUSH
POP
SP
ADDWG
SUBWG
post
PUSH
POP
PUSHU
POPU
[TDE+]
byte
(MOVW)
SACW
MACW
MACSW
Notes 1. SUBW and CMPW are the same as ADDW.
2. There is no second operand, or the second operand is not an operand address.
3. When saddrp is saddrp2 with this combination, an instruction with a short code exists.
4. MULUW and DIVUX are the same as MULW.
59
µPD784035, 784036, 784037, 784038
(3) 24-bit instructions (The instructions enclosed in parentheses are implemented by a combination of
operands, where WHL is described as rg.)
MOVG, ADDG, SUBG, INCG, DECG, PUSH, POP
Table 13-3. Instructions Implemented by 24-Bit Addressing
2nd operand #imm24
WHL
rg
saddrg
!!addr24
mem1 [%saddrg]
SP
NoneNote
1st operand
WHL
rg'
(MOVG) (MOVG) (MOVG) (MOVG) (MOVG) MOVG
MOVG
MOVG
(ADDG)
(SUBG)
(ADDG)
(SUBG)
(ADDG)
(SUBG)
ADDG
SUBG
rg
MOVG
ADDG
SUBG
(MOVG) MOVG
MOVG
MOVG
INCG
DECG
PUSH
POP
(ADDG)
(SUBG)
ADDG
SUBG
saddrg
!!addr24
mem1
(MOVG) MOVG
(MOVG) MOVG
MOVG
[%saddrg]
SP
MOVG
MOVG
MOVG
INCG
DECG
Note There is no second operand, or the second operand is not an operand address.
60
µPD784035, 784036, 784037, 784038
(4) Bit manipulation instructions
MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR, BFSET
Table 13-4. Bit Manipulation Instructions Implemented by Addressing
2nd operand
CY
saddr.bit sfr.bit
A.bit X.bit
/saddr.bit /sfr.bit
/A.bit /X.bit
NoneNote
PSWL.bit PSWH.bit
mem2.bit
/PSWL.bit /PSWH.bit
/mem2.bit
1st operand
!addr16.bit !!addr24.bit
/!addr16.bit /!!addr24.bit
CY
MOV1
AND1
OR1
AND1
OR1
NOT1
SET1
CLR1
XOR1
saddr.bit
sfr.bit
MOV1
NOT1
SET1
CLR1
BF
A.bit
X.bit
PSWL.bit
PSWH.bit
mem2.bit
!addr16.bit
!!addr24.bit
BT
BTCLR
BFSET
Note There is no second operand, or the second operand is not an operand address.
61
µPD784035, 784036, 784037, 784038
(5) Call/return instructions and branch instructions
CALL, CALLF, CALLT, BRK, RET, RETI, RETB, RETCS, RETCSB, BRKCS, BR, BNZ, BNE, BZ, BE, BNC, BNL,
BC, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, BH, BF, BT, BTCLR, BFSET, DBNZ
Table 13-5. Call/Return and Branch Instructions Implemented by Addressing
Instruction
address
$addr20 $!addr20
!addr16 !!addr20
rp
rg
[rp]
[rg]
!addr11 [addr5]
RBn
None
operand
Basic
BCNote
CALL
BR
CALL
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALL
BR
CALLF
CALLF
BRKCS
BRK
instruction BR
BR
RET
RETCS
RETCSB
RETI
RETB
Composite BF
instruction BT
BTCLR
BFSET
DBNZ
Note BNZ, BNE, BZ, BE, BNC, BNL, BL, BNV, BPO, BV, BPE, BP, BN, BLT, BGE, BLE, BGT, BNH, and BH
are the same as BC.
(6) Other instructions
ADJBA, ADJBS, CVTBW, LOCATION, SEL, NOT, EI, DI, SWRS
62
µPD784035, 784036, 784037, 784038
14. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS (TA = 25 °C)
Parameter
Supply voltage
Symbol
Conditions
Rating
-0.5 to +7.0
AVSS to VDD + 0.5
-0.5 to +0.5
-0.5 to VDD + 0.5
-0.5 to VDD + 0.5
15
Unit
V
VDD
AVDD
AVSS
VI
V
V
Input voltage
V
Output voltage
Output low current
VO
V
IOL
At one pin
mA
mA
mA
mA
V
Total of all output pins
At one pin
100
Output high current
IOH
-10
Total of all output pins
-100
A/D converter reference input
voltage
AVREF1
-0.5 to VDD + 0.3
D/A converter reference input
voltage
AVREF2
AVREF3
TA
-0.5 to VDD + 0.3
-0.5 to VDD + 0.3
-40 to +85
V
V
Operating ambient temperature
Storage temperature
°C
°C
Tstg
-65 to +150
Caution Absolute maximum ratings are rated values beyond which physical damage will be caused to the
product; if the rated value of any of the parameters in the above table is exceeded, even
momentarily, the quality of the product may deteriorate. Always use the product within its rated
values.
63
µPD784035, 784036, 784037, 784038
OPERATING CONDITIONS
• Operating ambient temperature (TA)
: -40 to +85 °C
• Rise time and fall time (tr, tf) (at pins which are not specified) : 0 to 200 µs
• Power supply voltage and clock cycle time : See Figure 14-1.
Figure 14-1. Power Supply Voltage and Clock Cycle Time
10,000
4,000
1,000
Guaranteed
operating
range
125
100
62.5
10
0
1
2
3
4
5
6
7
Power supply voltage [V]
CAPACITANCE (TA = 25 °C, VDD = VSS = 0 V)
Parameter
Input capacitance
Output capacitance
I/O capacitance
Symbol
CI
Conditions
MIN.
TYP.
MAX.
10
Unit
pF
f = 1 MHz
0 V on pins other than measured pins
CO
10
pF
CIO
10
pF
64
µPD784035, 784036, 784037, 784038
OSCILLATOR CHARACTERISTICS (TA = -40 to +85 °C, VDD = +4.5 to 5.5 V, VSS = 0 V)
Resonator
Recommended circuit
Parameter
MIN.
4
MAX.
32
Unit
Ceramic resonator
or crystal
Oscillator frequency (fXX)
MHz
VSS1 X1
X2
C1
C2
External clock
X1 input frequency (fX)
4
0
32
10
MHz
ns
X1 input rise and fall times
(tXR, tXF)
X1
X2
X1 input high-level and low-
level widths (tWXH, tWXL)
10
125
ns
HCMOS
inverter
Caution When using the system clock generator, run wires in the portion surrounded by broken lines
according to the following rules to avoid effects such as stray capacitance:
•
•
•
•
Minimize the wiring.
Never cause the wires to cross other signal lines.
Never cause the wires to run near a line carrying a large varying current.
Cause the grounding point of the capacitor of the oscillator circuit to have the same potential
as VSS1. Never connect the capacitor to a ground pattern carrying a large current.
Never extract a signal from the oscillator.
•
65
µPD784035, 784036, 784037, 784038
OSCILLATOR CHARACTERISTICS (TA = -40 to +85 °C, VDD = +2.7 to 5.5 V, VSS = 0 V)
Resonator
Recommended circuit
Parameter
MIN.
4
MAX.
16
Unit
Ceramic resonator
or crystal
Oscillator frequency (fXX)
MHz
VSS1 X1
X2
C1
C2
External clock
X1 input frequency (fX)
4
0
16
10
MHz
ns
X1 input rise and fall times
(tXR, tXF)
X1
X2
X1 input high-level and low-
level widths (tWXH, tWXL)
10
125
ns
HCMOS
inverter
Caution When using the system clock generator, run wires in the portion surrounded by broken lines
according to the following rules to avoid effects such as stray capacitance:
•
•
•
•
Minimize the wiring.
Never cause the wires to cross other signal lines.
Never cause the wires to run near a line carrying a large varying current.
Cause the grounding point of the capacitor of the oscillator circuit to have the same potential
as VSS1. Never connect the capacitor to a ground pattern carrying a large current.
Never extract a signal from the oscillator.
•
66
µPD784035, 784036, 784037, 784038
DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (1/2)
Parameter
Symbol
VIL1
Conditions
MIN.
-0.3
TYP.
MAX.
Unit
V
Input low voltage
For pins other than those described in
Notes 1, 2, 3, and 4
0.3VDD
VIL2
VIL3
VIH1
For pins described in Notes 1, 2, 3, and
4
-0.3
-0.3
0.2VDD
+0.8
V
V
V
VDD = +5.0 V ± 10 %
For pins described in Notes 2, 3, and 4
Input high voltage
For pins other than those described in
Note 1
0.7VDD
VDD + 0.3
VIH2
VIH3
For pins described in Note 1
0.8VDD
2.2
VDD + 0.3
VDD + 0.3
V
V
VDD = +5.0 V ± 10 %
For pins described in Notes 2, 3, and 4
Output low voltage
Output high voltage
VOL1
VOL2
IOL = 2 mA
0.4
1.0
V
V
VDD = +5.0 V ± 10 %
IOL = 8 mA
For pins described in Notes 2 and 5
VOH1
VOH2
IOH = -2 mA
VDD - 1.0
VDD - 1.4
V
V
VDD = +5.0 V ± 10 %
IOH = -5 mA
For pins described in Note 4
X1 input low current
X1 input high current
IIL
EXTC = 0
-30
µA
µA
0 V ≤ VI ≤ VIL2
IIH
EXTC = 0
+30
VIH2 ≤ VI ≤ VDD
Notes 1. X1, X2, RESET, P12/ASCK2/SCK2, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3,
P25/INTP4/ASCK/SCK1, P26/INTP5, P27/SI0, P32/SCK0/SCL, P33/SO0/SDA, TEST
2. P40/AD0-P47/AD7, P50/A8-P57/A15
3. P60/A16-P63/A19, P64/RD, P65/WR, P66/WAIT/HLDRQ, P67/REFRQ/HLDAK
4. P00-P07
5. P10-P17
67
µPD784035, 784036, 784037, 784038
DC CHARACTERISTICS (TA = -40 to +85 °C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V) (2/2)
Parameter
Symbol
ILI
Conditions
MIN.
TYP.
MAX.
Unit
Input leakage current
0 V ≤ VI ≤ VDD
±10
µA
For pins other than X1 when EXTC = 0
Output leakage current
VDD supply current
ILO
0 V ≤ VO ≤ VDD
±10
µA
IDD1
Operation mode
fXX = 32 MHz
25
12
13
8
45
mA
VDD = +5.0 V ± 10 %
fXX = 16 MHz
25
26
12
12
8
mA
mA
mA
mA
mA
kΩ
VDD = +2.7 to 3.3 V
IDD2
IDD3
RL
HALT mode
fXX = 32 MHz
VDD = +5.0 V ± 10 %
fXX = 16 MHz
VDD = +2.7 to 3.3 V
IDLE mode
(EXTC = 0)
fXX = 32 MHz
VDD = +5.0 V ± 10 %
fXX = 16 MHz
VDD = +2.7 to 3.3 V
Pull-up resistor
VI = 0 V
15
80
68
µPD784035, 784036, 784037, 784038
AC CHARACTERISTICS (TA = -40 to +85 °C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)
(1) Read/write operation (1/2)
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Symbol
tSAST
Conditions
VDD = +5.0 V ± 10 %
MIN.
MAX.
Address setup time
(0.5 + a) T - 15
(0.5 + a) T - 31
(0.5 + a) T - 17
(0.5 + a) T - 40
0.5T - 24
ASTB high-level width
Address hold time (to ASTB↓)
tWSTH
tHSTLA
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
0.5T - 34
Address hold time (to RD↑)
Delay from address to RD↓
tHRA
tDAR
0.5T - 14
VDD = +5.0 V ± 10 %
(1 + a) T - 9
(1 + a) T - 15
Address float time (to RD↓)
tFRA
0
Delay from address to data input tDAID
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
(2.5 + a + n) T - 37
(2.5 + a + n) T - 52
(2 + n) T - 40
Delay from ASTB↓ to data input
Delay from RD↓ to data input
tDSTID
tDRID
(2 + n) T - 60
(1.5 + n) T - 50
(1.5 + n) T - 70
Delay from ASTB↓ to RD↓
Data hold time (to RD↑)
tDSTR
tHRID
tDRA
0.5T - 9
0
After program
Delay from RD↑ to address active
VDD = +5.0 V ± 10 %
0.5T - 8
is read
0.5T - 12
After data is
read
VDD = +5.0 V ± 10 %
1.5T - 8
1.5T - 12
Delay from RD↑ to ASTB↑
tDRST
tWRL
0.5T - 17
RD low-level width
VDD = +5.0 V ± 10 %
(1.5 + n) T - 30
(1.5 + n) T - 40
0.5T - 14
Address hold time (to WR↑)
Delay from address to WR↓
tHWA
tDAW
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
(1 + a) T - 5
(1 + a) T - 15
Delay from ASTB↓ to data output
tDSTOD
0.5T + 19
0.5T + 35
0.5T - 11
Delay from WR↓ to data output
Delay from ASTB↓ to WR↓
tDWOD
tDSTW
0.5T - 9
Remarks T: TCYK (system clock cycle time)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)
69
µPD784035, 784036, 784037, 784038
(1) Read/write operation (2/2)
Unit
Parameter
Symbol
Conditions
VDD = +5.0 V ± 10 %
MIN.
MAX.
ns
ns
ns
ns
ns
ns
ns
Data setup time (to WR↑)
tSODW
(1.5 + n) T - 30
(1.5 + n) T - 40
0.5T - 5
Note
Data hold time (to WR↑)
tHWOD
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
0.5T - 25
Delay from WR↑ to ASTB↑
tDWST
tWWL
0.5T - 12
WR low-level width
(1.5 + n) T - 30
(1.5 + n) T - 40
Note The hold time includes the time during which VOH1 and VOL1 are held under the load conditions of
CL = 50 pF and RL = 4.7 kΩ.
Remarks T: TCYK (system clock cycle time)
n: Number of wait states (n ≥ 0)
(2) Bus hold timing
Unit
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Symbol
tFHQC
Conditions
MIN.
MAX.
(6 + a + n) T + 50
(7 + a + n) T + 30
(7 + a + n) T + 40
1T + 30
Delay from HLDRQ↑ to float
Delay from HLDRQ↑ to HLDAK↑
tDHQHHAH VDD = +5.0 V ± 10 %
Delay from float to HLDAK↑
tDCFHA
Delay from HLDRQ↓ to HLDAK↓ tDHQLHAL VDD = +5.0 V ± 10 %
2T + 40
2T + 60
Delay from HLDAK↓ to active
tDHAC
VDD = +5.0 V ± 10 %
1T - 20
1T - 30
Remarks T: TCYK (system clock cycle time)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)
70
µPD784035, 784036, 784037, 784038
(3) External wait timing
Symbol
tDAWT
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Conditions
VDD = +5.0 V ± 10 %
MIN.
MAX.
Delay from address to WAIT↓ input
(2 + a) T - 40
(2 + a) T - 60
1.5T - 40
tDSTWT
tHSTWTH
tDSTWTH
tDRWTL
tHRWT
Delay from ASTB↓ to WAIT↓ input
Hold time from ASTB↓ to WAIT
Delay from ASTB↓ to WAIT↑
Delay from RD↓ to WAIT↓ input
Hold time from RD↓ to WAIT↓
Delay from RD↓ to WAIT↑
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
1.5T - 60
(0.5 + n) T + 5
(0.5 + n) T +10
(1.5 + n) T - 40
(1.5 + n) T - 60
T - 50
T - 70
nT + 5
nT + 10
tDRWTH
tDWTID
(1 + n) T - 40
(1 + n) T - 60
0.5T - 5
Delay from WAIT↑ to data input
0.5T - 10
tDWTW
tDWTR
tDWWTL
Delay from WAIT↑ to WR↑
Delay from WAIT↑ to RD↑
Delay from WR↓ to WAIT↓ input
0.5T
0.5T
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
T - 50
T - 75
tHWWT
Hold time from WR↓ to WAIT
Delay from WR↓ to WAIT↑
nT + 5
nT + 10
tDWWTH
(1 + n) T - 40
(1 + n) T - 70
Remarks T: TCYK (system clock cycle time)
a: 1 (during address wait), otherwise, 0
n: Number of wait states (n ≥ 0)
(4) Refresh timing
Symbol
tRC
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Conditions
MIN.
MAX.
Random read/write cycle time
REFRQ low-level pulse width
3T
tWRFQL
VDD = +5.0 V ± 10 %
1.5T - 25
1.5T - 30
0.5T - 9
1.5T - 9
1.5T - 9
0.5T - 15
1.5T - 25
1.5T - 30
tDSTRFQ
tDRRFQ
tDWRFQ
tDRFQST
tWRFQH
Delay from ASTB↓ to REFRQ
Delay from RD↑ to REFRQ
Delay from WR↑ to REFRQ
Delay from REFRQ↑ to ASTB
REFRQ high-level pulse width
VDD = +5.0 V ± 10 %
Remark T: TCYK (system clock cycle time)
71
µPD784035, 784036, 784037, 784038
SERIAL OPERATION (TA = -40 to +85 °C, VDD = +2.7 to 5.5 V, AVSS = VSS = 0 V)
(1) CSI
Unit
ns
Parameter
Symbol
Conditions
MIN.
MAX.
Serial clock cycle time (SCK0)
tCYSK0
Input External clock
10/fXX + 380
When SCK0 and SO0 are CMOS I/O
µs
Output
T
ns
Serial clock low-level width
(SCK0)
tWSKL0
tWSKH0
Input External clock
5/fXX + 150
When SCK0 and SO0 are CMOS I/O
µs
Output
0.5T - 40
ns
Serial clock high-level width
(SCK0)
Input External clock
5/fXX + 150
When SCK0 and SO0 are CMOS I/O
µs
ns
ns
ns
Output
0.5T - 40
SI0 setup time (to SCK0↑)
SI0 hold time (to SCK0↑)
tSSSK0
tHSSK0
tDSBSK1
40
5/fXX + 40
0
SO0 output delay time
CMOS push-pull output
(3-wire serial I/O mode)
5/fXX + 150
5/fXX + 400
(to SCK0↓)
ns
tDSBSK2
Open-drain output
0
(2-wire serial I/O mode), RL = 1 kΩ
Remarks 1. The values in this table are those when CL is 100 pF.
2. T : Serial clock cycle set by software. The minimum value is 16/fXX.
3. fXX : Oscillator frequency
72
µPD784035, 784036, 784037, 784038
(2) IOE1, IOE2
Unit
Parameter
Symbol
tCYSK1
Conditions
MIN.
250
MAX.
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial clock cycle time
(SCK1, SCK2)
Input
VDD = +5.0 V ± 10 %
500
Output
Input
Internal, divided by 16
T
Serial clock low-level width
(SCK1, SCK2)
tWSKL1
tWSKH1
VDD = +5.0 V ± 10 %
85
210
Output
Input
Internal, divided by 16
0.5T - 40
85
Serial clock high-level width
(SCK1, SCK2)
VDD = +5.0 V ± 10 %
210
Output
Internal, divided by 16
0.5T - 40
40
Setup time for SI1 and SI2
tSSSK1
tHSSK1
(to SCK1, SCK2↑)
ns
ns
ns
Hold time for SI1 and SI2
40
(to SCK1, SCK2↑)
Output delay time for SO1 and tDSOSK
0
50
SO2 (to SCK1, SCK2↓)
Output hold time for SO1 and
tHSOSK
When data is transferred
0.5tCYSK1 - 40
SO2 (to SCK1, SCK2↑)
Remarks 1. The values in this table are those when CL is 100 pF.
2. T: Serial clock cycle set by software. The minimum value is 16/fXX.
(3) UART, UART2
Unit
ns
Parameter
Symbol
tCYASK
Conditions
VDD = +5.0 V ± 10 %
MIN.
125
250
52.5
85
MAX.
ASCK clock input cycle time
ns
ns
ASCK clock low-level width
ASCK clock high-level width
tWASKL
tWASKH
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
ns
ns
52.5
85
ns
73
µPD784035, 784036, 784037, 784038
CLOCK OUTPUT OPERATION
Symbol
Unit
Parameter
CLKOUT cycle time
CLKOUT low-level width
Conditions
MIN.
MAX.
tCYCL
tCLL
ns
ns
ns
ns
ns
ns
ns
ns
ns
nT
VDD = +5.0 V ± 10 %
0.5tCYCL - 10
0.5tCYCL - 20
0.5tCYCL - 10
0.5tCYCL - 20
tCLH
tCLR
tCLF
CLKOUT high-level width
CLKOUT rise time
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
VDD = +5.0 V ± 10 %
10
20
10
20
CLKOUT fall time
Remarks n: Divided frequency ratio set by software in the CPU (n = 1, 2, 4, 8, 16)
T: TCYK (system clock cycle time)
OTHER OPERATIONS
Unit
µs
Parameter
NMI low-level width
NMI high-level width
INTP0 low-level width
INTP0 high-level width
Symbol
tWNIL
Conditions
MIN.
10
MAX.
µs
tWNIH
10
ns
tWIT0L
tWIT0H
tWIT1L
4tCYSMP
4tCYSMP
4tCYCPU
ns
ns
Low-level width for INTP1-
INTP3 and CI
ns
µs
µs
High-level width for INTP1-
INTP3 and CI
tWIT1H
4tCYCPU
10
Low-level width for INTP4 and tWIT2L
INTP5
High-level width for INTP4 and tWIT2H
INTP5
10
µs
µs
RESET low-level width
RESET high-level width
tWRSL
tWRSH
10
10
Remarks tCYSMP: Sampling clock set by software
tCYCPU: CPU operation clock set by software in the CPU
74
µPD784035, 784036, 784037, 784038
A/D CONVERTER CHARACTERISTICS (TA = -40 to +85 °C, VDD = AVDD = AVREF1 = +2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
8
TYP.
MAX.
Unit
bit
Note
Total error
1.0
0.8
%
Note
Linearity calibration
Quantization error
Conversion time
%
±1/2
LSB
tCYK
tCYK
tCYK
tCYK
V
tCONV
FR = 1
FR = 0
FR = 1
FR = 0
120
180
24
Sampling time
tSAMP
36
Analog input voltage
Analog input impedance
AVREF1 current
VIAN
-0.3
AVREF1 + 0.3
RAN
1,000
0.5
MΩ
mA
mA
µA
AIREF1
AIDD1
AIDD2
1.5
5.0
20
AVDD supply current
fXX = 32 MHz, CS = 1
STOP mode, CS = 0
2.0
1.0
Note Quantization error is not included. This parameter is indicated as the ratio to the full-scale value.
Remark tCYK: System clock cycle time
75
µPD784035, 784036, 784037, 784038
D/A CONVERTER CHARACTERISTICS (TA = -40 to +85 °C, VDD = AVDD = +2.7 to 5.5 V, VSS = AVSS = 0 V)
Parameter
Resolution
Symbol
Conditions
MIN.
8
TYP.
MAX.
0.6
Unit
bit
Total error
Load conditions: VDD = AVDD = AVREF2
%
4 MΩ, 30 pF
= +2.7 to 5.5 V
AVREF3 = 0 V
V
DD = AVDD = +2.7 to 5.5 V
0.8
0.8
1.0
10
%
%
%
AVREF2 = 0.75VDD
AVREF3 = 0.25VDD
Load conditions: VDD = AVDD = AVREF2
2 MΩ, 30 pF
= +2.7 to 5.5 V
AVREF3 = 0 V
VDD = AVDD = +2.7 to 5.5 V
AVREF2 = 0.75VDD
AVREF3 = 0.25VDD
Settling time
Load conditions: 2 MΩ, 30 pF
µs
kΩ
V
Output resistance
Analog reference voltage
RO
DACS0, 1 = 55 H
10
8
AVREF2
AVREF3
RAIREF
0.75VDD
VDD
0
4
0.25VDD
V
Resistance of AVREF2 and
DACS0, 1 = 55 H
kΩ
AVREF3
Reference power supply
input current
AIREF2
AIREF3
0
5
0
mA
mA
-5
76
µPD784035, 784036, 784037, 784038
DATA RETENTION CHARACTERISTICS (TA = -40 to +85 °C)
Parameter
Symbol
VDDDR
IDDDR
Conditions
MIN.
2.5
TYP.
MAX.
5.5
50
Unit
V
Data retention voltage
Data retention current
STOP mode
VDDDR = +2.7 to 5.5 V
VDDDR = +2.5 V
10
2
µA
µA
µs
10
VDD rise time
VDD fall time
tRVD
tFVD
tHVD
200
200
0
µs
VDD hold time
ms
(to STOP mode setting)
STOP clear signal input time tDREL
0
ms
ms
ms
V
Oscillation settling time
tWAIT
Crystal
30
Ceramic resonator
5
0
Note
Input low voltage
Input high voltage
VIL
VIH
Specific pins
0.1VDDDR
0.9VDDDR
VDDDR
V
Note RESET, P20/NMI, P21/INTP0, P22/INTP1, P23/INTP2/CI, P24/INTP3, P25/INTP4/ASCK/SCK1,
P26/INTP5, P27/SI0, P32/SCK0/SCL, and P33/SO0/SDA pins
AC TIMING TEST POINTS
V
DD-1 V
0.8VDD or 2.2 V
0.8 V
0.8VDD or 2.2 V
0.8 V
Test points
0.45 V
77
µPD784035, 784036, 784037, 784038
TIMING WAVEFORM
(1) Read operation
t
WSTH
ASTB
t
SAST
t
DRST
t
DSTID
t
HSTLA
A8-A19
t
DAID
t
HRA
AD0-AD7
t
DSTR
t
FRA
t
HRID
t
DAR
t
DRID
t
DRA
RD
t
WRL
(2) Write operation
tWSTH
ASTB
tSAST
tDWST
tDSTOD
tHSTLA
A8-A19
tHWA
AD0-AD7
tDSTW
tHWOD
tDAW
tDWOD
tSODW
WR
tWWL
78
µPD784035, 784036, 784037, 784038
HOLD TIMING
ADTB, A8-A19,
AD0-AD7, RD, WR
t
FHQC
t
DCFHA
t
DHAC
HLDRQ
HLDAK
t
DHQLHAL
t
DHQHHAH
EXTERNAL WAIT SIGNAL INPUT TIMING
(1) Read operation
ASTB
t
DSTWTH
t
HSTWTH
t
DSTWT
A8-A19
AD0-AD7
RD
t
DAWT
t
DWTID
t
DRWTL
t
DWTR
WAIT
t
HRWT
DRWTH
t
(2) Write operation
ASTB
t
DSTWTH
t
HSTWTH
t
DSTWT
A8-A19
AD0-AD7
WR
t
DAWT
t
DWWTL
t
DWTW
WAIT
t
HWWT
DWWTH
t
79
µPD784035, 784036, 784037, 784038
REFRESH TIMING WAVEFORM
(1) Random read/write cycle
t
RC
ASTB
WR
t
RC
t
RC
t
RC
t
RC
RD
(2) When refresh memory is accessed for a read and write at the same time
ASTB
RD, WR
t
DSTRFQ
t
DRFQST
t
WRFQH
REFRQ
t
WRFQL
(3) Refresh after a read
ASTB
t
DRFQST
RD
t
DRRFQ
REFRQ
t
WRFQL
(4) Refresh after a write
ASTB
t
DRFQST
WR
t
DWRFQ
REFRQ
t
WRFQL
80
µPD784035, 784036, 784037, 784038
SERIAL OPERATION
(1) CSI
t
WSKL0
t
WSKH0
SCK
tSSSK0
t
HSSK0
t
CYSK0
SI
Input data
t
DSBSK1
SO
Output data
(2) IOE1, IOE2
t
WSKL1
t
WSKH1
SCK
tSSSK1
t
HSSK1
t
CYSK1
SI
Input data
t
HSOSK
t
DSOSK
SO
Output data
(3) UART, UART2
tWASKH
tWASKL
ASCK,
ASCK2
tCYASK
81
µPD784035, 784036, 784037, 784038
CLOCK OUTPUT TIMING
t
CLH
t
CLL
CLKOUT
t
CLR
t
CLF
t
CYCL
INTERRUPT INPUT TIMING
tWNIH
tWIT0H
tWIT1H
tWIT2H
tWNIL
NMI
tWIT0L
tWIT1L
tWIT2L
INTP0
CI,
INTP1-INTP3
INTP4, INTP5
RESET INPUT TIMING
t
WRSH
t
WRSL
RESET
82
µPD784035, 784036, 784037, 784038
EXTERNAL CLOCK TIMING
t
WXH
t
WXH
X1
t
XR
t
XF
t
CYX
DATA RETENTION CHARACTERISTICS
STOP mode setting
V
DD
V
DDDR
t
DREL
t
WAIT
t
HVD
t
FVD
t
RVD
RESET
NMI
(Clearing by falling edge)
NMI
(Clearing by rising edge)
83
µPD784035, 784036, 784037, 784038
15. PACKAGE DRAWINGS
80 PIN PLASTIC QFP (14x14)
A
B
60
61
41
40
detail of lead end
S
C D
R
Q
21
20
80
1
F
P
J
G
M
H
I
K
M
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
A
B
17.2±0.4
14.0±0.2
0.677±0.016
+0.009
0.551
–0.008
+0.009
0.551
C
14.0±0.2
–0.008
D
F
17.2±0.4
0.825
0.677±0.016
0.032
G
0.825
0.032
+0.004
0.012
H
0.30±0.10
–0.005
I
0.13
0.005
J
K
0.65 (T.P.)
1.6±0.2
0.026 (T.P.)
0.063±0.008
+0.009
0.031
L
0.8±0.2
–0.008
+0.004
0.006
+0.10
0.15
M
–0.003
–0.05
N
P
0.10
0.004
+0.005
0.106
2.7±0.1
–0.004
Q
R
S
0.1±0.1
5°±5°
0.004±0.004
5°±5°
3.0 MAX.
0.119 MAX.
S80GC-65-3B9-5
Remark The shape and material of the ES version are the same as those of the corresponding mass-produced
product.
84
µPD784035, 784036, 784037, 784038
80 PIN PLASTIC QFP (14×14)
A
B
60
61
41
40
detail of lead end
S
C
D
R
Q
80
1
21
20
F
J
M
G
P
H
I
K
L
M
N
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.13 mm (0.005 inch) of
its true position (T.P.) at maximum material condition.
A
B
17.20±0.20
14.00±0.20
0.677±0.008
+0.009
0.551
–0.008
+0.009
0.551
C
D
14.00±0.20
17.20±0.20
–0.008
0.677±0.008
F
0.825
0.825
0.032
0.032
G
+0.002
0.013
H
0.32±0.06
–0.003
I
0.13
0.005
J
K
0.65 (T.P.)
1.60±0.20
0.026 (T.P.)
0.063±0.008
+0.009
0.031
L
0.80±0.20
–0.008
+0.03
0.17
+0.001
0.007
M
–0.07
–0.003
N
P
Q
0.10
0.004
1.40±0.10
0.125±0.075
0.055±0.004
0.005±0.003
+7°
3°
+7°
3°
R
S
–3°
–3°
1.70 MAX.
0.067 MAX.
P80GC-65-8BT
Remark The shape and material of the ES version are the same as those of the corresponding mass-produced
product.
85
µPD784035, 784036, 784037, 784038
80 PIN PLASTIC TQFP (FINE PITCH) ( 12)
A
B
60
61
41
40
detail of lead end
80
21
20
1
G
M
I
J
H
K
N
L
NOTE
ITEM MILLIMETERS
INCHES
Each lead centerline is located within 0.10 mm (0.004 inch) of
its true position (T.P.) at maximum material condition.
+0.009
A
B
C
D
14.0±0.2
12.0±0.2
12.0±0.2
14.0±0.2
0.551
0.472
0.472
0.551
–0.008
+0.009
–0.008
+0.009
–0.008
+0.009
–0.008
F
1.25
1.25
0.049
0.049
G
+0.05
0.22
H
0.009±0.002
–0.04
I
0.10
0.004
J
0.5 (T.P.)
0.020 (T.P.)
+0.009
0.039
K
L
1.0±0.2
0.5±0.2
–0.008
+0.008
0.020
–0.009
+0.055
M
0.145
0.006±0.002
–0.045
N
P
Q
R
S
0.10
1.05
0.004
0.041
0.05±0.05
5°±5°
0.002±0.002
5°±5°
1.27 MAX.
0.050 MAX.
P80GK-50-BE9-4
Remark The shape and material of the ES version are the same as those of the corresponding mass-produced
product.
86
µPD784035, 784036, 784037, 784038
16. RECOMMENDED SOLDERING CONDITIONS
The conditions listed below shall be met when soldering the µPD784035, µPD784036, µPD784037, or
µPD784038.
For details of the recommended soldering conditions, refer to our document Semiconductor Device Mounting
Technology Manual (C10535E).
Please consult with our sales offices in case any other soldering process is used, or in case soldering is done under
different conditions.
Table 16-1. Soldering Conditions for Surface-Mount Devices (1/2)
(1) µPD784035GC-×××-3B9: 80-pin plastic QFP (14 × 14 × 2.7 mm)
µPD784036GC-×××-3B9: 80-pin plastic QFP (14 × 14 × 2.7 mm)
µPD784037GC-×××-3B9: 80-pin plastic QFP (14 × 14 × 2.7 mm)
µPD784038GC-×××-3B9: 80-pin plastic QFP (14 × 14 × 2.7 mm)
Soldering process
Infrared ray reflow
Soldering conditions
Symbol
IR35-00-3
Peak package's surface temperature: 235 °C
Reflow time: 30 seconds or less (210 °C or more)
Maximum allowable number of reflow processes: 3
VPS
Peak package's surface temperature: 215 °C
Reflow time: 40 seconds or less (200 °C or more)
Maximum allowable number of reflow processes: 3
VP15-00-3
WS60-00-1
Wave soldering
Solder temperature: 260 °C or less
Flow time: 10 seconds or less
Number of flow processes: 1
Preheating temperature
: 120 °C max. (measured on the package surface)
Partial heating method
Terminal temperature: 300 °C or less
-
Heat time: 3 seconds or less (for one side of a device)
Caution Do not apply two or more different soldering methods to one chip (except for partial heating
method for terminal sections).
(2) µPD784035GC-×××-8BT: 80-pin plastic QFP (14 × 14 × 1.4 mm)
µPD784036GC-×××-8BT: 80-pin plastic QFP (14 × 14 × 1.4 mm)
µPD784037GC-×××-8BT: 80-pin plastic QFP (14 × 14 × 1.4 mm)
µPD784038GC-×××-8BT: 80-pin plastic QFP (14 × 14 × 1.4 mm)
Soldering process
Infrared ray reflow
Soldering conditions
Symbol
IR35-00-2
Peak package's surface temperature: 235 °C
Reflow time: 30 seconds or less (210 °C or more)
Maximum allowable number of reflow processes: 2
VPS
Peak package's surface temperature: 215 °C
Reflow time: 40 seconds or less (200 °C or more)
Maximum allowable number of reflow processes: 2
VP15-00-2
WS60-00-1
Wave soldering
Solder temperature: 260 °C or less
Flow time: 10 seconds or less
Number of flow processes: 1
Preheating temperature
: 120 °C max. (measured on the package surface)
Partial heating method
Terminal temperature: 300 °C or less
-
Heat time: 3 seconds or less (for one side of a device)
Caution Do not apply two or more different soldering methods to one chip (except for partial heating
method for terminal sections).
87
µPD784035, 784036, 784037, 784038
Table 16-1. Soldering Conditions for Surface-Mount Devices (2/2)
(3) µPD784035GK-×××-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
µPD784036GK-×××-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
µPD784037GK-×××-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
µPD784038GK-×××-BE9: 80-pin plastic TQFP (fine pitch) (12 × 12 mm)
Soldering process
Infrared ray reflow
Symbol
IR35-107-2
Soldering conditions
Peak package’s surface temperature: 235 °C
Reflow time: 30 seconds or less (210 °C or more)
Maximum allowable number of reflow processes: 2
Note
Exposure limit: 7 days
(10 hours of pre-baking is required at 125 °C
afterward)
<Caution>
Non-heat-resistant trays, such as magazine and taping trays, cannot be
baked before unpacking.
VPS
VP15-107-2
Peak package’s surface temperature: 215 °C
Reflow time: 40 seconds or less (200 °C or more)
Maximum allowable number of reflow processes: 2
Note
Exposure limit: 7 days
afterward)
(10 hours of pre-baking is required at 125 °C
<Caution>
Non-heat-resistant trays, such as magazine and taping trays, cannot be
baked before unpacking.
Partial heating method
-
Terminal temperature: 300 °C or less
Heat time: 3 seconds or less (for one side of a device)
Note Maximum number of days during which the product can be stored at a temperature of 25 °C and a relative
humidity of 65 % or less after dry-pack package is opened.
Caution Do not apply two or more different soldering methods to one chip (except for partial heating
method for terminal sections).
88
µPD784035, 784036, 784037, 784038
APPENDIX A DEVELOPMENT TOOLS
The following development tools are available for system development using the µPD784038.
See also (5).
(1) Language processing software
RA78K4
CC78K4
Assembler package for all 78K/IV series models
C compiler package for all 78K/IV series models
DF784038
CC78K4-L
Device file for µPD784038 sub-series models
C compiler library source file for all 78K/IV series models
(2) PROM write tools
PG-1500
PROM programmer
PA-78P4026GC
PA-78P4038GK
PA-78P4026KK
Programmer adaptor, connects to PG-1500
PG-1500 controller
Control program for PG-1500
(3) Debugging tools
• When using the in-circuit emulator IE-78K4-NS
IE-78K4-NS
In-circuit emulator for all 78K/IV series models
IE-70000-MC-PS-B
IE-70000-98-IF-C
Power supply unit for IE-78K4-NS
Interface adapter when the PC-9800 series computer (other than a notebook)
is used as the host machine
IE-70000-CD-IF
PC card and interface cable when a PC-9800 series notebook is used as the
host machine
TM
IE-70000-PC-IF-C
Interface adapter when the IBM PC/AT
machine
or compatible is used as the host
Note
IE-784038-NS-EM1
NP-80GC
Emulation board for evaluating µPD784038 sub-series models
Emulation probe for 80-pin plastic QFP (GC-3B9 type)
Emulation probe for 80-pin plastic TQFP (GK-BE9 type)
Note
NP-80GK
EV-9200GC-80
TGK-080SDW
Socket for mounting on target system board made for 80-pin plastic QFP
(GC-3B9 type)
Adapter for mounting on target system board made for 80-pin plastic TQFP
(fine pitch) (GK-BE9 type)
EV-9900
Tool used to remove the µPD78P4038KK-T from the EV-9200GC-80
Integrated debugger for IE-78K4-NS
Note
ID78K4-NS
SM78K4-NS
DF784038
System simulator for all 78K/IV series models
Device file for µPD784038 sub-series models
Note Under development
89
µPD784035, 784036, 784037, 784038
• When using the in-circuit emulator IE-784000-R
IE-784000-R
IE-70000-98-IF-B
In-circuit emulator for all 78K/IV series models
Interface adapter when the PC-9800 series computer (other than a notebook)
is used as the host machine
Note
IE-70000-98-IF-C
IE-70000-98N-IF
Interface adapter and cable when a PC-9800 series notebook is used as the
host machine
IE-70000-PC-IF-B
IE-70000-PC-IF-C
Interface adapter when the IBM PC/AT or compatible is used as the host
machine
Note
IE-78000-R-SV3
Interface adapter and cable when the EWS is used as the host machine
Note
IE-784038-NS-EM1
IE-784038-R-EM1
Emulation board for evaluating µPD784038 sub-series models
IE-78400-R-EM
Emulation board for all 78K/IV series models
Note
IE-78K4-R-EX2
Conversion board for 80 pins to use the IE-784038-NS-EM1 on the
IE-784000-R. The board is not needed when the conventional product
IE-784038-R-EM1 is used.
EP-78230GC-R
EP-78054GK-R
Emulation probe for 80-pin plastic QFP (GC-3B9 type)
Emulation probe for 80-pin plastic TQFP (fine pitch) (GK-BE9 type) for all
µPD784038 sub-series
EV-9200GC-80
TGK-080SDW
Socket for mounting on target system board made for 80-pin plastic QFP
(GC-3B9 type)
Adapter for mounting on target system board made for 80-pin plastic TQFP
(fine pitch) (GK-BE9 type)
EV-9900
ID78K4
Tool used to remove the µPD78P4038KK-T from the EV-9200GC-80
Integrated debugger for IE-784000-R
SM78K4
System simulator for all 78K/IV series models
DF784038
Device file for µPD784038 sub-series models
Note Under development
(4) Real-time OS
RX78K/IV
MX78K4
Real-time OS for 78K/IV series models
OS for 78K/IV series models
90
µPD784035, 784036, 784037, 784038
(5) Notes when using development tools
• The ID78K-NS, ID78K4, and SM78K4 can be used in combination with the DF784038.
• The CC78K and RX78K/IV can be used in combination with the RA78K4 and DF784038.
• The NP-80GC is a product from Naito Densei Machida Mfg. Co., Ltd. (044-822-3813). Consult the NEC sales
representative for purchasing.
• The TGK-080SDW is a product from TOKYO ELETECH CORPORATION.
Refer to: Daimaru Kogyo, Ltd.
Tokyo Electronic Components Division (03-3820-7112)
Osaka Electronic Components Division (06-244-6672)
• The host machines and operating systems corresponding to each software are shown below.
Host machine
[OS]
PC
EWS
TM
TM
TM
PC-9800 Series [Windows
]
HP9000 Series 700
[HP-UX
]
TM
TM
IBM PC/AT and compatibles [Windows] SPARCstation
[SunOS
]
TM
TM
NEWS
(RISC) [NEWS-OS
]
Software
Note
Note
Note
RA78K4
CC78K4
PG-1500 controller
ID78K4-NS
ID78K4
-
-
SM78K4
-
Note
Note
RX78K/IV
MX78K4
Note Software under MS-DOS
91
µPD784035, 784036, 784037, 784038
APPENDIX B RELATED DOCUMENTS
Documents Related to Devices
Document No.
Document name
Japanese
U11507J
U10847J
U10848J
U11316J
English
U11507E
This manual
U10848E
U11316E
µPD784031 Data Sheet
µPD7840335, 784036, 784037, 784038
µPD78P4038 Data Sheet
µPD784038, 784038Y Sub-Series User's Manual, Hardware
µPD784038 Sub-Series Special Function Registers
78K/IV Series User's Manual, Instruction
78K/IV Series Instruction Summary Sheet
78K/IV Series Instruction Set
U11090J
U10905J
U10594J
U10595J
U10095J
-
U10905E
-
-
-
78K/IV Series Application Note, Software Basic
Documents Related to Development Tools (User’s Manual)
Document No.
Document name
Japanese
U11334J
English
U11334E
U11162E
U11743E
U11572E
U11571E
U12322E
U11940E
EEU-1291
U10540E
To be created
EEU-1534
To be created
U11383E
EEU-1515
EEU-1468
U10093E
U10092E
RA78K4 Assembler Package
Operation
Language
U11162J
RA78K Series Structured Assembler Preprocessor
CC78K4 C Compiler
U11743J
Operation
Language
U11572J
U11571J
CC78K Series Library Source File
PG-1500 PROM Programmer
U12322J
U11940J
TM
PG-1500 Controller PC-9800 Series (MS-DOS ) Base
EEU-704
EEU-5008
Under creation
U12903J
TM
PG-1500 Controller IBM PC Series (PC DOS ) Base
IE-78K4-NS
IE-784000-R
IE-784038-NS-EM1
IE-784038-R-EM1
To be created
U11383J
EP-78230
EEU-985
EEU-932
U10093J
EP-78054GK-R
SM78K4 System Simulator Windows Base
SM78K Series System Simulator
Reference
External Parts User Open
Interface Specifications
U10092J
ID78K4 Integrated Debugger
Reference
Reference
U12796J
U10440J
U12796E
U10440E
ID78K4 Integrated Debugger Windows Base
ID78K4 Integrated Debugger HP-UX, SunOS, NEW-OS Base Reference
U11960J
U11960E
Caution The above documents may be revised without notice. Use the latest versions when you design
application systems.
92
µPD784035, 784036, 784037, 784038
Documents Related to Software to Be Incorporated into the Product (User’s Manual)
Document No.
Document name
Japanese
English
78K/IV Series Real-Time OS
Basic
U10603J
U10604J
U10364J
U11779J
U10603E
Installation
Debugger
Basic
U10604E
-
-
OS for 78K/IV Series MX78K4
Other Documents
Document No.
Document name
Japanese
C10943X
C10535J
C11531J
C10983J
U11892J
C12769J
C11416J
English
IC PACKAGE MANUAL
Semiconductor Device Mounting Technology Manual
Quality Grades on NEC Semiconductor Device
C10535E
C11531E
C10983E
E11892E
-
NEC Semiconductor Device Reliability/Quality Control System
Guide to Prevent Damage for Semiconductor Devices by Electrostatic Discharge (ESD)
Semiconductor Device Quality Control/Reliability Handbook
Guide for Products Related to Microcomputer: Other Companies
-
Caution The above documents may be revised without notice. Use the latest versions when you design
application systems.
93
µPD784035, 784036, 784037, 784038
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of
the gate oxide and ultimately degrade the device operation. Steps must be taken
to stop generation of static electricity as much as possible, and quickly dissipate
it once, when it has occurred. Environmental control must be adequate. When
it is dry, humidifier should be used. It is recommended to avoid using insulators
that easily build static electricity. Semiconductor devices must be stored and
transported in an anti-static container, static shielding bag or conductive
material. All test and measurement tools including work bench and floor should
be grounded. The operator should be grounded using wrist strap. Semiconduc-
tor devices must not be touched with bare hands. Similar precautions need to
be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no
connection is provided to the input pins, it is possible that an internal input level
may be generated due to noise, etc., hence causing malfunction. CMOS device
behave differently than Bipolar or NMOS devices. Input levels of CMOS devices
must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have
a possibility of being an output pin. All handling related to the unused pins must
be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production
process of MOS does not define the initial operation status of the device.
Immediately after the power source is turned ON, the devices with reset function
have not yet been initialized. Hence, power-on does not guarantee out-pin
levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after
power-on for devices having reset function.
94
µPD784035, 784036, 784037, 784038
IEBus is a trademark of NEC Corporation.
MS-DOS and Windows are either registered trademarks or trademarks of Microsoft Corporation in the United
States and/or other countries.
PC/AT and PC DOS are trademarks of IBM Corporation.
HP9000 series 700 and HP-UX are trademarks of Hewlett-Packard Company.
SPARCstation is a trademark of SPARC International, Inc.
SunOS is a trademark of Sun Microsystems, Inc.
NEWS and NEWS-OS are trademarks of SONY Corporation.
95
µPD784035, 784036, 784037, 784038
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, please contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
• Device availability
• Ordering information
• Product release schedule
• Availability of related technical literature
• Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
• Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics Hong Kong Ltd.
Hong Kong
Tel: 2886-9318
NEC Electronics (Germany) GmbH
Benelux Office
Eindhoven, The Netherlands
Tel: 040-2445845
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore 1130
Tel: 253-8311
NEC Electronics (France) S.A.
Spain Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 250-3583
Tel: 01-504-2787
Fax: 01908-670-290
Fax: 01-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-719-2377
NEC Electronics Italiana s.r.1.
Milano, Italy
NEC Electronics (Germany) GmbH
Scandinavia Office
Tel: 02-66 75 41
Fax: 02-719-5951
Taeby, Sweden
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Cumbica-Guarulhos-SP, Brasil
Tel: 011-6465-6810
Fax: 08-63 80 388
Fax: 011-6465-6829
J97. 8
96
µPD784035, 784036, 784037, 784038
[MEMO]
97
µPD784035, 784036, 784037, 784038
Some related documents may be preliminary versions. Note, however, that whether a related document is preliminary is not
indicated in this document.
The export of this product from Japan is regulated by the Japanese government. To export this product may be prohibited
without governmental license, the need for which must be judged by the customer. The export or re-export of this product
from a country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
No part of this document may be copied or reproduced in any form or by any means without the prior written
consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this
document.
NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual
property rights of third parties by or arising from use of a device described herein or any other liability arising
from use of such device. No license, either express, implied or otherwise, is granted under any patents,
copyrights or other intellectual property rights of NEC Corporation or others.
While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,
the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or
property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety
measures in its design, such as redundancy, fire-containment, and anti-failure features.
NEC devices are classified into the following three quality grades:
"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on
a customer designated "quality assurance program" for a specific application. The recommended applications
of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each
device before using it in a particular application.
Standard: Computers, office equipment, communications equipment, test and measurement equipment,
audio and visual equipment, home electronic appliances, machine tools, personal electronic
equipment and industrial robots
Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems or medical equipment for life support, etc.
The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.
If customers intend to use NEC devices for applications other than those specified for Standard quality grade,
they should contact an NEC sales representative in advance.
Anti-radioactive design is not implemented in this product.
M4 96. 5
相关型号:
UPD784037GC-XXX-8BT-A
Microcontroller, 16-Bit, MROM, 32MHz, CMOS, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-80
NEC
UPD784037YGC-XXX-3B9
Microcontroller, 16-Bit, MROM, 32MHz, MOS, PQFP80, 14 X 14 MM, 2.70 MM HEIGHT, PLASTIC, QFP-80
NEC
UPD784037YGC-XXX-8BT
Microcontroller, 16-Bit, MROM, 32MHz, MOS, PQFP80, 14 X 14 MM, 1.40 MM HEIGHT, PLASTIC, QFP-80
NEC
UPD784037YGK-XXX-BE9
Microcontroller, 16-Bit, MROM, 32MHz, MOS, PQFP80, 12 X 12 MM, FINE PITCH, PLASTIC, TQFP-80
NEC
©2020 ICPDF网 联系我们和版权申明