UPD789071 [ETC]
78K/0S Series Instructions | User's Manual[11/2000] ; 78K / 0S系列指令|用户手册[ 11/2000 ]\n型号: | UPD789071 |
厂家: | ETC |
描述: | 78K/0S Series Instructions | User's Manual[11/2000]
|
文件: | 总123页 (文件大小:402K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
User’s Manual
78K/0S Series
8-Bit Single-Chip Microcontroller
Instructions
Common to 78K/0S Series
Document No. U11047EJ3V0UMJ1 (3rd edition)
Date Published November 2000 N CP(K)
©
1996
Printed in Japan
[MEMO]
User’s Manual U11047EJ3V0UM00
2
NOTES FOR CMOS DEVICES
1
PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note:
Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and
ultimately degrade the device operation. Steps must be taken to stop generation of static electricity
as much as possible, and quickly dissipate it once, when it has occurred. Environmental control
must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using
insulators that easily build static electricity. Semiconductor devices must be stored and transported
in an anti-static container, static shielding bag or conductive material. All test and measurement
tools including work bench and floor should be grounded. The operator should be grounded using
wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need
to be taken for PW boards with semiconductor devices on it.
2
HANDLING OF UNUSED INPUT PINS FOR CMOS
Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided
to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence
causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels
of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused
pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
being an output pin. All handling related to the unused pins must be judged device by device and
related specifications governing the devices.
3
STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note:
Power-on does not necessarily define initial status of MOS device. Production process of MOS
does not define the initial operation status of the device. Immediately after the power source is
turned ON, the devices with reset function have not yet been initialized. Hence, power-on does
not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the
reset signal is received. Reset operation must be executed immediately after power-on for devices
having reset function.
EEPROM is a trademark of NEC Corporation.
The export of these products from Japan is regulated by the Japanese government. The export of some or all of these
products may be prohibited without governmental license. To export or re-export some or all of these products from a
country other than Japan may also be prohibited without a license from that country. Please call an NEC sales
representative.
The following products are manufactured and sold based on a license contract with CP8 Transac
regarding the EEPROM microcontroller patent.
These products cannot be used for an IC card (SMART CARD).
Applicable products: µPD789146, 789156, 789197AY, 789217AY Subseries
User’s Manual U11047EJ3V0UM00
3
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•
The information in this document is current as of March, 1999. The information is subject to change
without notice. For actual design-in, refer to the latest publications of NEC's data sheets or data
books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all products
and/or types are available in every country. Please check with an NEC sales representative for
availability and additional information.
•
•
No part of this document may be copied or reproduced in any form or by any means without prior
written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.
NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of
third parties by or arising from the use of NEC semiconductor products listed in this document or any other
liability arising from the use of such products. No license, express, implied or otherwise, is granted under any
patents, copyrights or other intellectual property rights of NEC or others.
•
•
•
Descriptions of circuits, software and other related information in this document are provided for illustrative
purposes in semiconductor product operation and application examples. The incorporation of these
circuits, software and information in the design of customer's equipment shall be done under the full
responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third
parties arising from the use of these circuits, software and information.
While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers
agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize
risks of damage to property or injury (including death) to persons arising from defects in NEC
semiconductor products, customers must incorporate sufficient safety measures in their design, such as
redundancy, fire-containment, and anti-failure features.
NEC semiconductor products are classified into the following three quality grades:
"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products
developed based on a customer-designated "quality assurance program" for a specific application. The
recommended applications of a semiconductor product depend on its quality grade, as indicated below.
Customers must check the quality grade of each semiconductor product before using it in a particular
application.
"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio
and visual equipment, home electronic appliances, machine tools, personal electronic equipment
and industrial robots
"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster
systems, anti-crime systems, safety equipment and medical equipment (not specifically designed
for life support)
"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life
support systems and medical equipment for life support, etc.
The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's
data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not
intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness
to support a given application.
(Note)
(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.
(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for
NEC (as defined above).
M8E 00. 4
User’s Manual U11047EJ3V0UM00
4
Regional Information
Some information contained in this document may vary from country to country. Before using any NEC
product in your application, pIease contact the NEC office in your country to obtain a list of authorized
representatives and distributors. They will verify:
•
•
•
•
•
Device availability
Ordering information
Product release schedule
Availability of related technical literature
Development environment specifications (for example, specifications for third-party tools and
components, host computers, power plugs, AC supply voltages, and so forth)
•
Network requirements
In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary
from country to country.
NEC Electronics Inc. (U.S.)
Santa Clara, California
Tel: 408-588-6000
800-366-9782
NEC Electronics (Germany) GmbH NEC Electronics Hong Kong Ltd.
Benelux Office
Hong Kong
Eindhoven, The Netherlands
Tel: 040-2445845
Tel: 2886-9318
Fax: 2886-9022/9044
Fax: 408-588-6130
800-729-9288
Fax: 040-2444580
NEC Electronics Hong Kong Ltd.
Seoul Branch
Seoul, Korea
Tel: 02-528-0303
Fax: 02-528-4411
NEC Electronics (France) S.A.
Velizy-Villacoublay, France
Tel: 01-30-67 58 00
NEC Electronics (Germany) GmbH
Duesseldorf, Germany
Tel: 0211-65 03 02
Fax: 01-30-67 58 99
Fax: 0211-65 03 490
NEC Electronics Singapore Pte. Ltd.
United Square, Singapore
Tel: 65-253-8311
NEC Electronics (France) S.A.
Madrid Office
Madrid, Spain
NEC Electronics (UK) Ltd.
Milton Keynes, UK
Tel: 01908-691-133
Fax: 65-250-3583
Tel: 91-504-2787
Fax: 01908-670-290
Fax: 91-504-2860
NEC Electronics Taiwan Ltd.
Taipei, Taiwan
Tel: 02-2719-2377
NEC Electronics Italiana s.r.l.
Milano, Italy
Tel: 02-66 75 41
NEC Electronics (Germany) GmbH
Scandinavia Office
Taeby, Sweden
Fax: 02-2719-5951
Fax: 02-66 75 42 99
Tel: 08-63 80 820
NEC do Brasil S.A.
Electron Devices Division
Guarulhos-SP Brasil
Tel: 55-11-6462-6810
Fax: 55-11-6462-6829
Fax: 08-63 80 388
J00.7
User’s Manual U11047EJ3V0UM00
5
MAJOR REVISIONS IN THIS EDITION
Page
Contents
Throughout
•
•
Addition of the following target products
µPD789046, 789104, 789114, 789124, 789134, 789146, 789156, 789167, 789177, 789197AY,
789217AY, 789407A, 789417A, and 789842 Subseries
Deletion of the following target products
µPD789407, 789417, and 789806Y Subseries
p. 52
p. 52
p. 54
p. 54
Modification of MOV PSW, #byte instruction code
Modification of MOVW rp, AX instruction code
Modification of XOR A, r instruction code
Modification of CMP A, r instruction code
The mark shows major revised points.
User’s Manual U11047EJ3V0UM00
6
INTRODUCTION
Readers
This manual is intended for users who wish to understand the functions of 78K/0S
Series products and to design and develop its application systems and programs.
78K/0S Series products
• µPD789014 Subseries:
• µPD789026 Subseries:
• µPD789046 Subseries Note
• µPD789104 Subseries:
• µPD789114 Subseries:
• µPD789124 Subseries Note
• µPD789134 Subseries Note
• µPD789146 Subseries Note
• µPD789156 Subseries Note
• µPD789167 Subseries Note
• µPD789177 Subseries Note
µPD789011, 789012, 78P9014
µPD789022, 789024, 789025, 789026, 78F9026
µPD789046, 78F9046
:
µPD789101, 789102, 789104
µPD789111, 789112, 789114, 78F9116
µPD789121, 789122, 789124
µPD789131, 789132, 789134, 78F9136
µPD789144, 789146
:
:
:
:
:
:
µPD789154, 789156, 78F9156
µPD789166, 789167
µPD789176, 789177, 78F9177
• µPD789197AY Subseries Note: µPD789196AY, 789197AY, 78F9197AY
• µPD789217AY Subseries Note: µPD789216AY, 789217AY, 78F9217AY
• µPD789407A Subseries:
• µPD789417A Subseries:
• µPD789800 Subseries:
• µPD789842 Subseries Note
µPD789405A, 789406A, 789407A
µPD789415A, 789416A, 789417A, 78F9418A
µPD789800, 78F9801
:
µPD789841, 789842, 78F9842
Note Under development
Purpose
This manual is intended for users to understand the instruction functions of 78K/0S
Series products.
Organization
The contents of this manual are broadly divided into the following.
• CPU functions
• Instruction set
• Explanation of instructions
How to read this manual It is assumed that the reader of this manual has general knowledge in the fields of
electrical engineering, logic circuits, and microcontrollers.
• To check the details of the functions of an instruction whose mnemonic is known:
→ See APPENDICES A and B INSTRUCTION INDEX.
• To check an instruction whose mnemonic is not known but whose general function is
known:
→ Check the mnemonic in CHAPTER 4 INSTRUCTION SET, then the functions in
CHAPTER 5 EXPLANATION OF INSTRUCTIONS.
• To understand the overall functions of the 78K/0S Series products instructions in
general:
→ Read this manual in the order of the CONTENTS.
User’s Manual U11047EJ3V0UM00
7
• To learn the hardware functions of the 78K/0S Series products:
→ Refer to the user's manual for each product (see Related documents).
Conventions
Data significance:
Note:
Higher digits on the left and lower digits on the right
Footnote for item marked with Note in the text
Information requiring particular attention
Supplementary information
Caution:
Remark:
Numeral representation:
Binary...............×××× or ××××B
Decimal............××××
Hexadecimal....××××H
Related Documents
The related documents indicated in this publication may include preliminary versions. However, preliminary
versions are not marked as such.
Document common to 78K/0S Series
Document Name
Document Number
English Japanese
This manual U11047J
User's Manual Instructions
Individual documents
• µPD789014 Subseries
Document Name
Document Number
English Japanese
µPD789011, 789012 Data Sheet
µPD78P9014 Data Sheet
U11095E
U10912E
U11187E
U11095J
U10912J
U11187J
µPD789014 Subseries User's Manual
• µPD789026 Subseries
Document Name
Document Number
English Japanese
µPD789022, 789024, 789025, 789026 Data Sheet
µPD78F9026 Data Sheet
U11715E
U11858E
U11919E
U11715J
U11858J
U11919J
µPD789026 Subseries User's Manual
• µPD789046 Subseries
Document Name
Document Number
English Japanese
µPD789046 Preliminary Product Information
µPD78F9046 Preliminary Product Information
µPD789046 Subseries User’s Manual
U13380E
U13546E
U13600E
U13380J
U13546J
U13600J
User’s Manual U11047EJ3V0UM00
8
• µPD789104 Subseries
Document Name
Document Number
English Japanese
µPD789101, 789102, 789104 Data Sheet
µPD789134 Subseries User’s Manual
To be prepared U12815J
U13045E U13045J
• µPD789114 Subseries
Document Name
Document Number
English Japanese
µPD789111, 789112, 789114 Preliminary Product Information
µPD78F9116 Preliminary Product Information
µPD789134 Subseries User’s Manual
U13013E
U13037E
U13045E
U13013J
U13037J
U13045J
• µPD789124 Subseries
Document Name
Document Number
English Japanese
µPD789121, 789122, 789124 Preliminary Product Information
µPD789134 Subseries User’s Manual
U13025E
U13045E
U13025J
U13045J
• µPD789134 Subseries
Document Name
Document Number
English Japanese
µPD789131, 789132, 789134 Preliminary Product Information
µPD78F9136 Preliminary Product Information
µPD789134 Subseries User’s Manual
U13015E
U13036E
U13045E
U13015J
U13036J
U13045J
• µPD789146, 789156 Subseries
Document Name
Document Number
English Japanese
µPD789144, 789146, 789154, 789156 Preliminary Product Information
µPD78F9156 Preliminary Product Information
U13478E
To be prepared U13756J
U13651E U13651J
U13478J
µPD789146, 789156 Subseries User’s Manual
• µPD789167, 789177 Subseries
Document Name
Document Number
English Japanese
µPD789166, 789167, 789176, 789177 Preliminary Product Information
µPD78F9177 Preliminary Product Information
To be prepared U14017J
To be prepared U14022J
To be prepared To be prepared
µPD789177 Subseries User’s Manual
User’s Manual U11047EJ3V0UM00
9
• µPD789197AY Subseries
Document Name
Document Number
English Japanese
µPD789196AY, 789197AY Preliminary Product Information
µPD78F9197Y Preliminary Product Information
µPD789217Y Subseries User’s Manual
U13853E
U13224E
U13186E
U13853J
U13224J
U13186J
• µPD789217AY Subseries
Document Name
Document Number
English Japanese
µPD789216Y, 789217Y Preliminary Product Information
µPD78F9217Y Preliminary Product Information
µPD789217Y Subseries User’s Manual
U13196E
U13205E
U13186E
U13196J
U13205J
U13186J
• µPD789407A, 789417A Subseries
Document Name
Document Number
English Japanese
µPD789405A, 789406A, 789407A, 789415A, 789416A, 789417A Data Sheet
µPD78F9418A Data Sheet
To be prepared U14024J
To be prepared To be prepared
To be prepared U13952J
µPD789407A, 789417A Subseries User's Manual
• µPD789800 Subseries
Document Name
Document Number
English
U12627E
Japanese
U12627J
µPD789800 Data Sheet
µPD78F9801 Preliminary Product Information
µPD789800 Subseries User's Manual
U12626E
U12978E
U12626J
U12978J
• µPD789842 Subseries
Document Name
Document Number
English Japanese
µPD789841, 789842 Preliminary Product Information
µPD78F9842 Preliminary Product Information
µPD789842 Subseries User's Manual
U13790E
U13901E
U13776E
U13790J
U13901J
U13776J
Caution
The above documents are subject to change without prior notice. Be sure to use the latest
version document when starting design.
User’s Manual U11047EJ3V0UM00
10
CONTENTS
CHAPTER 1 MEMORY SPACE................................................................................................................ 15
1.1
1.2
1.3
1.4
1.5
1.6
Memory Space...........................................................................................................................................15
Internal Program Memory (Internal ROM) Space ...................................................................................15
Vector Table Area .....................................................................................................................................17
CALLT Instruction Table Area .................................................................................................................20
Internal Data Memory Space....................................................................................................................20
Special Function Register (SFR) Area ....................................................................................................22
CHAPTER 2 REGISTERS ........................................................................................................................ 23
2.1
Control Registers......................................................................................................................................23
2.1.1
2.1.2
2.1.3
Program counter (PC)...................................................................................................................23
Program status word (PSW) .........................................................................................................23
Stack pointer (SP).........................................................................................................................24
2.2
2.3
General-Purpose Registers......................................................................................................................25
Special Function Registers (SFRs) .........................................................................................................27
CHAPTER 3 ADDRESSING ..................................................................................................................... 29
3.1
Addressing of Instruction Address.........................................................................................................29
3.1.1
3.1.2
3.1.3
3.1.4
Relative addressing ......................................................................................................................29
Immediate addressing ..................................................................................................................30
Table indirect addressing..............................................................................................................31
Register addressing......................................................................................................................32
3.2
Addressing of Operand Address.............................................................................................................33
3.2.1
3.2.2
3.2.3
3.2.4
3.2.5
3.2.6
3.2.7
Direct addressing..........................................................................................................................33
Short direct addressing.................................................................................................................34
Special function register (SFR) addressing ..................................................................................35
Register addressing......................................................................................................................36
Register indirect addressing .........................................................................................................37
Based addressing.........................................................................................................................38
Stack addressing ..........................................................................................................................38
CHAPTER 4 INSTRUCTION SET ............................................................................................................. 39
4.1 Operation...................................................................................................................................................40
4.1.1
4.1.2
4.1.3
4.1.4
4.1.5
4.1.6
Operand representation and description formats .........................................................................40
Description of operation column ...................................................................................................41
Description of flag column ............................................................................................................41
Description of clock column..........................................................................................................42
Operation list.................................................................................................................................43
Instruction list by addressing ........................................................................................................48
4.2
Instruction Codes .....................................................................................................................................51
4.2.1
4.2.2
Description of instruction code table.............................................................................................51
Instruction code list.......................................................................................................................52
User’s Manual U11047EJ3V0UM00
11
CHAPTER 5 EXPLANATION OF INSTRUCTIONS.................................................................................. 57
5.1
5.2
5.3
5.4
5.5
5.6
5.7
5.8
5.9
8-Bit Data Transfer Instructions .............................................................................................................. 59
16-Bit Data Transfer Instructions ............................................................................................................ 62
8-Bit Operation Instructions .................................................................................................................... 65
16-Bit Operation Instructions .................................................................................................................. 74
Increment/Decrement Instructions.......................................................................................................... 78
Rotate Instructions................................................................................................................................... 83
Bit Manipulation Instructions .................................................................................................................. 88
CALL/RETURN Instructions..................................................................................................................... 92
Stack Manipulation Instructions.............................................................................................................. 97
5.10 Unconditional Branch Instruction......................................................................................................... 101
5.11 Conditional Branch Instructions ........................................................................................................... 103
5.12 CPU Control Instructions....................................................................................................................... 111
APPENDIX A INSTRUCTION INDEX (MNEMONIC: BY FUNCTION) .................................................. 117
APPENDIX B INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER)............................ 119
APPENDIX C REVISION HISTORY........................................................................................................ 121
User’s Manual U11047EJ3V0UM00
12
LIST OF FIGURES
Figure No.
Title
Page
2-1. Format of Program Counter..............................................................................................................................23
2-2. Format of Program Status Word.......................................................................................................................23
2-3. Format of Stack Pointer....................................................................................................................................24
2-4. Data to Be Saved to Stack Memory .................................................................................................................25
2-5. Data to Be Restored from Stack Memory.........................................................................................................25
2-6. General-Purpose Register Configuration .........................................................................................................26
LIST OF TABLES
Table No.
Title
Page
1-1. Internal ROM Space of 78K/0S Series Products..............................................................................................15
1-2. Vector Table (0000H to 0013H) (µPD789014 Subseries) ................................................................................17
1-3. Vector Table (0000H to 002BH) (µPD789026 Subseries)................................................................................17
1-4. Vector Table (0000H to 0019H) (µPD789046 Subseries) ................................................................................17
1-5. Vector Table (0000H to 0015H) (µPD789104, 789114, 789124, 789134 Subseries) ......................................17
1-6. Vector Table (0000H to 0019H) (µPD789146, 789156 Subseries) ..................................................................18
1-7. Vector Table (0000H to 0023H) (µPD789167, 789177 Subseries) ..................................................................18
1-8. Vector Table (0000H to 0027H) (µPD789197AY, 789217AY Subseries).........................................................18
1-9. Vector Table (0000H to 0023H) (µPD789407A and µPD789417A Subseries).................................................19
1-10. Vector Table (0000H to 0019H) (µPD789800 Subseries) ................................................................................19
1-11. Vector Table (0000H to 0023H) (µPD789842 Subseries) ................................................................................19
1-12. Internal Data Memory Space of 78K/0S Series Products.................................................................................20
4-1. Operand Representation and Description Formats..........................................................................................40
User’s Manual U11047EJ3V0UM00
13
[MEMO]
User’s Manual U11047EJ3V0UM00
14
CHAPTER 1 MEMORY SPACE
1.1 Memory Space
The 78K/0S Series product program memory map varies depending on the internal memory capacity. For details
of the memory mapped address area, refer to the User's Manual of each product.
1.2 Internal Program Memory (Internal ROM) Space
The 78K/0S Series product has internal ROM in the address space shown below. Program and table data, etc.
are stored in ROM. This memory space is usually addressed by the program counter (PC).
Table 1-1. Internal ROM Space of 78K/0S Series Products (1/2)
Capacity
2 Kbytes
4 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
Address
Space
0000H to
07FFH
0000H to
0FFFH
0000H to
1FFFH
0000H to
2FFFH
0000H to
3FFFH
0000H to
5FFFH
0000H to
7FFFH
Subseries Name
µPD789014
µPD789011
µPD789012
µPD789022
µPD78P9014
µPD789024
Subseries
µPD789026
µPD789025
µPD789026
Subseries
µPD78F9026
µPD789046
µPD789046
Subseries
µPD78F9046
µPD789104
µPD789101
µPD789111
µPD789121
µPD789131
µPD789102
µPD789112
µPD789122
µPD789132
µPD789104
µPD789114
µPD789124
µPD789134
µPD789144
µPD789154
Subseries
µPD789114
µPD78F9116
Subseries
µPD789124
Subseries
µPD789134
µPD78F9136
µPD789146
Subseries
µPD789146
Subseries
µPD789156
µPD789156
Subseries
µPD78F9156
µPD789167
µPD789166
µPD789176
µPD789196AY
µPD789167
Subseries
µPD789177
µPD789177
Subseries
µPD78F9177
µPD789197AY
µPD789197AY
µPD78F9197AY
Subseries
User’s Manual U11047EJ3V0UM00
15
CHAPTER 1 MEMORY SPACE
Table 1-1. Internal ROM Space of 78K/0S Series Products (2/2)
Capacity
2 Kbytes
4 Kbytes
8 Kbytes
12 Kbytes
16 Kbytes
24 Kbytes
32 Kbytes
Address
Space
0000H to
07FFH
0000H to
0FFFH
0000H to
1FFFH
0000H to
2FFFH
0000H to
3FFFH
0000H to
5FFFH
0000H to
7FFFH
Subseries Name
µPD789217AY
µPD789216AY
µPD789217AY
µPD78F9217AY
Subseries
µPD789407A
µPD789405A µPD789406A µPD789407A
Subseries
µPD789417A
µPD789415A µPD789416A µPD789417A µPD78F9418A
µPD78F9801
Subseries
µPD789800
µPD789800
µPD789841
Subseries
µPD789842
µPD789842
Subseries
µPD78F9842
User’s Manual U11047EJ3V0UM00
16
CHAPTER 1 MEMORY SPACE
1.3 Vector Table Area
The vector table area stores program start addresses to which execution branches when the RESET signal is
input or when an interrupt request is generated. Of the 16-bit address, the lower 8 bits are stored in an even
address, and the higher 8 bits are stored in an odd address.
Table 1-2. Vector Table (0000H to 0013H) (µPD789014 Subseries)
Vector Table Address
0000H
Interrupt Request
RESET input
Vector Table Address
000CH
Interrupt Request
INTSR/INTCSI0
0004H
0006H
0008H
000AH
INTWDT
INTP0
INTP1
INTP2
000EH
0010H
0012H
INTST
INTTM0
INTTM1
Table 1-3. Vector Table (0000H to 002BH) (µPD789026 Subseries)
Vector Table Address
Interrupt Request
RESET input
Vector Table Address
000CH
Interrupt Request
INTSR/INTCSI0
0000H
0004H
0006H
0008H
000AH
INTWDT
INTP0
INTP1
INTP2
000EH
0010H
0014H
002AH
INTST
INTTM0
INTTM2
INTKR
Table 1-4. Vector Table (0000H to 0019H) (µPD789046 Subseries)
Vector Table Address
Interrupt Request
RESET input
Vector Table Address
000EH
Interrupt Request
INTST20
0000H
0004H
0006H
0008H
000AH
000CH
INTWDT
INTP0
0010H
0012H
0014H
0016H
0018H
INTWT
INTWTI
INTP1
INTTM80
INTTM90
INTKR00
INTP2
INTSR20/INTCSI20
Table 1-5. Vector Table (0000H to 0015H) (µPD789104, 789114, 789124, 789134 Subseries)
Vector Table Address
Interrupt Request
RESET input
Vector Table Address
000CH
Interrupt Request
INTSR20/INTCSI20
0000H
0004H
0006H
0008H
000AH
INTWDT
INTP0
INTP1
INTP2
000EH
0010H
0012H
0014H
INTST20
INTTM80
INTTM20
INTAD0
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CHAPTER 1 MEMORY SPACE
Table 1-6. Vector Table (0000H to 0019H) (µPD789146, 789156 Subseries)
Vector Table Address
0000H
Interrupt Request
RESET input
Vector Table Address
000EH
Interrupt Request
INTST20
0004H
0006H
0008H
000AH
000CH
INTWDT
INTP0
0010H
0012H
0014H
0016H
0018H
INTTM80
INTTM20
INTAD0
INTLVI0
INTEE1
INTP1
INTP2
INTSR20/INTCSI20
Table 1-7. Vector Table (0000H to 0023H) (µPD789167, 789177 Subseries)
Vector Table Address
Interrupt Request
RESET input
Vector Table Address
0012H
Interrupt Request
0000H
0004H
0006H
0008H
000AH
000CH
000EH
0010H
INTWT
INTWDT
INTP0
0014H
0016H
0018H
001AH
001CH
0022H
INTWTI
INTTM80
INTTM81
INTTM82
INTTM90
INTAD0
INTP1
INTP2
INTP3
INTSR20/INTCSI20
INTST20
Table 1-8. Vector Table (0000H to 0027H) (µPD789197AY, 789217AY Subseries)
Vector Table Address
Interrupt Request
RESET input
Vector Table Address
0016H
Interrupt Request
INTTM80
0000H
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
0014H
INTWDT
INTP0
0018H
001AH
001CH
001EH
0020H
0022H
0024H
0026H
INTTM81
INTTM82
INTTM90
INTSMB0
INTSMBOV0
INTAD0
INTP1
INTP2
INTP3
INTSR20/INTCSI20
INTST20
INTWT
INTLVI0
INTEE1
INTWTI
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CHAPTER 1 MEMORY SPACE
Table 1-9. Vector Table (0000H to 0023H) (µPD789407A and µPD789417A Subseries)
Vector Table Address
0000H
Interrupt Request
RESET input
Vector Table Address
0014H
Interrupt Request
INTWTI
0004H
0006H
0008H
000AH
000CH
000EH
0010H
0012H
INTWDT
INTP0
0016H
0018H
001AH
001CH
001EH
0020H
0022H
INTTM00
INTTM01
INTTM02
INTTM50
INTKR00
INTAD0
INTP1
INTP2
INTP3
INTSR00/INTCSI00
INTST00
INTWT
INTCMP0
Table 1-10. Vector Table (0000H to 0019H) (µPD789800 Subseries)
Vector Table Address
Interrupt Request
RESET input
Vector Table Address
000EH
Interrupt Request
INTUSBRE
0000H
0004H
0006H
0008H
000AH
000CH
INTWDT
0010H
0012H
0014H
0016H
0018H
INTP0
INTUSBTM
INTUSBRT
INTUSBRD
INTUSBST
INTCSI10
INTTM00
INTTM01
INTKR00
Table 1-11. Vector Table (0000H to 0023H) (µPD789842 Subseries)
Vector Table Address
Interrupt Request
RESET input
Vector Table Address
0016H
Interrupt Request
INTST00
0000H
0004H
0006H
0008H
000AH
000CH
000EH
INTWDT
INTP0
0018H
001AH
001CH
001EH
0020H
0022H
INTWT
INTWTI
INTTM80
INTTM81
INTTM82
INTAD
INTP1
INTTM7
INTSER00
INTSR00
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CHAPTER 1 MEMORY SPACE
1.4 CALLT Instruction Table Area
In a 64-byte address area 0040H to 007FH, the subroutine entry address of a 1-byte call instruction (CALLT) can
be stored.
1.5 Internal Data Memory Space
The 78K/0S Series products incorporate the following data memory:
(1) Internal high-speed RAM
The 78K/0S Series products incorporate internal high-speed RAM in the address space shown in Table 1-12.
The internal high-speed RAM is also used as a stack memory.
(2) LCD display RAM (µPD789407A and µPD789417A Subseries)
LCD display RAM is allocated in the area between FA00H and FA1BH.
The LCD display RAM can also be used as ordinary RAM.
(3) EEPROMTM (µPD789146, 789156, 789197AY, 789217AY Subseries)
Electrically erasable PROM (EEPROM) is allocated in the address space shown in Table 1-12.
Unlike ordinary RAM, EEPROM retains the data it contains even when the power is turned off. Also, unlike
EPROM, the contents of EEPROM can be erased electrically, without the need to expose the chip to
ultraviolet light.
Table 1-12. Internal Data Memory Space of 78K/0S Series Products (1/2)
Subseries Name
µPD789014
Product Name
µPD789011
High-Speed RAM
LCD Display RAM
EEPROM
FE80H to FEFFH
(128 bytes)
Subseries
µPD789012
µPD78P9014
FE00H to FEFFH
(256 bytes)
µPD789026
µPD789022
µPD789024
µPD789025
µPD789026
µPD78F9026
µPD789046
µPD78F9046
µPD789101
µPD789102
µPD789104
µPD789111
µPD789112
µPD789114
µPD78F9116
FE00H to FEFFH
(256 bytes)
Subseries
FD00H to FEFFH
(512 bytes)
µPD789046
Subseries
µPD789104
Subseries
FD00H to FEFFH
(512 bytes)
FE00H to FEFFH
(256 bytes)
µPD789114
FE00H to FEFFH
(256 bytes)
Subseries
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CHAPTER 1 MEMORY SPACE
Table 1-12. Internal Data Memory Space of 78K/0S Series Products (2/2)
Subseries Name
µPD789124
Product Name
µPD789121
High-Speed RAM
FE00H to FEFFH
(256 bytes)
LCD Display RAM
EEPROM
Subseries
µPD789122
µPD789124
µPD789131
µPD789132
µPD789134
µPD78F9136
µPD789144
µPD789146
µPD789154
µPD789156
µPD78F9156
µPD789166
µPD789167
µPD789176
µPD789177
µPD78F9177
µPD789196AY
µPD789197AY
µPD78F9197AY
µPD789216AY
µPD789217AY
µPD78F9217AY
µPD789405A
µPD789406A
µPD789407A
µPD789415A
µPD789416A
µPD789417A
µPD78F9418A
µPD789800
µPD78F9801
µPD789841
µPD789842
µPD78F9842
µPD789134
FE00H to FEFFH
(256 bytes)
Subseries
µPD789146
Subseries
µPD789156
Subseries
FE00H to FEFFH
(256 bytes)
F800H to F8FFH
(256 bytes)
FE00H to FEFFH
(256 bytes)
F800H to F8FFH
(256 bytes)
µPD789167
Subseries
µPD789177
Subseries
FD00H to FEFFH
(512 bytes)
FD00H to FEFFH
(512 bytes)
µPD789197AY
FD00H to FEFFH
(512 bytes)
F800H to F87FH
(128 bytes)
Subseries
µPD789217AY
FD00H to FEFFH
(512 bytes)
F800H to F87FH
(128 bytes)
Subseries
µPD789407A
FD00H to FEFFH
(512 bytes)
FA00H to FA1BH
(28 bytes)
Subseries
µPD789417A
FD00H to FEFFH
(512 bytes)
FA00H to FA1BH
(28 bytes)
Subseries
µPD789800
Subseries
µPD789842
Subseries
FE00H to FEFFH
(256 bytes)
FE00H to FEFFH
(256 bytes)
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CHAPTER 1 MEMORY SPACE
1.6 Special Function Register (SFR) Area
Special-function registers (SFRs) of on-chip peripheral hardware are allocated to the area FF00H to FFFFH
(refer to the User's Manual of each product).
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CHAPTER 2 REGISTERS
2.1 Control Registers
The control registers have dedicated functions such as controlling the program sequence, statuses, and stack
memory. The control registers include a program counter, program status word, and stack pointer.
2.1.1 Program counter (PC)
The program counter is a 16-bit register that holds the address information of the next program to be executed.
In normal operation, the PC is automatically incremented according to the number of bytes of the instruction to be
fetched. When a branch instruction is executed, immediate data and register contents are set.
______________
When the RESET signal is input, the program counter is set to the value of the reset vector table, which are
located at addresses 0000H and 0001H.
Figure 2-1. Format of Program Counter
15
0
PC PC15 PC14 PC13 PC12 PC11 PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0
2.1.2 Program status word (PSW)
Program status word is an 8-bit register consisting of various flags to be set/reset by instruction execution.
The contents of program status word are automatically stacked when an interrupt request is generated or when
the PUSH PSW instruction is executed and, are automatically reset when the RETI and POP PSW instruction are
executed.
______________
RESET input sets PSW to 02H.
Figure 2-2. Format of Program Status Word
7
0
IE
Z
0
AC
0
0
1
CY
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CHAPTER 2 REGISTERS
(1) Interrupt enable flag (IE)
This flag controls interrupt request acknowledge operations of the CPU.
When IE = 0, all interrupts except non-maskable interrupts are disabled (DI status).
When IE = 1, interrupts are enabled (EI status). At this time, acknowledgment of interrupt requests is
controlled by the interrupt mask flag for each interrupt source.
The IE flag is reset (0) when the DI instruction execution is executed or when an interrupt is acknowledged,
and set (1) when the EI instruction is executed.
(2) Zero flag (Z)
When the operation result is zero, this flag is set (1); otherwise, it is reset (0).
(3) Auxiliary carry flag (AC)
If the operation result has a carry from bit 3 or a borrow to bit 3, this flag is set (1); otherwise, it is reset (0).
(4) Carry flag (CY)
This flag records an overflow or underflow upon add/subtract instruction execution. It also records the shift-
out value upon rotate instruction execution, and functions as a bit accumulator during bit operation instruction
execution.
2.1.3 Stack pointer (SP)
This is a 16-bit register that holds the first address of the stack area in the memory. Only the internal high-speed
RAM area can be set as the stack area.
Figure 2-3. Format of Stack Pointer
15
0
SP SP15 SP14 SP13 SP12 SP11 SP10 SP9 SP8 SP7 SP6 SP5 SP4 SP3 SP2 SP1 SP0
The SP is decremented ahead of write (save) to the stack memory, and is incremented after read (reset) from the
stack memory.
The data saved/restored as a result of each stack operation are as shown in Figures 2-4 and 2-5.
______
Caution
Since RESET input makes the SP contents undefined, be sure to initialize the SP before
executing an instruction.
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CHAPTER 2 REGISTERS
Figure 2-4. Data to Be Saved to Stack Memory
Interrupt
PUSH rp
CALL, CALLT
instruction
instructions
SP SP − 3
SP − 3
SP − 2
SP − 1
SP
SP SP − 2
SP − 2
SP − 1
SP
SP SP − 2
SP − 2
SP − 1
SP
PC7 to PC0
PC15 to PC8
PSW
Lower byte in
register pair
PC7 to PC0
Upper byte in
register pair
PC15 to PC8
Figure 2-5. Data to Be Restored from Stack Memory
POP rp
RET instruction
RETI instruction
instruction
Lower byte in
register pair
SP
SP + 1
SP
SP + 1
SP
SP + 1
PC7 to PC0
PC7 to PC0
PC15 to PC8
PSW
Upper byte in
register pair
PC15 to PC8
SP SP + 2
SP SP + 2
SP + 2
SP SP + 3
2.2 General-Purpose Registers
The general-purpose register consists of eight 8-bit registers (X, A, C, B, E, D, L, and H).
Each register can be used as an 8-bit register, or two 8-bit registers in pairs can be used as a 16-bit register (AX,
BC, DE, and HL).
Registers can be described in terms of functional names (X, A, C, B, E, D, L, H, AX, BC, DE, and HL) and
absolute names (R0 to R7 and RP0 to RP3).
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CHAPTER 2 REGISTERS
Figure 2-6. General-Purpose Register Configuration
(a) Absolute name
16-bit processing
RP3
8-bit processing
R7
R6
R5
R4
RP2
RP1
RP0
R3
R2
R1
R0
15
0
7
0
(b) Functional name
16-bit processing
HL
8-bit processing
H
L
D
E
DE
BC
AX
B
C
A
X
15
0
7
0
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CHAPTER 2 REGISTERS
2.3 Special Function Registers (SFRs)
Unlike general-purpose registers, special function registers have their own functions and are allocated to the 256-
byte area FF00H to FFFFH.
A special function register can be manipulated, like a general-purpose register, by using operation, transfer, and
bit manipulation instructions. The bit units in which one register is to be manipulated (1, 8, and 16) differ depending
on the special function register type.
The bit unit for manipulation is specified as follows.
•
•
•
1-bit manipulation
Describes a symbol reserved by the assembler for the 1-bit manipulation instruction operand (sfr.bit). This
manipulation can also be specified with an address.
8-bit manipulation
Describes a symbol reserved by the assembler for the 8-bit manipulation instruction operand (sfr). This
manipulation can also be specified with an address.
16-bit manipulation
Describes a symbol reserved by the assembler for the 16-bit manipulation instruction operand. When
addressing an address, describe an even address.
For details of the special function registers, refer to the User's Manual of each product.
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[MEMO]
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CHAPTER 3 ADDRESSING
3.1 Addressing of Instruction Address
An instruction address is determined by the program counter (PC) contents. The PC contents are normally
incremented (+1 per byte) automatically according to the number of bytes of an instruction to be fetched each time
another instruction is executed. When a branch instruction is executed, the branch destination information is set in
the PC and branched by the following addressing (For details of each instruction, see CHAPTER 5 EXPLANATION
OF INSTRUCTIONS).
3.1.1 Relative addressing
[Function]
The value obtained by adding the 8-bit immediate data (displacement value: jdisp8) of an instruction code to
the first address of the following instruction is transferred to the program counter (PC) and program branches.
The displacement value is treated as signed two’s complement data (–128 to +127) and bit 7 becomes a sign bit.
Thus, relative addressing causes a branch to an address within the range of –128 to +127, relative to the first
address of the next instruction.
This function is carried out when the BR $addr16 instruction or a conditional branch instruction is executed.
[Illustration]
15
15
0
0
...
PC holds the first address
of instruction next to
BR instruction.
PC
+
8
7
6
α
S
jdisp8
15
0
PC
When S = 0, all bits of α are 0.
When S = 1, all bits of α are 1.
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CHAPTER 3 ADDRESSING
3.1.2 Immediate addressing
[Function]
Immediate data in the instruction word is transferred to the program counter (PC) and program branches.
This function is carried out when the CALL !addr16 or BR !addr16 instruction is executed.
The CALL !addr16 and BR !addr16 instructions can be used to branch to any address within the memory
spaces.
[Illustration]
In case of CALL !addr16 or BR !addr16 instruction
7
0
CALL or BR
Low addr.
High addr.
15
8 7
0
PC
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CHAPTER 3 ADDRESSING
3.1.3 Table indirect addressing
[Function]
Table contents (branch destination address) of a particular location, addressed by the immediate data of bits 1
to 5 of an instruction code are transferred to the program counter (PC), and program branches.
Table indirect addressing is performed when the CALLT [addr5] instruction is executed. This instruction
references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory
space.
[Illustration]
7
6
1
5
1
0
1
Instruction code
Effective address
0
ta4 to 0
15
8
0
7
0
6
1
5
1
0
0
0
0
0
0
0
0
0
7
Memory (table)
Low addr.
0
High addr.
Effective address + 1
15
8
7
0
PC
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CHAPTER 3 ADDRESSING
3.1.4 Register addressing
[Function]
Register pair (AX) contents specified with an instruction word are transferred to the program counter (PC) and
program branches.
This function is carried out when the BR AX instruction is executed.
[Illustration]
7
0
8
7
7
0
0
rp
A
X
15
PC
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CHAPTER 3 ADDRESSING
3.2 Addressing of Operand Address
The following methods are available to specify the register and memory (addressing) which undergo manipulation
during instruction execution.
3.2.1 Direct addressing
[Function]
This addressing directly addresses a memory to be manipulated with immediate data in an instruction word.
[Operand format]
Operand
addr16
Description
Label or 16-bit immediate data
[Description example]
MOV A, !FE00H; When setting !addr16 to FE00H
Instruction code
0
0
1
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
0
1
1
0
0
OP code
00H
FEH
[Illustration]
7
0
OP code
addr16 (lower)
addr16 (higher)
Memory
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CHAPTER 3 ADDRESSING
3.2.2 Short direct addressing
[Function]
This addressing directly addresses memory to be manipulated in the fixed space with the 8-bit data in an
instruction word.
This addressing is applied to the 256-byte fixed space of FE20H to FF1FH. An internal high-speed RAM and
special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively.
The SFR area (FF00H-FF1FH) to which short direct addressing is applied constitutes only part of the overall
SFR area. In this area, ports that are frequently accessed in a program and a compare register of the timer/event
counter are mapped, and these SFRs can be manipulated with a small number of bytes and clocks.
When 8-bit immediate data is 20H to FFH, bit 8 of an effective address is set to 0. When it is 00H to 1FH, bit 8
is set to 1. See Illustration below.
[Operand format]
Operand
Description
saddr
saddrp
Label or FE20H to FF1FH immediate data
Label or FE20H to FF1FH immediate data (even address only)
[Description example]
MOV FE30H, #50H; When setting saddr to FE30H and the immediate data to 50H
Instruction code
1
0
0
1
0
1
1
1
0
1
1
1
0
0
0
1
0
0
0
0
0
1
0
0
OP code
30H (saddr-offset)
50H (immediate data)
[Illustration]
7
0
OP code
saddr-offset
Short direct memory
15
1
8
0
Effective
address
1
1
1
1
1
1
α
When 8-bit immediate data is 20H to FFH, α = 0.
When 8-bit immediate data is 00H to 1FH, α = 1.
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CHAPTER 3 ADDRESSING
3.2.3 Special function register (SFR) addressing
[Function]
This addressing is to address special function registers (SFRs) mapped to the memory with the 8-bit immediate
data in an instruction word.
This addressing is applied to the 240-byte spaces of FF00H to FFCFH and FFE0H to FFFFH. However, the
SFRs mapped at FF00H to FF1FH can also be accessed by means of short direct addressing.
[Operand format]
Operand
Description
sfr
Special function register name
[Description example]
MOV PM0, A; When selecting PM0 for sfr
Instruction code
1
0
1
0
1
1
0
0
0
0
1
0
1
0
1
0
[Illustration]
7
0
OP code
sfr-offset
SFR
15
1
8 7
0
Effective
address
1
1
1
1
1
1
1
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CHAPTER 3 ADDRESSING
3.2.4 Register addressing
[Function]
This addressing is to access a general-purpose register by specifying it as an operand. The general-purpose
register to be accessed is specified with a register specification code in an instruction code or function name.
Register addressing is carried out when an instruction with the following operand format is executed. When an
8-bit register is specified, one of the eight registers is specified with 3 bits (register specification code) in the
instruction code.
[Operand format]
Operand
Description
r
X, A, C, B, E, D, L, H
AX, BC, DE, HL
rp
'r' and 'rp' can be described with absolute names (R0 to R7 and RP0 to RP3) as well as functional names (X, A,
C, B, E, D, L, H, AX, BC, DE, and HL).
[Description example]
MOV A, C; When selecting the C register for r
Instruction code
0
0
0
0
0
1
0
0
1
0
0
1
1
0
0
1
Register specification code
INCW DE; When selecting the DE register pair for rp
Instruction code
1
0
0
0
1
0
0
0
Register specification code
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CHAPTER 3 ADDRESSING
3.2.5 Register indirect addressing
[Function]
This addressing is to address memory using the contents of the special register pair as an operand. The
register pair to be accessed is specified with the register pair specification code in an instruction code. This
addressing can be carried out for the entire memory space.
[Operand format]
Operand
Description
[DE], [HL]
[Description example]
MOV A, [DE]; When selecting register pair [DE]
Instruction code
0
0
1
0
1
0
1
1
[Illustration]
15
8
7
0
0
DE
D
E
Memory address
specified with
register pair DE
7
The contents of
the specified memory
address are transferred.
7
0
A
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CHAPTER 3 ADDRESSING
3.2.6 Based addressing
[Function]
This addressing is to address the memory by using the result of adding 8-bit immediate data to the contents of
the base register, i.e., the HL register pair. The addition is performed by expanding the offset data as a positive
number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for the entire memory
space.
[Operand format]
Operand
Description
[HL + byte]
[Description example]
MOV A, [HL+10H]; When setting “byte” to 10H
Instruction code
0
0
0
0
1
0
0
1
1
0
1
0
0
0
1
0
3.2.7 Stack addressing
[Function]
This addressing is to indirectly address the stack area with the stack pointer (SP) contents.
This addressing method is automatically employed when the PUSH, POP, subroutine call, or RETURN
instructions is executed or when the register is saved/restored upon generation of an interrupt request.
Stack addressing can address the internal high-speed RAM area only.
[Description example]
In the case of PUSH DE
Instruction code
1
0
1
0
1
0
1
0
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CHAPTER 4 INSTRUCTION SET
This chapter lists the instruction set of the 78K/0S Series. The instructions are common to all 78K/0S Series
products.
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CHAPTER 4 INSTRUCTION SET
4.1 Operation
4.1.1 Operand representation and description formats
In the operand column of each instruction, an operand is described according to the description format for
operand representation of that instruction (for details, refer to the assembler specifications). When there are two or
more description methods, select one of them. Uppercase characters, #, !, $ and [ ] are keywords and must be
described as is. Each symbol has the following meaning.
•
•
# : Immediate data
: Absolute address
•
•
$ : Relative address
[ ] : Indirect address
!
In the case of immediate data, describe an appropriate numeric value or a label. When using a label, be sure to
describe #, !, $, or [ ].
For operand register description formats, r and rp, either functional names (X, A, C, etc.) or absolute names
(names in parentheses in the table below, R0, R1, R2, etc.) can be described.
Table 4-1. Operand Representation and Description Formats
Operand
Description Format
r
X (R0), A (R1), C (R2), B (R3), E (R4), D (R5), L (R6), H (R7)
AX (RP0), BC (RP1), DE (RP2), HL (RP3)
Special function register symbol
rp
sfr
saddr
FE20H to FF1FH Immediate data or labels
saddrp
FE20H to FF1FH Immediate data or labels (even addresses only)
addr16
addr5
0000H to FFFFH Immediate data or labels (only even addresses for 16-bit data transfer instructions)
0040H to 007FH Immediate data or labels (even addresses only)
word
byte
bit
16-bit immediate data or label
8-bit immediate data or label
3-bit immediate data or label
Remark Refer to the User's Manual of each product for symbols of special function registers.
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CHAPTER 4 INSTRUCTION SET
4.1.2 Description of operation column
A:
A register; 8-bit accumulator
X register
X:
B:
B register
C:
C register
D:
D register
E:
E register
H:
H register
L:
L register
AX:
BC:
DE:
HL:
PC:
SP:
PSW:
CY:
AC:
Z:
AX register pair; 16-bit accumulator
BC register pair
DE register pair
HL register pair
Program counter
Stack pointer
Program status word
Carry flag
Auxiliary carry flag
Zero flag
IE:
Interrupt request enable flag
NMIS: Non-maskable interrupt servicing flag
( ): Memory contents indicated by address or register contents in parentheses
XH, XL: Higher 8 bits and lower 8 bits of 16-bit register
:
:
:
Logical product (AND)
Logical sum (OR)
Exclusive logical sum (exclusive OR)
Inverted data
:
addr16: 16-bit immediate data or label
jdisp8: Signed 8-bit data (displacement value)
4.1.3 Description of flag column
(Blank): Not affected
0:
1:
×:
R:
Cleared to 0
Set to 1
Set/cleared according to the result
Previously saved value is restored
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CHAPTER 4 INSTRUCTION SET
4.1.4 Description of clock column
The number of clock cycles during instruction execution is outlined as follows.
One instruction clock cycle is equal to one CPU clock cycle (fCPU) selected by the processor clock control register
(PCC).
The operation list is shown below.
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CHAPTER 4 INSTRUCTION SET
4.1.5 Operation list
Mnemonic
Operand
Byte Clock
Operation
Flag
Z
AC CY
MOV
r, #byte
3
3
3
2
2
2
2
2
2
3
3
3
2
2
1
1
1
1
2
2
1
2
2
2
1
1
2
6
6
6
4
4
4
4
4
4
8
8
6
4
4
6
6
6
6
6
6
4
6
6
6
8
8
8
r ← byte
saddr, #byte
sfr, #byte
A, r
(saddr) ← byte
sfr ← byte
A ← r
Note 1
Note 1
r, A
r ← A
A, saddr
saddr, A
A, sfr
A ← (saddr)
(saddr) ← A
A ← sfr
sfr, A
sfr ← A
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
A ← (addr16)
(addr16) ← A
PSW ← byte
A ← PSW
PSW ← A
A ← (DE)
(DE) ← A
A ← (HL)
×
×
×
×
×
×
[DE], A
A, [HL]
[HL], A
(HL) ← A
A, [HL + byte]
[HL + byte], A
A, X
A ← (HL + byte)
(HL + byte) ← A
A ↔ X
XCH
Note 2
A, r
A ↔ r
A, saddr
A, sfr
A ↔ (saddr)
A ↔ sfr
A, [DE]
A ↔ (DE)
A ↔ (HL)
A ↔ (HL + byte)
A, [HL]
A, [HL + byte]
Notes 1. Except r = A.
2. Except r = A, X.
Remark One instruction clock cycle is equal to one CPU clock (fCPU) cycle selected by the processor clock control
register (PCC).
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CHAPTER 4 INSTRUCTION SET
Mnemonic
MOVW
Operand
Byte Clock
Operation
Flag
Z
AC CY
rp, #word
3
2
2
1
1
1
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
6
6
8
4
4
8
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
rp ← word
AX, saddrp
saddrp, AX
AX, rp
AX ← (saddrp)
(saddrp) ← AX
AX ← rp
Note
Note
Note
rp, AX
rp ← AX
XCHW
ADD
AX, rp
AX ↔ rp
A, #byte
saddr, #byte
A, r
A, CY ← A + byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
(saddr), CY ← (saddr) + byte
A, CY ← A + r
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr)
A, CY ← A + (addr16)
A, CY ← A + (HL)
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A, CY ← A + (HL + byte)
A, CY ← A + byte + CY
(saddr), CY ← (saddr) + byte + CY
A, CY ← A + r + CY
ADDC
A, saddr
A, !addr16
A, [HL]
A, CY ← A + (saddr) + CY
A, CY ← A + (addr16) + CY
A, CY ← A + (HL) + CY
A, CY ← A + (HL + byte) + CY
A, CY ← A – byte
A, [HL + byte]
A, #byte
saddr, #byte
A, r
SUB
(saddr), CY ← (saddr) – byte
A, CY ← A – r
A, saddr
A, !addr16
A, [HL]
A, CY ← A – (saddr)
A, CY ← A – (addr16)
A, CY ← A – (HL)
A, [HL + byte]
A, CY ← A – (HL + byte)
Note Only when rp = BC, DE, or HL.
Remark One instruction clock cycle is equal to one CPU clock (fCPU) cycle selected by the processor clock control
register (PCC).
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CHAPTER 4 INSTRUCTION SET
Mnemonic
Operand
Byte Clock
Operation
Flag
Z
AC CY
SUBC
A, #byte
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
2
3
2
2
3
1
2
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
4
6
4
4
8
6
6
A, CY ← A – byte – CY
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
saddr, #byte
A, r
(saddr), CY ← (saddr) – byte – CY
A, CY ← A – r – CY
A, CY ← A – (saddr) – CY
A, CY ← A – (addr16) – CY
A, CY ← A – (HL) – CY
A, CY ← A – (HL + byte) – CY
A ← A byte
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
×
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
AND
(saddr) ← (saddr) byte
A ← A r
A, saddr
A, !addr16
A, [HL]
A ← A (saddr)
A ← A (addr16)
A ← A (HL)
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A ← A (HL + byte)
A ← A byte
OR
(saddr) ← (saddr) byte
A ← A r
A, saddr
A, !addr16
A, [HL]
A ← A (saddr)
A ← A (addr16)
A ← A (HL)
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A ← A (HL + byte)
A ← A byte
XOR
(saddr) ← (saddr) byte
A ← A r
A, saddr
A, !addr16
A, [HL]
A ← A (saddr)
A ← A (addr16)
A ← A (HL)
A, [HL + byte]
A, #byte
saddr, #byte
A, r
A ← A (HL + byte)
A – byte
CMP
×
×
×
×
×
×
×
×
×
×
×
×
×
×
(saddr) – byte
A – r
A, saddr
A, !addr16
A, [HL]
A – (saddr)
A – (addr16)
A – (HL)
A, [HL + byte]
A – (HL + byte)
Remark One instruction clock cycle is equal to one CPU clock (fCPU) cycle selected by the processor clock control
register (PCC).
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CHAPTER 4 INSTRUCTION SET
Mnemonic
Operand
Byte Clock
Operation
Flag
Z
AC CY
ADDW
SUBW
CMPW
INC
AX, #word
3
3
3
2
2
2
2
1
1
1
1
1
1
3
3
2
3
2
3
3
2
3
2
1
1
1
6
6
6
4
4
4
4
4
4
2
2
2
2
6
6
4
6
10
6
6
4
6
10
2
2
2
AX, CY ← AX + word
AX, CY ← AX – word
AX – word
×
×
×
×
×
×
×
×
×
×
×
AX, #word
AX, #word
r
×
×
×
×
×
×
r ← r + 1
saddr
r
(saddr) ← (saddr) + 1
r ← r – 1
DEC
saddr
rp
(saddr) ← (saddr) – 1
rp ← rp + 1
INCW
DECW
ROR
rp
rp ← rp – 1
A, 1
(CY, A7 ← A0, Am–1 ← Am) × 1
(CY, A0 ← A7, Am+1 ← Am) × 1
(CY ← A0, A7 ← CY, Am–1 ← Am) × 1
(CY ← A7, A0 ← CY, Am+1 ← Am) × 1
(saddr.bit) ← 1
×
×
×
×
ROL
A, 1
RORC
ROLC
SET1
A, 1
A, 1
saddr.bit
sfr.bit
A.bit
sfr.bit ← 1
A.bit ← 1
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
PSW.bit ← 1
×
×
×
(HL).bit ← 1
CLR1
(saddr.bit) ← 0
sfr.bit ← 0
A.bit ← 0
PSW.bit
[HL].bit
CY
PSW.bit ← 0
×
×
×
(HL).bit ← 0
SET1
CLR1
NOT1
CY ← 1
1
0
×
CY
CY ← 0
_____
CY
CY ← CY
CALL
!addr16
[addr5]
3
1
6
8
(SP – 1) ← (PC + 3)H, (SP – 2) ← (PC + 3)L,
PC ← addr16, SP ← SP – 2
CALLT
(SP – 1) ← (PC + 1)H, (SP – 2) ← (PC + 1)L,
PCH ← (00000000, addr5 + 1),
PCL ← (00000000, addr5), SP ← SP – 2
Remark One instruction clock cycle is equal to one CPU clock (fCPU) cycle selected by the processor clock control
register (PCC).
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CHAPTER 4 INSTRUCTION SET
Mnemonic
Operand
Byte Clock
Operation
Flag
Z
AC CY
RET
1
1
6
8
PCH ← (SP + 1), PCL ← (SP), SP ← SP + 2
RETI
PCH ← (SP + 1), PCL ← (SP),
R
R
R
R
PSW ← (SP + 2), SP ← SP + 3, NMIS ← 0
PUSH
PSW
1
1
1
1
2
2
3
2
1
2
2
2
2
4
4
3
4
4
4
3
4
2
2
3
2
4
(SP – 1) ← PSW, SP ← SP – 1
(SP – 1) ← rpH, (SP – 2) ← rpL, SP ← SP – 2
PSW ← (SP), SP ← SP + 1
rp
POP
MOVW
BR
PSW
4
R
R
rp
6
rpH ← (SP + 1), rpL ← (SP), SP ← SP + 2
SP ← AX
SP,AX
AX,SP
!addr16
$addr16
AX
8
6
AX ← SP
6
PC ← addr16
6
PC ← PC + 2 + jdisp8
6
PCH ← A, PCL ← X
BC
$addr16
$addr16
$addr16
$addr16
6
PC ← PC + 2 + jdisp8 if CY = 1
PC ← PC + 2 + jdisp8 if CY = 0
PC ← PC + 2 + jdisp8 if Z = 1
PC ← PC + 2 + jdisp8 if Z = 0
PC ← PC + 4 + jdisp8 if (saddr.bit) = 1
PC ← PC + 4 + jdisp8 if sfr.bit = 1
PC ← PC + 3 + jdisp8 if A.bit = 1
PC ← PC + 4 + jdisp8 if PSW.bit = 1
PC ← PC + 4 + jdisp8 if (saddr.bit) = 0
PC ← PC + 4 + jdisp8 if sfr.bit = 0
PC ← PC + 3 + jdisp8 if A.bit = 0
PC ← PC + 4 + jdisp8 if PSW.bit = 0
B ← B – 1, then PC ← PC + 2 + jdisp8 if B ≠ 0
C ← C – 1, then PC ← PC + 2 + jdisp8 if C ≠ 0
BNC
BZ
6
6
BNZ
BT
6
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
10
10
8
10
10
10
8
BF
10
6
DBNZ
C, $addr16
6
saddr, $addr16
8
(saddr) ← (saddr) – 1, then
PC ← PC + 3 + jdisp8 if (saddr) ≠ 0
NOP
EI
1
3
3
1
1
2
6
6
2
2
No Operation
IE ← 1 (Enable Interrupt)
IE ← 0 (Disable Interrupt)
Set HALT Mode
DI
HALT
STOP
Set STOP Mode
Remark One instruction clock cycle is equal to one CPU clock (fCPU) cycle selected by the processor clock control
register (PCC).
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CHAPTER 4 INSTRUCTION SET
4.1.6 Instruction list by addressing
(1) 8-bit instructions
MOV, XCH, ADD, ADDC, SUB, SUBC, AND, OR, XOR, CMP, INC, DEC, ROR, ROL, RORC, ROLC, PUSH,
POP, DBNZ
2nd operand
1st operand
A
r
sfr
PSW
[DE]
[HL]
1
None
#byte
saddr !addr16
$addr16
[HL + byte]
A
ADD
ADDC
SUB
SUBC
AND
OR
MOVNote MOV MOV MOV
MOV MOV MOV MOV
ROR
XCHNote XCH
XCH
ADD
XCH
XCH
ADD
XCH
ADD
ROL
ADD
ADD
RORC
ROLC
ADDC
SUB
ADDC ADDC
SUB SUB
SUBC SUBC
ADDC ADDC
SUB SUB
SUBC SUBC
SUBC
AND
XOR
CMP
AND
OR
AND
OR
AND
OR
AND
OR
OR
XOR
XOR
CMP
XOR
CMP
XOR
CMP
XOR
CMP
CMP
r
MOV MOVNote
INC
DEC
B, C
sfr
DBNZ
DBNZ
MOV MOV
saddr
MOV MOV
ADD
INC
DEC
ADDC
SUB
SUBC
AND
OR
XOR
CMP
!addr16
PSW
MOV
MOV MOV
PUSH
POP
[DE]
MOV
MOV
MOV
[HL]
[HL + byte]
Note Except r = A.
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CHAPTER 4 INSTRUCTION SET
(2) 16-bit instructions
MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW
2nd operand
1st operand
#word
AX
rpNote
saddrp
SP
None
AX
ADDW
MOVW
XCHW
MOVW
MOVW
SUBW
CMPW
rp
MOVW
MOVWNote
INCW
DECW
PUSH
POP
saddrp
SP
MOVW
MOVW
Note Only when rp = BC, DE, HL.
(3) Bit manipulation instructions
SET1, CLR1, NOT1, BT, BF
2nd operand
1st operand
$saddr
None
A.bit
BT
BF
SET1
CLR1
sfr.bit
BT
BF
SET1
CLR1
saddr.bit
PSW.bit
[HL].bit
CY
BT
BF
SET1
CLR1
BT
BF
SET1
CLR1
SET1
CLR1
SET1
CLR1
NOT1
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CHAPTER 4 INSTRUCTION SET
(4) Call instructions/branch instructions
CALL, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, DBNZ
2nd operand
AX
!addr16
[addr5]
$addr16
1st operand
Basic instructions
BR
CALL
BR
CALLT
BR
BC
BNC
BZ
BNZ
Compound instructions
DBNZ
(5) Other instructions
RET, RETI, NOP, EI, DI, HALT, STOP
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CHAPTER 4 INSTRUCTION SET
4.2 Instruction Codes
4.2.1 Description of instruction code table
r
rp
P1
R2
R1
R0
reg
R0
P0
reg-pair
0
0
0
0
1
1
1
1
0
0
X
A
C
B
E
D
L
0
0
1
1
0
1
0
1
RP0
RP1
RP2
RP3
AX
0
1
1
0
0
1
1
1
0
1
0
1
0
1
R1
R2
R3
R4
R5
R6
R7
BC
DE
HL
H
Bn:
Data:
Low/High byte: 16-bit immediate data corresponding to “word”
Saddr-offset: 16-bit address lower 8-bit offset data corresponding to “saddr”
Sfr-offset: sfr 16-bit address lower 8-bit offset data
Low/High addr: 16-bit immediate data corresponding to “addr16”
Immediate data corresponding to “bit”
8-bit immediate data corresponding to “byte”
jdisp:
Signed two's complement data (8 bits) of relative address distance between the start and branch
addresses of the next instruction
ta4 to 0
:
5 bits of immediate data corresponding to “addr5”
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CHAPTER 4 INSTRUCTION SET
4.2.2 Instruction code list
Mnemonic
MOV
Operand
Instruction Code
B1
B2
B3
B4
r, #byte
0 0 0 0 1 0 1 0 1 1 1 1 R2 R1 R0 1
Data
Data
Data
saddr, #byte
sfr, #byte
A, r
1 1 1 1 0 1 0 1
1 1 1 1 0 1 1 1
Saddr-offset
Sfr-offset
Note 1
Note 1
0 0 0 0 1 0 1 0 0 0 1 0 R2 R1 R0 1
0 0 0 0 1 0 1 0 1 1 1 0 R2 R1 R0 1
r, A
A, saddr
saddr, A
A, sfr
0 0 1 0 0 1 0 1
1 1 1 0 0 1 0 1
0 0 1 0 0 1 1 1
1 1 1 0 0 1 1 1
0 0 1 0 1 0 0 1
1 1 1 0 1 0 0 1
Saddr-offset
Saddr-offset
Sfr-offset
sfr, A
Sfr-offset
A, !addr16
!addr16, A
PSW, #byte
A, PSW
PSW, A
A, [DE]
Low addr
High addr
High addr
Data
Low addr
1 1 1 1 0 1 0 1 0 0 0 1 1 1 1 0
0 0 1 0 0 1 0 1 0 0 0 1 1 1 1 0
1 1 1 0 0 1 0 1 0 0 0 1 1 1 1 0
0 0 1 0 1 0 1 1
[DE], A
1 1 1 0 1 0 1 1
A, [HL]
0 0 1 0 1 1 1 1
[HL], A
1 1 1 0 1 1 1 1
A, [HL + byte]
[HL + byte], A
A, X
0 0 1 0 1 1 0 1
1 1 1 0 1 1 0 1
1 1 0 0 0 0 0 0
Data
Data
XCH
Note 2
A, r
0 0 0 0 1 0 1 0 0 0 0 0 R2 R1 R0 1
A, saddr
A, sfr
0 0 0 0 0 1 0 1
0 0 0 0 0 1 1 1
0 0 0 0 1 0 1 1
0 0 0 0 1 1 1 1
0 0 0 0 1 1 0 1
1 1 1 1 P1 P0 0 0
1 1 0 1 0 1 1 0
1 1 1 0 0 1 1 0
1 1 0 1 P1 P0 0 0
1 1 1 0 P1 P0 0 0
1 1 0 0 P1 P0 0 0
Saddr-offset
Sfr-offset
A, [DE]
A, [HL]
A, [HL + byte]
rp, #word
AX, saddrp
saddrp, AX
AX, rp
Data
MOVW
Low byte
High byte
Saddr-offset
Saddr-offset
Note 3
Note 3
Note 3
rp, AX
XCHW
AX, rp
Notes 1. Except r = A.
2. Except r = A, X.
3. Only when rp = BC, DE, or HL.
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CHAPTER 4 INSTRUCTION SET
Mnemonic
ADD
Operand
Instruction Code
B1
B2
Data
B3
B4
A, #byte
1 0 0 0 0 0 1 1
1 0 0 0 0 0 0 1
saddr, #byte
A, r
Saddr-offset
Data
0 0 0 0 1 0 1 0 1 0 0 0 R2 R1 R0 1
A, saddr
A, !addr16
A, [HL]
1 0 0 0 0 1 0 1
1 0 0 0 1 0 0 1
1 0 0 0 1 1 1 1
1 0 0 0 1 1 0 1
1 0 1 0 0 0 1 1
1 0 1 0 0 0 0 1
Saddr-offset
Low addr
High addr
A, [HL + byte]
A, #byte
saddr, #byte
A, r
Data
Data
ADDC
Saddr-offset
Data
0 0 0 0 1 0 1 0 1 0 1 0 R2 R1 R0 1
A, saddr
A, !addr16
A, [HL]
1 0 1 0 0 1 0 1
1 0 1 0 1 0 0 1
1 0 1 0 1 1 1 1
1 0 1 0 1 1 0 1
1 0 0 1 0 0 1 1
1 0 0 1 0 0 0 1
Saddr-offset
Low addr
High addr
A, [HL + byte]
A, #byte
saddr, #byte
A, r
Data
Data
SUB
Saddr-offset
Data
0 0 0 0 1 0 1 0 1 0 0 1 R2 R1 R0 1
A, saddr
A, !addr16
A, [HL]
1 0 0 1 0 1 0 1
1 0 0 1 1 0 0 1
1 0 0 1 1 1 1 1
1 0 0 1 1 1 0 1
1 0 1 1 0 0 1 1
1 0 1 1 0 0 0 1
Saddr-offset
Low addr
High addr
A, [HL + byte]
A, #byte
saddr, #byte
A, r
Data
Data
SUBC
Saddr-offset
Data
0 0 0 0 1 0 1 0 1 0 1 1 R2 R1 R0 1
A, saddr
A, !addr16
A, [HL]
1 0 1 1 0 1 0 1
1 0 1 1 1 0 0 1
1 0 1 1 1 1 1 1
1 0 1 1 1 1 0 1
0 1 1 0 0 0 1 1
0 1 1 0 0 0 0 1
Saddr-offset
Low addr
High addr
A, [HL + byte]
A, #byte
saddr, #byte
A, r
Data
Data
AND
Saddr-offset
Data
0 0 0 0 1 0 1 0 0 1 1 0 R2 R1 R0 1
A, saddr
A, !addr16
A, [HL]
0 1 1 0 0 1 0 1
0 1 1 0 1 0 0 1
0 1 1 0 1 1 1 1
0 1 1 0 1 1 0 1
Saddr-offset
Low addr
High addr
A, [HL + byte]
Data
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CHAPTER 4 INSTRUCTION SET
Mnemonic
OR
Operand
Instruction Code
B1
B2
Data
B3
B4
A, #byte
0 1 1 1 0 0 1 1
0 1 1 1 0 0 0 1
saddr, #byte
A, r
Saddr-offset
Data
0 0 0 0 1 0 1 0 0 1 1 1 R2 R1 R0 1
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
0 1 1 1 0 1 0 1
0 1 1 1 1 0 0 1
0 1 1 1 1 1 1 1
0 1 1 1 1 1 0 1
0 1 0 0 0 0 1 1
0 1 0 0 0 0 0 1
Saddr-offset
Low addr
High addr
Data
Data
XOR
Saddr-offset
Data
0 0 0 0 1 0 1 0 0 1 0 0 R2 R1 R0 1
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
A, #byte
saddr, #byte
A, r
0 1 0 0 0 1 0 1
0 1 0 0 1 0 0 1
0 1 0 0 1 1 1 1
0 1 0 0 1 1 0 1
0 0 0 1 0 0 1 1
0 0 0 1 0 0 0 1
Saddr-offset
Low addr
High addr
Data
Data
CMP
Saddr-offset
Data
0 0 0 0 1 0 1 0 0 0 0 1 R2 R1 R0 1
A, saddr
A, !addr16
A, [HL]
A, [HL + byte]
AX, #word
AX, #word
AX, #word
r
0 0 0 1 0 1 0 1
0 0 0 1 1 0 0 1
0 0 0 1 1 1 1 1
0 0 0 1 1 1 0 1
1 1 0 1 0 0 1 0
1 1 0 0 0 0 1 0
1 1 1 0 0 0 1 0
Saddr-offset
Low addr
High addr
Data
ADDW
SUBW
CMPW
INC
Low byte
Low byte
Low byte
High byte
High byte
High byte
0 0 0 0 1 0 1 0 1 1 0 0 R2 R1 R0 1
1 1 0 0 0 1 0 1 Saddr-offset
0 0 0 0 1 0 1 0 1 1 0 1 R2 R1 R0 1
saddr
DEC
r
saddr
1 1 0 1 0 1 0 1
1 0 0 0 P1 P0 0 0
1 0 0 1 P1 P0 0 0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0
0 0 0 0 0 0 1 0
0 0 0 1 0 0 1 0
Saddr-offset
INCW
DECW
ROR
rp
rp
A, 1
ROL
A, 1
RORC
ROLC
A, 1
A, 1
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CHAPTER 4 INSTRUCTION SET
Mnemonic
SET1
Operand
Instruction Code
B1
B2
B3
B4
saddr.bit
0 0 0 0 1 0 1 0 0 B2 B1 B0 1 0 1 0
0 0 0 0 1 0 1 0 0 B2 B1 B0 0 1 1 0
0 0 0 0 1 0 1 0 0 B2 B1 B0 0 0 1 0
Saddr-offset
Sfr-offset
sfr.bit
A.bit
PSW.bit
[HL].bit
saddr.bit
sfr.bit
A.bit
0 0 0 0 1 0 1 0 0 B2 B1 B0 1 0 1 0 0 0 0 1 1 1 1 0
0 0 0 0 1 0 1 0 0 B2 B1 B0 1 1 1 0
CLR1
0 0 0 0 1 0 1 0 1 B2 B1 B0 1 0 1 0
0 0 0 0 1 0 1 0 1 B2 B1 B0 0 1 1 0
0 0 0 0 1 0 1 0 1 B2 B1 B0 0 0 1 0
Saddr-offset
Sfr-offset
PSW.bit
[HL].bit
CY
0 0 0 0 1 0 1 0 1 B2 B1 B0 1 0 1 0 0 0 0 1 1 1 1 0
0 0 0 0 1 0 1 0 1 B2 B1 B0 1 1 1 0
0 0 0 1 0 1 0 0
SET1
CLR1
NOT1
CALL
CALLT
RET
CY
0 0 0 0 0 1 0 0
CY
0 0 0 0 0 1 1 0
!addr16
[addr5]
0 0 1 0 0 0 1 0
0 1 ta4 to 0
Low addr
High addr
0
0 0 1 0 0 0 0 0
0 0 1 0 0 1 0 0
0 0 1 0 1 1 1 0
1 0 1 0 P1 P0 1 0
0 0 1 0 1 1 0 0
1 0 1 0 P1 P0 0 0
RETI
PUSH
PSW
rp
POP
MOVW
BR
PSW
rp
SP, AX
1 1 1 0 0 1 1 0 0 0 0 1 1 1 0 0
1 1 0 1 0 1 1 0 0 0 0 1 1 1 0 0
AX, SP
!addr16
1 0 1 1 0 0 1 0
0 0 1 1 0 0 0 0
1 0 1 1 0 0 0 0
0 0 1 1 1 0 0 0
0 0 1 1 1 0 1 0
0 0 1 1 1 1 0 0
0 0 1 1 1 1 1 0
Low addr
jdisp
High addr
$addr16
AX
BC
$addr16
$addr16
$addr16
$addr16
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
jdisp
jdisp
jdisp
jdisp
BNC
BZ
BNZ
BT
0 0 0 0 1 0 1 0 1 B2 B1 B0 1 0 0 0
0 0 0 0 1 0 1 0 1 B2 B1 B0 0 1 0 0
0 0 0 0 1 0 1 0 1 B2 B1 B0 0 0 0 0
Saddr-offset
Sfr-offset
jdisp
jdisp
jdisp
0 0 0 0 1 0 1 0 1 B2 B1 B0 1 0 0 0 0 0 0 1 1 1 1 0
jdisp
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CHAPTER 4 INSTRUCTION SET
Mnemonic
BF
Operand
Instruction Code
B1
B2
B3
B4
saddr.bit, $addr16
sfr.bit, $addr16
A.bit, $addr16
PSW.bit, $addr16
B, $addr16
0 0 0 0 1 0 1 0 0 B2 B1 B0 1 0 0 0
0 0 0 0 1 0 1 0 0 B2 B1 B0 0 1 0 0
0 0 0 0 1 0 1 0 0 B2 B1 B0 0 0 0 0
Saddr-offset
Sfr-offset
jdisp
jdisp
jdisp
0 0 0 0 1 0 1 0 0 B2 B1 B0 1 0 0 0 0 0 0 1 1 1 1 0
jdisp
DBNZ
0 0 1 1 0 1 1 0
0 0 1 1 0 1 0 0
0 0 1 1 0 0 1 0
0 0 0 0 1 0 0 0
jdisp
jdisp
C, $addr16
saddr, $addr16
Saddr-offset
jdisp
NOP
EI
0 0 0 0 1 0 1 0 0 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0
0 0 0 0 1 0 1 0 1 1 1 1 1 0 1 0 0 0 0 1 1 1 1 0
0 0 0 0 1 1 0 0
DI
HALT
STOP
0 0 0 0 1 1 1 0
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
This chapter explains the instructions of 78K/0S Series. Each instruction is described in the unit of mnemonic,
including description of multiple operands.
The basic configuration of instruction descriptions is shown on the next page.
For the number of instruction bytes and operation codes, refer to CHAPTER 4 INSTRUCTION SET.
All the instructions are common to 78K/0S Series products.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
DESCRIPTION EXAMPLE
Mnemonic
Full name
Move
Byte Data Transfer
MOV
Meaning of instruction
[Instruction format]
[Operation]
MOV dst, src: Indicates the basic description format of the instruction.
dst ← src: Indicates instruction operation using symbols.
[Operand]
Indicates operands that can be specified with this instruction. Refer to 4.1 Operation
for a description of each operand symbol.
Mnemonic
MOV
Operand (dst, src)
r, #byte
Mnemonic
MOV
Operand (dst, src)
A, PSW
A, saddr
[HL], A
saddr, A
A, [HL + byte]
[HL + C], A
PSW, #byte
[Flag]
Indicates the operation of the flag that changes by instruction execution.
Each flag operation symbol is shown in the legend.
Z
AC
CY
Legend
Symbol
Description
Blank
Unchanged
Cleared to 0
Set to 1
0
1
×
R
Set or cleared according to the result
Previously saved value is restored
[Description] Describes the instruction operation in detail.
•
The contents of the source operand (src) specified by the 2nd operand are transferred to the destination
operand (dst) specified by the 1st operand.
[Description example]
MOV A, #4DH; 4DH is transferred to A register.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
5.1 8-Bit Data Transfer Instructions
The following instructions are 8-bit data transfer instructions.
MOV ... 60
XCH ... 61
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Move
MOV
Byte Data Transfer
[Instruction format]
[Operation]
MOV dst, src
dst ← src
[Operand]
Mnemonic
MOV
Operand (dst, src)
Mnemonic
MOV
Operand (dst, src)
!addr16, A
r, #byte
saddr, #byte
sfr, #byte
A, r
PSW, #byte
A, PSW
Note
Note
PSW, A
r, A
A, [DE]
A, saddr
saddr, A
A, sfr
[DE], A
A, [HL]
[HL], A
sfr, A
A, [HL + byte]
[HL + byte], A
A, !addr16
Note Except r = A
[Flag]
PSW, #byte and PSW, A
operands
All other operand
combinations
Z
AC
CY
Z
AC
CY
×
×
×
[Description]
•
The contents of the source operand (src) specified by the 2nd operand are transferred to the destination
operand (dst) specified by the 1st operand.
•
No interrupts are acknowledged between the “MOV PSW, #byte” instruction or the “MOV PSW, A” instruction
and the subsequent instruction.
[Description example]
MOV A, #4DH; 4DH is transferred to A register.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Exchange
XCH
Byte Data Exchange
[Instruction format]
[Operation]
XCH dst, src
dst ↔ src
[Operand]
Mnemonic
XCH
Operand (dst, src)
A, X
A, r
Note
A, saddr
A, sfr
A, [DE]
A, [HL]
A, [HL + byte]
Note Except r = A, X
[Flag]
Z
AC
CY
[Description]
The 1st and 2nd operand contents are exchanged.
•
[Description example]
XCH A, 0FEBCH; The A register contents and address FEBCH contents are exchanged.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
5.2 16-Bit Data Transfer Instructions
The following instructions are 16-bit data transfer instructions.
MOVW ... 63
XCHW ... 64
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Move Word
MOVW
Word Data Transfer
[Instruction format]
[Operation]
MOVW dst, src
dst ← src
[Operand]
Mnemonic
MOVW
Operand (dst, src)
rp, #word
AX, saddrp
saddrp, AX
AX, rp
Note
Note
rp, AX
Note Only when rp = BC, DE or HL
[Flag]
Z
AC
CY
[Description]
•
The contents of the source operand (src) specified by the 2nd operand are transferred to the destination
operand (dst) specified by the 1st operand.
[Description example]
MOVW AX, HL; The HL register contents are transferred to the AX register.
[Caution]
Only an even address can be specified to saddrp. An odd address cannot be specified.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Exchange Word
XCHW
Word Data Exchange
[Instruction format]
[Operation]
XCHW dst, src
dst ↔ src
[Operand]
Mnemonic
XCHW
Operand (dst, src)
Note
AX, rp
Note Only when rp = BC, DE or HL
[Flag]
Z
AC
CY
[Description]
The 1st and 2nd operand contents are exchanged.
•
[Description example]
XCHW AX, BC; The memory contents of AX register are exchanged with those of the BC register.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
5.3 8-Bit Operation Instructions
The following are 8-bit operation instructions.
ADD ... 66
ADDC ... 67
SUB ... 68
SUBC ... 69
AND ... 70
OR ... 71
XOR ... 72
CMP ... 73
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Add
ADD
Byte Data Addition
[Instruction format]
[Operation]
ADD dst, src
dst, CY ← dst + src
[Operand]
Mnemonic
ADD
Operand (dst, src)
Mnemonic
ADD
Operand (dst, src)
A, !addr16
A, #byte
saddr, #byte
A, r
A, [HL]
A, [HL + byte]
A, saddr
[Flag]
Z
AC
CY
×
×
×
[Description]
•
The destination operand (dst) specified with the 1st operand is added to the source operand (src) specified
with the 2nd operand and the result is stored in the CY flag and the destination operand (dst).
If the addition result shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
If the addition generates a carry from bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared (0).
If the addition generates a carry from bit 3 to bit 4, the AC flag is set (1). In all other cases, the AC flag is
cleared (0).
•
•
•
[Description example]
ADD CR10, #56H; 56H is added to the CR10 register and the result is stored in the CR10 register.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Add with Carry
ADDC
Addition of Byte Data with Carry
[Instruction format]
[Operation]
ADDC dst, src
dst, CY ← dst + src + CY
[Operand]
Mnemonic
ADDC
Operand (dst, src)
Mnemonic
ADDC
Operand (dst, src)
A, !addr16
A, #byte
saddr, #byte
A, r
A, [HL]
A, [HL + byte]
A, saddr
[Flag]
Z
AC
CY
×
×
×
[Description]
•
The destination operand (dst) specified with the 1st operand, the source operand (src) specified with the 2nd
operand, and the CY flag are added and the result is stored in the destination operand (dst) and the CY flag.
The CY flag is added to the least significant bit. This instruction is mainly used to add two or more bytes.
If the addition result shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
If the addition generates a carry from bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared (0).
If the addition generates a carry from bit 3 to bit 4, the AC flag is set (1). In all other cases, the AC flag is
cleared (0).
•
•
•
[Description example]
ADDC A, [HL]; The A register contents, the contents at address (HL register), and the CY flag are added and
the result is stored in the A register.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Subtract
SUB
Byte Data Subtraction
[Instruction format]
[Operation]
SUB dst, src
dst, CY ← dst – src
[Operand]
Mnemonic
SUB
Operand (dst, src)
Mnemonic
SUB
Operand (dst, src)
A, !addr16
A, #byte
saddr, #byte
A, r
A, [HL]
A, [HL + byte]
A, saddr
[Flag]
Z
AC
CY
×
×
×
[Description]
•
The source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst)
specified with the 1st operand and the result is stored in the destination operand (dst) and the CY flag.
The destination operand can be cleared to 0 by equalizing the source operand (src) and the destination
operand (dst).
•
•
If the subtraction shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
If the subtraction generates a borrow at bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared
(0).
•
If the subtraction generates a borrow from bit 4 to bit 3, the AC flag is set (1). In all other cases, the AC flag
is cleared (0).
[Description example]
SUB A, D; The D register is subtracted from the A register and the result is stored in the A register.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Subtract with Carry
SUBC
Subtraction of Byte Data with Carry
[Instruction format]
[Operation]
SUBC dst, src
dst, CY ← dst – src – CY
[Operand]
Mnemonic
SUBC
Operand (dst, src)
Mnemonic
SUBC
Operand (dst, src)
A, !addr16
A, #byte
saddr, #byte
A, r
A, [HL]
A, [HL + byte]
A, saddr
[Flag]
Z
AC
CY
×
×
×
[Description]
•
The source operand (src) specified with the 2nd operand and the CY flag are subtracted from the destination
operand (dst) specified with the 1st operand and the result is stored in the destination operand (dst).
The CY flag is subtracted from the least significant bit. This instruction is mainly used for subtraction of two
or more bytes.
•
•
If the subtraction shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
If the subtraction generates a borrow at bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared
(0).
•
If the subtraction generates a borrow from bit 4 to bit 3, the AC flag is set (1). In all other cases, the AC flag
is cleared (0).
[Description example]
SUBC A, [HL]; The (HL register) address contents and the CY flag are subtracted from the A register and the
result is stored in the A register.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
And
AND
Logical Product of Byte Data
[Instruction format]
[Operation]
AND dst, src
dst ← dst src
[Operand]
Mnemonic
AND
Operand (dst, src)
Mnemonic
AND
Operand (dst, src)
A, #byte
A, !addr16
saddr, #byte
A, r
A, [HL]
A, [HL + byte]
A, saddr
[Flag]
Z
AC
CY
×
[Description]
•
The destination operand (dst) specified with the 1st operand and the source operand (src) specified with the
2nd operand are ANDed bit wise, and the result is stored in the destination operand (dst).
•
If the logical product shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
[Description example]
AND 0FEBAH, #11011100B; The FEBAH contents and 11011100B are ANDed bit wise and the result is stored
at FEBAH.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Or
OR
Logical Sum of Byte Data
[Instruction format]
[Operation]
OR dst, src
dst ← dst src
[Operand]
Mnemonic
OR
Operand (dst, src)
Mnemonic
OR
Operand (dst, src)
A, #byte
A, !addr16
saddr, #byte
A, r
A, [HL]
A, [HL + byte]
A, saddr
[Flag]
Z
AC
CY
×
[Description]
•
The destination operand (dst) specified with the 1st operand and the source operand (src) specified with the
2nd operand are ORed bit wise, and the result is stored in the destination operand (dst).
•
If the logical sum shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
[Description example]
OR A, 0FE98H; The A register and FE98H are ORed bit wise and the result is stored in the A register.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Exclusive Or
XOR
Exclusive Logical Sum of Byte Data
[Instruction format]
[Operation]
XOR dst, src
dst ← dst src
[Operand]
Mnemonic
XOR
Operand (dst, src)
Mnemonic
XOR
Operand (dst, src)
A, !addr16
A, #byte
saddr, #byte
A, r
A, [HL]
A, [HL + byte]
A, saddr
[Flag]
Z
AC
CY
×
[Description]
•
The destination operand (dst) specified with the 1st operand and the source operand (src) specified with the
2nd operand are XORed bit wise, and the result is stored in the destination operand (dst).
Logical negation of all bits of the destination operand (dst) is possible with this instruction by selecting #0FFH
for the source operand (src).
•
If the exclusive logical sum shows that all bits are 0, the Z flag is set (1). In all other cases, the Z flag is
cleared (0).
[Description example]
XOR A, L; The A and L registers are XORed bit wise and the result is stored in the A register.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Compare
CMP
Byte Data Comparison
[Instruction format]
[Operation]
CMP dst, src
dst – src
[Operand]
Mnemonic
CMP
Operand (dst, src)
Mnemonic
CMP
Operand (dst, src)
A, #byte
A, !addr16
A, [HL]
A, [HL + byte]
saddr, #byte
A, r
A, saddr
[Flag]
Z
AC
CY
×
×
×
[Description]
•
The source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst)
specified with the 1st operand.
The subtraction result is not stored anywhere and only the Z, AC, and CY flags are changed.
If the subtraction result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
If the subtraction generates a borrow at bit 7, the CY flag is set (1). In all other cases, the CY flag is cleared
(0).
•
•
•
If the subtraction generates a borrow from bit 4 to bit 3, the AC flag is set (1). In all other cases, the AC flag
is cleared (0).
[Description example]
CMP 0FE38H, #38H; 38H is subtracted from the contents at address FE38H and only the Z, AC, and CY flags
are changed (comparison of contents at address FE38H and the immediate data).
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
5.4 16-Bit Operation Instructions
The following are 16-bit operation instructions.
ADDW ... 75
SUBW ... 76
CMPW ... 77
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Add Word
ADDW
Word Data Addition
[Instruction format]
[Operation]
ADDW dst, src
dst, CY ← dst + src
[Operand]
Mnemonic
ADDW
Operand (dst, src)
AX, #word
[Flag]
Z
AC
CY
×
×
×
[Description]
•
The destination operand (dst) specified with the 1st operand is added to the source operand (src) specified
with the 2nd operand and the result is stored in the destination operand (dst).
If the addition result shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
If the addition generates a carry from bit 15, the CY flag is set (1). In all other cases, the CY flag is cleared
(0).
•
•
•
As a result of addition, the AC flag becomes undefined.
[Description example]
ADDW AX, #0ABCDH; ABCDH is added to the AX register and the result is stored in the AX register.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Subtract Word
SUBW
Word Data Subtraction
[Instruction format]
[Operation]
SUBW dst, src
dst, CY ← dst – src
[Operand]
Mnemonic
SUBW
Operand (dst, src)
AX, #word
[Flag]
Z
AC
CY
×
×
×
[Description]
•
The source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst)
specified with the 1st operand and the result is stored in the destination operand (dst) and the CY flag.
The destination operand can be cleared to 0 by equalizing the source operand (src) and the destination
operand (dst).
•
•
If the subtraction shows that dst is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
If the subtraction generates a borrow at bit 15, the CY flag is set (1). In all other cases, the CY flag is cleared
(0).
•
As a result of subtraction, the AC flag becomes undefined.
[Description example]
SUBW AX, #0ABCDH; ABCDH is subtracted from the AX register contents and the result is stored in the AX
register.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Compare Word
CMPW
Word Data Comparison
[Instruction format]
[Operation]
CMPW dst, src
dst – src
[Operand]
Mnemonic
CMPW
Operand (dst, src)
AX, #word
[Flag]
Z
AC
CY
×
×
×
[Description]
•
The source operand (src) specified with the 2nd operand is subtracted from the destination operand (dst)
specified with the 1st operand.
The subtraction result is not stored anywhere and only the Z, AC, and CY flags are changed.
If the subtraction result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
If the subtraction generates a borrow at bit 15, the CY flag is set (1). In all other cases, the CY flag is cleared
(0).
•
•
•
As a result of subtraction, the AC flag becomes undefined.
[Description example]
CMPW AX, #0ABCDH; ABCDH is subtracted from the AX register and only the Z, AC, and CY flags are
changed (comparison of the AX register and the immediate data).
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
5.5 Increment/Decrement Instructions
The following are increment/decrement instructions.
INC ... 79
DEC ... 80
INCW ... 81
DECW ... 82
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Increment
INC
Byte Data Increment
[Instruction format]
[Operation]
INC dst
dst ← dst + 1
[Operand]
Mnemonic
INC
Operand (dst)
r
saddr
[Flag]
Z
AC
CY
×
×
[Description]
•
•
•
The destination operand (dst) contents are incremented by only one.
If the increment result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
If the increment generates a carry from bit 3 to bit 4, the AC flag is set (1). In all other cases, the AC flag is
cleared (0).
•
Because this instruction is frequently used for a counter for repeated operations, the CY flag contents are not
changed (to hold the CY flag contents in multiple-byte operation).
[Description example]
INC B; The B register is incremented.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Decrement
DEC
Byte Data Decrement
[Instruction format]
[Operation]
DEC dst
dst ← dst – 1
[Operand]
Mnemonic
DEC
Operand (dst)
r
saddr
[Flag]
Z
AC
CY
×
×
[Description]
•
•
•
The destination operand (dst) contents are decremented by only one.
If the decrement result is 0, the Z flag is set (1). In all other cases, the Z flag is cleared (0).
If the decrement generates a carry from bit 4 to bit 3, the AC flag is set (1). In all other cases, the AC flag is
cleared (0).
•
•
Because this instruction is frequently used for a counter for repeated operations, the CY flag contents are
not changed (to hold the CY flag contents in multiple-byte operation).
If dst is the B or C register or saddr, and it is not desired to change the AC and CY flag contents, the DBNZ
instruction can be used.
[Description example]
DEC 0FE92H ; The contents at address FE92H are decremented.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Increment Word
INCW
Word Data Increment
[Instruction format]
[Operation]
INCW dst
dst ← dst + 1
[Operand]
Mnemonic
INCW
Operand (dst)
rp
[Flag]
Z
AC
CY
[Description]
•
•
The destination operand (dst) contents are incremented by only one.
Because this instruction is frequently used for increment of a register (pointer) used for addressing, the Z, AC,
and CY flag contents are not changed.
[Description example]
INCW HL ; The HL register is incremented.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Decrement Word
DECW
Word Data Decrement
[Instruction format]
[Operation]
DECW dst
dst ← dst – 1
[Operand]
Mnemonic
DECW
Operand (dst)
rp
[Flag]
Z
AC
CY
[Description]
•
•
The destination operand (dst) contents are decremented by only one.
Because this instruction is frequently used for decrement of a register (pointer) used for addressing, the Z,
AC, and CY flag contents are not changed.
[Description example]
DECW DE ; The DE register is decremented.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
5.6 Rotate Instructions
The following are rotate instructions.
ROR ... 84
ROL ... 85
RORC ... 86
ROLC ... 87
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Rotate Right
ROR
Byte Data Rotation to the Right
[Instruction format]
[Operation]
ROR dst, cnt
(CY, dst7 ← dst0, dstm–1 ← dstm) × one time
[Operand]
Mnemonic
ROR
Operand (dst, cnt)
A, 1
[Flag]
Z
AC
CY
×
[Description]
•
•
The destination operand (dst) contents specified with the 1st operand are rotated to the right just once.
The LSB (bit 0) contents are simultaneously rotated to MSB (bit 7) and transferred to the CY flag.
CY
7
0
[Description example]
ROR A, 1; The A register contents are rotated one bit to the right.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Rotate Left
ROL
Byte Data Rotation to the Left
[Instruction format]
[Operation]
ROL dst, cnt
(CY, dst0 ← 0dst7, dstm+1 ← dstm) × one time
[Operand]
Mnemonic
ROL
Operand (dst, cnt)
A, 1
[Flag]
Z
AC
CY
×
[Description]
•
•
The destination operand (dst) contents specified with the 1st operand are rotated to the left just once.
The MSB (bit 7) contents are simultaneously rotated to LSB (bit 0) and transferred to the CY flag.
CY
7
0
[Description example]
ROL A, 1; The A register contents are rotated to the left by one bit.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Rotate Right with Carry
Byte Data Rotation to the Right with Carry
RORC
[Instruction format]
[Operation]
RORC dst, cnt
(CY ← dst0, dst7 ← CY, dstm–1 ← dstm) × one time
[Operand]
Mnemonic
RORC
Operand (dst, cnt)
A, 1
[Flag]
Z
AC
CY
×
[Description]
•
The destination operand (dst) contents specified with the 1st operand are rotated just once to the right
including the CY flag.
CY
7
0
[Description example]
RORC A, 1; The A register contents are rotated to the right by one bit including the CY flag.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Rotate Left with Carry
Byte Data Rotation to the Left with Carry
ROLC
[Instruction format]
[Operation]
ROLC dst, cnt
(CY ← dst7, dst0 ← CY, dstm+1 ← dstm) × one time
[Operand]
Mnemonic
ROLC
Operand (dst, cnt)
A, 1
[Flag]
Z
AC
CY
×
[Description]
•
The destination operand (dst) contents specified with the 1st operand are rotated just once to the left
including the CY flag.
CY
7
0
[Description example]
ROLC A, 1; The A register contents are rotated to the left by one bit including the CY flag.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
5.7 Bit Manipulation Instructions
The following are bit manipulation instructions.
SET1 ... 89
CLR1 ... 90
NOT1 ... 91
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Set Single Bit (Carry Flag)
1 Bit Data Set
SET1
[Instruction format]
[Operation]
SET1 dst
dst ← 1
[Operand]
Mnemonic
SET1
Operand (dst)
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
[Flag]
dst = PSW.bit
dst = CY
Z
In all other cases
Z
AC
CY
AC
CY
1
Z
AC
CY
×
×
×
[Description]
•
•
The destination operand (dst) is set (1).
When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is set (1).
[Description example]
SET1 0FE55H.1; Bit 1 of FE55H is set (1).
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Clear Single Bit (Carry Flag)
1 Bit Data Clear
CLR1
[Instruction format]
[Operation]
CLR1 dst
dst ← 0
[Operand]
Mnemonic
CLR1
Operand (dst)
saddr.bit
sfr.bit
A.bit
PSW.bit
[HL].bit
CY
[Flag]
dst = PSW.bit
dst = CY
Z
In all other cases
Z
AC
CY
AC
CY
0
Z
AC
CY
×
×
×
[Description]
•
•
The destination operand (dst) is cleared (0).
When the destination operand (dst) is CY or PSW.bit, only the corresponding flag is cleared (0).
[Description example]
CLR1 P3.7; Bit 7 of port 3 is cleared (0).
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Not Single Bit (Carry Flag)
1 Bit Data Logical Negation
NOT1
[Instruction format]
[Operation]
NOT1 dst
_______
dst ← dst
[Operand]
Mnemonic
NOT1
Operand (dst)
CY
[Flag]
Z
AC
CY
×
[Description]
•
The CY flag is inverted.
[Description example]
NOT1 CY; The CY flag is inverted.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
5.8 CALL/RETURN Instructions
The following are call/return instructions.
CALL ... 93
CALLT ... 94
RET ... 95
RETI ... 96
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Call
CALL
Subroutine Call (16 Bit Direct)
[Instruction format]
[Operation]
CALL target
(SP – 1) ← (PC + 3)H,
(SP – 2) ← (PC + 3)L,
SP
PC
← SP – 2,
← target
[Operand]
Mnemonic
CALL
Operand (target)
!addr16
[Flag]
Z
AC
CY
[Description]
•
•
This is a subroutine call with a 16-bit absolute address or a register indirect address.
The next instruction’s start address (PC + 3) is saved in the stack and is branched to the address specified
with the target operand (target).
[Description example]
CALL !3059H; Subroutine call to 3059H
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Call Table
Subroutine Call (Call Table Reference)
CALLT
[Instruction format]
[Operation]
CALLT [addr5]
(SP – 1) ← (PC + 1)H,
(SP – 2) ← (PC + 1)L,
SP
← SP – 2,
PCH
PCL
← (00000000,addr5 + 1)
← (00000000,addr5)
[Operand]
Mnemonic
CALLT
Operand ([addr5])
[addr5]
[Flag]
Z
AC
CY
[Description]
•
•
This is a subroutine call for call table reference.
The next instruction’s start address (PC + 1) is saved in the stack and is branched to the address indicated
with the word data of a call table (the higher 8 bits of address are fixed to 00000000B and the following 5 bits
are specified with addr5).
[Description example]
CALLT [40H]; Subroutine call to the addresses indicated by word data of 0040H and 0041H.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Return
RET
Return from Subroutine
[Instruction format]
[Operation]
RET
PCL ← (SP),
PCH ← (SP + 1),
SP ← SP + 2
[Operand]
None
[Flag]
Z
AC
CY
[Description]
•
•
This is a return instruction from the subroutine call made with the CALL and CALLT instructions.
The word data saved in the stack returns to the PC, and the program returns from the subroutine.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Return from Interrupt
Return from Hardware Vectored Interrupt
RETI
[Instruction format]
[Operation]
RETI
PCL ← (SP),
PCH ← (SP + 1),
PSW ← (SP + 2),
SP
← SP + 3,
NMIS ← 0
[Operand]
None
[Flag]
Z
AC
R
CY
R
R
[Description]
•
•
This is a return instruction from the vectored interrupt.
The data saved in the stack returns to the PC and PSW, and the program returns from the interrupt service
routine.
•
•
None of interrupts are acknowledged between this instruction and the next instruction to be executed.
The NMIS flag is set to 1 by acknowledgment of a non-maskable interrupt, and cleared to 0 by the RETI
instruction.
[Caution]
When the return from non-maskable interrupt servicing is performed by an instruction other than the RETI
instruction, the NMIS flag is not cleared to 0, and therefore no interrupts (including non-maskable interrupts) can
be acknowledged.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
5.9 Stack Manipulation Instructions
The following are stack manipulation instructions.
PUSH ... 98
POP ... 99
MOVW SP, AX ... 100
MOVW AX, SP ... 100
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Push
Push
PUSH
[Instruction format]
[Operation]
PUSH src
When src = rp
When src = PSW
(SP – 1) ← srcH,
(SP – 2) ← srcL,
(SP – 1) ← src
SP
← SP − 1
SP
←SP − 2
[Operand]
Mnemonic
PUSH
Operand (src)
PSW
rp
[Flag]
Z
AC
CY
[Description]
•
The data of the register specified with the source operand (src) is saved in the stack.
[Description example]
PUSH AX; AX register contents are saved in the stack.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Pop
Pop
POP
[Instruction format]
[Operation]
POP dst
When dst = rp
When dst = PSW
dst ← (SP)
dstL ← (SP),
dstH ← (SP + 1),
SP ← SP + 1
SP
← SP + 2
[Operand]
Mnemonic
POP
Operand (dst)
PSW
rp
[Flag]
dst = rp
PSW
Z
AC
CY
Z
AC
R
CY
R
R
[Description]
•
•
•
Data is returned from the stack to the register specified with the destination operand (dst).
When the operand is PSW, each flag is replaced with stack data.
No interrupts are acknowledged between the POP PSW instruction and the subsequent instruction.
[Description example]
POP AX; The stack data is returned to the AX register.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Move Word
Word Data Transfer with Stack Pointer
MOVW SP, AX
MOVW AX, SP
[Instruction format]
[Operation]
MOVW dst, src
dst ← src
[Operand]
Mnemonic
Operand (dst, src)
MOVW
SP, AX
AX, SP
[Flag]
Z
AC
CY
[Description]
•
•
This is an instruction to manipulate the stack pointer contents.
The source operand (src) specified with the 2nd operand is stored in the destination operand (dst) specified
with the 1st operand.
[Description example]
MOVW SP, AX; AX register contents are stored in the stack pointer.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
5.10 Unconditional Branch Instruction
The following is an unconditional branch instruction.
BR ... 102
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Branch
BR
Unconditional Branch
[Instruction format]
[Operation]
BR target
PC ← target
[Operand]
Mnemonic
BR
Operand (target)
!addr16
AX
$addr16
[Flag]
Z
AC
CY
[Description]
•
•
This is an instruction to branch unconditionally.
The word data of the target address operand (target) is transferred to PC and program branches.
[Description example]
BR AX; The AX register contents are regarded as an address to which the program branches.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
5.11 Conditional Branch Instructions
The following are conditional branch instructions.
BC ... 104
BNC ... 105
BZ ... 106
BNZ ... 107
BT ... 108
BF ... 109
DBNZ ... 110
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Branch if Carry
Conditional Branch with Carry Flag (CY = 1)
BC
[Instruction format]
[Operation]
BC $addr16
PC ← PC + 2 + jdisp8 if CY = 1
[Operand]
Mnemonic
BC
Operand ($addr16)
$addr16
[Flag]
Z
AC
CY
[Description]
•
When CY = 1, program branches to the address specified with the operand.
When CY = 0, no processing is carried out and the subsequent instruction is executed.
[Description example]
BC $300H; When CY = 1, program branches to 0300H (with the start of this instruction set in the range of
addresses 027FH to 037EH).
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Branch if Not Carry
Conditional Branch with Carry Flag (CY = 0)
BNC
[Instruction format]
[Operation]
BNC $addr16
PC ← PC + 2 + jdisp8 if CY = 0
[Operand]
Mnemonic
Operand ($addr16)
BNC
$addr16
[Flag]
Z
AC
CY
[Description]
•
When CY = 0, program branches to the address specified with the operand.
When CY = 1, no processing is carried out and the subsequent instruction is executed.
[Description example]
BNC $300H; When CY = 0, program branches to 0300H (with the start of this instruction set in the range of
addresses 027FH to 037EH).
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Branch if Zero
Conditional Branch with Zero Flag (Z = 1)
BZ
[Instruction format]
[Operation]
BZ $addr16
PC ← PC + 2 + jdisp8 if Z = 1
[Operand]
Mnemonic
BZ
Operand ($addr16)
$addr16
[Flag]
Z
AC
CY
[Description]
•
When Z = 1, program branches to the address specified with the operand.
When Z = 0, no processing is carried out and the subsequent instruction is executed.
[Description example]
DEC B
BZ $3C5H; When the B register is 0, program branches to 03C5H (with the start of this instruction set in the
range of addresses 0344H to 0443H).
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Branch if Not Zero
Conditional Branch with Zero Flag (Z = 0)
BNZ
[Instruction format]
[Operation]
BNZ $addr16
PC ← PC + 2 + jdisp8 if Z = 0
[Operand]
Mnemonic
BNZ
Operand ($addr16)
$addr16
[Flag]
Z
AC
CY
[Description]
•
When Z = 0, program branches to the address specified with the operand.
When Z = 1, no processing is carried out and the subsequent instruction is executed.
[Description example]
CMP A, #55H
BNZ $0A39H; If the A register is not 0055H, program branches to 0A39H (with the start of this instruction set in
the range of addresses 09B8H to 0AB7H).
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Branch if True
BT
Conditional Branch by Bit Test (Byte Data Bit = 1)
[Instruction format]
[Operation]
BT bit, $addr16
PC ← PC + b + jdisp8 if bit = 1
[Operand]
Mnemonic
BT
Operand (bit, $addr16)
saddr.bit, $addr16
sfr.bit, $addr16
b (Number of bytes)
4
4
3
4
A.bit, $addr16
PSW.bit, $addr16
[Flag]
Z
AC
CY
[Description]
•
If the 1st operand (bit) contents have been set (1), program branches to the address specified with the 2nd
operand ($addr16).
If the 1st operand (bit) contents have not been set (1), no processing is carried out and the subsequent
instruction is executed.
[Description example]
BT 0FE47H.3, $55CH; When bit 3 at address FE47H is 1, program branches to 055CH (with the start of this
instruction set in the range of addresses 04DAH to 05D9H).
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Branch if False
BF
Conditional Branch by Bit Test (Byte Data Bit = 0)
[Instruction format]
[Operation]
BF bit, $addr16
PC ← PC + b + jdisp8 if bit = 0
[Operand]
Mnemonic
BF
Operand (bit, $addr16)
saddr.bit, $addr16
sfr.bit, $addr16
b (Number of bytes)
4
4
3
4
A.bit, $addr16
PSW.bit, $addr16
[Flag]
Z
AC
CY
[Description]
•
If the 1st operand (bit) contents have been cleared (0), program branches to the address specified with the
2nd operand ($addr16).
If the 1st operand (bit) contents have not been cleared (0), no processing is carried out and the subsequent
instruction is executed.
[Description example]
BF P2.2, $1549H; When bit 2 of port 2 is 0, program branches to address 1549H (with the start of this instruction
set in the range of addresses 14C6H to 15C5H).
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Decrement and Branch if Not Zero
Conditional Loop (R1 ≠ 0)
DBNZ
[Instruction format]
[Operation]
DBNZ dst, $addr16
dst ← dst – 1,
then PC ← PC + b + jdisp16 if dst R1 ≠ 0
[Operand]
Mnemonic
DBNZ
Operand (dst, $addr16)
B, $addr16
b (Number of bytes)
2
2
3
C, $addr16
saddr, $addr16
[Flag]
Z
AC
CY
[Description]
•
•
•
One is subtracted from the destination operand (dst) contents specified with the 1st operand and the
subtraction result is stored in the destination operand (dst).
If the subtraction result is not 0, program branches to the address indicated with the 2nd operand ($addr16).
When the subtraction result is 0, no processing is carried out and the subsequent instruction is executed.
The flag remains unchanged.
[Description example]
DBNZ B, $1215H; The B register contents are decremented. If the result is not 0, program branches to 1215H
(with the start of this instruction set in the range of addresses 1194H to 1293H).
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
5.12 CPU Control Instructions
The following are CPU control instructions.
NOP ... 112
EI ... 113
DI ... 114
HALT ... 115
STOP ... 116
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
No Operation
No Operation
NOP
[Instruction format]
[Operation]
NOP
no operation
[Operand]
None
[Flag]
Z
AC
CY
[Description]
•
No processing is performed and only time is consumed.
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Enable Interrupt
Interrupt Enabled
EI
[Instruction format]
[Operation]
EI
IE ← 1
[Operand]
None
[Flag]
Z
AC
CY
[Description]
•
•
•
The maskable interrupt acknowledge-enable status is set (by setting the interrupt enable flag (IE) (1)).
Interrupts are acknowledged immediately after this instruction is executed.
If this instruction is executed, vectored interrupt acknowledgment with another source can be disabled. For
details, refer to "Interrupt Functions" in the User's Manual of each product.
User’s Manual U11047EJ3V0UM00
113
CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Disable Interrupt
Interrupt Disabled
DI
[Instruction format]
[Operation]
DI
IE ← 0
[Operand]
None
[Flag]
Z
AC
CY
[Description]
•
Maskable interrupt acknowledgment with vectored interrupt is disabled (with the interrupt enable flag (IE)
cleared (0)).
•
•
No interrupts are acknowledged between this instruction and the subsequent instruction.
For details of interrupt servicing, refer to "Interrupt Functions" in the User's Manual of each product.
User’s Manual U11047EJ3V0UM00
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CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Halt
HALT
HALT Mode Set
[Instruction format]
[Operation]
HALT
Set HALT Mode
[Operand]
None
[Flag]
Z
AC
CY
[Description]
•
This instruction is used to set the HALT mode to stop the CPU operation clock. Total power consumption of
the system can be reduced with intermittent operations through combination with the normal operation mode.
User’s Manual U11047EJ3V0UM00
115
CHAPTER 5 EXPLANATION OF INSTRUCTIONS
Stop
STOP
Stop Mode Set
[Instruction format]
[Operation]
STOP
Set STOP Mode
[Operand]
None
[Flag]
Z
AC
CY
[Description]
•
This instruction is used to set the STOP mode to stop the main system clock oscillator and to stop the whole
system. Power dissipation can be minimized to an ultra-low leakage current level only.
User’s Manual U11047EJ3V0UM00
116
APPENDIX A INSTRUCTION INDEX (MNEMONIC: BY FUNCTION)
[8-bit data transfer instructions]
[Bit manipulation instructions]
MOV ... 60
XCH ... 61
SET1 ... 89
CLR1 ... 90
NOT1 ... 91
[16-bit data transfer instructions]
[Call/return instructions]
MOVW ... 63
XCHW ... 64
CALL ... 93
CALLT ... 94
RET ... 95
[8-bit operation instructions]
RETI ... 96
ADD ... 66
ADDC ... 67
SUB ... 68
SUBC ... 69
AND ... 70
OR ... 71
[Stack manipulation instructions]
PUSH ... 98
POP ... 99
MOVW SP, AX ... 100
MOVW AX, SP ... 100
XOR ... 72
CMP ... 73
[Unconditional branch instruction]
BR ... 102
[16-bit operation instructions]
ADDW ... 75
SUBW ... 76
CMPW ... 77
[Conditional branch instructions]
BC ... 104
BNC ... 105
BZ ... 106
[Increment/decrement instructions]
INC ... 79
BNZ ... 107
BT ... 108
DEC ... 80
INCW ... 81
DECW ... 82
BF ... 109
DBNZ ... 110
[Rotate instructions]
[CPU control instructions]
ROR ... 84
ROL ... 85
RORC ... 86
ROLC ... 87
NOP ... 112
EI ... 113
DI ... 114
HALT ... 115
STOP ... 116
User’s Manual U11047EJ3V0UM00
117
[MEMO]
User’s Manual U11047EJ3V0UM00
118
APPENDIX B INSTRUCTION INDEX (MNEMONIC: IN ALPHABETICAL ORDER)
[A]
[M]
ADD ... 66
MOV ... 60
ADDC ... 67
ADDW ... 75
AND ... 70
MOVW ... 63
MOVW AX, SP ... 100
MOVW SP, AX ... 100
[B]
[N]
BC ... 104
BF ... 109
BNC ... 105
BNZ ... 107
BR ... 102
BT ... 108
BZ ... 106
NOP ... 112
NOT1 ... 91
[O]
OR ... 71
[P]
[C]
POP ... 99
CALL ... 93
CALLT ... 94
CLR1 ... 90
CMP ... 73
PUSH ... 98
[R]
CMPW ... 77
RET ... 95
RETI ... 96
ROL ... 85
ROLC ... 87
ROR ... 84
RORC ... 86
[D]
DBNZ ... 110
DEC ... 80
DECW ... 82
DI ... 114
[S]
[E]
SET1 ... 89
STOP ... 116
SUB ... 68
EI ... 113
[H]
SUBC ... 69
SUBW ... 76
HALT ... 115
[I]
[X]
XCH ... 61
XCHW ... 64
XOR ... 72
INC ... 79
INCW ... 81
User’s Manual U11047EJ3V0UM00
119
[MEMO]
User’s Manual U11047EJ3V0UM00
120
APPENDIX C REVISION HISTORY
A history of the revisions up to this edition is shown below. “Applied to:” indicates the chapters to which the
revision was applied.
Edition
Contents
Addition of the following target products
Applied to:
Throughout
2nd
3rd
µPD789026, 789407, 789417, 789800, and 789806Y Subseries
Modification of the format of the table of the internal data memory space of the
78K/0S Series products
CHAPTER 1 MEMORY
SPACE
Addition of the following target products
Throughout
µPD789046, 789104, 789114, 789124, 789134, 789146, 789156, 789167,
789177, 789197AY, 789217AY, 789407A, 789417A, and 789842 Subseries
Deletion of the following target products
µPD789407, 789417, and 789806Y Subseries
Modification of MOV PSW, #byte instruction code
Modification of MOVW rp, AX instruction code
Modification of XOR A, r instruction code
Modification of CMP A, r instruction code
CHAPTER 4 INSTRUCTION
SET
User’s Manual U11047EJ3V0UM00
121
[MEMO]
User’s Manual U11047EJ3V0UM00
122
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CS 00.6
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