UPD78F4928_技术文档

Application Note

µPD784915, 784928, 784928Y

Subseries

16-bit Single-chip Microcontrollers

VCR Servo Basics

µPD784915

µPD784927

µPD784927Y

µPD784915A µPD78F4928 µPD78F4928Y

µPD784916A

µPD784915B

µPD784916B

µPD78P4916

Document No. U11361EJ3V0AN00 (3rd edition)

Date Published March 1998 N CP(K)

©

1996

Printed in Japan

[MEMO]

2

NOTES FOR CMOS DEVICES

1

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

2

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

3

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

3

The export of these products from Japan is regulated by the Japanese government. The export of some or all of these

products may be prohibited without governmental license. To export or re-export some or all of these products from a

country other than Japan may also be prohibited without a license from that country. Please call an NEC sales

representative.

The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.

The information in this document is subject to change without notice.

No part of this document may be copied or reproduced in any form or by any means without the prior written

consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in

this document.

NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property

rights of third parties by or arising from use of a device described herein or any other liability arising from use

of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other

intellectual property rights of NEC Corporation or others.

While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices,

the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or

property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety

measures in its design, such as redundancy, fire-containment, and anti-failure features.

NEC devices are classified into the following three quality grades:

"Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a

customer designated “quality assurance program“ for a specific application. The recommended applications of

a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device

before using it in a particular application.

Standard: Computers, office equipment, communications equipment, test and measurement equipment,

audio and visual equipment, home electronic appliances, machine tools, personal electronic

equipment and industrial robots

Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems or medical equipment for life support, etc.

The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books.

If customers intend to use NEC devices for applications other than those specified for Standard quality grade,

they should contact an NEC sales representative in advance.

Anti-radioactive design is not implemented in this product.

M7 96.5

4

Regional Information

Some information contained in this document may vary from country to country. Before using any NEC

product in your application, please contact the NEC office in your country to obtain a list of authorized

representatives and distributors. They will verify:

• Device availability

• Ordering information

• Product release schedule

• Availability of related technical literature

• Development environment specifications (for example, specifications for third-party tools and

components, host computers, power plugs, AC supply voltages, and so forth)

• Network requirements

In addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary

from country to country.

NEC Electronics Inc. (U.S.)

Santa Clara, California

Tel: 408-588-6000

800-366-9782

NEC Electronics Hong Kong Ltd.

Hong Kong

Tel: 2886-9318

NEC Electronics (Germany) GmbH

Benelux Office

Eindhoven, The Netherlands

Tel: 040-2445845

Fax: 2886-9022/9044

Fax: 408-588-6130

800-729-9288

Fax: 040-2444580

NEC Electronics Hong Kong Ltd.

Seoul Branch

Seoul, Korea

Tel: 02-528-0303

Fax: 02-528-4411

NEC Electronics (France) S.A.

Velizy-Villacoublay, France

Tel: 01-30-67 58 00

NEC Electronics (Germany) GmbH

Duesseldorf, Germany

Tel: 0211-65 03 02

Fax: 01-30-67 58 99

Fax: 0211-65 03 490

NEC Electronics Singapore Pte. Ltd.

United Square, Singapore 1130

Tel: 65-253-8311

NEC Electronics (France) S.A.

Spain Office

Madrid, Spain

NEC Electronics (UK) Ltd.

Milton Keynes, UK

Tel: 01908-691-133

Fax: 65-250-3583

Tel: 01-504-2787

Fax: 01908-670-290

Fax: 01-504-2860

NEC Electronics Taiwan Ltd.

Taipei, Taiwan

Tel: 02-719-2377

NEC Electronics Italiana s.r.1.

Milano, Italy

NEC Electronics (Germany) GmbH

Scandinavia Office

Tel: 02-66 75 41

Fax: 02-719-5951

Taeby, Sweden

Fax: 02-66 75 42 99

Tel: 08-63 80 820

NEC do Brasil S.A.

Cumbica-Guarulhos-SP, Brasil

Tel: 011-6465-6810

Fax: 08-63 80 388

Fax: 011-6465-6829

J98. 2

5

Major Revisions in This Edition

Page

Throughout

Introduction

p. 15

Description

The µPD784928, 784928Y Subseries and the µPD784915B, 784916B are added.

Document numbers of related documents are added or corrected.

CHAPTER 1 OUTLINE OF NEC VCR SERVO MICROCONTROLLER PRODUCTS is added.

Table 2-1 Differences among µPD784915 Subseries Products is added.

CHAPTER 3 OUTLINE OF µPD784928, 784928Y SUBSERIES is added.

p. 19

p. 25

The mark shows major revised points.

6

INTRODUCTION

Readers

This application note is intended for user engineers who understand the functions of

the µPD784915, 784928, 784928Y Subseries and wish to design and develop its

application systems and programs.

Purpose

The purpose of this application note is to help users understand the hardware capa-

bilities of the target device using application examples.

Organization

The main topics of this application note are listed below.

•

Outline of µPD784915 Subseries

Outline of µPD784928, 784928Y Subseries

Outline of VCR servo

Servo control examples of stationary VCR

Analog circuit

VISS

How to Read This Manual

It is assumed that the readers of this manual have a general knowledge of electronics,

logical circuits, and microcontrollers. Moreover, readers should also have a general

knowledge of VCRs and servo control.

When there are no functional differences in the products, the application note men-

tions the µPD784915 Subseries as the representative subseries and the µPD784915

as the representative version, although its descriptions also apply to the versions

other than the µPD784915.

Quality Grade

Legends

Standard (for general electronic appliances)

Data significance

Active low

Note

: Left: higher digit, right: lower digit

: ××× (top bar over pin or signal name)

: Footnote explaining items marked with “Note”

in the text

Caution

: Description of point that requires particular

attention

Remark

: Supplementary information

: Binary ... ××××B or ××××

Decimal ... ××××

Numerical representation

Hexadecimal ... ××××H

Easily confused characters : 0 (zero), O (uppercase letter “o”)

1 (one), l (lowercase of letter “L”),

I (uppercase of letter “i”)

7

Related Documents

The related documents indicated in this publication may include preliminary versions.

However, preliminary versions are not marked as such.

Device related documents

Document Number

Document Name

Japanese

English

µPD784915 Data Sheet

U11044J

U11044E

µPD784915A, 784916A Data Sheet

U11022J

U11930J

U11045J

U10976J

U10444J

U12255J

U12188J

U12798J

U12373J

U12271J

U12719J

U12648J

U11361J

U10905J

U10594J

U10595J

U10095J

U11022E

To be prepared

U11045E

—

µPD784915B, 784916B Data Sheet

µPD78P4916 Data Sheet

µPD784915 Subseries Special Function Register Table

µPD784915 Subseries User’s Manual

U10444E

To be prepared

U12188E

—

µPD784927 Data Sheet

µPD78F4928 Preliminary Product Information

µPD784928 Subseries Special Function Register Table

µPD784927Y Data Sheet

U12373E

U12271E

—

µPD78F4928Y Preliminary Product Information

µPD784928Y Subseries Special Function Register Table

µPD784928, 784928Y Subseries User’s Manual

µPD784915, 784928, 784928Y Subseries Application Note — VCR Servo Basics

78K/IV Series User’s Manual — Instruction

78K/IV Series Instruction Table

U12648E

This manual

U10905E

—

78K/IV Series Instruction Set

—

78K/IV Series Application Note — Software Basics

U10095E

Register Format

7

6

1

5

0

4

3

2

1

0

Bit number that is circled indicates that it is a

reserved word in the RA78K4 and sfr variable

with #pragma sfr instruction in the CC78K4, and

it is defined with a file.

EDC

B

×

A

×

Write operation

Write 0 or 1.

Read operation

Read 0 or 1.

Neither value affects

operation.

Write 0.

Write 1.

Register name

Write the value corres-

Read a value according

ponding to a function to use. to operation status.

Never write a combination of codes marked “setting prohibited” in the register formats in the text.

8

CONTENTS

CHAPTER 1 OUTLINE OF NEC VCR SERVO MICROCONTROLLER PRODUCTS ......................... 15

1.1 Outline .............................................................................................................................. 15

1.2 Features............................................................................................................................ 17

CHAPTER 2 OUTLINE OF µPD784915 SUBSERIES ......................................................................... 19

2.1 Features and Application Fields .................................................................................... 20

2.2 Pin Configuration (Top View) ......................................................................................... 21

2.3 Block Diagram.................................................................................................................. 23

2.4 Outline of Functions ........................................................................................................ 24

CHAPTER 3 OUTLINE OF µPD784928, 784928Y SUBSERIES......................................................... 25

3.1 Features and Application Fields .................................................................................... 26

3.2 Pin Configuration (Top View) ......................................................................................... 27

3.3 Internal Block Diagram.................................................................................................... 29

3.4 Outline of Functions ........................................................................................................ 30

3.5 Differences among µPD784928, 784928Y Subseries and µPD784915 Subseries ...... 32

CHAPTER 4 OUTLINE OF VCR SERVO SYSTEM ............................................................................. 33

4.1 Outline of Software Servo............................................................................................... 33

4.2 Servo Control of VCR ...................................................................................................... 34

4.3 Servo for Recording ........................................................................................................ 36

4.4 Servo for Playback .......................................................................................................... 36

4.5 Motor to be Used ............................................................................................................. 37

4.6 VCR Control Systems...................................................................................................... 38

4.7 VCR Servo System Control............................................................................................. 38

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL ................................... 39

5.1 Examples of System Configuration ............................................................................... 39

5.2 Outline of System ............................................................................................................ 41

5.3 Using Example of Super Timer Unit............................................................................... 43

5.4 Head Switching Signal Generation ................................................................................ 46

5.4.1 Internal head switching signal (HSW-N) generation.............................................................. 46

5.4.2 Head switching signal (V-HSW) generation .......................................................................... 48

5.4.3 Audio head switching signal (A-HSW) generation................................................................. 54

5.5 Drum Speed Control........................................................................................................ 58

5.6 Drum Phase Control ........................................................................................................ 60

5.6.1 Phase reference .................................................................................................................... 60

5.6.2 Drum phase control for playback ........................................................................................... 69

5.6.3 Drum phase control for recording .......................................................................................... 74

5.7 Capstan Speed Control ................................................................................................... 79

5.8 Capstan Phase Control ................................................................................................... 83

5.8.1 Capstan phase control for playback ...................................................................................... 83

5.8.2 Capstan phase control for recording ..................................................................................... 90

5.9 Recording Control Signal Generation ........................................................................... 94

5.10 Quasi Vertical Synchronizing Signal (Quasi-VSYNC) Generation ................................. 100

9

5.11 Treatment of Servo Error Amount.................................................................................. 103

5.11.1 Drum control system processing ........................................................................................... 103

5.11.2 Capstan control system processing ...................................................................................... 107

5.12 Compensation Filter ........................................................................................................ 112

5.12.1 Filter types ............................................................................................................................. 112

5.12.2 Biprimary conversion method ................................................................................................ 113

5.12.3 Digital filter designing method ............................................................................................... 119

5.12.4 Primary IIR type digital filter transfer function ........................................................................ 120

5.12.5 Lag-lead filter configuration method ...................................................................................... 121

5.12.6 Filter processing method ....................................................................................................... 124

CHAPTER 6 CTL AMPLIFIER ............................................................................................................. 127

6.1 CTL Amplifier Auto Gain Control Processing............................................................... 127

6.1.1 CTL amplifier auto gain control method ................................................................................ 129

6.1.2 CTL amplifier auto gain control processing ........................................................................... 134

CHAPTER 7 VISS DETECTION........................................................................................................... 137

7.1 What is VISS..................................................................................................................... 137

7.2 VISS Detection ................................................................................................................. 138

7.2.1 VISS detection method.......................................................................................................... 138

7.2.2 VISS detection processing .................................................................................................... 142

7.3 VISS Rewrite .................................................................................................................... 147

7.3.1 VISS rewrite method ............................................................................................................. 147

7.3.2 VISS rewrite processing ........................................................................................................ 149

CHAPTER 8 PROGRAM LIST .............................................................................................................. 151

APPENDIX REVISION HISTORY.......................................................................................................... 221

10

LIST OF FIGURES (1/2)

Figure No.

4-1

Title

Page

Track Pattern on Video Tape ............................................................................................................ 35

5-1

Application to Stationary Type VCR .................................................................................................. 40

Software Digital Servo System Block Diagram ................................................................................. 42

Super Timer Unit Block Diagram ...................................................................................................... 44

Use of Event Counter (EC) ............................................................................................................... 46

Event Counter (EC) Operation Timing .............................................................................................. 47

Use of Timer 0................................................................................................................................... 49

Head Switching Signal (V-HSW) Timing (PTO00) ............................................................................ 50

Input Control Register (ICR) Format (when generating V-HSW) ...................................................... 51

Timer 0 Output Mode Register (TOM0) Format (when generating V-HSW) ..................................... 52

Timer 0 Output Control Register (TOC0) Format (when generating V-HSW)................................... 52

Timer Control Register 0 (TMC0) Format (when generating V-HSW) .............................................. 53

Assigning A-HSW to Timer 0 ............................................................................................................ 54

V-HSW and A-HSW Timings............................................................................................................. 55

Timer 0 Output Mode Register (TOM0) Format (when generating A-HSW) ..................................... 55

Timer 0 Output Control Register (TOC0) Format (when generating A-HSW)................................... 56

Timer Control Register 0 (TMC0) Format (when generating A-HSW) .............................................. 57

Drum Speed Error Amount Detection Method .................................................................................. 58

Drum Speed Control Timings ............................................................................................................ 59

Timer 1 Peripheral Circuit ................................................................................................................. 61

Example of Timer 1 Operation Timings (for playback)...................................................................... 63

Timer Control Register 0 (TMC0) Format (drum phase control for playback)................................... 64

Example of Timer 1 Operation Timings (for recording) ..................................................................... 67

Timer Control Register 0 (TMC0) Format (drum phase control for recording) .................................. 68

Use of Timer for Drum Phase Control (for playback) ........................................................................ 69

Drum Phase Control Timing (for playback) ....................................................................................... 70

Capture Mode Register (CPTM) Format ........................................................................................... 73

Use of Timer for Drum Phase Control (for recording) ....................................................................... 75

Drum Phase Control Timing (for recording) ...................................................................................... 76

Capture Mode Register (CPTM) Format ........................................................................................... 77

Capstan Speed Detection Method .................................................................................................... 81

Capstan Speed Control Timing ......................................................................................................... 82

Model of Capstan Phase Control ...................................................................................................... 83

Capstan Phase Error Detection Method (for playback) .................................................................... 85

Capture Mode Register (CPTM) Format ........................................................................................... 86

Capstan Phase Control Timing (playback mode, phase locked) ...................................................... 87

Capstan Phase Control Timing (playback mode, phase delayed) .................................................... 88

Capstan Phase Control Timing (playback mode, phase advanced) ................................................. 89

Capstan Phase Error Detection Method (for recording).................................................................... 91

Capture Mode Register (CPTM) Format ........................................................................................... 92

Capstan Phase Control Timing (for recording) ................................................................................. 93

Connection of µPD784915 and Control Head................................................................................... 95

5-2

5-3

5-4

5-5

5-6

5-7

5-8

5-9

5-10

5-11

5-12

5-13

5-14

5-15

5-16

5-17

5-18

5-19

5-20

5-21

5-22

5-23

5-24

5-25

5-26

5-27

5-28

5-29

5-30

5-31

5-32

5-33

5-34

5-35

5-36

5-37

5-38

5-39

5-40

5-41

11

LIST OF FIGURES (2/2)

Figure No.

Title

Page

5-42

5-43

5-44

5-45

5-46

5-47

5-48

5-49

5-50

5-51

5-52

5-53

5-54

5-55

5-56

5-57

5-58

5-59

RECCTL Driver Block Diagram ......................................................................................................... 95

Example of RECCTL Signal Writing Operation Timings ................................................................... 96

Timer 1 Output Mode Register (TOM1) Format ................................................................................ 98

RECCTL Write Timing Using CR11 .................................................................................................. 99

Quasi-V^SYNCWaveform ..................................................................................................................... 101

Middle Level Generation ................................................................................................................... 101

Quasi-V^SYNCGeneration Timing ........................................................................................................ 102

Drum Control System Configuration ................................................................................................. 103

Trapezoidal Pattern for Error Value Detection (drum control system) .............................................. 104

Capstan Control System Configuration............................................................................................. 107

Trapezoidal Pattern for Error Value Detection (capstan control system) .......................................... 108

Fold Error .......................................................................................................................................... 114

Pole Location when Sampling Theorem is Satisfied ......................................................................... 115

Pole Location when Sampling Theorem is Not Satisfied .................................................................. 115

Mapping by Standard z Transform.................................................................................................... 116

Mapping by Biprimary Transform ...................................................................................................... 118

Primary IIR Type Digital Filter Block Diagram................................................................................... 120

Lag-lead Filter Configuration and Characteristics ............................................................................. 121

6-1

6-2

6-3

6-4

6-5

6-6

CTL Amplifier Configuration .............................................................................................................. 127

Relationship between CTL Amplifier Output and Each Detection Level/Flag ................................... 128

Gain Change Timing for PLAY or CUE/REV in Forward Direction ................................................... 130

Gain Change Timing for PLAY or CUE/REV in Reverse Direction ................................................... 131

Gain Change Timing for FF/REW in Forward Direction .................................................................... 132

Gain Change Timing for FF/REW in Reverse Direction .................................................................... 133

7-1

7-2

7-3

7-4

7-5

7-6

7-7

7-8

VISS Cue Code................................................................................................................................. 137

VISS Detection Circuit (Pulse Width Detection Circuit) Configuration .............................................. 138

Data Pattern Discrimination Mode Block Configuration .................................................................... 140

Addressing and Data Setting in Data Pattern Discrimination Mode.................................................. 141

INTCR12 Macro Service Processing in Forward Direction ............................................................... 145

INTCR12 Macro Service Processing in Reverse Direction ............................................................... 146

VISS Rewrite..................................................................................................................................... 147

VISS = 1 Signal Rewrite Operation Timing Chart ............................................................................. 149

12

LIST OF TABLES

Table No.

2-1

Title

Page

Differences among µPD784915 Subseries Products........................................................................ 19

3-1

3-2

Differences among µPD784928, 784928Y Subseries Products ....................................................... 25

Differences among µPD784928, 784928Y Subseries and µPD784915 Subseries .......................... 32

5-1

5-2

5-3

5-4

Using Examples of Super Timer Unit ................................................................................................ 43

RECCTL Driver REC Mode Sequence ............................................................................................. 95

Capstan Loop Gain in Each Operation Mode ................................................................................... 110

Capstan Bias Value in Each Operation Mode................................................................................... 111

6-1

CTL Detection Flag Read Value and CTL Amplifier Gain Adjustment .............................................. 128

7-1

7-2

7-3

VISS Data ......................................................................................................................................... 137

RECCTL Driver Rewrite Mode Sequence......................................................................................... 148

VISS Write Operation Timings .......................................................................................................... 150

13

[MEMO]

14

CHAPTER 1 OUTLINE OF NEC VCR SERVO MICROCONTROLLER PRODUCTS

1.1 Outline

NEC’s microcontrollers for VCR servos are 78K/IV Series products featuring a high-speed, high-performance 16-

bit CPU that are improved versions of the 78K/I Series of 8-bit single-chip microcontrollers for VCR software servo

control.

Microcontrollers for VCR servo control comprise the following three subseries.

•

µPD784915 Subseries

µPD784928 Subseries

µPD784928Y Subseries

NEC’s lineup of microcontrollers for VCR servo control is shown below.

The Y subseries support I²C bus specifications.

Under mass production

Under development

78K/IV Series

100-pin QFP. Internal flash memory

µPD784928

µPD784928Y

Expanded on-chip memory capacity

Enhanced analog amplifiers. Improved VCR functions. Increased number of I/Os.

Large-current port added. I²C function added (Y products only).

100-pin QFP

µ

PD784915

PD78148

PD78138

Expanded on-chip memory capacity

On-chip analog amplifiers. Enhanced super timer.

Low-power-dissipation mode added.

78K/I Series

100-pin QFP

µ

Expanded on-chip RAM capacity. On-chip operational amplifier, clock function, multiplier.

µ

80-pin QFP

15

CHAPTER 1 OUTLINE OF NEC VCR SERVO MICROCONTROLLER PRODUCTS

Microcontrollers for VCR Servo Control

•

µPD784915 Subseries

Part Number µPD784915, 784915A,

µPD784915B

Mask ROM

µPD784916A,

µPD784916B

µPD78P4916

Parameter

Internal ROM capacity

One-time PROM

48 Kbytes

1280 bytes

62 Kbytes

Internal RAM capacity

2048 bytes

•

µPD784928, 784928Y Subseries

Note

Part Number

µPD784927,

µPD784927Y

Mask ROM

µPD78F4928

,

Note

Parameter

µPD78F4928Y

Internal ROM capacity

Internal RAM capacity

Flash memory

128 Kbytes

3584 bytes

96 Kbytes

2048 bytes

Note Under development

16

CHAPTER 1 OUTLINE OF NEC VCR SERVO MICROCONTROLLER PRODUCTS

1.2 Features

In this section, the µPD784915 Subseries is explained as the representative subseries, which is enhanced,

compared with the 78K/I Series, in the points mentioned below.

(1) Equipped with the 78K/IV core, a 16-bit high-performance CPU

The instruction set of the µPD784915 Subseries is perfectly upward-compatible with that of the existing 78K/

I series. Therefore, the software assets of the 78K/I Series are effectively utilized.

The 78K/IV Series supports 1-Mbyte linear address space, resulting in improved program handlability.

Moreover, the instruction set of the 78K/IV Series has been greatly enhanced, and realizes high-speed servo

arithmetic processing by using powerful multiplication and 16-bit transmit instructions.

(2) Enhanced power management function

The µPD784915 Subseries realizes internal 8 MHz (minimum instruction execution time = 250 ns) high-speed

operation in 4.5 to 5.5 V voltage range in normal operation. Its CPU guarantees 4.0-V operation.

Moreover, the µPD784915 Subseries is equipped with a low power consumption mode which enables CPU

operation using 32.768-kHz subsystem clock. Selection of CPU clock dividing ratio is made possible by on-

chip clock frequency dividing circuit. Since operation up to 2.7 V is guaranteed, reduction of the power

consumption of the whole system is possible using these functions. The use of these functions in combination

with the standby function realizes ultra low power consumption according to the operation conditions, that is,

back-up supply voltage operation or battery operation.

(3) Realizes low-frequency/high-speed operation for reducing radiation noise

The µPD784915 Subseries provides a low-frequency oscillation mode which enables internal operation with

the clock frequency equal to the external oscillation frequency. It realizes reduction of radiation noise by

enabling high-speed operation with a frequency lower than that of conventional products.

(4) On chip VCR servo control timer “Super Timer Unit”

The super timer unit consists of six 16-bit timers, two 8-bit timers, and a 5-bit up/down counter for linear tape

in addition to 22-bit free running counter (FRC) to carry out cycle measurement of various VCR motors.

Therefore, VCR servo control by software can be performed easily.

The µPD784915 is incorporated with special circuits such as VSYNC and HSYNC separation circuits required for

VCR servo control in addition to three 16-bit resolution PWM outputs and three 8-bit resolution PWM outputs

required for motor control.

(5) On-chip analog circuits for VCR

The analog circuits for VCR consist of a CTL amplifier to amplify record signals of the tape with any gain, a

RECCTL driver required for writing CTL and VISS signals, and other constituents required for VCR servo

control such as a drum FG amplifier, drum PG comparator, DPFG separation circuit (three-value separation

circuit), CFG amplifier, reel FG comparator (2 channels), and C^SYNCcomparator.

The CTL amplifier can switch gain in 32 steps by software. In actuality, the CTL amplifier output gain is

controlled by setting the CTL detection plug with software. Compared with conventional CTL amplifiers, the

circuit configuration is more optimized, which results in a reduction of the number of pins from eleven to six.

The analog circuits for VCR have made it possible to largely reduce the number of parts, enabling system

cost reduction.

17

CHAPTER 1 OUTLINE OF NEC VCR SERVO MICROCONTROLLER PRODUCTS

[MEMO]

18

CHAPTER 2 OUTLINE OF µPD784915 SUBSERIES

The µPD784915 Subseries under the 78K/IV Series consists of products provided with an on-chip high-speed, high-

performance 16-bit CPU that are improved versions of the 78K/I Series of 8-bit single-chip microcontrollers for VCR

software servo control.

The µPD784915 Subseries provides on chip optimum peripheral hardware for VCR control, including a multifunc-

tion timer unit (super timer unit) ideal for software servo control, and analog circuits, thus enabling the realization of

VCR system/servo/timer control with a single chip.

Moreover, a product with on-chip one-time PROM, the µPD78P4916, is also available.

This chapter describes the µPD784915 as the representative product.

Table 2-1. Differences among µPD784915 Subseries Products

Part Number

µPD784915, 784915A,

µPD784915B

µPD784916A,

µPD784916B

µPD78P4916

Parameter

Internal ROM capacity

Mask ROM

48 Kbytes

One-time PROM

62 Kbytes

Internal RAM capacity

1280 bytes

Not provided

2048 bytes

Provided

Internal memory capacity

selection register (IMS)

IC pin

Provided

Not provided

Provided

VPP pin

Not provided

Electrical characteristics

Refer to data sheet of individual products.

19

CHAPTER 2 OUTLINE OF µPD784915 SUBSERIES

2.1 Features and Application Fields

(1) Features

Minimum instruction execution time: 250 ns (operation when internal clock = 8 MHz)

•

On-chip timer unit for VCR servo control (Super timer unit)

I/O ports: 54

On-chip VHS-compliant VCR analog circuits

•

CTL amplifier

•

DPG comparator

RECCTL driver (rewrite-capable)

CFG amplifier

DPFG separation circuit (3-value separation circuit)

Reel FG comparator (2 channels)

CSYNC comparator

DFG amplifier

Serial interface: 2 channels (3-wire serial I/O)

•

A/D comparator: 8-bit resolution × 12 channels (conversion time: 10 µs)

PWM output: 16-bit resolution × 3 channels, 8-bit resolution × 3 channels

Interrupt functions

•

Vectored interrupt function

Macro service function

Context switching function

Low-frequency oscillation mode supported: main system clock frequency = internal clock frequency

Low-power-dissipation mode supported: CPU operation using subsystem clock possible

Power supply voltage: VDD = 2.7 to 5.5 V

•

On-chip hardware clock function: Low voltage (VDD = 2.7 V (MIN.)), low-current-dissipation clock operation

possible

(2) Application fields

System/servo/timer control for VCR (stationary type, camcorder)

20

CHAPTER 2 OUTLINE OF µPD784915 SUBSERIES

2.2 Pin Configuration (Top View)

•

100-pin plastic QFP (14 × 20 mm)

µPD784915GF-×××-3BA, 784915AGF-×××-3BA, 784916AGF-×××-3BA,

µPD784915BGF-×××-3BA, 784916BGF-×××-3BA, 78P4916GF-3BA

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

P64

P65/HWIN

P66/PWM4

P67/PWM5

P60/STRB/CLO

P61/SCK1/BUZ

P62/SO1

1

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

ANI9

2

ANI8

3

P77/ANI7

P76/ANI6

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

P71/ANI1

P70/ANI0

AV^REF

4

5

6

7

P63/SI1

8

PWM0

9

PWM1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

SCK2

SO2

AVDD2

SI2/BUSY

P96

VDD

P95/KEY4

P94/KEY3

P93/KEY2

P92/KEY1

P91/KEY0

P90/ENV

NMI

XT1

XT2

V

SS

X2

X1

RESET

IC (V^PP

)

INTP0

PTO02

PTO01

INTP1

INTP2

PTO00

P00

P87/PTO11

P86/PTO10

P85/PWM3

P84/PWM2

P83/ROTC

P82/HASW

P01

P02

P03

P04

P05

P06

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Caution

Connect IC (Internally Connected) pin directly to V^SS.

Remark ( ): µPD78P4916

21

CHAPTER 2 OUTLINE OF µPD784915 SUBSERIES

ANI0 to ANI11

AV^DD1, AVDD2

AV^SS1, AVSS2

AVREF

: Analog Input

P00 to P07

P40 to P47

P50 to P57

P60 to P67

P70 to P77

P80, P82 to P87

: Port0

: Analog Power Supply

: Analog Ground

: Port4

: Port5

: Analog Reference Voltage

: Serial Busy

: Port6

BUSY

: Port7

BUZ

: Buzzer Output

: Port8

CFGAMPO

CFGCPIN

CFGIN

: Capstan FG Amplifier Output P90 to P96

: Port9

: Capstan FG Capacitor Input

: Analog Unit Input

: Clock Output

PTO00 to PTO02,

: Programmable Timer Output

PTO10, PTO11

PWM0 to PWM5

CLO

: Pulse Width Modulation Output

CSYNCIN

CTLDLY

CTLIN

: Analog Unit Input

: Control Delay Input

RECCTL+, RECCTL– : RECCTL Output/PBCLT Input

REEL0IN, REEL1IN : Analog Unit Input

: CTL Amplifier Input Capacitor RESET

: Reset

CTLOUT1, CTLOUT2 : CTL Amplifier Output

ROTC

: Chrominance Rotate Output

: Serial Clock

DFGIN

DPGIN

ENV

: Analog Unit Input

: Envelope Input

SCK1, SCK2

SI1, SI2

: Serial Input

SO1, SO2

: Serial Output

HASW

: Head Amplifier Switch Output STRB

: Hardware Timer External Input V^DD

: Serial Strobe

HWIN

: Power Supply

IC

: Internally Connected

: Interrupt From Peripherals

: Key Return

VREFC

V^SS

: Reference Amplifier Capacitor

: Ground

INTP0 to INTP3

KEY0 to KEY4

NMI

X1, X2

XT1, XT2

: Crystal (Main System Clock)

: Crystal (Subsystem Clock)

: Non-maskable Interrupt

22

CHAPTER 2 OUTLINE OF µPD784915 SUBSERIES

2.3 Block Diagram

NMI

V^DD

VSS

X1

INTERRUPT

CONTROL

INTP0 to INTP3

X2

XT1

XT2

RESET

PWM0 to PWM5

PTO00 to PTO02

PTO10 and PTO11

SYSTEM

CONTROL

SUPER TIMER

UNIT

D0 to D7

A0 to A16

CE

OE

PGM

V^PP

VREFC

REEL0IN

REEL1IN

CSYNCIN

DFGIN

CLOCK OUTPUT

BUZZER OUTPUT

CLO

BUZ

DPGIN

CFGIN

CFGAMPO

CFGCPIN

CTLOUT1

CTLOUT2

CTLIN

78K/IV

16-bit CPU CORE

KEY INPUT

KEY0 to KEY4

RECCTL +

RECCTL –

CTLDLY

P00 to P07

AV^DD1and AVDD2

AVSS1 and AVSS2

AVREF

ANALOG UNIT

&

A/D CONVERTER

REAL - TIME

OUTPUT PORT

P80, P82, P83

ANI0 to ANI11

PORT0

PORT4

PORT5

PORT6

PORT7

PORT8

PORT9

P00 to P07

P40 to P47

P50 to P57

P60 to P67

P70 to P77

P80, P82 to P87

P90 to P96

RAM

ROM

SI1

SO1

SERIAL

INTERFACE 1

SCK1

SI2/BUSY

SO2

SERIAL

INTERFACE 2

SCK2

STRB

Remarks 1. Internal ROM capacity and RAM capacity differ depending on the product.

2. The broken line indicates the connection in PROM programming mode.

23

CHAPTER 2 OUTLINE OF µPD784915 SUBSERIES

2.4 Outline of Functions

Part Number

µPD784915, 784915A,

µPD784915B

µPD784916A,

µPD784916B

µPD78P4916

Parameter

Instructions

113

Minimum instruction execution time

Internal ROM capacity

250 ns (internal clock: 8 MHz)

Mask ROM

One-time PROM

2048 bytes

48 Kbytes

1280 bytes

62 Kbytes

Internal RAM capacity

Interrupt

4-level (programmable), vectored interrupts, macro service, context switching

External source

Internal source

9 (including NMI)

19

Macro service available interrupt 25

Number of macro service 10 (4 types)

I/O ports

Input

I/O

8

46

Time-based counter

• 22-bit FRC

• Resolution: 125 ns, maximum count time: 524 ms

Capture register

Input Signal

CFG

Number of Bits

Measurement Cycle Operation Edge

22

16

22

16

22

125 ns to 524 ms

1 µs to 65.5 ms

125 ns to 524 ms

1 µs to 65.5 ms

125 ns to 524 ms

↑

↓

DFG

HSW

↓

VSYNC

CTL

↓

TREEL

SREEL

General-purpose timer

16-bit timer × 3

PBCTL duty discrimination

• Duty discrimination for Play control signal

• VISS detection, wide aspect detection

Linear time counter

Real-time output port

Serial interface

A/D converter

CTL signal counting with 5-bit UDC

11

Clock synchronous (3-wire): 2 channels

8-bit resolution × 12 channels, conversion time: 10 µs

PWM output

• 16-bit resolution × 3 channels, 8-bit resolution × 3 channels

• Carrier frequency: 62.5 kHz

Clock function

Standby function

Analog circuits

0.5-second measurement, low-voltage operation possible

HALT mode/STOP mode/Low power dissipation mode/Low power dissipation HALT mode

• CTL amplifier

• DPG comparator

• RECCTL driver (rewrite-capable)

• DPFG separation circuit

(3-value separation circuit)

• Reel FG comparator

• CSYNC comparator

• CFG amplifier

• DFG amplifier

Power supply voltage

Package

VDD = 2.7 to 5.5 V

100-pin plastic QFP (14 × 20 mm)

24

CHAPTER 3 OUTLINE OF µPD784928, 784928Y SUBSERIES

The µPD784928, 784928Y Subseries under the 78K/IV Series of products with an on-chip high-speed, high-

performance 16-bit CPU consists of products for VCR software servo control.

The µPD784928, 784928Y Subseries provides on chip optimum peripheral hardware for VCR control, including

a multifunction timer unit (super timer unit) ideal for software servo control, and analog circuits, thus enabling the

realization of VCR system/servo/timer control with a single chip.

Moreover, products with on-chip flash memory, the µPD78F4928 and 78F4928Y, are now under development.

This chapter describes the µPD784927 as the representative product.

Table 3-1. Differences among µPD784928, 784928Y Subseries Products

Note

Part Number

µPD784927,

µPD784927Y

µPD78F4928

,

Note

Parameter

µPD78F4928Y

Internal ROM capacity

Internal RAM capacity

96 Kbytes (Mask ROM)

128 Kbytes (Flash memory)

3584 bytes

2048 bytes

Internal memory capacity

selection register (IMS)

Not provided

Provided

IC pin

Provided

Not provided

Provided

VPP pin

Not provided

Electrical characteristics

Refer to data sheet of individual products.

Note Under development

25

CHAPTER 3 OUTLINE OF µPD784928, 784928Y SUBSERIES

3.1 Features and Application Fields

(1) Features

Minimum instruction execution time: 250 ns (operation when internal clock = 8 MHz)

•

On-chip timer unit for VCR servo control (Super timer unit)

I/O ports: 74

On-chip VHS-compliant VCR analog circuits

•

CTL amplifier

•

DPG amplifier

RECCTL driver (rewrite-capable)

CFG amplifier

DPFG separation circuit (3-value separation circuit)

Reel FG comparator (2 channels)

CSYNC comparator

DFG amplifier

Serial interface: 3 channels

•

3-wire serial I/O: 2 channels

I²C bus interface: 1 channel (µPD784928Y Subseries only)

A/D converter: 12 channels (conversion time: 10 µs)

PWM output: 16-bit resolution × 3 channels, 8-bit resolution × 3 channels

Interrupt functions

•

Vectored interrupt function

Macro service function

Context switching function

Low-frequency oscillation mode supported: main system clock frequency = internal clock frequency

Low-power-dissipation mode supported: CPU operation using subsystem clock possible

Power supply voltage: VDD = 2.7 to 5.5 V

•

On-chip hardware clock function: Low voltage (VDD = 2.7 V (MIN.)), low-current-dissipation clock operation

possible

(2) Application fields

Stationary type VCRs, camcorders, etc.

26

CHAPTER 3 OUTLINE OF µPD784928, 784928Y SUBSERIES

3.2 Pin Configuration (Top View)

•

100-pin plastic QFP (14 × 20 mm)

µPD784927GF-×××-3BA, 78F4928GF-3BA^{Note 1}

µPD784927YGF-×××-3BA, 78F4928YGF-3BA^{Note 1}

,

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81

80

DFGMON/P64/BUZ

DPGMON/P65/HWIN

CFGMON/P66/PWM4

CTLMON/P67/PWM5

P60/STRB/CLO

P61/SCK1/BUZ

P62/SO1

1

ANI9/P111

ANI8/P110

P77/ANI7

P76/ANI6

P75/ANI5

P74/ANI4

P73/ANI3

P72/ANI2

P71/ANI1

P70/ANI0

AV^REF

2

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

3

4

5

6

7

P63/SI1

8

P37/PWM0

9

P36/PWM1

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

P35/SCK2

P34/SO2

AVDD2

P33/SI2/BUSY

P96

VDD

P95/KEY4

P94/KEY3

P93/KEY2

P92/KEY1

P91/KEY0

P90/ENV

NMI/P20

INTP0/P21

INTP1/P22

INTP2/P23

P00

XT1

XT2

V

SS

X2

X1

RESET

Note 2

IC/V^PP

P32/PTO02

P31/PTO01

P30/PTO00

P87/PTO11

P01

P86/PTO10

P02

SCL^{Note 3}/P85/PWM3

SDA^{Note 3}/P84/PWM2

P83/ROTC

P03

P04

P05

P82/HASW

P06

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

Notes 1. Under development

2. The VPP pin is provided only for the µPD78F4928, 78F4928Y.

3. The SCL pin and SDA pin are provided only for the µPD784928Y Subseries.

Caution

In the normal operation mode, connect the IC (Internally Connected)/V^PPpin directly to VSS.

27

CHAPTER 3 OUTLINE OF µPD784928, 784928Y SUBSERIES

ANI0 to ANI11

AV^DD1, AVDD2

AV^SS1, AVSS2

AVREF

: Analog Input

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P77

P80, P82 to P87

: Port3

: Analog Power Supply

: Analog Ground

: Port4

: Port5

: Analog Reference Voltage

: Serial Busy

: Port6

BUSY

: Port7

BUZ

: Buzzer Output

: Port8

CFGAMPO

CFGCPIN

CFGIN

: Capstan FG Amplifier Output P90 to P96

: Port9

: Capstan FG Capacitor Input

: Analog Unit Input

P100 to P103

: Port10

P110 to P113

: Port11

CFGMON

CLO

: Capstan FG Monitor

: Clock Output

PTO00 to PTO02,

PTO10, PTO11

PWM0 to PWM5

: Programmable Timer Output

CSYNCIN

CTLDLY

CTLIN

: Analog Unit Input

: Pulse Width Modulation Output

: Control Delay Input

RECCTL+, RECCTL– : RECCTL Output/PBCLT Input

: CTL Amplifier Input Capacitor REEL0IN, REEL1IN : Analog Unit Input

CTLMON

: CTL Amplifier Monitor

RESET

: Reset

CTLOUT1, CTLOUT2 : CTL Amplifier Output

ROTC

: Chrominance Rotate Output

: Serial Clock

DFGIN

: Analog Unit Input

: DFG Monitor

SCK1, SCK2

SCL^{Note 1}

SDA^{Note 1}

SI1, SI2

DFGMON

DPGIN

: Serial Clock

: Analog Unit Input

: DPG Monitor

: Serial Data

DPGMON

ENV

: Serial Input

: Envelope Input

SO1, SO2

: Serial Output

HASW

: Head Amplifier Switch Output STRB

: Hardware Timer External Input V^DD

: Serial Strobe

HWIN

: Power Supply

Note 2

IC

: Internally Connected

: Interrupt From Peripherals

: Key Return

V^PP

: Programming Power Supply

: Reference Amplifier Capacitor

: Ground

INTP0 to INTP3

KEY0 to KEY4

NMI

VREFC

V^SS

: Non-maskable Interrupt

: Port0

X1, X2

XT1, XT2

: Crystal (Main System Clock)

: Crystal (Subsystem Clock)

P00 to P07

P20 to P23

: Port2

Notes 1. The SCL pin and SDA pin are provided only for the µPD784928Y Subseries.

2. The VPP pin is provided only for the µPD78F4928, 78F4928Y.

28

CHAPTER 3 OUTLINE OF µPD784928, 784928Y SUBSERIES

3.3 Internal Block Diagram

NMI

V

X1

DD

SS

INTERRUPT

CONTROL

INTP0 to INTP3

X2

SYSTEM

XT1

XT2

CONTROL

PWM0 to PWM5

PTO00 to PTO02

PTO10, PTO11

RESET

Note 1

SUPER TIMER

UNIT

VPP

CLOCK OUTPUT

BUZZER OUTPUT

CLO

BUZ

VREFC

REEL0IN

REEL1IN

CSYNCIN

DFGIN

KEY INPUT

KEY0 to KEY4

DPGIN

CFGIN

CFGAMPO

CFGCPIN

CTLOUT1

CTLOUT2

CTLIN

78K/IV

16-bit CPU CORE

(RAM : 512 bytes)

P00 to P07

REAL - TIME

OUTPUT PORT

P80, P82, P83

RECCTL+

_

RECCTL

CTLDLY

DFGMON

DPGMON

CFGMON

CTLMON

AV^DD1, AVDD2

AVSS1, AVSS2

AVREF

PORT0

PORT2

PORT3

PORT4

PORT5

PORT6

PORT7

PORT8

PORT9

PORT10

PORT11

P00 to P07

P20 to P23

P30 to P37

P40 to P47

P50 to P57

P60 to P67

P70 to P77

P80, P82 to P87

P90 to P96

P100 to P103

P110 to P113

ANALOG UNIT

&

A/D CONVERTER

RAM

ROM

ANI0 to ANI11

SI1

SO1

SERIAL

INTERFACE 1

SCK1

SI2/BUSY

SO2

SERIAL

INTERFACE 2

SCK2

STRB

SDA

SCL

SERIAL^{Note 2}

INTERFACE 3

Notes 1. The VPP pin is provided only for the µPD78F4928, 78F4928Y.

2. Provided only for the µPD784928Y Subseries. Supports the I²C bus interface.

Remark The internal ROM and RAM capacities differ according to the product.

29

CHAPTER 3 OUTLINE OF µPD784928, 784928Y SUBSERIES

3.4 Outline of Functions

(1/2)

Note

Part Number

µPD784927,

µPD784927Y

µPD78F4928

,

Note

Parameter

µPD78F4928Y

Instructions

113

Minimum instruction execution time

250 ns (internal clock: 8 MHz)

Mask ROM

Internal memory capacity Type

Flash memory

ROM

RAM

96 Kbytes

128 Kbytes

3584 bytes

2048 bytes

Interrupt sources

External 9 (including NMI)

(µPD784928 Subseries)

Internal

22 (including software interrupts)

• 4-level programmable priority

• 3 types of servicing:

Vectored interrupts, macro service, context switching

External 9 (including NMI)

Internal 23 (including software interrupts)

Interrupt sources

(µPD784928Y Subseries)

• 4-level programmable priority

• 3 types of servicing:

Vectored interrupts, macro service, context switching

I/O ports

Input

I/O

20

54 (including 8 LED direct drive ports)

Time-based counter

• 22-bit FRC

• Resolution: 125 ns, maximum count time: 524 ms

Capture register

Input Signal

CFG

Number of Bits

Measurement Cycle Operation Edge

22

16

22

16

22

125 ns to 524 ms

1 µs to 65.5 ms

125 ns to 524 ms

1 µs to 65.5 ms

125 ns to 524 ms

↑

↓

DFG

HSW

↓

VSYNC

CTL

↓

TREEL

SREEL

General-purpose timer

16-bit timer × 3

PBCTL duty discrimination

• Duty discrimination for Play control signal

• VISS detection, wide aspect detection

Linear time counter

Real-time output port

Serial interface

CTL signal counting with 5-bit UDC

11

• 3-wire serial I/O: 2 channels (including 1 BUSY/STRB function-enabled channel)

2

• I C bus interface (multi-master supported): 1 channel (µPD784928Y Subseries only)

Buzzer output function

1.95 kHz, 3.91 kHz, 7.81 kHz, 15.6 kHz (Operation when internal clock = 8 MHz)

2.048 kHz, 4.096 kHz, 32.768 kHz (Operation when subsystem clock = 32.768 kHz)

A/D converter

PWM output

8-bit resolution × 12 channels, conversion time: 10 µs

• 16-bit resolution × 3 channels, 8-bit resolution × 3 channels

• Carrier frequency: 62.5 kHz

Clock function

0.5-second measurement, low-voltage operation possible (VDD = 2.7 V)

Standby function

HALT mode/STOP mode/Low power dissipation mode/Low power dissipation HALT mode

Note Under development

30

CHAPTER 3 OUTLINE OF µPD784928, 784928Y SUBSERIES

(2/2)

Note

Part Number

µPD784927,

µPD784927Y

µPD78F4928

,

Note

Parameter

µPD78F4928Y

Analog circuits

• CTL amplifier

• DPG amplifier

• RECCTL driver (rewrite-capable)

• DPFG separation circuit

(3-value separation circuit)

• Reel FG comparator

• CSYNC comparator

• CFG amplifier

• DFG amplifier

Power supply voltage

Package

VDD = 2.7 to 5.5 V

100-pin plastic QFP (14 × 20 mm)

Note Under development

31

CHAPTER 3 OUTLINE OF µPD784928, 784928Y SUBSERIES

3.5 Differences among µPD784928, 784928Y Subseries and µPD784915 Subseries

The µPD784927 is a VCR software servo control product that includes on-chip a high-speed, high-performance

16-bit CPU, enabling the realization of VCR system/servo/timer control with a single chip. The µPD784928 Subseries

is an enhanced function version of the µPD784915 Subseries. Moreover, the µPD784928Y Subseries is a product

featuring the addition of the I²C bus interface.

Table 3-2 shows the differences among these three subseries.

Table 3-2. Differences among µPD784928, 784928Y Subseries and µPD784915 Subseries

Parameter

µPD784928 Subseries,

µPD784928Y Subseries

µPD784915 Subseries

Internal ROM capacity

Internal RAM capacity

96 Kbytes/128 Kbytes

48 Kbytes/62 Kbytes

2048/3584 bytes

1280/2084 bytes

I/O ports

Total

Input

I/O

74

54

20

8

54

46

Serial interface

• 3-wire serial I/O

: 2 channels

: 1 channel

• 3-wire serial I/O : 2 channels

2

Note

• I C bus interface

Analog

circuit

CTL amplifier

√

RECCTL driver

DPFG separation circuit

DFG amplifier

√

DPG comparator

DPG amplifier

CFG amplifier

√

—

√

Reel FG comparator

CSYNC comparator

External

√

Interrupt

9 (including NMI)

19 (including software interrupts)

Internal

22 (including software interrupts)

23 (including software interrupts)

Note

Flash memory/PROM

µPD78F4928, 78F4928Y

µPD78P4916

Note In the case of the µPD784928Y Subseries

32

CHAPTER 4 OUTLINE OF VCR SERVO SYSTEM

4.1 Outline of Software Servo

In the current VCR market, software servo has become the mainstream in VCR servo systems in order to reduce

the manufacturing process and improve the reliability of sets. High-performance microcontrollers which can control

the whole system with a single chip have been called for to simplify the manufacturing process and lower costs by

reducing the number of parts. On the other hand, along with the trend toward sets with high performance and a many

functions, microcontrollers with larger memory capacity are increasingly being used.

Analog control servo systems, which have conventionally been the mainstream in VCR servos, present the

following problems:

(1) Reliability

The analog servo system uses many components whose characteristics are affected by external environment,

such as resistors and capacitors, which makes it difficult to keep the characteristics constant over a long period

of time. Moreover, analog servo systems tend to have changing characteristics over-time, which affects

reliability.

(2) System adjustment

Due to the uneven characteristics of the resistors/capacitors, a lot of adjustments are required prior to shipment

in order to gain desired characteristics.

(3) Number of parts

Analog servos have a large number of parts, which makes it difficult to reduce the size of sets.

VCR servo systems, then, have switched over to digital servos with dedicated ICs. However, servos with dedicated

ICs cannot perform flexible control because the servo control algorithm is fixed, and it cannot integrate compensation

elements such as digital filter into a device.

In order to solve the above problems, software digital servos using single-chip microcontrollers have come into

increasing use in recent years.

Realizing VCR servo systems by software offers the following advantages:

<1> Improved reliability

Because software digital servo systems carry out control using the CPU system clock as a reference, stable

operation free from environmental conditions can be realized.

Moreover, software digital servos convert all error amounts to digital values and store them in memory,

resulting in accurate sample-and-hold operation. Therefore, unlike analog servo systems, hold values do

not change due to capacitor leak.

33

CHAPTER 4 OUTLINE OF VCR SERVO SYSTEM

<2> Compactness and light weight

The number of discrete parts is minimized to enable high-density mounting (reduced mounting space).

Moreover, compensation filter is realized as a digital filter, resulting in improved reliability as well as reduction

of the number of parts.

<3> Flexible of servo control

Software servos can freely change servo system gain according to the amount of speed error/phase error.

Moreover, trick plays such as suspension of control and open loop control for a given time period according

to the error amount can be easily realized. Also, AI-related functions such as digital tracking can be

integrated.

<4> Easy product development of VCR set

Software servos easily keep up with changes of the drum motor and capstan motor to be used simply by

changing software. As a result, design with a high degree of freedom is made possible.

Software servos flexibly support various TV broadcasting systems in the world (such as NTSC and PAL),

enabling worldwide use of VCR sets.

To realize software servo control of a VCR, the microcontroller to be used is required to have an advanced arithmetic

ability and strong timer function.

In order to easily realize servo control, the µPD784915 Subseries incorporates a variety of peripheral hardware

such as the super timer unit and analog circuits for VCR, which are ideal for software servo control of VCRs. By

incorporating a 16-bit CPU, the µPD784915 supports high-speed arithmetic instructions and large capacity memory.

Therefore, it can easily handle servo processing, which must be real-time, and makes system/servo/timer control of

VCRs possible with a single chip.

4.2 Servo Control of VCR

A VCR records video signals forming diagonal patterns on magnetic tape (video tape) using a rotary head. This

recording method is called rotary head azimuth recording system.

The recorded pattern of the video signals on the magnetic tape is strictly specified with each format such as VHS

system and β system.

Figure 4-1 shows the track pattern of video tapes.

The recording pattern of video signals is as thin as several tens of microns. During VCR playback, the head must

accurately trace the recording pattern. This operation is called tracking.

Forming of the recording pattern and playback tracking are controlled by the rotating condition of the rotary head

and the running condition of the tape.

A VCR has a drum motor to control the rotation of the rotary head and a capstan motor to control tape running.

The VCR carries out record/playback by controlling these two motors.

The servo for recording and playback is explained below.

34

CHAPTER 4 OUTLINE OF VCR SERVO SYSTEM

Figure 4-1. Track Pattern on Video Tape

One field’s

video signal

Audio head

Audio track

Head

direction

Video track

Vertical synchronous

signal

Control track

Tape running direction

Playback control signal

Control head

Remark VHS standard tape speed

Standard mode : 33.35 mm/s

Triple mode

: 11.12 mm/s

35

CHAPTER 4 OUTLINE OF VCR SERVO SYSTEM

4.3 Servo for Recording

A VCR records exactly one field’s video signals on each video track recorded diagonally on a video tape. In TV

broadcasting, a frame is composed of two fields.

On a video track, positions on which synchronous signals are recorded are specified. Therefore, control should

be made so that the recording drum motor servo synchronizes with the frame cycle of the input video signal and the

relation of the position of the video head and vertical synchronous signal are kept constant.

On the other hand, the capstan motor rotates at constant speed because it runs tape accurately at the speed defined

in each format.

In addition to these, home VCRs of VHS and β system, etc., record control signals synchronized with the rotation

of the drum along with the longer direction of the tape when recording is performed.

Control signal is a pulse signal with 30 [Hz] cycle which is used as a mark when performing playback tracking.

Remarks 1. Video tape running speed of VHS system VCR is 33.35 [mm/s] in standard mode and 11.12 [mm/s] in

triple mode.

2. For VHS system VCRs, control signal pulse is normally specified as a signal with 60% high level and

40% low level.

4.4 Servo for Playback

When playing back, rotation of a drum motor and control signals played back from the video tape is synchronized

with the reference frame cycle generated in the servo control circuit.

Thereby, the drum motor and the control signals are synchronized indirectly using the reference signal as an

intermediary so that the relation between them are made the same as when recording.

As a result, the head is controlled to accurately trace the track on the tape, because the running condition of the

tape and the rotation of the head become the same as when recording.

In addition, because the recording condition of the control signals are uneven among sets, it needs to be corrected.

Thereby, the relation of the position of the control signals and the video head can be externally adjusted. This is called

tracking adjustment. When playing back, the amount of the tracking adjustment is set using an external potentiometer

(VR).

36

CHAPTER 4 OUTLINE OF VCR SERVO SYSTEM

4.5 Motor to be Used

Generally, a DC motor is used for VCRs (drum motor and capstan motor). DC motors are motors whose rotation

speed varies according to the applied voltage.

Direct drive systems, in which no belts and gears are involved, are becoming the mainstream in the driving method

of drum and capstan.

The rotation speed of DC motors fluctuates according to variations in the load and the applied voltage. Therefore,

servo systems must control the rotation speed and rotation phase.

Rotation speed control keeps the motor rotation constant. Rotation phase control keeps the relationship between

the phase signal and reference phase signal of the motor constant.

37

CHAPTER 4 OUTLINE OF VCR SERVO SYSTEM

4.6 VCR Control Systems

VCRs are mainly composed of the following control systems.

(1) System control

Supervises and controls the whole VCR system.

(2) Servo control

Controls drum motor, capstan motor, and related operations.

(3) Timer control

Performs clock function such as timer reservation, front panel control, and display control.

(4) Camera control (camcorder)

Performs camera section control such as AF and AE.

(5) Others

Blurring correction control, etc. (camcorder).

The µPD784915 is a 16-bit single-chip microcontroller which can perform the three types of control (1) to (3) listed

above.

Especially, the super timer unit incorporated in the µPD784915 is designed to easily realize software digital servo

control.

4.7 VCR Servo System Control

Servo systems for VCRs control the drum motor for the rotating head and the capstan motor, which runs the tape

in low speed.

The VCR elements controlled by a servo system are shown below.

(1) Drum motor speed/phase control

(2) Capstan motor speed/phase control

(3) Generation of head switching signal

(4) Generation of quasi-V^SYNCsignal for special playback

(5) Generation of recording control signal (RECCTL) (for recording), rewriting (for playback)

(6) Index search control (VISS detection)

Remark This manual mainly explains the method to perform servo control shown in 4.6 (2) and other controls shown

in 4.7 (1) to (6).

38

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

This chapter describes examples of stationary type VCR servo system control.

5.1 Examples of System Configuration

In this chapter, the drum motor whose FG wave number (the number of FG signals generated in one rotation of

the motor) is 24 poles and the capstan motor whose FG wave number is 36 poles are assumed to be used.

The drum motor is controlled so that the number of rotations is equal to the frame frequency of TV broadcast f^F

= 29.97 Hz (NTSC) (the number of rotation is 29.97 r.p.s.) with the servo system locked.

Therefore, the drum FG signal frequency fDFG is as follows:

• f^DFG= fF × FG wave number = 719.28 [Hz]

Similarly, the capstan motor FG frequency in standard mode (SP mode) is as follows:

• f^CFGSP= 1080 [Hz]

The capstan motor FG frequency in triple mode (EP mode), since it is one third the speed of the standard mode,

is as follows:

• f^CFGSP= 1080 ÷ 3 = 360 [Hz]

Each motor is driven by PWM output pulse smoothed in external circuit and input to motor driving driver.

PWM0 output is used for driving the drum motor and PWM1 output for capstan motor.

PWM output pulse is smoothed (carrier elimination) through external low pass filter (C-R filter, etc.), impedance

converted with operation amplifier, etc., and then input to motor driving driver.

Figure 5-1 shows an example of VCR system configuration to be controlled in this manual.

39

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-1. Application to Stationary Type VCR

µPD784915

DFG

DFGIN

STB

CLK

DOUT

DIN

PORT

SCK1

SI1

DPGIN

PWM0

CFGIN

DPG

CFG

FIP C/D

µPD16311

SO1

Drum motor

M

FIP

Key matrix

Capstan motor

PWM1

PORT

SCK2

SO2

CS

OSD

µPD6454

CLK

DATA

RECCTL+

RECCTL–

CTL head

PORT

Composite synchronizing signal

Audio video system

signal processing circuit

CSYNCIN

PTO00

PTO01

P80

Video head switch

Audio head switch

Quasi-vertical synchronizing signal

Loading motor

M

PWM2

ReelFG0

REEL0IN

PWM3

PWM5

PORT

Tuner

M

Reel motor

PORT

INTP2

Mechanical block

PWM4

Remote control

receive signal

Remote

control signal

ReelFG1

REEL1IN

µPC2800A

Low-frequency

oscillation mode

X1

X2

XT1

XT2

8 MHz

32.768 kHz

40

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.2 Outline of System

This system performs VCR servo control using the µPD784915.

The system executes most of the dedicated digital servo IC functions which have been built in the original sets

by software. Moreover the system configures the loop filter, which is a compensation element of the servo system,

with a digital filter and realizes it with arithmetic processing by software.

Figure 5-2 shows the processing block diagram in the software digital servo system.

The VCR servo system performs speed/phase control of the drum and capstan motor. Therefore, speed control

loop and phase control loop exist in the control loop of each motor.

The FG signal output from the motor is used for detection of the speed error amount and PG signal for detection

of the phase error amount. The gains of speed control system and phase control system are set independently from

each other.

The detected speed and phase error amount are added respectively and then converted to PWM with bias value

added. PWM pulse drives each motor after carriers are eliminated through external low pass filter.

The µPD784915 is equipped with analog amplifiers so that amplification of FG and PG signal output from each

motor is possible.

The value of the servo circuit built in the set is used as it is for the error amount detection gain and the characteristics

of loop filter in the servo system.

In addition to the speed/phase control of drum and capstan motor explained above, the system also generates

head switching signal, quasi vertical synchronizing signal, etc.

41

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.3 Using Example of Super Timer Unit

Table 5-1 shows the using examples of the Super Timer Unit, and Figure 5-1 shows the Super Timer Unit block

diagram.

Table 5-1. Using Examples of Super Timer Unit

Timer/Counter Name

Event Counter (EC)

Register

Use

ECC0/ECC1/ECC2/ECC3

Generation of internal head switching signal

Video head switching signal delay control

Timer 0 (TM0)

CR00

CR01

Audio head switching signal delay control

CR02

Quasi-VSYNC output timing control

Free Running Counter (FRC)

CPT0

Reference phase detection (for drum phase control)

Drum motor phase detection (for drum phase control)

Drum motor speed detection (for drum speed control)

Capstan motor speed detection (for capstan speed control)

Tape remain detection by reel FG input

CPT1

CPT2

CPT3

CPT4, CPT5

CR10

Timer 1 (TM1)

Generation of internal reference signal (for playback)

Buffer oscillator for missing VSYNC (for recording)

CR11

CR12

RECCTL output timing control

Capstan motor phase control

(for capstan phase controller)

CR13

Unnecessary VSYNC input mask control

PBCTL signal duty detection timing control

PBCTL signal cycle measurement

Timer 3 (TM3)

CR30, CR31

CPT30

CR20

Timer 2 (TM2)

Timer 4 (TM4)

Can be used as an interval timer (for system controller)

CR40

Remote control signal duty detection

(for remote control decode)

CR41

CR50

UDCC

Remote control signal cycle measurement

(for remote control decode)

Timer 5 (TM5)

Can be used as internal timer

(for system controller)

Up/Down Counter

Generation of linear tape counter

43

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-3. Super Timer Unit Block Diagram (2/2)

Clear

TM2

CR20

INTCR20

Mask

Clear

TM4

Remote control

receive signal

CR40

CR41

INTCR40

INTP2

Clear

TM5

CR50

INTCR50

RTP, A/D

SELUD

P77

PTO10

PTO11

UP/DOWN

EDVCoutput

PBCTL

UDC

UDCC

INTUDC

45

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.4 Head Switching Signal Generation

5.4.1 Internal head switching signal (HSW-N) generation

(a) HSW-N generation method

This system uses timer 0 clear pulse as phase comparison signal in the drum phase control system. This

is called internal head switching signal (HSW-N).

HSW-N is a pulse with 50% duty which is generated from PG and FG signals from the drum motor and

synchronizes with the drum rotation.

µPD784915 can generate HSW-N from drum FG signal (DFG signal) and drum PG signal (DPG signal) using

event counter (EC).

The DPG signal is input to the DPGIN pin and the DFG signal to the DFGIN pin of the µPD784915.

The pulse generated here is one which is reset, after DPG input, at the rising edge of the second DFG signal

and at the falling edge of the fourteenth DFG signal. In this case, the following values are set to the two compare

registers of EC.

ECC1...01H

ECC0...0DH

EC output changes at the clock after the clock at which the EC coincides with the compare register. Therefore,

the value with 1 subtracted is set as the setting value to the compare register.

Figure 5-4 shows the use of EC, and Figure 5-5 shows the operation timing of EC. Timer 0 is cleared at the

rising and falling edges of HSW-N generated in EC.

Figure 5-4. Use of Event Counter (EC)

DPGsignal

DPGIN

DFGIN

Through

EC

00H write to EC

Analog

circuit

Clear

DFGsignal

ECC3 = 00H

ECC2 = 00H

ECC1 = 01H

ECC0 = 0DH

Internal head

switching signal

(HSW-N)

S

R

Q

Coincidence

EC-

F/F1

46

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.4.2 Head switching signal (V-HSW) generation

(a) V-HSW generation method

A VCR is required to externally adjust the head switching signal (V-HSW) and correct the mounting position

of the PG signal detector. In order to perform the correction, the internal head switching signal (HSW-N)

generated as shown in 5.4.1 is delayed using timer 0 programmable pulse delay circuit.

Figure 5-6 shows the use of timer 0. Figure 5-7 shows the V-HSW timing. Timer 0 is a timer which is cleared

at both rising and falling edges of HSW-N.

When a digital value equivalent to the amount of the head switching signal delay is set to compare register

00 (CR00), signals with HSW-N are delayed according to the value set to the compare register are output from

the PTO00 output pin. This signal is used as the actual V-HSW.

The relation between the digital value set to CR00 and the delay amount is as follows:

Delay amount = (Setting value to CR00) × 8/f^CLK

At 16-MHz operation, 8/fCLK = 1 [µs], then, this is the resolution of timer 0.

In order to correct the positional relation of the PG signal detector and PG magnet, the delay amount to HSW-

N should be externally adjustable. Thereby, the data stored in CR00 should be adjustable with analog voltage

externally input using the A/D comparator of the µPD784915.

The digital value stored in CR00 is set as follows:

In EP mode/ LP mode

•

(Setting value to CR00) = (A/D conversion result) × 11 + 012CH

In SP mode

•

(Setting value to CR00) = (A/D conversion result) × 13 + 0190H

When using analog circuit, EC is counted at the reverse edge of the DFG signal, so that correction is required

as follows:

In EP mode/LP mode

•

(Setting value to CR00) = (A/D conversion result) × 11 + 0120H

In SP mode

•

(Setting value to CR00) = (A/D conversion result) × 13 + 0150H

48

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-6. Use of Timer 0

EN

CLR0

DPGIN pin input

Internal pulse by EC

Internal head switching signal(HSW-N)

fCLK/8

TM0

Output control circuit

PTO00

INTCR00

V-HSW (CR00)

A-HSW (CR01)

Output control circuit

PTO01

INTCR01

PTO02

INTCR02

RTP

Quasi-V^SYNC(CR02)

H^SYNCseparation circuit

49

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-7. Head Switching Signal (V-HSW) Timing (PTO00)

29.97 Hz

(33.37 ms)

DPG signal input

(DPGIN pin)

2

131415

24

2

131415

2

DFG signal input

(DFGIN pin)

Internal head

switching signal

(HSW-N)

(16.68 ms)

(Clear)

CR00

ϒD1

Head switching

pulse signal

(V-HSW)

(PTO00 pin)

Remark τD1: Head switching signal delay amount

50

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

(b) Timer mode setting

The timer mode setting when generating head switching signal (V-HSW) is as shown in Figure 5-8 to 5-11.

Figure 5-8. Input Control Register (ICR) Format (when generating V-HSW)

7

6

5

4

3

2

1

0

Address

FF50H

After Reset

10H

R/W

ICR SELCLR0 ECFFLVL ECMOD ECFFCLR SELDPG1 SELDPG0

SELDPG1 SELDPG0 DPG Signal Frequency Division Specification

R/W

0

Do not divide

Reset FF1 and FF2 of EC when writing 0

(when reading, 1 is always read )

ECFFCLR

R/W

ECMOD Event Counter Operation Mode Selection

Internal pulse generation mode

1

ECFFLVL EC Output Pulse Level

R

SELCLR0 Timer 0 Clear Pulse Selection

R/W

1

EC output pulse

51

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-9. Timer 0 Output Mode Register (TOM0) Format (when generating V-HSW)

7

–

6

–

5

4

3

2

1

0

Address

FF58H

After Reset

R/W

W

TOM0

MOD021 MOD020 MOD011 MOD010 MOD001 MOD000

××000000

MOD001 MOD000 PTO00 Output Mode Specification

Delay pulse output mode 2

1

MOD0n1 MOD0n0 PTO0n Output Mode Specification (n=1, 2)

0

1

0

1

0

1

General-purpose output mode

RS output mode

Delay pulse output mode 1

Delay pulse output mode 2

Figure 5-10. Timer 0 Output Control Register (TOC0) Format (when generating V-HSW)

7

6

5

4

3

2

1

0

Address

FF59H

After Reset

00H

R/W

W

TOC0 ENHSY SELPTO ENTO02 ALV02 ENTO01 ALV01 ENTO00 ALV00

ALV00 PTO00 Timer Output Active Level Specification

Active high

1

ENTO00 PTO00 Timer Output Enable Specification

Output enabled

1

ALV0n PTO0n Timer Output Active Level Specification

(n = 1, 2)

0

1

Active low

Active high

ENTO0n PTO0n Timer Output Enable Specification

0

1

Output disabled (fixed to inactive level)

Output enabled

SELPTO

HSYNC Superimposition Pin Specification

0

1

Superimpose to PTO02

Superimpose to PTO01

ENHSY

HSYNC Superimposition Enable to PTO0n Pin Specification

0

1

Do not superimpose

Superimpose

52

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-11. Timer Control Register 0 (TMC0) Format (when generating V-HSW)

7

6

5

4

3

2

1

0

Address

FF38H

After Reset

00H

R/W

TMC0 CS1 SELFFLG ATMSK ENCLR1 CS0 INTTMSK

ENCLR0

ENCLR0 Timer 0 Clear Control

R/W

1

Clear TM0 with TM0 clear signal

INTTMSK

HSYNC Separation Circuit Initialization Flag

Initialize H^SYNCseparation circuit mask

period measurement counter when writing 1.

When reading, 0 is always read.

CS0 Timer 0 Operation

Count operation

R/W

1

ENCLR1 Timer 1 Clear Control

0

Mask CSYNC signal input.

TM1 is not cleared.

1

TM1 is cleared with CSYNC signal input

ATMSK CSYNC Signal Mask Auto Cancellation Control

R/W

0

CSYNC signal mask is not canceled with

TM1-CR13 coincidence signal

1

CSYNC signal mask is canceled (set ENCLR1)

with TM1- CR13 coincidence signal

SELFFLG

HSYNC Self Generation Condition

R

0

1

Self generation pulse is not output

Self generation pulse is output

CS1 Timer 1 Operation Control

R/W

0

1

Clear and stop counting

Count operation

53

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.4.3 Audio head switching signal (A-HSW) generation

(a) A-HSW generation method

A Hi-Fi VCR requires audio head switching signal (A-HSW) because it records audio signals on the video track

with a rotating head.

The audio head is tilted at 270° degrees against the video head, so that A-HSW is output at 270° degrees

against the head switching signal (V-HSW).

A-HSW is generated, as well as V-HSW, using timer 0 pulse delay circuit. The compare register uses CR01.

Figure 5-12. Assigning A-HSW to Timer 0

HSW-N

Clear

f

CLK/8

TM0

Coincidence

CR00

CR01

PTO00 (V-HSW signal)

PTO01 (A-HSW signal)

A-HSW is tilted at 270° degrees, so that correction of more than 180° degrees is necessary. The delay pulse

output mode 1 is used for 180°-degree correction of A-HSW while the delay pulse output mode 2 is used for

V-HSW. Therefore, the delay amount to CR01 is set for the remaining 90° degrees.

The value of V-HSW delay amount with one fourth of a cycle (90° degrees) added is set as the digital value

to CR01.

CR01 = CR00 + 1/4 of one V-HSW cycle (1/4 of frame cycle)

Figure 5-13 shows the V-HSW and A-HSW timings.

54

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-13. V-HSW and A-HSW Timings

DPG signal input

(DPGIN pin)

1 2 3 4 5 6 7 8 9 10 12 14 16 18 20 22 24

2

4

6

8

10 12 14 16

DFG signal input

(DFGIN pin)

EC clear

HSW-N

internal head

switching signal

(Set)

clear

(Reset)

clear

(Set)

clear

(Reset)

clear

CR01

CR00

CR01

CR00

CR01

Timer 0

count value

CR00

τ

D1

V-HSW

(PTO00 pin)

τ

D2

A-HSW

(PTO01 pin)

(b) Timer mode settings

Figures 5-14 to 5-16 show the timer mode settings when generating audio head switching signal (A-HSW).

Figure 5-14. Timer 0 Output Mode Register (TOM0) Format (when generating A-HSW)

7

–

6

–

5

4

3

2

1

0

Address

FF58H

After Reset

R/W

W

TOM0

MOD021 MOD020 MOD011 MOD010 MOD001 MOD000

××000000

MOD0n1 MOD0n0 PTO0n Output Mode Specification (n = 0, 2)

0

1

0

1

0

1

General-purpose output mode

RS output mode

Delay pulse output mode 1

Delay pulse output mode 2

MOD011 MOD010 PTO01 Output Mode Specification

Delay pulse output mode 1

1

0

55

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-15. Timer 0 Output Control Register (TOC0) Format (when generating A-HSW)

7

6

5

4

3

2

1

0

Address

FF59H

After Reset

00H

R/W

W

TOC0 ENHSY SELPTO ENTO02 ALV02 ENTO01 ALV01 ENTO00 ALV00

ALV0n PTO0n Timer Output Active Level Specification

(n = 0, 2)

0

1

Active low

Active high

ENTO0n PTO0n Timer Output Enable Specification (n = 0, 2)

0

1

Output disabled (fixed to inactive level)

Output enabled

ALV01 PTO01 Timer Output Active Level

Specification

1

Active high

ENTO01 PTO01 Timer Output Enable Specification

1

Output enabled

SELPTO

HSYNC Superimposition Pin Specification

0

1

Superimpose to PTO02

Superimpose to PTO01

ENHSY

HSYNC Superimposition Enable to

PTO0n Pin Specification

Do not superimpose

Superimpose

0

1

56

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-16. Timer Control Register 0 (TMC0) Format (when generating A-HSW)

7

6

5

4

3

2

1

0

Address

FF38H

After Reset

00H

R/W

TMC0 CS1 SELFFLG ATMSK ENCLR1 CS0 INTTMSK

ENCLR0

ENCLR0 Timer 0 Clear Control

R/W

1

Clear TM0 with TM0 clear signal

INTTMSK

H

SYNC Separation Circuit Initialization Flag

Initialize mask period measurement counter of

SYNC separation circuit when writing 1.

When reading, 0 is always read.

H

CS0 Timer 0 Operation Control

Count Operation

R/W

1

ENCLR1 Timer 1 Clear Control

0

Mask CSYNC signal input.

TM1 is not cleared.

1

TM1 is cleared with CSYNC signal input

ATMSK CSYNC Signal Mask Auto Cancellation Control

R/W

0

CSYNC signal mask is not canceled with

TM1-CR13 coincidence signal

1

CSYNC signal mask is canceled (set ENCLR1)

with TM1-CR13 coincidence signal

SELFFLG

HSYNC Self Generation Condition

R

0

1

Self generation pulse is not output

Self generation pulse is output

CS1 Timer 1 Operation Control

R/W

0

1

Clear and stop counting

Count operation

57

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.5 Drum Speed Control

The drum FG signal (DFG) from the drum motor is input to DFGIN input pin of the µPD784915. The value of the

free running counter (FRC) is captured to capture register 2 (CPT2H and CPT2L) at the rising edge of DFG and

INTCPT2 interrupt request is generated.

Since the FRC of the µPD784915 is 22-bit configuration and has 6 CPTs (22-bit), the measurement of generation

cycle can be carried out for 6 types of capture trigger.

The CPT is configured with CPT2H, which captures the higher 6 bits, and the CPT2L, which captures the lower

16 bits.

The FRC value is stored in CPT2H and CPT2L respectively with DFG input.

This program uses the FRC as speed control information by DFG input.

The drum speed error amount is calculated in INTCPT2 interrupt processing routine. In INTCPT2 interrupt

processing routine, the cycle of FG signal is measured by subtracting the current capture value. Then, the speed

error amount is detected by comparing the cycle data when the speed control system is locked. The concrete method

of finding the drum speed error amount is shown below. Figure 5-18 shows an example of drum speed control timings.

Figure 5-17. Drum Speed Error Amount Detection Method

FRCH

FRCL

fCLK (8 MHz)

DFGIN pin input

INTCPT2

Drum speed

control interrupt

CPT2H

CPT2L

58

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-18. Drum Speed Control Timings

719.28 [Hz]

(1.39 [ms])

n–1

n

n+1

DFGIN

drum FG signal

INTCPT2

FRC

count

INTCPT2

n+1

DV

N

Nⁿ_DV

∆Nⁿ_DV

n–1

DV

N

When the frame frequency of TV broadcast is assumed as f^F, the fF is as follows:

• f^F= 29.97 [Hz]

Then, since the drum FG wave number is 24 poles, the drum FG signal frequency in the standard playback is as

follows:

• f^DFG= 24 × fF = 719.28 [Hz]

Therefore, the drum FG signal cycle NDFG becomes as follows:

1

T^DFG=

f^DFG

T^DFG

1

NDFG =

=

= 11122.2 = 2B72H [Count]

TFRC

TFRC × fDFG

Where: TFRC = 125 [ns]

The drum speed error amount E^DVis represented by the following expression:

n

EDV = (NDV – NDV^n–1) – NDFG

n

= ∆ NDV – NDFG

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

n

In the above expression, NDV represents the value of the free running counter (FRC) captured at the n-th FG pulse.

The meanings of the signs for the drum speed error amount E^DVcalculated from the expression above are as follows:

(1) When DFG cycle is longer than the target value...+

(when the rotation of the drum motor is slow)

(2) When DFG cycle is shorter than the target value...–

(when the rotation of the drum motor is fast)

5.6 Drum Phase Control

The drum phase error amount is detected by comparing the capture value (CPT1) of the free running counter (FRC)

by the internal head switching signal (HSW-N) and the FRC capture value (CPT0) by the reference frame cycle (V^SYNC

for recording, the coincidence of timer 0 and compare register 10 (CR10) for playback).

Basically, the only difference between the processing for recording and for playback is that the capture source of

the capture 0 (CPT0) of FRC is switched.

5.6.1 Phase reference

Timer 1 of the Super Timer Unit is used to generate the phase/reference signal of the servo system in all the modes.

The TM1 operation differs for recording and for playback.

Figure 5-19 shows the TM1 peripheral circuit. The setting of selectors differs for recording and playback.

[For recording]

When recording, TM1 is operated as an interval timer synchronized with the frame cycle of TV broadcast.

Composite synchronizing signal is input for CSYNCIN input pin. TM1 is cleared at the rising edge of the composite

synchronizing signal using a digital noise elimination circuit incorporated in the CPU. Thus, timer 1 is operated

as a frame synchronous interval timer synchronized with vertical synchronous signal input externally.

Approximately 90% of the frame sync of the CSYNCIN pin input should be masked so that misoperation caused

by noise, etc., is prevented.

[For playback]

When playing back, TM1 is operated as a free running interval timer which has the frequency equal to the frame

cycle of TV broadcast. The value corresponding to the frame cycle is stored in CR10 of TM1 because vertical

synchronous signal is not externally input when playing back.

When playing back, TM1 clear timing is the reference signal of phase control. The phase reference signal is the

TM1 clear timing.

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

(1) Phase reference for playback

When playing back, ENCLR1 flag is reset and timer 1 (TM1) clear by CLR1 input is always disabled. Data

which makes the TM1 clear interval equal to the frame cycle is set to compare register 10 (CR10). Thereby,

TM1 is operated as a free running interval timer having the frequency equal to the frame cycle.

Figure 5-20 shows the TM1 operation timings for playback.

Since the reference frame cycle is 33.366 [ms], the set value of CR10 is as follows:

33.366 [ms]

CR10 =

= 33366 = 8256H

1.0 [µs]

Figure 5-21 shows the mode settings of timer 1 for playback.

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-21. Timer Control Register 0 (TMC0) Format (drum phase control for playback)

7

6

5

4

3

2

1

0

Address

FF38H

After Reset

00H

R/W

TMC0 CS1 SELFFLG ATMSK ENCLR1 CS0 INTTMSK

ENCLR0

ENCLR0 Timer 0 Clear Control

R/W

0

Mask timer 0 clear signal.

TM0 is not cleared.

1

TM0 is cleared by TM0 clear signal

INTTMSK

HSYNC Separation Circuit Initialization Flag

R/W

When writing 1, mask period measurement

counter of H^SYNCseparation circuit is initialized.

When reading, 0 is always read.

CS0 Timer 0 Operation Control

0

1

Clear and stops counting

Count operation

ENCLR1 Timer 1 Clear Control

R/W

0

Mask CSYNC signal input.

TM1 is not cleared.

ATMSK CSYNC Signal Mask Auto Cancellation Control

0

CSYNC signal mask is not canceled by

TM1-CR13 coincidence signal

1

CSYNC signal mask is canceled by TM1-CR13

coincidence signal (ENCLR1 is set).

SELFFLG

HSYNC Self Generation Condition

R

0

1

Self generation pulse is not output

Self generation pulse is output

CS1 Timer 1 Operation Control

Count operation

R/W

1

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

(2) Phase reference for recording

When recording, timer 1 (TM1) is operated as an interval timer synchronized with a vertical synchronizing

signal. Figure 5-22 shows an example of TM1 operation timings for recording.

Composite synchronizing signals are input from the video processing circuit to the CSYNCIN input pin. The

composite synchronizing signal includes cut-in pulse, equalizing pulse, and horizontal synchronizing signal,

as well as vertical synchronizing signal, so that vertical synchronizing signal needs to be separated from these

signals. The digital noise elimination circuit incorporated in the µPD784915 is used for this purpose.

By using the digital noise elimination circuit, it is possible to clear TM1 at the rising edge of the vertical

synchronizing signal included in the composite synchronizing signal and generate interrupt for INTCLR1.

TM1 is cleared in synchronization with the falling edge of the vertical synchronizing signal in the composite

synchronizing signal input to the CSYNCIN pin. If noise is mixed in the composite synchronizing signal input

to the CSYNCIN pin, TM1 clear may be mistakenly carried out. TM1 clear by CSYNCIN input is disabled for

the certain period of time using the ENCLR1 flag and compare register 13 (CR13) in CSYNCIN input which

controls TM1 clear enable/disable. Figure 5-23 shows the timer 1 mode setting for recording.

In this program, TM1 clear input disabled time is set to approximately 90% of the frame cycle after inputting

a separated vertical synchronizing signal.

Since the frame cycle is 33.36 [ms], the time 90% of it is calculated as follows:

33.36 × 0.9 = 30.03 [ms]

In this program, the mask period is set with CR13 so that interrupt is generated at a point which is 90% of

a field cycle. Since the TM1 count clock frequency is f^CLK/8 = (1.0 [µs]), the value set for CR13 is as follows:

30.03 [ms]

CR13 =

= 30030 = 754EH

1.0 [µs]

When the ATMSK flag, which controls CSYNCIN signal mask auto cancellation, is set, 754EH is set to CR13,

and the timer is started, ENCLR1 control bit is set when 90% of a field cycle is passed. If ENCLR1 control

bit is controlled, CSYNCIN pin input is masked for the 90% period of time of a frame cycle.

If, for some reason, vertical synchronizing signal is not input, the compare register 10 (CR10) value is set so

that clear is executed at a cycle approximately equal to the frame cycle by coincidence signal of CR10 of timer

1 and timer 1. In this case, CR10 is set with additional 3% of the frame cycle. Therefore, as the frame frequency

is 29.97 [Hz] (33.36 [µs]), the set cycle is as follows:

33.36 × 1.03 = 34.37 [ms]

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Since the count clock frequency of timer 1 is fCLK/8 = (1.0 [µs]), the set value to CR10 is as follows:

34.37 [ms]

CR10 =

= 34370 = 8642H

1.0 [µs]

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-23. Timer Control Register 0 (TMC0) Format (drum phase control for recording)

7

6

5

4

3

2

1

0

Address

FF38H

After Reset

00H

R/W

TMC0 CS1 SELFFLG ATMSK ENCLR1 CS0 INTTMSK

ENCLR0

ENCLR0 Timer 0 Clear Control

R/W

0

Mask timer 0 clear signal.

TM0 is not cleared.

1

TM0 is cleared by TM0 clear signal

INTTMSK

HSYNC Separation Circuit Initialization Flag

R/W

When writing 1, H^SYNCseparation circuit mask

period measurement counter is initialized.

When reading, 0 is always read.

CS0 Timer 0 Operation Control

0

1

Clear and stops counting

Count operation

ENCLR1 Timer 1 Clear Control

R/W

1

TM1 is cleared by CSYNC signal input

ATMSK CSYNC Signal Mask Auto Cancellation Control

1

CSYNC signal mask is canceled by TM1-CR13

coincidence signal (ENCLR1 is set)

SELFFLG

HSYNC Self Generation Condition

R

0

1

Self generation pulse is not output

Self generation pulse is output

CS1 Timer 1 Operation Control

Count operation

R/W

1

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.6.2 Drum phase control for playback

For drum phase control for playback, drum motor rotation phase is synchronized with a reference timer which has

the frequency equal to the TV broadcast frame cycle f^F.

Timer 1 (TM1) of Super Timer Unit is used for the reference timer as mentioned earlier.

For VHS standards, the locking point of the drum phase in this program is specified as 6.5H before the phase

reference signal.

1H, here, shows one cycle of horizontal synchronizing signal (1H = 63.56 [µs]).

Figure 5-24 shows the use of timer for drum phase control for playback. Figure 5-25 shows the drum phase control

timing chart for playback.

Figure 5-24. Use of Timer for Drum Phase Control (for playback)

FRC

Capture

CPT0

(Clear)

TM1

Operates as a reference timer

for generating phase reference

signal for playback

CR10

INTCR10

69

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-25. Drum Phase Control Timing (for playback)

HSW-N

V-HSW

(PTO00)

HSW pulse

delay amount

Phase lock

delay amount

CR10

INTCR10

(Drum phase error

amount detection)

CPT0

Coincidence signal

with TM1 and CR10

CPT1

HSW-N

falling edge

70

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

The drum phase error amount detection method is shown below.

The count value of free running counter (FRC) is stored in the capture register 1 (CPT1) at the falling edge of internal

head switching signal (HSW-N).

INTCR10 interrupt is generated at the coincidence timing with the count value of timer 1 (TM1) and compare register

10 (CR10). The value of FRC is, at the same time, stored in CPT0.

The drum phase error amount E^DPis shown in the expression below. Figure 5-26 shows the method to set CPT0

and CPT1 capture trigger source.

E^DP= ( (CPT0 value) – (CPT1 value) ) – NDPL

NDPL, here, is the target value of drum phase control.

The count clock of the capture registers of CPT0 and CPT1 is 125 [ns] of FRC. However, since timer 0 (TM0)

to generate head switching signal (V-HSW), which is the object of comparison, is 1 [µs], CPT1 is subtracted from

CPT 0, and then the result is made 1/4 so that data can be handled in 16 bits.

The sampling clock cycle of drum phase error, hereafter, is calculated as 0.5 [µs].

The target value of the drum phase control NDPL is the remainder of the subtraction between CPT0 and CPT1,

therefore, calculated with the following expression.

Video head

N^DPL= switching pulse

delay amount

Delay amount

for half a frame

cycle

Delay amount

for 6.5H

Delay for VSYNC

separation

+

Each value of the above expression is calculated here.

(1) The digital value equivalent to the head switching signal (V-HSW) delay amount

The digital value equivalent to the head switching signal (V-HSW) is calculated. The V-HSW delay is stored

in compare register 00 (CR00) of timer 0 as the delay amount from HSW-N. The TM0 sampling clock frequency

is twice as large as that of the drum phase error. Therefore, the value equivalent to V-HSW delay amount

when counted with FRC is twice as large as the value set in CR00.

(2) The delay amount for half a frame cycle

The half of a frame cycle T^F/2 is stored in CR10, therefore:

CR10/2 = 16.68 [ms]

The above value is counted with the sampling clock cycle 0.5 [µs] of drum phase error as follows:

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

CR10/2

= CR10

0.5 [µs]

(3) The delay amount for 6.5H

1H = 63.56 [µs], therefore, the time for 6.5 H is:

63.56 × 6.5 = 413.14 [µs]

Therefore, if counted with the drum phase error sampling clock:

413 [µs]

= 826

0.5 [µs]

(4) The delay for V^SYNCseparation

Drum control system for recording uses the vertical synchronizing signal VSYNC as the phase reference signal.

VSYNC, here, is acquired by being separated from the composite synchronizing signal in order to make the phase

control system program for playback and recording equal.

The delay time for V^SYNCseparation is with the time for the separation is considered.

µPD784915 is equipped with digital noise elimination circuit, so that 13.5 [µs] (INTTM2.4 = 0) of the delay is

the delay for V^SYNCseparation.

If the time for 13.5 [µs] necessary for VSYNC separation is counted with the sampling clock of the drum phase

error, the value is as follows:

13.5 [µs]

= 27

0.5 [µs]

From above, N^DPLis calculated as follows:

NDPL = (CR00 × 2) + (CR10) + 826 + 27

= (CR00 × 2) + (CR10) + 355H

The drum phase error amount is calculated from the free running counter (FRC) value (CPT1) captured at

the falling edge of the internal head switching signal (HSW-N) and the FRC value (CPT0) captured at the timer

1 (TM1) clear timing.

Therefore, the capture trigger selector of CPT0 is switched so that the CPT0 capture trigger source becomes

the coincidence signal of the TM1 value and compare register 10 (CR10).

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Timer 1 (TM1) is used as a reference timer which is cleared with frame cycle. The value set to CR10 of TM1

is as follows:

33.366 [ms]

CR10 =

= 33366 = 8256H

1.0 [µs]

Figure 5-26. Capture Mode Register (CPTM) Format

7

6

5

4

3

0

2

1

0

Address

FF53H

After Reset

00H

R/W

CPTM FCPT5 FCPT4 TRGS011 TRGS010

TRGS120 TRGS001 TRGS000

TRGS001 TRGS000 CPT0 Capture Trigger Specification

R/W

0

TM1-CR10 coincidence signal

CR12 Capture Trigger Specification

TRGS120

R/W

PBCTL signal input edge detection signal

(signal specified with bits 6 and 7 of INTM1)

0

CFG signal input frequency dividing signal

(EDV-EDVC coincidence signal)

1

TRGS011 TRGS010 CPT1 Capture Trigger Specification

R/W

R

0

Falling edge of timer 0 clear pulse

FCPT4 CPT4 Capture Flag

0

1

CPT4 is not captured

CPT4 is captured

FCPT5 CPT5 Capture Flag

R

0

1

CPT5 is not captured

CPT5 is captured

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.6.3 Drum phase control for recording

For drum phase control for recording, the rotational phase of the drum motor is synchronized with vertical

synchronizing signal externally input.

The point of phase lock is where the rising and falling edges of the head switching signal (V-HSW) are 6.5H before

the vertical synchronizing signal, which complies with VHS standard. However, the time required for V^SYNCseparation,

as mentioned in the section about the control for playback, must be taken in consideration.

Figure 5-27 shows the use of the timer in drum phase control for recording. Figure 5-28 shows the drum phase

control timing chart for recording.

When recording, the phase error amount is calculated from the free running counter (FRC) value (CPT1) captured

at the falling edge of internal head switching signal (HSW-N) and the FRC value (CPT0) captured at the falling edge

of the vertical synchronizing signal input from the CSYNCIN pin.

The phase error amount detection method is described below.

The method to capture the FRC value in CPT1 only at the falling edge of HSW-N is the same as for playback.

On the other hand, the CPT0 capture operation is performed when the vertical synchronizing signal is input to the

CSYNCIN input pin, and TM1 is cleared simultaneously. In fact, the phase error detection is performed in frame cycle,

so that TM1 clearance by inputting CSYNC is masked for the 90% time period of a frame cycle.

Compare register 13 (CR13) is used for the setting of the mask time.

Figure 5-29 shows the CPT0 and CPT1 capture trigger source setting method for recording.

The phase error amount is detected in INTCLR1 interrupt processing. The phase error amount E^DPis calculated

as follows:

E^DP= ( (CPT0 value) – (CPT1 value) ) – NDPL

NDPL, here, is the difference between CPT0 and CPT1 when the drum phase control is locked, that is, the target

value of the phase control.

The difference between CPT0 and CPT1 when the phase is locked, is the sum of head switching signal delay

amount, frame half cycle, VHS standard 6.5H delay, and the delay amount for V^SYNCseparation.

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-28. Drum Phase Control Timing (for recording)

HSW - N

V-HSW

(PTO00)

(Mask)

VSYNC

VSYNC missing

V-HSW pulse

delay amount

Phase lock

delay amount

Coincides with CR10

CR10

(Drum phase error amount detection)

INTCLR1

(Drum phase error

amount detection)

CPT0

CPT1

CPT0

VSYNC

rising edge

CPT1

HSW-N

falling edge

Remark Phase lock delay amount: value determined by VCR standard

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-29. Capture Mode Register (CPTM) Format

7

6

5

4

3

0

2

1

0

Address

FF53H

After Reset

00H

R/W

CPTM FCPT5 FCPT4 TRGS011 TRGS010

TRGS120 TRGS001 TRGS000

TRGS001 TRGS000 CPT0 Capture Trigger Specification

R/W

1

0

TM1 Clear Signal

CR12 Capture Trigger Specification

TRGS120

R/W

PBCTL signal input edge detection signal

(signal specified with bits 6 and 7 of INTM1)

0

CFG signal input frequency dividing signal

(EDV-EDVC coincidence signal)

1

TRGS011 TRGS010 CPT1 Capture Trigger Specification

R/W

R

0

Falling edge of timer 0 clear pulse

FCPT4 CPT4 Capture Flag

0

1

CPT4 is not captured

CPT4 is captured

FCPT5 CPT5 Capture Flag

R

0

1

CPT5 is not captured

CPT5 is captured

77

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

The µPD784915 uses vertical synchronizing signal (VSYNC) as phase reference signal. Therefore, digital noise

elimination circuit is used to separate only vertical synchronizing signals from composite synchronizing signals. In

this application example, the amount of time required for V^SYNCof digital noise elimination circuit is 13.5 [µs].

The count value of drum phase error for 6.5H sampling clock is 826.

The count value for 13.5 [µs] required for VSYNC separation is shown in the following expression:

13.5 [µs]

= 27

0.5 [µs]

Therefore, the target value is represented with the expressions as follows:

Digital value

Delay amount

for half a frame

cycle

equivalent to

video head

switching pulse

delay amount

Delay for V^SYNC

separation

Delay amount

for 6.5H

N^DPL=

+

= (CR00 × 2) + (CR10) + 826 + 27

= (CR00 × 2) + (CR10) + 355H

This expression is the same as that for phase error amount for playback.

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.7 Capstan Speed Control

Delay of capstan speed error amount is carried out, as well as drum speed control, by capturing the free running

counter (FRC) value at the capstan FG signal input edge.

The capstan FG signal (CFG) is input to the DFGIN input pin. INTCPT3 interrupt request occurs simultaneously

with the capture of the FRC value to CPT3 at the CFG edge input.

The difference from drum speed control is that CFG frequency f^CFvaries according to the tape running mode. In

this set, the CFG frequency for normal playing back is as follows:

• SP mode : 1080.00 [Hz]

• LP mode : 540.00 [Hz]

• EP mode : 360.00 [Hz]

In order to equalize error detection gain in the servo system according to each running mode, CFG is divided with

the 8-bit event divider control register (EDVC) incorporated in the CFGIN pin input of the Super Timer Unit.

Since this counter operates as the event divider of the DFGIN pin input pulse, the detection cycle in the SP mode

becomes the same as that in the EP mode if CFG is divided by one third.

Figure 5-30 shows the capstan speed detection method. Figure 5-31 shows the capstan speed control timing chart.

The capstan speed error ECV is calculated in the INTCPT3 interrupt request processing routine.

The expression is as follows:

n

∆N^CV

= ∆NCV

– NCV

n

ECV

= NCVL

– ∆NCV

NCVL, here, is the target value of capstan speed control.

The CFG frequency fCF in the EP mode is as follows:

f^CF= 360.00 [Hz]

fCFEP = 360.00 [Hz]

Therefore, it becomes the CFG frequency in the SP mode, and the CFG cycle f^CFis calculated with the following

expressions:

f^CFSP/3 = 360.00

f^CF/3 = 239.7602093 [Hz]

T^CF= 2.7778 [ms]

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

The time interval counted by the free running counter (FRC) becomes the target value NCFL of capstan FG signal

(CFG). Since the FRC count pulse cycle (T^FRC) is 125 [ns], NCFL is as follows:

2.778 [ms]

N^CFL=

= 22222 = 56CEH

125 [ns]

The meaning of the signs for capstan speed error amount ECV is shown below:

(1) When CFG cycle is longer than the target value...–

(when the rotation of capstan motor is slow)

(2) When CFG cycle is shorter than the target value...+

(when the rotation of capstan motor is fast)

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-31. Capstan Speed Control Timing

360.00 Hz

(2.78 ms)

Capstan FG signal

EP mode

(CFGIN)

SP mode

(CFGIN)

1/3 frequency

divide with EDVC

1080.00 Hz

(0.93 ms)

INTCPT3

n

N_CV

INTCPT3

n

∆N_CV

n–1

N_CV

82

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.8 Capstan Phase Control

The phase detection of the capstan motor is performed by compare register 12 (CR12), and capstan phase control

is performed by the INTCR12 interrupt routine.

The control method differs for playback and recording. The control method for each case is explained below.

5.8.1 Capstan phase control for playback

The purpose of capstan phase control for playback is to keep the phase relation constant between the playback

control signal (PBCTL) and the head switching signal (V-HSW) acquired when playing back.

The relation between timer 1 (TM1), which is the reference timer in drum phase control, and V-HSW is already

kept constant (refer to 5.6.2 Drum phase control for playback). Therefore, the phase relation between V-HSW and

PBCTL is indirectly kept constant by keeping the phase relation between TM1 and PBCTL constant (refer to Figure

5-32).

Figure 5-32. Model of Capstan Phase Control

V-HSW

Timer 1

PBCTL

Keep phase constant

(drum phase control)

Keep phase constant

(capstan phase control)

Phase is indirectly kept constant

In capstan phase control for playback, the selector is selected so that PBCTL signal is set to CR12 of timer 1. Figure

5-33 shows the capstan phase error detection method for playback. Figure 5-34 shows how to set the capture trigger

source of CR12 for playback.

In capstan phase control, the lock point is the point tilted for the amount of time from video head to control head

(x value correction amount). The x value correction amount differs according to the VCR sets and the tape running

mode.

Figures 5-35 to 5-37 show the phase control timing charts. The phase error amount E^CPis calculated from the

following expression.

E^CP= (Value captured by PBCTL signal) – NCPL

= (CR12 value) – NCPL

NCPL : capstan phase control target value

The capstan phase control target value (NCPL), here, is the TM1 value captured in CR12 when the phase is locked.

Taking it into account that the phase between the video head position (V-HSW timing) and the reference timer is 6.5H,

N^CPLis calculated as follows:

83

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

NCPL

=

(x value correction amount) – 6.5H + tracking adjustment amount

T^TM1

= (x value correction amount) – 6.5H + tracking adjustment amount

8/f^CLK

=

(x value correction amount) – 6.5H × 63.55 [µsec] + tracking adjustment amount

8/8[MHz]

If the phase control range is set equally for both advance/delay directions centered in the phase lock, the amount

of time before the phase lock is shortened. In other words, in the condition of Figure 5-36, the distance to the lock

point is shorter if the condition is considered as advanced rather than delayed so that the amount of time before the

phase lock is shorter. Concretely, the N^F/2 range (NF: the full count value of timer 1: CR10 set value) is regarded

as it is, centered in the locking point, and the value corrected by adding N^Fto (or subtracting NF from) the value captured

is used for the other range.

In addition, digital filter arithmetic is performed to the capstan phase error amount acquired here so that the result

is used for the phase control.

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-34. Capture Mode Register (CPTM) Format

7

6

5

4

3

0

2

1

0

Address

FF53H

After Reset

00H

R/W

CPTM FCPT5 FCPT4 TRGS011 TRGS010

TRGS120 TRGS001 TRGS000

TRGS001 TRGS000 CPT0 Capture Trigger Specification

R/W

0

1

TM1-CR10 coincidence signal

CSYNC signal input edge detection

signal

1

0

1

TM1 clear signal

OR of TM1-CR10 coincidence signal

and CSYNC signal input edge

detection signal

CR12 Capture Trigger Specification

TRGS120

R/W

PBCTL signal input edge detection signal

0

TRGS011 TRGS010 CPT1 Capture Trigger Specification

0

1

0

1

0

1

Falling edge of timer 0 clear pulse

Rising edge of timer 0 clear pulse

Setting prohibited

Both falling/rising edge of timer 0

clear pulse

FCPT4 CPT4 Capture Flag

R

0

1

CPT4 is not captured

CPT4 is captured

FCPT5 CPT5 Capture Flag

0

1

CPT5 is not captured

CPT5 is captured

86

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.8.2 Capstan phase control for recording

The capstan control for recording is performed by dividing capstan FG signal (CFG). As long as the capstan motor

is steadily rotating while recording, it is not necessary to consider absolute phase.

Figure 5-38 shows the capstan phase error detection method for recording. Figure 5-39 shows the method of setting

the capture trigger source of compare register 12 (CR12) for recording. The capstan phase control for recording,

as well as for playback, uses the CR12 and INTCR12 interrupts. Although a value is captured in CR12 every time

CFG is input, CFG has to be divided because only one captured value is needed for one frame. In actuality, the input

is not divided but interrupt is divided using the macro service counter mode, and the CR12 value when a vectored

interrupt is generated is used. The number of frequency division is the same as the FG wave number (in EP mode).

CFG input is triple divided by event divider control register (EDVC) in SP mode. Therefore, the required value is

acquired by dividing the interrupt for the capstan FG wave number in EP mode.

Figure 5-40 shows the phase control timing chart.

Capstan phase error amount is calculated in the same way as for playback.

E^CP= (Captured value by CFG frequency dividing signal) – NCPL

= (CR12 value) – NCPL

Remark NCPL: capstan phase control target value

However, since there is not an absolute phase for recording, target value NCPL can be any value.

Capstan phase control range is determined in the same way as for playback.

Further, digital filter arithmetic is performed to the capstan phase error amount acquired from the above calculation,

and the result is used for phase control.

90

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-39. Capture Mode Register (CPTM) Format

7

6

5

4

3

0

2

1

0

Address

FF53H

After Reset

00H

R/W

CPTM FCPT5 FCPT4 TRGS011 TRGS010

TRGS120 TRGS001 TRGS000

TRGS001 TRGS000 CPT0 Capture Trigger Specification

R/W

0

1

TM1-CR10 coincidence signal

CSYNC signal input edge detection

signal

1

0

1

TM1 clear signal

OR of TM1-CR10 coincidence signal

and CSYNC signal input edge

detection signal

CR12 Capture Trigger Specification

TRGS120

R/W

CFG signal input dividing signal

(EDV-EDVC coincidence signal)

1

TRGS011 TRGS010 CPT1 Capture Trigger Specification

0

1

0

1

0

1

Falling edge of timer 0 clear pulse

Rising edge of timer 0 clear pulse

Setting prohibited

Both falling/rising edges of timer 0

clear pulse

FCPT4 CPT4 Capture Flag

R

0

1

CPT4 is not captured

CPT4 is captured

FCPT5 CPT5 Capture Flag

0

1

CPT5 is not captured

CPT5 is captured

92

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-40. Capstan Phase Control Timing (for recording)

1 2 3 4

36 1

CFG

SP mode

EDVC

(1/3)

CFG

EP mode

Macro service

(1/12)

0

11

10

9

8

2

1

0

11

10

9

8

Note

Macro service

counter value

INTCR12

interrupt

request

(Capture)

(Clear)

0

VSYNC

(CSYNCIN)

Note The arrows have the following meanings.

(Solid line) : vectored interrupt

(Broken line): macro service

93

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.9 Recording Control Signal Generation

Recording control signal (RECCTL) is a signal synchronized with head switching signal (V-HSW) and recorded

on the control track for recording. The RECCTL cycle is equal to TF and the duty is normally 60% (27.5% for index

signal, may become other duty).

RECCTL rising timing t^RECRis the point tilted for the amount of time from video head to control head (x value

correction amount).

The x value correction amount differs according to the VCR sets and the tape running mode.

The RECCTL write timing is calculated as follows:

(1) [RECCTL rising timing (t^RECR)]

RECCTL rising timing (t^RECR) is the point tilted for the amount of time from the video head position to control

head (x value correction amount). The video head position has the phase tilted for 6.5H from the reference

timer. Therefore, t^RECRis represented as follows:

t^RECR= (x value correction amount) – 6.5H – τd

Remark τd : digital noise elimination circuit (V^SYNCseparation) delay time (80/fCLK or 128/fCLK)

0 if not using digital noise elimination circuit

(2) RECCTL falling timing (t^RECF)

RECCTL falling timing (t^RECF) is the point tilted for 60% of the frame frequency from rising timing.

t^RECF= tRECR + (60% of frame frequency)

= [(x value correction amount) – 6.5H – τd] + (T^F× 0.6)

Remark τd : digital noise elimination circuit (V^SYNCseparation) delay time (80/fCLK or 128/fCLK)

0 if not using digital noise elimination circuit

T^F: TV broadcast frame frequency (33.36 msec: NTSC)

First, connect directly the µPD784915 and control head as shown in Figure 5-41 and set registers so that RECCTL

write circuit is used.

94

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-41. Connection of µPD784915 and Control Head

µPD784915

RECCTL+

RECCTL–

Control head

The recording control signal (RECCTL) driver of the µPD784915 has the REC mode, which is used for RECCTL

signal write. Figure 5-42 shows RECCTL driver configuration.

Figure 5-42. RECCTL Driver Block Diagram

Internal bus

Write strobe signal

TOM1

AMPM0

DRV SEL SEL SEL

MOD 13 11 30

EN

REC

SEL

CTLD

Initialization

CTLDLY

ANI11

INTCR11

RECCTL control

INTCR13

INTCR30

RECCTL output

RECCTL+

RECCTL–

CTL

head

The REC mode sequence of RECCTL driver operates RECCTL+ pin and RECCTL– pin as shown in Table 5-2.

Therefore, RECCTL signal write is realized taking only the interrupt occurrence timing, which is a trigger signal, into

consideration.

Table 5-2. RECCTL Driver REC Mode Sequence

Sequence

RECCTL+

Low level

High level

RECCTL–

High level

Low level

0

1

Figure 5-43 shows an example of RECCTL signal writing operation timings.

95

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-43. Example of RECCTL Signal Writing Operation Timings

TM1

CR11 rewrite

INTCR11

CR11 rewrite

TOM1 write

(Sequence initialized)

Sequence

ENREC bit

0

1

0

1

0

1

0

RECCTL+

RECCTL–

When

writing

ends^Note

writing

starts^Note

CTL signal

written

Note R/W to TOM1 register is not executed until approximately 800 µs from the setting of ENREC = 1 (start of REC

mode), or ENREC = 0 (end of REC mode).

Caution

Keep CTL amplifier in operation (ENCTL (AMPC.1) = 1) even while REC driver is operating.

96

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

The case using only compare register 11 (CR11) as a register for setting timing is explained here.

Set Timer 1 output mode register (TOM1) to use CR11 as shown in Figure 5-44. Then, write the value corresponding

to rising timing to CR11. When timer register 1 (TM1) coincides with CR11, the rising edge is recorded and INTCR11

interrupt occurs. Rewrite the value to the value corresponding to the falling timing. And the falling edge is recorded

at the next coincidence of TM1 and CR11, then write again the value corresponding to the rising timing to CR11. By

repeating this procedure, RECCTL can be recorded.

Figure 5-45 shows the timing chart.

97

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-44. Timer 1 Output Mode Register (TOM1) Format

7

6

5

4

3

2

1

0

Address

FF5AH

After Reset

80H

R/W

TOM1 DRVMOD SEL13 SEL11 SEL30 MOD111 MOD110 MOD101 MOD100

MOD101 MOD100 PTO10 Output Mode Specification

R/W

0

1

0

1

General purpose output mode

Setting prohibited

Delay pulse output mode 1

Delay pulse output mode 2

MOD111 MOD110 PTO11 Output Mode Specification

W

0

1

0

1

General purpose output mode

Setting prohibited

Delay pulse output mode 1

Delay pulse output mode 2

SEL30 RECCTL Write Circuit Operation Trigger Setting

W

0

TM3-CR30 coincidence signal is

not selected as a trigger

1

TM3-CR30 coincidence signal is selected

as a trigger

SEL11 RECCTL Write Circuit Operation Trigger Setting

W

1

TM1-CR11 coincidence signal is selected

as a trigger

SEL13 RECCTL Write Circuit Operation Trigger Setting

0

TM1-CR13 coincidence signal is

not selected as a trigger

1

TM1-CR13 coincidence signal is selected

as a trigger

DRVMOD RECCTL Write Circuit Operation Mode Setting

REC mode

W

0

98

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.10 Quasi Vertical Synchronizing Signal (Quasi-VSYNC) Generation

The method to generate quasi vertical synchronizing signal (quasi-VSYNC) for special playback is explained.

There are several types of wave forms for quasi-VSYNC depending on the signal processing circuit to be used. The

method to output the wave form shown in Figure 5-48 is explained here.

The wave form shown in Figure 5-46 requires not only “H” and “L” but also “M” (middle level) outputs.

Real-time output port RTP80 incorporated with the µPD784915 is used, for this port can output “H”, “L”, and “Hi-

Z”. For the middle level, the level of Hi-Z output is set with external pull-up and pull-down resistors (refer to Figure

5-47).

RTP80 can superimpose H^SYNCpulse during Hi-Z period, so that HSYNC does not need to occur for every HSYNC.

The procedure is shown below:

<1> Set P80 in real time output port mode. And select TM0-CR02 coincidence signal as the RTP8 output trigger.

<2> Set H^SYNCoutput timing (rising (Figure 5-48 <1>)) to CR02. And set 00010001B (superimpose high-level

H^SYNCto Hi-Z) to P8L.

<3> The wave form with Hi-Z that have high-level HSYNC superimposed is output from P80 pin by the coincidence

of TM0 and CR02. INTCR02 occurs simultaneously.

<4> Set V^SYNCoutput timing (rising (Figure 5-48 <2>)) to CR02 by the INTCR02 interrupt routine. Set 00000001B

(high-level output) to P8L.

<5> High level is output from P80 pin by the coincidence of TM0 and CR02. INTCR02 occurs simultaneously.

<6> Set V^SYNCoutput timing (falling (Figure 5-48 <3>)) by the INTCR02 interrupt routine. Set 00000000B (low-

level output) to P8L.

<7> Low level is output from P80 pin by the coincidence of TM0 and CR02. INTCR02 occurs simultaneously.

<8> Set H^SYNCoutput timing (rising (Figure 5-48 <1>)) to CR02 by the INTCR02 interrupt routine. Set 00010001B

(superimpose high-level H^SYNCto Hi-Z) to P8L.

<9> Go back to <3> (repeat this procedure).

100

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-46. Quasi-VSYNC Waveform

H

M

L

Figure 5-47. Middle Level Generation

µ

PD784915

V

DD

R1

P80

Quasi-VSYNC

R2

Remark When P80 is Hi-Z, the output level is

V^DD

R1 + R2

101

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-48. Quasi-VSYNC Generation Timing

HSYNC pulse is superimposed

by hardware

1

2

3

H

M

L

INTCR02

N 3

INTCR02

N 2

INTCR02

Rewrite

N 1

Rewrite

CR02

P8L

N 1

N 2

N 3

N 1

00010001B

00000001B

00000000B

00010001B

102

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.11 Treatment of Servo Error Amount

5.11.1 Drum control system processing

Drum control system performs the calculation and filtering processing of drum speed error and phase error and

output of drum motor control signal (PWM0).

Figure 5-49 shows the drum control system configuration.

Figure 5-49. Drum Control System Configuration

Speed error

detection

KV

(Drum speed gain)

Bias value

addition

PWM

conversion

+

Phase error

detection

Digital filter

K

P

(Drum phase gain)

Drum speed control interrupt processed with INTCPT2

Drum phase control interrupt processed with INTCR10

As shown in Figure 5-49, the drum speed control system performs only phase error calculation and phase control

system filtering. The drum phase control system reads out the filtered phase error, adds it with speed system error,

and performs PWM output.

First, the total error amount of drum motor is calculated from the speed error amount and phase error amount.

The speed error amount E^DVacquired from drum speed control interrupt and the phase error amount EDP (digital filter

arithmetic result) acquired from drum phase control interrupt are multiplied with gains, respectively (the gains are

defined as K^DVand KDP, respectively). The sum of these results is defined as the drum error amount ED.

E^D= KDV • EDV + KDP • EDP

The sum of the drum total error amount and the bias value is PWM output.

The bias value is PWM output to control the motor in open loop and output the voltage required to rotate the motor

in the approximate target rotation. However, the bias is not necessarily a strict value because the actual control is

carried out by feedback control and errors are automatically corrected to a certain extent.

In addition, the servo system characteristics can be improved, such as reduction of motor rising time and

improvement of locking stability, by changing the gain according to the speed error amount and phase error amount

and canceling phase control.

103

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

The speed error gain KDV and phase error gain KDP vary according to the motor characteristics. Set these values

according to the characteristics of the motor to be used (in fact, find the value that has the best characteristics in cut

and try).

(1) Error amount maximum control processing (limit limiter)

Error amount maximum control processing is the same as trapezoidal pattern for servo IC error value detection,

and it controls the maximum of internal error value (error amount) to input to digital filter.

Figure 5-50. Trapezoidal Pattern for Error Value Detection (drum control system)

– limiter Lock point + limiter

In this application example, the control range is specified also from loop gain so as to prevent data overflow

in the arithmetic processing of digital filter. A maximum limit is set for speed error and phase error, respectively,

and each control range is set as follows:

•

Drum speed control range ±735H (1 count = 125 nsec) ±230.625 µsec

Drum phase control range ±2220H (1 count = 500 nsec) ±4368 µsec

104

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

(2) Special processing in drum control system

(a) Special processing for error amount calculation

By checking the drum speed error amount detected in the drum speed error amount calculation routine,

if the drum speed deviates ±5% or more from the target value, 0 is set to the drum phase error amount.

The purpose of this processing is to prohibit addition of the drum phase error amount while the drum speed

control system is not in operation and to reduce the lock time of the motor by operating the drum motor

only with the speed control system.

(b) Special processing in drum phase system digital filter

This special processing limits the maximum of Y^n-1data value in the arithmetic processing of drum phase

system digital filter. Y^n-1is the data to reflect the past output data of the filter. If the drum phase becomes

out of phase for a long period of time (when applying load by lightly holding the drum manually, etc.), Yn-1

data keeps increasing. The increased Yn-1 data will start decreasing gradually when the applied load is

removed. However, the lock time is affected because it takes an extremely long time before Y^n-1is

decreased. In order to avoid this, the lock time should be reduced by setting the maximum limit for Yn-1

data.

The limit value for Y^n-1is set as follows:

Yn-1 maximum : 13FH

The Y^n-1limit value setting method is adopted according to experimental values.

(3) Loop gain multiplication

K^Vand KP shown in Figure 5-50 are loop gains in speed control system and phase control system, respectively.

When handling the error amount data (calculated from FRC) which is digital filtering processed as PWM data,

the variable range of PWM data is small (the dynamic range is narrow) because the range available for the

data is narrow.

Loop gain also has the functions to widen the dynamic range by amplifying the filtered data and to adjust the

addition rate of speed system and phase system.

The loop gains of the speed system and phase system are as follows:

Speed system loop gain : K^V= 17.76 times

Phase system loop gain : KP = 46.0 times

Speed/phase addition rate : K^V: KP = 4.74 :1

105

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

(4) Bias value addition

Bias value addition is carried out to keep the motor control voltage at the lock point during servo lock (speed/

phase error amount 0).

The bias value setting method is adopted according to experimental values. PWM output data in the condition

that drum is controlled only with speed control and stabilized at the drum speed target value is adopted as

the bias value.

The bias value in drum control system is as follows:

Bias value in NTSC : 66F0 [HEX]

Bias value is added to the sum of speed correction amount and phase correction amount. However, the

arithmetic result may overflow, so that overflow check is carried out. The arithmetic result is fixed to the

maximum if overflow occurs and to the minimum if borrow occurs.

(5) PWM output for drum motor control

The PWM of the data which is the addition of speed/phase correction amount and bias value is output. The

data is processed as 16-bit data. However, since the operation range of PWM output unit is 0FF00H to 0100H,

when operating outside this range, the maximum or the minimum is written. The PWM for drum motor control

is output in the drum speed control interrupt routine.

106

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.11.2. Capstan control system processing

Capstan control system performs the calculation and filtering processing of capstan speed error and phase error

and the output of capstan motor control signal (PWM1).

Figure 5-51 shows the capstan control system configuration.

Figure 5-51. Capstan Control System Configuration

KV

/KP

Speed error

amount detection

(Capstan

MIX gain)

Bias value

addition

PWM

conversion

+

Digital filter

KM

Phase error

amount detection

Digital filter

Capstan speed control interrupt processed with INTCPT3

Capstan phase control interrupt processed with INTCR12

As shown in Figure 5-51, capstan phase control system performs the calculation of phase error amount and filtering

of phase system. Capstan speed control system reads out the filtered phase error, adds it with speed system error,

and performs PWM output.

First, the capstan motor total error amount is calculated from the speed error amount and phase error amount.

Speed error amount E^CVacquired from the capstan speed control interrupt and phase error amount ECP (digital filter

arithmetic result) acquired from the capstan phase control interrupt are multiplied with gains, respectively (the gains

are defined as K^CVand KCP, respectively). The sum of these results are defined as capstan error amount EC.

E^C= KCV • ECV + KCP • ECP

The sum of the capstan total error amount and bias value is PWM output.

The bias value is PWM output to control the motor in open loop and output the voltage required to rotate the motor

in the approximate target rotation. However, the bias is not necessarily a strict value because the actual control is

carried out by feedback control and errors are automatically corrected to a certain extent.

In addition, the servo system characteristics can be improved, such as reduction of motor rising time and

improvement of locking stability, by changing the gain according to the speed error amount and phase error amount

and canceling phase control.

The speed error gain K^CVand phase error gain KCP vary according to the motor characteristics. Set these values

according to the characteristics of the motor to be used (in fact, find the value that has the best characteristics in cut

and try).

107

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

(1) Error amount maximum control processing (limit limiter)

Error amount maximum control processing is the same as trapezoidal pattern for servo IC error value detection,

and it controls the maximum of internal error value (error amount) to input to digital filter.

Figure 5-52. Trapezoidal Pattern for Error Value Detection (capstan control system)

–

limiter Lock point + limiter

This also prevents data overflow in digital filter arithmetic processing.

The limit range is specified by limiting the error maximum.

The maximum limit is set for speed error and phase error, respectively, and each control range is set as follows:

•

Capstan speed control range ±1E79H (1 count = 125 nsec) ±975.125 µsec

Capstan phase control range ±15A0H (1 count = 1 µsec) ±5536 µsec

(2) Special processing in capstan control system

(a) Special processing for error amount calculation

<1> Relation with drum speed error amount

In drum speed error calculation, if the drum speed deviates ±10% or more from the target value,

0 is set to the capstan phase error amount. The purpose of this processing is to prohibit addition

of the capstan phase error amount while the drum speed control system is not in operation and to

reduce the lock time of the motor by operating the capstan motor only with the speed control system.

<2> Relation with capstan speed error amount

By checking the capstan speed error amount detected in the capstan speed error amount calculation

routine, if the capstan speed deviates ±5% or more from the target value, 0 is set to the capstan

phase error amount. The purpose of this processing is to prohibit addition of the capstan phase

error amount while the capstan speed control system is not in operation and to reduce the lock time

of the motor by operating the capstan motor only with the speed control system.

108

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

<3> Relation with playback control (PBCTL) signal missing

When playback control (PBCTL) signal missing occurs, 0 is set to the capstan phase error amount.

PBCTL signal missing is detected by PBCTL signal missing counter. Normally, while PBCTL signal

is input, the PBCTL signal missing counter is incremented in the capstan speed control interrupt

(INTCPT3), and the PBCTL signal missing counter is reset to 0 in the capstan phase control interrupt

(INTCR12).

However, the PBCTL signal missing counter is not reset if the PBCTL signal misses. Therefore,

if PBCTL signal missing counter is 28H (40d) by checking during INTCPT3 interrupt processing,

it is judged that PBCTL signal missing has occurred and a flag is set.

This processing prevents PBCTL signal missing due to tape damage and misdetection of the phase

error amount for playback non-recorded tapes, etc. and keeps the tape speed at the target value.

(b) Capstan extreme high-speed rotation processing

When the capstan rotates in an extremely high speed (when motor control shorts to 5 V, etc.), CFG

interrupt occurs extremely frequently, interrupt processing gets behind, and runs out of time to return to

main routine. Once lapsed into this condition, even the short circuit is repaired, the speed error amount

detection continues to misdetect, keeps high speed rotation, and is unable to return to main routine, so

that pushing keys has no effect.

To avoid this, when the capstan rotates faster than at a certain speed, the interrupt processing thereafter

is not performed and interrupt processing ends by lowering PWM data (to shorten the processing time).

In this program, the processing becomes effective when the CFG cycle becomes 600 µs or higher.

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CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

(3) Loop gain multiplication for each running mode

K^Vand KP shown in Figure 5-51 are, as well as drum control system, loop gains for speed control system and

phase control system, respectively. K^Mis the gain correction coefficient corresponding to each operation mode

and changes according to VCR playback modes.

As discussed in drum control system, K^Vand KP are for adjusting the addition rate of speed system and phase

system.

In the drum control system, there is little speed difference among the operation modes. Accordingly, the entire

loop gain is not varied. However, in capstan control system, there is a large difference between the SP and

EP modes even in standard playback, and speed difference exists in special playback such as CUE/REVIEW.

Therefore, the gain also varies according to each operation mode. K^Mis set as the correction coefficient to

correct the variation.

K^Vand KP are used only as adjustment of addition rate, so that they are represented as KV/KP.

Table 5-3 shows the capstan loop gain in each operation mode.

Table 5-3. Capstan Loop Gain in Each Operation Mode

Operation Mode

KV/KP

4.2

1.1

4.2

3.3

4.2

3.3

4.2

3.3

4.2

3.3

4.2

3.3

KM

6.0

5.25

4.25

6.0

5.25

4.25

Standard playback (PB)

SP

LP

EP

SP

LP

EP

SP

LP

EP

SP

LP

EP

SP

LP

EP

SP

LP

EP

Fast forward search 1 (CUE1)

Fast forward search 2 (CUE2)

Rewind search 1 (REV1)

Rewind search 2 (REV2)

Still, frame (STILL, FRAME)

110

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

(4) Bias value addition

Bias value addition is carried out to keep the motor control voltage at the lock point during servo lock (speed/

phase error amount 0).

The bias value setting method is adopted according to the experimental values. PWM output data in the

condition that capstan is controlled by only speed control and stabilized at the capstan speed target value is

adopted as the bias value.

Since capstan speed differs according to each operation mode, different bias value is required in each

operation mode.

Table 5-4 shows the capstan bias value in each operation mode.

Table 5-4. Capstan Bias Value in Each Operation Mode

Operation Mode

Bias Value

85E0H

8695H

86DFH

8678H

8695H

86DFH

8678H

8695H

86DFH

8678H

8695H

86DFH

8678H

8695H

86DFH

8678H

8695H

86DFH

Standard playback (PB)

SP

LP

EP

SP

LP

EP

SP

LP

EP

SP

LP

EP

SP

LP

EP

SP

LP

EP

Fast forward search 1 (CUE1)

Fast forward search 2 (CUE2)

Rewind search 1 (REV1)

Rewind search 2 (REV2)

Still, frame (STILL, FRAME)

Bias value is added to the sum of speed correction amount and phase correction amount. However, the

arithmetic result may overflow, so that overflow check is carried out. The arithmetic result is fixed to the

maximum if overflow occurs and to the minimum if borrow occurs.

(5) PWM output for capstan motor control

PWM output of the data which is the addition of speed/phase correction amount and bias value is performed.

The data is processed as 16-bit data. However, since the operation range of the PWM output unit is 0FF00H

to 0100H, when operating outside this range, the maximum or the minimum is written. The PWM for capstan

motor control is output in the capstan speed control interrupt routine.

111

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.12 Compensation Filter

The digital servo system only with proportional control element requires a digital filter in the control system for

steady-state deviation elimination. The configuration method of the lag-lead type digital filter, which is often used

in VCR servo systems, is discussed here.

5.12.1 Filter types

Filters are divided into analog filter and digital filter by the difference of operational principle. Analog filters are

configured with circuits such as capacitors (C) and resistors (R) and realize filter characteristics electronically.

Digital filters are configured also with microcontrollers and signal processors, and realize the characteristics equal

to analog filters by performing various arithmetic processing on the input signals which are sampled and quantized.

Digital filters are divided into FIR type and IIR type by the difference of filter configurations.

(1) FIR type (Finite Impulse Response) filter

The finite impulse response filter is also called acyclic filter.

FIR has finite response and no feedback loop due to its filter configuration, that is, the filter output value is

determined only with the input value of the present and the past.

(2) IIR type (Infinite Impulse Response) filter

The Infinite impulse response filter is also called cyclic filter.

Since FIR has feedback loop due to its filter configuration, impulse response continues infinitely. Therefore,

the filter output value is determined not only with the input of the present and the past but also with the output

value of the past. This type of filter realizes steep cut-off characteristics in much lower degree than that of

FIR type filter. The VCR servo system mainly uses the IIR type filter.

112

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.12.2 Biprimary conversion method

(1) Sampling theorem

When using a digital filter, sampling processing is required in the course of converting analog input signals

to digital values.

That is, analog signals are converted to discrete numeric sequences in certain constant time intervals T^S.

However, if the sampling cycle TS is made too long, restoration of the original analog signal is impossible.

The limit of the cycle that the original analog signal can be restored is described with the well-known sampling

theorem below:

1

2f^max.≤ fS =

T^S

fmax. ........... The maximum frequency included in the original analog signal

f^S............... Sampling frequency

That is, unless the frequency twice or more of the maximum frequency included in the original analog signal

is selected for the sampling frequency f^S, it is impossible to restore the original analog signal from the sampled

digital signal.

Figure 5-53 shows sampling theorem observed on frequency spectrum.

Figure 5-53 (1) shows the case the maximum frequency component f^max. satisfies

2fmax. < fS

that is, the original signal is band limited.

In such case, the original signal can be completely restored if the sideband component is eliminated, extracting

only the basic spectral component using ideal low-pass filter whose cut-off frequency f^Cis fC = fS/2.

However, in the case that f^max. does not satisfy sampling theorem, that is,

2f^max. > fS

sections where the original signal spectrum and fold spectrum are overlapped, that is, fold error is generated

as shown in Figure 5-53 (2).

In this case, the restoration of the original signal is impossible even if ideal low-pass filter is used.

Next, sampling theorem is examined on s planar.

The time function of the original signal is defined as f (t), and the result of Laplace transform of the function

is defined as F (s).

Further, F (s) is sampled with sampling cycle T^S. This is defined as F* (s).

Now, assuming the maximum frequency f^max. of the original signal satisfies sampling theorem, the pole of F

(s), as shown in Figure 5-54 (1), is in basic band. The basic band is folded as shown in Figure 5-54 (2) by

sampling processing, as a result, sideband whose width is 2 π/TS is generated, and the pole of F (s) is also

folded.

113

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Since the basic band and sideband are exactly the same, the original signal can be completely restored if only

the basic band component is extracted using ideal low-pass filter.

On the other hand, the case that the original signal does not satisfy sampling theorem is shown in Figure 5-

55.

In this case, the pole of F (s) is located out of the basic band. Therefore, if pole is folded by sampling processing,

pole is generated in the basic band, where pole is not originally located.

Once this happens, the restoration of the original signal is impossible even if only the basic band component

is extracted using ideal low-pass filter, since the basic band component is different from the original one.

Figure 5-53. Fold Error

(1) When 2f^max. < fS

Original spectrum

Ideal low-pass filter

Fold spectrum

(Sampling)

f

max.

f

s

f

max.

f

s

f

s

/2

fs/2

Original spectrum

(2) When 2fmax. > fS

Original spectrum

Fold spectrum

f

max.

f

s

f

max.

f

s

f

s

/2

fs/2

Fold error

114

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-54. Pole Location when Sampling Theorem is Satisfied

(1) Pole location of F (s)

before sampling processing

(2) Pole location of F (s)

after sampling processing

F ^(S)

jω

F* ^(S)

jω

Folded pole

3π

T^s

3π

T^s

Sideband

Basic band

Sideband

F ^(S)pole

π

T^s

π

T^s

Basic band

0

π

T^s

–

π

T^s

2π

T^s

–

3π

T^s

3π

T^s

Figure 5-55. Pole Location when Sampling Theorem is Not Satisfied

(1) Pole location of F (s)

(2) Pole location of F (s)

after sampling processing

before sampling processing

F

(S)

F* ^(S)

jω

3π

F

(S) pole

Ts

3π

Ts

Sideband

Basic band

Sideband

π

Ts

π

Ts

Basic band

0

π

–

Ts

π

2π

–

Ts

3π

Ts

3π

Pole generated by fold

Ts

115

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

(2) Biprimary transform method

Biprimary transform is a transform method to prevent intrusion of fold errors in the standard z function for

analysis of control.

Generally, when analyzing a control system, the analysis in a continuous system is performed on s planar

using Laplace transform and the analysis in a discrete system on z planar using z transform. Transform of

s planar to z planar is called standard z transform.

When configuring a digital filter, it is easier if the filter is designed in a continuous system before transforming

to a discrete system. The issue here is the effect by sampling processing.

That is, if T^Sis made too long when transforming analog signal to discrete numeric sequence in certain time

interval TS, the restoration of original signal is impossible.

The limit sampling frequency fS to restore the original analog signal can be described with the well-known

sampling theorem below:

1

2 • f^max.≤ fS =

T^S

fmax. : The maximum frequency included in the original analog signal

fS

: Sampling frequency

T^S: Sampling cycle

The expression above shows that the restoration of the original analog signal from the sampled digital signal

unless setting the sampling frequency f^Sto twice or more of the frequency included in the original analog signal.

In the following paragraph, this is considered in the corresponding relation of s planar and z planar.

Figure 5-56 shows the mapping by standard z transform. The band of 2π/T^Swidth on s planar is generated

with sampling processing. The area corresponding to the width of this band is mapped on the whole z planar.

That is, block A on s planar (shaded area) is mapped to inside the unit circle on z planar and block B on s

planar is mapped to outside the unit circle on z planar, respectively. Therefore, if a pole by fold error exists

in the 2π/T^Sband on s planar, the fold error is also mapped on z planar.

Figure 5-56. Mapping by Standard z Transform

jω

3π

j

Ts

1

B, D, F

C

A

D

B

π

Ts

A, CE

0

–1

1

π

–

Ts

E

F

–1

3π

–

(Z planar)

Ts

(S planar)

116

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Biprimary transform is one of the processing methods to prevent fold errors from intruding into z planar. In

biprimary conversion, when sampling processing is performed, the whole s planar is transformed to 2π/T^Sband

area before performing standard z transform so that fold errors are not generated. The planar where the whole

s planer is transformed to is defined as s planar.

Figure 5-57 shows the mapping by biprimary transform. Since s transform is a cyclic function consisting of

the band with 2π/T^Swidth, s-z transform with no fold error is acquired if standard z transform is carried out

after s transform.

In biprimary transform, the relation between s operator, which is the parameter of a continuous system, and

z operator, which is the parameter of a discrete system, is represented in the following expression:

2

1 – Z^–1

1 + Z^–1

s =

×

TS

TS : Sampling cycle

From the above expression, the following operation is performed to transform transfer function G (s) expressed

in a continuous system to transfer function G (z) of a discrete system with no fold error.

2

1 – Z^–1

1 + Z^–1

G (z) = G (s) | s =

×

TS

117

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-57. Mapping by Biprimary Transform

jω

0

(S planar)

Biprimary transform

jω

3π

Ts

π

Ts

Basic band

0

π

2π

–

Ts

3π

–

Ts

(S planar)

(Standard z transform)

j

1

– 1

1

0

– 1

(Z planar)

118

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.12.3 Digital filter designing method

An example of digital filter designing methods is shown below.

(1) Determination of specification

Determine the specification of the digital filter to realize, such as frequency characteristics, cut-off frequency,

time area response, and sampling cycle.

(2) Configuration on analog circuit

Design the analog filter satisfying the specification in (1).

At this time, transform operation to digital filter is made easier if the analog circuit is configured with passive

filter using LCR.

(3) Calculation of transfer function

Find the transfer function G (s) in continuous time area of the analog filter found in (2).

(4) Biprimary transform processing

Transform the analog filter transfer function G (s) to discrete time sequence transfer function G (z). At this

time, perform biprimary transform to (s) so that fold errors by sampling processing are avoided.

(5) Determination of filter constant

Calculate digital filter constant from the specification in (1) and quantize the filter coefficient.

The setting of the coefficient word length of the digital filter is determined according to the filter cut-off

frequency, sampling cycle, and dynamic range.

(6) Program generation of digital filter

(7) Measurement of characteristics

Measure whether the digital filter generated in (6) is operating or not as specified using servo analyzer.

Also, measure the dynamic range of the digital filter. The dynamic range refers to the maximum digital value

which will not cause overflow if input to the filter.

(8) Improvement of characteristics

Change the arithmetic word length and filter configuration to improve the characteristics acquired in (7).

Also, shorten the arithmetic word length and change algorithm if the calculation time of the digital filter is too

long.

119

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.12.4 Primary IIR type digital filter transfer function

Figure 5-58 shows primary IIR type digital filter block diagram.

Figure 5-58. Primary IIR Type Digital Filter Block Diagram

+

U

n

X

n

G

Y

n

–

+

Z ^–1

B

A

Un – 1

In Figure 5-58, A, B, and G are filter constants and the meanings of them are as follows:

A : non-cyclic filter constant

B : cyclic filter constant

G : filter gain constant

Assume n-th input value of this filter as Xⁿ, output value as Yn, calculation value in n-th filter arithmetic process

as Un, calculation value of n–1-th filter arithmetic process as Un–1.

From the block diagram in Figure 5-58 , the following expression is found:

Uⁿ= Xn – B × Un–1

Yn = (Un + A × Un-1) × G

(Expression 5-1)

(Expression 5-2)

(Expression 5-3)

If the expression above is solved for Xn:

Xⁿ= Un + B × Un–1

Yn = (Un + A × Un-1) × G

Both parts in the expressions above are z transformed to acquire the following expression:

X (z) = U (z) + Bz^–1U (z)

Y (z) = G (U (z) + Az^–1U (z))

From the expression above, the transfer function G (z) in the system is as follows:

Y (z)

X (z)

G (U (z) + Az^–1U (z))

U (z) + Bz^–1U (z)

G (z) =

=

1 + Az^–1

1 + Bz^–1

= G ×

(Expression 5-4)

120

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

5.12.5 Lag-lead filter configuration method

The lag-lead filter is often used as the drum phase control system compensation filter for VCRs. The purpose is

to eliminate the constant deviation and improve the accuracy of the system.

Figure 5-59 shows the lag-lead filter configuration and characteristics.

Figure 5-59. Lag-lead Filter Configuration and Characteristics

(a) Lag-lead filter configuration

R1

R2

Vin

Vout

i

C

Cut-off frequency

1

f1 =

f2 =

2 π C (R1+R2)

1

2 π CR2

(b) Lag-lead filter board line graph

IG (jω) I [dB]

f1

f2

0

f

(Gain characteristics)

G (jω) I [deg]

0

f

(Phase characteristics)

121

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Figure 5-59 (b) shows lag-lead filter gain characteristics and phase characteristics (board line graph) of the analog

circuit configuration shown in Figure 5-59 (a).

Lag-lead filter has two segmented point frequencies f1 and f2. By freely setting these, the filter gain characteristics

and phase characteristics can be changed.

The method to find the constants (A, B, and G) used in primary IIR type digital filter to realize lag-lead filter

characteristics is as follows:

In the case of the filter shown in Figure 5-59 (a), the segmented point frequencies f1 and f2 are found in the following

expression:

1

f1 =

2πC (R1 + R2)

(Expression 5-5)

(Expression 5-6)

1

f2 =

2πCR2

The transfer function of the filter in Figure 5-59 (a) is found as follows (the transfer function is find by plus

transforming the relational expressions for Vin and Vout, respectively):

1 + ^SCR2

G (s) =

1 + SC (R1 + R2)

1

1 +

S

2πf1

1

=

2πf2

(Expression 5-7)

(Expression 5-8)

1

a =

b =

2πf2

2πf1

Now, if parameter a and b are assumed and assigned as the expression above, the transfer function of lag-lead

filter is as follows:

1 + bS

G (s) =

1 + aS

(Expression 5-9)

Since the transfer function in the expression above is represented in continuous time system, this is transformed

to be represented in discrete time system.

In this case, biprimary transform is used because fold error is generated if standard z transform is performed. That

is, S arithmetic operator is replaced as follows:

2

1 – Z^–1

1 + Z^–1

S =

×

TS

TS : Sampling cycle

(Expression 5-10)

The S operator is assigned to the transfer function, the expression is reorganized.

122

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

2a

T^S

2b

TS

1 – Z^–1

1 + Z^–1

1–Z^–1

1 + Z^–1

T^S– 2a

TS + 2a

TS – 2b

TS + 2b

1 +

×

T^S(1 + Z^–1) +2a (1 – Z^–1

TS (1 + Z^–1) +2b (1 – Z^–1

)

G (z) =

=

×

1 +

Z^–1

T^S+ 2a

TS + 2b

1 + AZ^–1

= G ×

=

×

1 + BZ^–1

Z^–1

(Expression 5-11)

The above transfer function found here has the same configuration as the one found from the primary IIR type

digital filter block diagram in Figure 5-58.

G, A, and B in the expression above are filter coefficients, and turn out as follows:

T^S+ 2a

G =

T^S+ 2b

TS – 2a

A =

TS + 2a

T^S– 2b

B =

T^S+ 2b

(Expression 5-12)

If G, A, and B are found from sampling cycle T^S[sec] and two segmented point frequencies, f1 and f2, which are

filter characteristics, primary IIR type digital filter coefficient can be found. An example of this is shown below.

•

Filter design specification

Sampling cycle

T^S: 4.0 [msec] (sampling frequency 250 Hz)

Segmented point frequency f1 : 1.0 [Hz]

f2 : 10.0 [Hz]

Filter coefficients, G, A, and B are found from the above filter design specification.

a and b are found from Expression 5-8.

1

a =

b =

=

= 0.01591549

= 0.15915494

2π f2

1

2π × 10

1

2π f1

2π × 1

123

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

If a, b, and TS found from the above are assigned to Expression 5-12, filter coefficients G, A, and B are found as

follows:

G = 0.111169375

A = –0.77672957

B = –0.97517917

5.12.6 Filter processing method

Lag-lead filter is configured with product-sum instruction.

Lag-lead filter propagation function is as follows:

Yⁿ= G (Xn + AXn–1) – BYn–1

= G • Xn + AG • Xn–1 + (–B) • Yn–1

The operation of product-sum instruction when the number of operations is two is as follows:

AXDE ← (B) × (C) + (B + 2) × (C + 2) + AXDE

Then each parameter of lag-lead filter is assigned as follows:

AXDE (Left part) : Yⁿ

signed 32 bits

signed 16 bits

signed 32 bits

(B)

: G

(C)

: Xⁿ

(B + 2)

(C + 2)

: AG

: X^n–1

AXDE (Right part) : (–B) • Yn–1

Signed multiplication is considered here.

First, the coefficients G, AG, and (–B) of lag-lead filter are designed with gain of 1, so that they become values

with an absolute value of 1 or less.

| G | <1, | AG | <1, | (–B) | <1

Therefore, the values multiplied with the 15th power of 2 (32768) are actually used for operation.

For example,

0.980 → 0.98 × 32768 = 32112.64 → 7D70H

– 0.980 → –0.98 × 32768 = –32112.64 → 8290H

124

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

The data has the following range if the error amount is also dealt with signs.

8000H–7FFFH (–32768 to +32767)

If this is calculated with signed multiplier:

Example HEX data

decimal

Sign

G

.

8290H

1000H

– 0.980

Sign

Xn

×

4096

F8290000H

– 4014.08

Sign

.

Left shift 1 bit

F052 0000H

Pick higher 16 bits

– 4014

The 1/2 of the actual calculation result enters higher 16 bits of the arithmetic result of signed multiplication.

Therefore, the result is doubled (right shift) after executing product-sum instruction. However, gain multiplication

is normally performed after digital filter calculation, so that there is a method which abbreviates the shift processing

if the gain is doubled.

The propagation function becomes as follows:

Yⁿ’ = G • Xn + AG • Xn–1 + (–B) • Yn–1’

Where

Yⁿ’ = Yn/2

(–B) • Y^n–1’ = (–B) • Yn–1/2

This enables filter calculation only with product-sum instruction.

However, calculation of (–B) Y^n–1is necessary for the following sampling timing, then, singed multiplication is

performed again. Since the result is made 1/2 as it is, right shift processing is performed before multiplication.

125

CHAPTER 5 EXAMPLES OF STATIONARY TYPE VCR SERVO CONTROL

Filter calculation is summarized as follows:

(1) Set values for each register

(B)

(C)

: G

: Xn

(B + 2) : AG

(C + 2) : X^n–1

AXDE : (–B) • Yn–1’ (Already stored in memory at the previous sampling timing)

(2) Execute product-sum instruction

MACSW 2

The value stored in calculation result AXDE is “Yⁿ”

(3) Right shift AXDE 1 bit to “Yn”

SHLW

ROLC

DE

X

A

(4) Find (–B) • Yn´

MULW DE

Store calculation result AXDE in memory and use it as (–B) • Y^n–1’

; DE ← (–B)

126

CHAPTER 6 CTL AMPLIFIER

6.1 CTL Amplifier Auto Gain Control Processing

CTL amplifier is used for amplifying the playback control (PBCTL) signal which is the playback of the CTL signal

recorded on VCR tape. Figure 6-1 shows the CTL amplifier configuration.

Figure 6-1. CTL Amplifier Configuration

To RECCTL driver

VREF

AMPC.1

RECCTL+

RECCTL–

+

–

CTL head

AMPC.1

CTL detection flag L (AMPM0.1)

CTL detection flag S (AMPM0.3)

+

Gain control signal

generation circuit

CTLIN

–

CTL detection flag clear

(write 1 to AMPM0.6)

CTLOUT1

CTLM.0-CTLM.4

Waveform

PBCTL signal (to timer)

CTLOUT2

shaping circuit

127

CHAPTER 6 CTL AMPLIFIER

CTL amplifier is configured with two OP amplifiers and the forestage amplifier is fixed to 20 dB. Therefore, gains

are adjusted by changing the gain of the second stage amplifier.

The gain setting of CTL amplifier can be changed with CTLM register in 32 steps (by 1.78 dB).

Caution

Changing of the gain setting should be avoided while CTL signal is being input.

The µPD784915 has a gain control signal generation circuit which uses CTL detection flags to discriminate the

amplifying state of CTL amplifier output.

CTL detection flags are divided into CTL detection flag S and CTL detection flag L according to the detection level.

CTL detection flags S and L can be cleared by writing “1” to FLGCLR (AMPC0.6).

Using these two detection flags, auto gain control of CTL amplifier is carried out.

Table 6-1 shows the relation between the CTL detection flag read value and CTL amplifier gain adjustment.

Table 6-1. CTL Detection Flag Read Value and CTL Amplifier Gain Adjustment

CTL Detection Flag Read

Discrimination

CTL Amplifier Gain Adjustment

Flag L

Flag S

1

0

1

0

Gain large

Lower gain

No change

Raise gain

Gain optimum

Gain small

Figure 6-2 shows the relationship between CTL amplifier output and each detection level/flag.

Figure 6-2. Relationship between CTL Amplifier Output and Each Detection Level/Flag

Detection level L

Detection level S

Waveform shaping

VREF

Waveform shaping

Detection level S

Detection level L

1

Detection flag S

0

1

Detection flag L

0

128

CHAPTER 6 CTL AMPLIFIER

6.1.1 CTL amplifier auto gain control method

CTL amplifier auto gain control is performed with the timings of CTL detection flag read and the amplifier gain setting

which are determined by the playback control (PBCTL) signal edge interrupt.

•

Timing of CTL detection flag read and CTL amplifier gain setting

As mentioned earlier, change of the gain setting must be done avoiding PBCTL signal input (rising and falling edges

of amplifier amplifying point).

Moreover, since CTL detection flag S and L are specified at the rising and falling edges of PBCTL signal, so that

after changing CTL amplifier gain, the both edge must be passed more than once before flag is read.

In order to pass both edges avoiding PBCTL signal input, the timings of the CTL detection flag read and the amplifier

gain setting are determined by the PBCTL signal edge interrupt (one edge).

•

For PLAY, CUE/REV

<In forward direction> (refer to Figure 6-3)

Gain is changed at 70% point of PBCTL signal.

<In reverse direction> (refer to Figure 6-4)

Gain is changed at 30% point of PBCTL signal.

For FF/REW

<In forward direction> (refer to Figure 6-5)

Gain is changed at 180% point of PBCTL signal.

<In reverse direction> (refer to Figure 6-6)

Gain is changed at 120% point of PBCTL signal.

Remark For PLAY or CUE/REV, gain is changed 65% or more of PBCTL signal in forward direction and less than

35% in reverse direction and the order of the signal input has been set so that the rising edge of the PBCTL

signal is input first and then the falling edge is input.

In addition, for FF/REW, CTL signal input is the fastest, approx. 130 µs (= 33.37 ms/256) in 256-time speed

(when tape mode is EP), and it would take 198 µs Max. before PBCTL signal input INTCR12 interrupt (due

to other priority interrupt), so that the timing has been set at +100%.

129

CHAPTER 6 CTL AMPLIFIER

6.1.2 CTL amplifier auto gain control processing

The following setting and processing are carried out to perform CTL amplifier auto gain control.

(1) The following setting is carried out at every forward/reverse direction change

PBCTL signal input edge is set as follows:

•

The input edge is generated at rising edge of PBCTL signal.

The input edge is generated at falling edge of PBCTL signal.

Remark When the tape mode is EP, INTCR12 vectored interrupt is generated with every PBCTL signal for

PLAY, every nine PBCTL signals for CUE/REV, and every eight PBCTL signals for FF/REW at the

edge shown above.

(2) The following setting and processing are carried out by INTCR12 vectored interrupt

The following time is set to compare register 13 (CR13) by INTCR12 vectored interrupt

•

For PLAY/CUE/REV

Set time 70% of PBCTL signal cycle to CR13

CR13 = CR12 + (CPT30 × 70%)

Set time 30% of PBCTL signal cycle to CR13

CR13 = CR12 + (CPT30 × 30%)

•

For FF/REW

Set time 180% of PBCTL signal cycle to CR13

CR13 = CR12 + (CPT30 × 180%)

Set time 120% of PBCTL signal cycle to CR13

CR13 = CR12 + (CPT30 × 120%)

134

CHAPTER 6 CTL AMPLIFIER

Explanation

•

CR12 : TM1 count value is captured with every INTCR12 vectored interrupt by PBCTL signal

CPT30 : TM3 count value is captured with every INTCR12 vectored interrupt by PBCTL signal

Since CR12 captures TM1 count value and CR13 captures TM3 count value, value need to be set to

CR13 after adding up the input clock ratio of TM1 and TM3 (however, in this time, the setting is

unnecessary because both have the same clock [f^CLK/8]).

INTCR13 interrupt request clear and interrupt enabled

•

(3) Processing at INTCR13

CTL gain control signal detection and gain change

•

According to the status of CTL detection flag S and L, gain is changed by ±1 step as follows:

•

If CTL detection flag S and L are both “1”, gain is large; therefore, decrease the gain for 1 step (1.78

dB)

If CTL detection flag S and L are both “0”, gain is small; therefore, decrease the gain for 1 step (1.78

dB)

If CTL detection flag S is “1” and L is “0”, gain is optimum; therefore, no change is made for the gain.

INTCR13 interrupt disabled

•

(4) Processing at PBCTL

Increase the gain by +5 steps, every time there is no CTL signal and 40 interrupts does not occur

•

continuously at INTCPT13 interrupt (capstan FG interrupt)

The gain is maximum (1FH) on non-recorded tape

(5) Processing in each mode transition

Set the optimum gain previously measured in each mode in every mode transition of each mode (equipment

•

operation such as PLAY and CUE, and tape mode such as EP and SP)

(this processing is optional; however, it has the advantage that the optimum gain can be quickly achieved.)

135

CHAPTER 6 CTL AMPLIFIER

[MEMO]

136

CHAPTER 7 VISS DETECTION

The following shows the VISS detection method.

7.1 What is VISS

VISS stands for “VHS Index Search System”. In VHS, cue code is set by varying the duty ratio of control signal

to be recorded on control track.

Each VISS data is specified as shown in Table 7-1. The cue code as index information is set by data sequence

of control signal as shown in Figure 7-1.

Table 7-1. VISS Data

Data

Waveform in

forward

“ 0 ”

“ 1 ”

100%

60 ±5%

100%

27.5 ±2.5%

direction

PBCTL signal

(before wave-

form shaping)

PBCTL signal

(before wave-

form shaping)

PBCTL signal

(after wave-

form shaping)

PBCTL signal

(after wave-

form shaping)

Waveform in

reverse

100%

60 ±5%

100%

27.5 ±2.5%

PBCTL signal

(before wave-

form shaping)

PBCTL signal

(before wave-

form shaping)

direction

PBCTL signal

(after wave-

form shaping)

PBCTL signal

(after wave-

form shaping)

Figure 7-1. VISS Cue Code

Reference point

61 ±3 bits

Tape running direction

Control track

........

...

0

1

0

63 ±3 bits

137

CHAPTER 7 VISS DETECTION

VISS write (cue code write) is carried out at the following timings.

•

When starting recording (except joint recording)

When starting programmed recording

When index writing by pushing down INDEX key

7.2 VISS Detection

7.2.1 VISS detection method

VISS detection is performed using macro service in data pattern discrimination mode by playback control (PBCTL)

signal edge interrupt (INTCR12).

INTCR12 interrupt also performs PBCTL signal frequency division.

(1) About VISS detection method

In VISS detection, PBCTL signal level is taken at 43.75% (in forward direction) or 56.25% (in reverse direction)

of one PBCTL signal cycle as VISS detection point. According to the level, if the level is high, “0” is set, if

it is low, “1” is set. It is judged that VISS signal exists when “0” is detected 10 times after “1” is consecutively

detected 15 times (According to the specification of system controller, it may be judged VISS signal exists

if “1” is consecutively detected several times).

The µPD784915 is provided with timer 3 (TM3) and capture register 30 (CPT30) to find a cycle, compare

register (CR30) to store VISS detection point, and control flip flop (CTL F/F) to take in control signal level at

detection point, in order to keep up with the change of tape running speed, so that it can perform VISS detection.

Figure 7-2. VISS Detection Circuit (Pulse Width Detection Circuit) Configuration

TM1 (16)

EDVC

Capture

INTCR12

Clear

TM3 (16)

PBCTL

PTR10

PTR11

CR12 (16)

D

CTL

F/F

CK

CPTM (8)

8

CR30 (16)

CR31 (16)

CPT30

(16)

16

Internal bus

FF

. . .

TMC3

FASP

1

LVL2

LVL1

7

0

138

CHAPTER 7 VISS DETECTION

µPD784915 uses macro service in data pattern discrimination mode to perform VISS detection.

The comparison data to perform comparison with the data stored in buffer area is set to an address indicated with

comparison area pointer (not only program space in memory but also internal RAM space can be specified as the

comparison area).

(2) About macro service in data pattern discrimination mode (VISS detection mode)

This is a macro service to sequentially store the output from control flip flop (CTL F/F) in the pulse detection

circuit (timer 3) in the Super Timer Unit into the buffer set in the RAM area with left shift.

The timer measures the PBCTL signal pulse duty from the CTL amplifier circuit, and latches “1” to CTL F/F

if the duty is larger than the value previously set, and “0” if the duty is smaller.

Caution

Take note that “1” and “0” of the VISS signal are reversed.

The contents of SFR (bit 7 of timer control 3) specified with SFR pointer 1 is buffer area left shifted at interrupt

generation. At the same time, the data of buffer area and comparison area are compared, and a vectored

interrupt is generated if they coincide (macro service counter is decremented and if it becomes 0, a vectored

interrupt is also generated).

By option specification (bit 5 of macro service mode register = “1”), the operation is made so that the contents

of SFR [capture trigger 30 (CPT30)] specified with SFR pointer 2 is multiplied with the coefficient and stored

to SFR [compare register 30 (CR30)] specified with SFR pointer 3 (automatic updating of discrimination

threshold when tape speed is varying).

139

CHAPTER 7 VISS DETECTION

Figure 7-3. Data Pattern Discrimination Mode Block Configuration

INTCR12 vectored interrupt

Buffer area (memory) Comparison area (memory)

Coefficient (memory)

CPT30

TM3

Multiplication

Upper address

CR30

CTL F/F

(Bit 7 of TMC3)

Explanation

•

CPT30

: PBCTL signal cycle enters

: multiplier to find detection point enters

Coefficient

CR30

: detection point (the result of CPT30 multiplied with coefficient) enters

: VISS signal data with left shift enters

Buffer area

Comparison area : VISS detection pattern enters

Vectored interrupt is generated when either one of the following conditions is satisfied.

<1> If the contents of macro service counter 8 (MSC) is 0 (if interrupt request is generated for the number of

times set in MSC).

<2> If the data stored in buffer area coincides with the data in the comparison area separately set.

140

CHAPTER 7 VISS DETECTION

Figure 7-4 shows the addressing and data setting in data pattern discrimination mode.

Figure 7-4. Addressing and Data Setting in Data Pattern Discrimination Mode

INTCR12 macro service control register

Channel pointer

(sets lower 8 bits of the

address in MSC)

FE0Dh

FE0Ch

Mode register

( “ 00100100B ” : sets multiplication in

data pattern discrimination mode)

INTCR12 vectored interrupt

(MSC = 0)

Macro service counter

(sets number of PBCTL signal frequen-

cy division in each mode to MSC)

Capture register

(CPT30)

SFR pointer 2

Upper

(sets lower 8 bits of the address

in CPT30)

address

Multiplication coefficient

(sets forward direction: 43.75%(“70h”),

reverse direction: 56.25% (“90h”))

Timer

(TM3)

SFR pointer 3

(sets lower 8 bits of the

address in CR30)

Multiplication

(Coincidence)

SFR pointer 1

(sets lower 8 bits of the

address in TMC3)

Buffer size specification register

(sets 2 bytes)

Compare register

(CR30)

PBCTL

Buffer area (upper)

Buffer area (lower)

D

CK

CLT F/F

Comparison area pointer [upper]

(sets upper 8 bits of upper

address in comparison area)

Bit 7

Lower

address

Timer control register

(TMC3)

INTCR12

vectored interrupt

Comparison area pointer [lower]

(sets lower 8 bits of upper

address in comparison area)

(Coincidence)

Data comparison area [upper]

(00000000B)

Data comparison area [lower]

(0000001B)

(Explanation)

Data flow <by PBCTL signal edge>

Data flow <by coincidence of CPT3 and CR30>

Address specification

Interrupt generation

141

CHAPTER 7 VISS DETECTION

7.2.2 VISS detection processing

The following setting and processing are carried out to perform VISS detection.

(1) Macro service initialization is performed before starting VISS detection

Set data with data pattern discrimination mode multiplication (“14H”) to mode register

•

Set lower 8 bits of the address in macro service counter (MSC) to channel pointer

•

Set buffer area size specification register to 2 bytes (“02H”)

•

Set clear (“0FFFFH”) to 2 bytes of buffer area

•

Set lower 8 bits (“3BH”) of the address in timer control register 3 (TMC3) to SFR pointer 1

•

Set lower 8 bits (“56H”) of the address in timer 3 capture register 0 (CPT30) to SFR pointer 2

•

Set lower 8 bits (“5CH”) of the address in timer 3 compare register 0 (CR30) to SFR pointer 3

•

Set data comparison area address to comparison area pointer

•

Set comparison data (“0001H”) in comparison area

•

Remark The value in the comparison setting area (“0001H”) means that VISS data “0” is entered once after

VISS data “1” is entered 15 times.

Caution

Duty detection malfunction prevent circuit control (TMC3.6) is made operation enable for

preventing VISS signal malfunction. Therefore, take note that unless VISS data “0” is

entered twice consecutively, it is not judged that data “0” is entered (if VISS “1” data is

entered once, it is judged that “1” is entered).

(2) The frequency division of CTL signal is also set in each mode transition (equipment operation such as PLAY/

CUE, and macro service counter (MSC) of tape mode such as EP and SP)

Caution

PBCTL signal frequency division is also performed in INTCR12 interrupt.

In sets not provided with VISS detection, the counter mode macro service is used for PBCTL

signal frequency division while, in sets provided with VISS detection, the data pattern

discrimination mode macro service is used.

142

CHAPTER 7 VISS DETECTION

(3) The following setting is carried out at every forward/reverse direction change

Set each multiplication coefficient as follows:

•

Set 0.4375 time multiplier (70H) which is the value of the 43.75% position of PBCTL signal.

Set 0.5625 time multiplier (90H) which is the value of the 56.25% position of PBCTL signal.

Remark <1> The middle point of the percentage of VISS data “0” and “1” is adopted for multiplication

coefficient.

In forward direction ... (60% + 27.5%) ÷ 2 = 43.75%

In reverse direction ... (40% + 72.5%) ÷ 2 = 56.25%

<2> The multiplication coefficient set value is set as follows:

In forward direction ... 0.4375 × 256 = 112 (70H)

In reverse direction ... 0.5625 × 256 = 144 (90H)

Set PBCTL signal input 4 edge as follows:

•

Generated at PBCTL signal rising edge

Generated at PBCTL signal falling edge

143

CHAPTER 7 VISS DETECTION

(4) INTCR12 macro service processing (automatically executed by macro service)

The following INTCR12 macro service processing is automatically executed with trigger by PBCTL signal edge.

The result of the automatic multiplication of the value of CPT30 and multiplication coefficient is set to CR30.

•

(VISS detection setting)

<In forward direction> (refer to Figure 7-5)

Set 43.75% time of PBCTL signal cycle to CR30.

CR30 ← CPT30 × 43.75%

<In reverse direction> (refer to Figure 7-6)

Set 56.25% time of PBCTL signal cycle to CR30.

CR13 ← CPT30 × 56.25%

(Explanation) CPT30:

TM3 count value (a cycle of PBCTL signal) is captured at every PBCTL signal edge

interrupt.

Value of CLT F/F (TMC3.7) is left shifted to buffer area (the entire buffer is also left shifted).

•

Compared with the value in comparison area, and if they coincide, INTCR12 vectored interrupt is generated.

INTCR12 vectored interrupt is also generated when macro service counter is “0”.

144

CHAPTER 7 VISS DETECTION

Figure 7-5. INTCR12 Macro Service Processing in Forward Direction

Tape running direction

100%

43.75%

PBCTL signal

(before waveform

shaping)

PBCTL signal

(after waveform

shaping)

Specify PBCTL signal

rising edge

(n)

(n+1)

TM3 count value

CTL F/F (TMC3.7)

CPT30 (n)

CR30 (n+1)

INTCR12 macro

service processing

Level taken into CTL F/F

(VISS detection point)

The following processings are automatically performed with INTR12 macro service

CR30 (n+1) ← CPT30 (n) × 0.4375

Left shift CTL F/F (TMC3.7) value to buffer area

Compare the values in comparison area and buffer area if they coincide,

INTCR12 vectored interrupt is generated

(if MSC is “ 0 ”, INTCR12 vectored interrupt is also generated).

145

CHAPTER 7 VISS DETECTION

Figure 7-6. INTCR12 Macro Service Processing in Reverse Direction

Tape running direction

100%

56.25%

PBCTL signal

(before waveform

shaping)

PBCTL signal

(after waveform shaping)

Specify PBCTL signal

falling edge

(n)

(n+1)

TM3 count value

CTL F/F (TMC3.7)

CPT30 (n)

CR30 (n+1)

INTCR12 macro

service processing

Level taken into CTL F/F

(VISS detection point)

The following processings are automatically performed with INTR12 macro service

CR30 (n+1) ← CPT30 (n) × 0.5625

Left shift CTL F/F (TMC3.7) value to buffer area

Compare the values in comparison area and buffer area if they coincide,

INTCR12 vectored interrupt is generated

(if MSC is “ 0 ”, INTCR12 vectored interrupt is also generated).

(5) The following processing is performed at INTCR12 vectored interrupt

Since interrupt is generated either at every CTL signal frequency division or coincidence of data comparison,

the following method is taken to judge which one is generated.

•

If macro service counter (MSC) is not “00H”, it is judged as <interrupt by coincidence of VISS data

comparison>

•

If macro service counter (MSC) is “00H” and the contents of buffer area is “0001H” (the same value as

that of comparison discrimination area) , it is judged as <interrupt by coincidence of VISS data

comparison>

•

Set macro service counter value again

Set macro service interrupt enable

VISS signal is detected. Set VISS detection flag and notify system controller processing

•

Set macro service counter value again

Set macro service interrupt enable

146

CHAPTER 7 VISS DETECTION

7.3 VISS Rewrite

7.3.1 VISS rewrite method

Newly writing VISS signal on recorded tape or erasing VISS signal already written is called VISS rewrite.

Rewrite is performed by rewriting PBCTL signal as shown in Figure 7-7.

Figure 7-7. VISS Rewrite

(a) VISS write

(b) VISS delete

PBCTL signal

Hi-Z

RECCTL +

RECCTL –

PBCTL signal

after rewrite

147

CHAPTER 7 VISS DETECTION

The recording control signal (RECCTL) driver of µPD784915 has rewrite mode used for rewriting VISS signal.

RECCTL driver internally holds sequence data, and the sequence is updated with specific interrupt as trigger.

RECCTL driver sequence in rewrite mode operates RECCTL+ Pin and RECCTL– pin as shown in Table 7-2.

Therefore, VISS signal rewrite is realized considering only the interrupt generation timing, which is a trigger signal.

Table 7-2. RECCTL Driver Rewrite Mode Sequence

Sequence

RECCTL+

RECCTL–

0

1

2

3

High impedance

Low level

High level

Low level

High level

148

CHAPTER 7 VISS DETECTION

7.3.2 VISS rewrite processing

Rewrite processing is realized using INTCR11 and INTCR12.

For rewrite timing, trigger timing is set to compare register 11 (CR11) using PBCTL signal interrupt INTCR12 as

reference.

Figure 7-8 shows VISS = 1 signal rewrite operation timing.

Figure 7-8. VISS = 1 Signal Rewrite Operation Timing Chart

Reference

PBCTL signal

VISS = 0

erase

INTCR12

INTCR11

Timer 1

INTCR11

1

0

2

1

3

2

4

3

Sequence

0

1

RECCTL + pin

RECCTL – pin

PBCTL signal

after rewrite

VISS = 1

rewrite

149

CHAPTER 7 VISS DETECTION

Timing <1> in Figure 7-8 is PBCTL signal rising. At this point, the sequence is initialized, and the changing point

from sequence 0 to sequence 1 is found with timer 1 (TM1) using the captured value as reference value, stored in

compare register 11 (CR11), and INTCR11 interrupt is enabled.

For the following timing <2> and <3> INTCR11 interrupt, each changing point to sequence 2 and 3 is found on

timer 1 and stored in CR11. Rewrite is completed at timing <4> and INTCR11 interrupt is disabled.

Each timing in NTSC is as shown in Table 7-3. VISS = 1 signal and VISS = 0 signal have different timings.

Table 7-3. VISS Write Operation Timings

Timings

PBCTL rising <1> → <2>

<2> → <3>

VISS = 1 Write

VISS = 0 Write

5 ms

4.176 ms

16.192 ms

5 ms

20.021 ms

5.345 ms

5 ms

<3> → <4>

<4> → PBCTL rising

Hi-Z cancellation timing from PBCTL rising is not specified for the period between the timing to become Hi-Z <4>

and PBCTL rising. However, it is set as 5 ms for the sake of convenience, assuming it as the timing approximately

a half way from PBCTL high pulse to PBCTL low pulse when VISS is 1.

150

CHAPTER 8 PROGRAM LIST

This chapter lists programs of this application software.

151

CHAPTER 8 PROGRAM LIST

$

DEBUG

swOLD EQU

0

;-----------------------------

PUBLIC, EXTRN Declaration

;-----------------------------

;------------------------------

PUBLIC

;------------------------------

;/////

PUBLIC

PROCESS ///////

VPT2_000

VR10_000

VPT3_000

VR12_000

VR00_000

VR02_000

VR13_000

; INTCPT2

; PROCESS ROUTINE

; INTCR10

; INTERRUPTION PROCESS

; INTCRP3

; INTERRUPTION

; INTCR12

; DETECTION INTERRUPT

; INTCR00

; TIMING SETTING

; INTCR02

; TIMING SETTING

; INTCR02

; TIMING SETTING

; %INTCR13

; %CTL

DRUM FG INTERRUPTION

DRUM PHASE ERROR DETECTION

CAPSTAN FG

CAPSTAN PHASE ERROR

QUASI Vsync

CTL DETECTION & OUTPUT SETTING

;/////

PUBLIC

;/////

SUBROUTINE /////

YVTBL_00

; SERVO DATA SETTING SUB

RAM ///////////////

PUBLIC

RVSCR12

RVCCR12

; INTCR12 MACRO SERVICE MODE REGISTER

; INTCR12 MACRO SERVICE

; CHANNEL POINTER

PUBLIC

RVMCMPP

RVB2CR12

RVB1CR12

;%INTCR12 MACRO SERVICE COMPARE AREA

; POINTER

; INTCR12 MACRO SERVICE BUFFER

; AREA 2(L)

; INTCR12 MACRO SERVICE BUFFER

; AREA 1(H)

PUBLIC

RVBFREG

; INTCR12 MACRO SERVICE BUFFER SIZE REG

;%INTCR12 MACRO SERVICE SFR POINTER 1

;%INTCR12 MACRO SERVICE SFR POINTER 3

;%INTCR12 MACRO SERVICE KEISU AREA

;%INTCR12 MACRO SERVICE SFR POINTER 2

; INTCR12 MACRO SERVICE COUNTER AREA

;%INTCR12 MACRO SERVICE COMPARE DATA

RVMSFRP1

RVMSFRP3

RVMKEISU

RVMSFRP2

RVMCCR12

RVMCMPD

;////

MACRO SERVICE DATA //// ;%

PUBLIC

PTN_FF

PTN_REW

DT_CMP

;%POSITIVE DIRECTION MULTIPLIER

COEFFICIENT (0.4375) DATA

;%REVERSE DIRECTION MULTIPLIER

COEFFICIENT (0.5625) DATA

;%CR12 COMPARISON DATA

;%VISS

PUBLIC

152

CHAPTER 8 PROGRAM LIST

PUBLIC

RVCPT3

RVSRVCD

RVCPRF

;_L

; CPT3 LOW DATA MEMORY

; SERVO CODE AREA

; CAPSTAN PHASE REFERENCE LOW

PUBLIC

RVCPT2

;_L

;_M

; CPT2 LOW DATA MEMORY

; CPT2 MIDDLE & HIGH DATA MEMORY

PUBLIC

RVCPT1

RVCPT0

; % CPT1

; % CPT0

PUBLIC

RVFSRV_2

RVCEVFG

; SERVO DATA FLAG AREA 2

; SP/LP/EP AUTO DETECT CFG DIVIDE

; COUNTER

PUBLIC

;/////

RVPSVCNT

RVCRAM

; QUASI V SIGNAL COUNTER

; MACRO SERVICE COUNT DATA

; CR10 DATA BUFFER AREA

RVBCR10

BIT ///////////////

PUBLIC

FVPBLP

FVPBSEP

; RUNNING MODE FPBLP FPBSEP

;

SP :

LP :

EP :

PAL:

0

1

0

1

0

1

PUBLIC

;/////

FVDOUT

; QUASI Vsync OUTPUT

FVFLCTL

; SET PBCTL MISSING FLAG

CONSTANT /////

PUBLIC

VSP

VLP

VSLP

VPAL

$

EJECT

;------------------------------

EXTRN

;------------------------------

;

;/////

EXTRN

PROCESS ///////

SR12_000

;/////

EXTRN

SUB ///////////////

YPGADCHG

; SET PG VALUE

EXTRN

;/////

EXTRN

YSA01_R1

; 1SEC TIMER START FOR AUTO-TRACKING

RAM ///////////////

RSNOW

; TRANSITION NOW MODE

153

CHAPTER 8 PROGRAM LIST

EXTRN

RSNEXT

; TRANSITION NEXT MODE

EXTRN

RSCFG90C

RNSTIMO

; CFG 90 PULSE COUNTER CHECK

; TRANSITION TIMER AREA

EXTRN

RSFRSPED

BIT ///////////////

FSVMOFRQ

FSMDCHG

; CAPSTAN FF/REW SPEED LEVEL

;/////

EXTBIT

; V-MUTE OFF REQUEST

; FLAG DURING MODE TRANSITION

; INTCPT2 ENABLE REQUEST FLAG

; DRUM ON/OFF FLAG

FSEICPT2

FSDRMON

FHIFIM

; Hi-Fi MODE FLAG

FSVISSI

; INDEX SEARCH

MODE FLAG

FSVISSO

; ONCE MORE SEARCH MODE FLAG

; VISS MARK/ERASE MODE FLAG

; VISS SEARCH START FLAG

; VISS DETECTION FLAG

FSVISSME

FSVISTR

FSVISSOK

FSAFRQ

; RFS DOWN EDGE FOR AUTO-TRACKING

; CAPSTAN ON FLAG

FSCAPON

FSCRRFRQ

; CAPSTAN REVERSE RFS EDGE ON REQUEST

; FLAG

EXTBIT

;/////

EXTBIT

FNSTENA

FSAEND

; SEARCH DETECT DI TIMER END FLAG

; AUTO TRACKING END FLAG

FNSTENO

FSDFG

; TRANSITION TIMER END FLAG

; DFG EDGE DETECTION FLAG

; TAPE SPEED CHANGE FLAG

FSSPDCHG

PORT ///////////////

PRFS

; RF SWITCHING PULSE

; V-MUTE

PQVD

PCAPFWD

PCAPF_R

; CAPSTAN FORWARD/REVERSE

; CAPSTAN FORWARD/REVERSE (to DECK)

; %

$

INCLUDE (PORT. INC)

EXTBIT FPCAPF_R

; FLAG FOR PORT REFRESH

154

CHAPTER 8 PROGRAM LIST

EXTBIT

;/////

FPQVD

; FLAG FOR PORT REFRESH

CODE /////////////

EXTRN

CSMLOAD

CSMPLAY

; TAPE LOADING

; PLAY

EXTRN

CVPLAY

; PLAY

CVFFRW2H

CVFFRW6H

CVFFRWX3

CVFFREW

CVCUE

CVREV

CVSTILL

CVCUPL

; 2Hrs PLAY (PH FIX)

; 6Hrs PLAY (PH FIX)

; 3Hrs PLAY x3 (PH FIX)

; FF/REW (PH FIX)

; CUE

; REVIEW (VD OUT)

(VD OUT)

; STILL

(VD OUT)

; CUE → PLAY (VD OUT)

; RVS PLAY (VD OUT & PH FIX)

; 6Hrs PLAY (VD OUT & PH FIX)

CVRVS

CVFR6HVD

$

EJECT

;--------------------------------

SERVO RELATED EQU AREA

;

;--------------------------------

;*** SERVO DATA AREA ***

VSEQU1

DSEG

SADDR

;%

;*** SERVO REFERENCE DATA ***

RVDFRF:

RVCPT2:

RVCPT22:

DS

3

; DRUM SPEED REFERENCE

; CPT2 DATA MEMORY

; FOR DEBUG

;*** CAPTURE DATA MEMORY ***

RVCPT0:

RVCPT1:

DS

3

; CPT0 DATA MEMORY

; CPT1 LOW DATA MEMORY

;*** SERVO ERROR DATA ***

RVERDF:

RVERDF_1:

DS

2

; DRUM SPEED ERROR

; DRUM SPEED ERROR(–1)

RVERDP:

RVERDP_1:

DS

2

; DRUM PHASE ERROR

; DRUM PHASE ERROR(–1)

;--- PWM OUTPUT BIAS DATA AREA ---

RVDBAS:

;RVDBAS_L:

;RVDBAS_H:

DS

2

1

; DRUM BIAS LOW BYTE

; DRUM BIAS HIGH BYTE

;--- DRUM PHASE FILTER UNKNOWN-QUANTITY ---

RVERDP_Y:

RVERDP_bY:

RVERDF_Y

DS

2

4

2

4

RVERDF_bY

155

CHAPTER 8 PROGRAM LIST

$

EJECT

;*** FILTER MEMORY ***

;*** FILTER COEFFICIENT DATA *** ; %FILTER PRODUCT-SUM OPERATION WORK AREA

B_buf:

DS

2

; (LOOP GAIN)

; (FILTER COEFFICIENT ” a ”) x

; (LOOP GAIN)

DS

2

; (FILTER COEFFICIENT ” b ”) x

; (OUTPUT) x (–1)

RVC_Kmp:

$EJECT

; CAPSTAN LOOP GAIN ” G1 ”

;*** CAPSTAN DATA ***

RVCFRF:

RVCPRF:

DS

3

2

; CAPSTAN SPEED REFERENCE

; CAPSTAN PHASE REFERENCE

;*** SERVO ERROR DATA ***

RVERCF:

DS

2

; CAPSTAN SPEED ERROR

RVERCP:

RVERCP_1:

DS

2

; CAPSTAN PHASE ERROR

; CAPSTAN PHASE ERROR(–1)

RVERCMX:

DS

2

; CAPSTAN SPEED & PHASE MIXED

; ERROR

: CAPSTAN SPEED & PHASE MIXED

; ERROR(–1)

RVERCMX_1

;*** CAPTURE DATA MEMORY ***

RVCPT3: DS

3

; CPT3 DATA MEMORY

;--- PWM OUTPUT BIAS DATA AREA ---

RVCBAS: DS

2

; CAPSTAN BIAS LEVEL

;--- CAPSTAN PHASE FILTER UNKNOWN-QUANTITY ---

RVERCP_Y:

RVERCP_by:

DS

2

4

; CAPSTAN PHASE ” Y ”

; CAPSTAN PHASE ” b x Y ”

;--- CAPSTAN SPEED/PHASE MIX FILTER UNKNOWN-QUANTITY ---

RVERCMX_Y:

DS

2

4

; CAPSTAN SPEED/PHASE MIX

; ” Y ”

; CAPSTAN SPEED/PHASE MIX

; ” b x Y ”

RVERCMX_bY:

RVSRVCD:

DS

1

; SERVO CODE AREA

FVDOUT

FVPHFX

EQU

RVSRVCE.7

RVSRVCD.6

; QUASI Vsync OUTPUT

; PHASE CONTROL IS NOT PERFORMED

RVCRAM:

DS

1

; MACRO SERVICE COUNT DATA

RVCEVFG:

; SP/LP/EP AUTO DETECT CFG

; DIVIDE COUNTER

156

CHAPTER 8 PROGRAM LIST

RVSLPCH:

DS

1

; SP/LP/EP CHATTERING COUNT

; AREA

RVFSRV_2:

; SERVO DATA FLAG AREA 2

FVDFE10 EQU

FVCFERR EQU

FVCPLCK EQU

RVFSRV_2.7

RVFSRV_2.6

RVFSRV_2.5

; DRUM SPEED ERROR 10% OVER FLAG

; CAPSTAN SPEED ERROR (+/–)SIGN FLAG

; CAPSTAN PHASE LOCK FLAG

; 0:LOCK 1: UNLOCK

FVCFE05 EQU

FVHQVDT EQU

FVFLCTL EQU

RVFSRV_2.4

RVFSRV_2.3

RVFSRV_2.2

RVFSRV_2.1

RVFSRV_2.0

; CAPSTAN SPEED ERROR 5% OVER FLAG

; QVD HIGH TIMING FLAG

; PBCTL ERROR FLAG

; PB LP DATA FLAG

; PB SP/EP DATA FLAG

FVPBLP

EQU

FVPBSEP EQU

;

FPBLP FPBSEP

SP :

0

1

0

1

0

1

LP :

EP :

PAL:

RVPSVCNT:

DS

1

; QUASI V SIGNAL COUNTER

;///// CAPSTAN KV/KP ////////////////

RVC_Kvp:

RVBCR10:

DS

2

;

; Kv/Kp REAL NUMBER (1 BYTE) + DECIMAL

FRACTION (1 BYTE)

;*** CR10 DATA BUFFER AREA ***

; %930

; CR10 BUFFER REG LOW

DS

2

;--- MODE NTSC/MODE PAL FOR ROM READ ---

MODE NTSC

MODE PAL

MODE LP

EQU

0

2

4

;

NTSC_PAL:

DS

1

; FOR SPEED UP

;*** INTCR12 MACRO SERVICE DATA ***

MCRAREA

RVSCR12:

RVCCR12:

DSEG AT 0FE0CH

;%

DS

1

; INTCR12 MACRO SERVICE MODE REGISTER

; INTCR12 MACRO SERVICE CHANNEL

; POINTER

RVMCMPP:

DS

2

;%INTCR12 MACRO SERVICE COMPARE AREA

; POINTER

RVB2CR12:

RVB1CR12:

RVBFREG:

RVMSFRP1:

RVMSFRP3:

RVMKEISU:

RVMSFRP2:

RVMCCR12:

RVMCMPD:

DS

1

2

; INTCR12 MACRO SERVICE BUFFER AREA 2(L)

; INTCR12 MACRO SERVICE BUFFER AREA 1(H)

; INTCR12 MACRO SERVICE BUFFER SIZE REG

;%INTCR12 MACRO SERVICE SFR POINTER 1

;%INTCR12 MACRO SERVICE SFR POINTER 3

;%INTCR12 MACRO SERVICE KEISU AREA

;%INTCR12 MACRO SERVICE SFR POINTER 2

; INTCR12 MACRO SERVICE COUNTER

;%INTCR12 MACRO SERVICE COMPARE AREA

157

CHAPTER 8 PROGRAM LIST

PTN_FF

PTN_REW

DT_CMP

EQU

70H

; %POSITIVE DIRECTION MULTIPLIER

; COEFFICIENT (0.4375)

EQU (PTN_FF XOR 0FFH)+1 ; %REVERSE DIRECTION MULTIPLIER

; COEFFICIENT (0.5625)

EQU

;--- FOR DEBUG ---- %%%%

DSEG UNIT

0000H or 0001H

; %CR30 COMPARISON DATA

; %VISS

DEB

SAVE_CNT:

SAVE_AREA:

DS

2

256

;

;--- SP/LP/EP PAL MODE CODE ----

CVSP

CVSLP

CVLP

EQU

00H

01H

02H

03H

; SP MODE

; EP MODE

; LP MODE

; SP (PAL) MODE

CVPAL

$

EJECT

;-----------------------------

SERVO DATA TABLE

;-----------------------------

VtSRVO CSEG

;////

UNIT

5% of maximum drum speed error amount ////

tDF_5per:

DW

022CH

029AH

;NTSC 1.3903ms / 125ns * 0.05 = 556.1

;PAL 1.6667ms / 125ns * 0.05 = 666.7

;////

10% of maximum drum speed error amount ////

tDF_10per:

DW 0458H

;NTSC 1.3903ms / 125ns * 0.1 = 1112.2

DW 0535H

;////

;PAL 1.6667ms / 125ns * 0.1 = 1333.3

Drum speed gain ////

tDF_Kv:

DW 011C2H

;NTSC 32767 / (0.23066ms / 125ns)= 17.76

;PAL

;////

Maximum drum speed error amount xx.xx ////

tDF_max:

DW 0735H

;NTSC 8388607 / 4546 = 1845.3

;PAL

DW 0735H

;////

Minimum drum speed error amount ////

tDF_min:

DW 10000H - 0735H

;NTSC

;PAL

;////

Filter coefficient of drum speed (G) ////

tDF_fG:

158

CHAPTER 8 PROGRAM LIST

DW

015FDH

015A0H

; NTSC

; PAL

;////

Filter coefficient of drum speed (aG) ////

tDF_fAG:

DW

0F2A8H

0F22CH

; NTSC

; PAL

;////

Filter coefficient of drum speed (-b) ////

tDF_fB:

DW

0775AH

07832H

; NTSC

; PAL

;////

Drum phase gain ////

tDP_Kp:

; NTSC 32767 / (5.710ms / 125ns) = 0.717

; NTSC %8/18 ADJUSTMENT

; PAL

DW 0FC40H

;////

Maximum drum phase error amount ////

tDP_max:

DW 2220H

; NTSC 8386607 / 0B7 = 45839.4 > 32767

; NTSC

;////

Minimum drum phase error amount ////

tDP_min:

DW 10000H - 2220H

; NTSC

; PAL

;////

Filter coefficient of drum phase (G) ////

tDP_fG:

DW 006D2H

DW 0086EH

; NTSC

; PAL

;////

Filter coefficient of drum phase (aG) ////

tDP_fAG:

DW 0F987H

DW 0F815H

; NTSC

; PAL

;////

tDP_fB:

Filter coefficient of drum phase (-b) ////

DW 07FA5H

DW 07F7BH

; NTSC

; PAL

;////

10% of maximum capstan speed error amount ////

tCF_10per:

DW 0458H

DW 0C60H

; NTSC 2.7778ms / 125ns * 0.1 = 2222.2

; PAL 3.9602ms / 125ns * 0.1 = 3668.2

159

CHAPTER 8 PROGRAM LIST

;

;////

Capstan speed gain ////

;tCF_Kv, tCP_Kp are given in table per mode.

;//// Maximum capstan speed error amount ////

tCF_max:

DW

1E79H

; NTSC 8386607 / 433(1075) = 7801.5...4.2

; PAL 8386607 / 433(1075) = 7801.5

;////

Minimum capstan speed error amount ////

tCF_min:

DW

10000H - 1E79H

10000h - 1E79H

; NTSC

; PAL

;////

Filter coefficient of capstan speed phase composite (G) ////

tCMX_fG:

DW

0205FH

01478H

01796H

; NTSC

; PAL

; LP

;////

Filter coefficient of capstan speed phase composite (aG) ////

tCMX_fAG:

DW

0E0A1H

0ECDCH

0E9C0H

; NTSC

; PAL

; LP

;////

Filter coefficient of capstan speed phase composite (-b) ////

tCMX_fB:

DW

07EFEH

07EA9H

; NTSC

; PAL

; LP

;////

Maximum capstan phase error amount ////

tCP_max:

DW

15A0H

; NTSC 8386607 / 0BD5 = 2768.8

; PAL 8386607 / 0BD5 = 2768.8

;////

Minimum capstan phase error amount ////

tCP_min:

DW

10000H - 15A0H

; NTSC

; PAL

;////

Filter coefficient of capstan phase control (G) ////

fCP_fG:

DW

01264H

010D8H

; 01164H %% ; NTSC

; PAL

;////

Filter coefficient of capstan phase control (aG) ////

fCP_fAG:

DW

0EE74H

0EFF1H

; NTSC

; PAL

160

CHAPTER 8 PROGRAM LIST

;////

Filter coefficient of capstan phase control (–b) ////

tCP_fB:

DW

07F57H

07F35H

; NTSC

; PAL

;------- Data store subroutine ---------------------

;

FOR DEBUG

SAVE_AX:

XCH

ADD

MOVW

XCH

RET

B,!SAVE_CNT

B, #2

SAVE_AREA[B], AX

B,!SAVE_CNT

$

EJECT

CSEG

VDFG

UNIT

;----------------------------------------------------

INTCPT2 DRUM FG INTERRUPTION PROCESS ROUTINE

;

;----------------------------------------------------

;

VPT2_000 : Interruption initial processing

VPT2_100 : Drum speed error calculation

VPT2_200 : Drum phase error x loop gain (Kp)

VPT2_300 : Drum speed error x loop gain (Kv)

VPT2_400 : Drum speed adjustment amount + drum

phase adjustment degree + bias value

;

VPT2_500 : Save capture value (next CPT2n - 1)

VPT2_600 : Processing after interruption

;----------------------------------------------------

Interruption initial process

;

;----------------------------------------------------

VPT2_000:;V

:///// Register setting /////////

SEL

VPT2_010:

;///// Highest order interruption enable ///

RB2

MOVW

PUSH

MOVW

NOP

AX,MK0

AX

AX,MK1

;%%%

AX

; SAVE MASK REGISTER

;%SAVE MASK REGISTER

;%

PUSH

OR

MK0L,#11101111b

MK0H,#01111100b

MK1L,#11110111b

MK1H,#11111110b

;%INTCR00 ENABLE

;%INTP2, INTCR02, INTCR11 ENABLE

;%INTCR13 ENABLE ;%ctl

;%INTP3 ENABLE

EI

SET1

FSDFG

; SET DFG EDGE DETECTION FLAG

161

CHAPTER 8 PROGRAM LIST

MOVG

RVCPT22,WHL

; FOR DEBUG %%%

MOVG

ADDG

SUBG

BH

TDE,RVDFRF

TDE,#7FFFH

TDE,WHL

; LIMIT THE MAXIMUM VALUE

;

; SET THE MAXIMUM VALUE TO 7FFFH + TARGET VALUE

;

$VPT2_101

ADDG

WHL,TDE

;

VPT2_101:

VPT2_110:

;///// E DV CALCULATION ///////////

SUBG

WHL,RVDFEF

; E DV = ∆NDF – NDFL

; DRUM SPEED ERROR = MEASURED SPEED –

TARGET SPEED

VPT2_120:;B

;///// Get error amount /////////

MOVW

BF

AX,HL

A.7,$VPT2_128

; ABSOLUTE VALUE CALCULATION

;

MOVW

SUBW

HL,#0

HL,AX

;

; HL ← ABSOLUTE VALUE

VPT2_128:

MOVW

VP,AX

; VP ← ERROR AMOUNT

MOV

AND

A,RVFSRV_2

A,#00000011b

; READ RUN MODE

;

MOV

B,#MODE NTSC

CMP

BNE

A,#CVPAL

$VPT2_129

; PAL?

; No

MOV

B,#MODE PAL

NTSC PAL,B

;

VPT2_129:

MOV

; STORE NTSC = 0/PAL = 2

VPT2_130:;B

;///// Check error amount 5% ///

MOVW

AX, tDF_5per[B]

;

DW

022CH

029AH

;

CMPW

BC

HL,AX

$VPT2_140

;

MOVW

RVERDP_1,#0000H

RVERDP_Y,#0000H

RVERDP_bY,#0000H

;%

; DRUM PHASE ERROR ← 0000H

;%

162

CHAPTER 8 PROGRAM LIST

MOVW

VPT2_140:;B

;///// Check error 10% ///

RVERDP_bY+2,#0000H

;%

MOVW

AX,tDF_10per[B]

;

DW

0458H

0535H

;

VPT2_140_10 :

CMPW

MOV1

AX,HL

FVDFE10,CY

;

; SET FLAG IF DRUM SPEED ERROR IS 10% OR MORE

VPT2_150:;B

;///// Check maximum error value ///

MOVW

AX,tDF_MAX[B]

; LIMIT MAXIMUM VALUE OF DRUM SPEED ERROR

;

DW

0735H

;

CMPW

BNC

AX,HL

$VPT2_160

; MAXIMUM VALUE: DRUM SPEED ERROR

;

>=

CMPW

BC

VP,#8000H

$VPT2_151

; SIGN

; CY = 1 POSITIVE NUMBER

; CY = 0 NEGATIVE NUMBER

MOVW

AX,tDF_MIN[B]

; MINIMUM VALUE: DRUM SPEED ERROR

;

DW

10000H-0735H

;

VPT2_151:;B

MOVW

VPT2_160:;B

;///// Save speed error ///////

VP,AX

;

XCHW

MOVW

VP,RVERDF

RVERDF_1,VP

; RVERDF ← ERROR AMOUNT OF THIS TIME

; RVERDF_1 ← ERROR AMOUNT OF LAST TIME

163

CHAPTER 8 PROGRAM LIST

;---------------------------------------------------------------------------------

;

Lag read filter processing

;---------------------------------------------------------------------------------

;

0. Set filter coefficient

NTSC:

f1

f2

=

8

56

calculation from

DFG = 719.28Hz

MAL a = –0.60695401

MBL b = –0.93247632

MGL g = 0.17179585

PAL:

f1

f2

=

6

42

calculation from

DFG = 600.00Hz

MAL a = –0.63946320

MBL b = –0.93908194

MGL g = 0.16896488

----------------------------------------------------------------------------------

VPT2_170:

;/////Set filter coefficient ///

MOV

B,NTSC_PAL

;

MOVW

AX,tDF_fG[B]

B_buf,AX

AX,tDF_fAG[B]

B_buf+2,AX

AX,tDF_fB[B]

B_buf+4,AX

;

;/////Filter calculation processing ///

MOV

MOVW

B,#LOW(B_buf)

C,#LOW(RVERDF)

DE,RVERDF_bY

;

AX,RVERDF_bY+2

MACSW

MOVW

2

; LAG READ FILTER PROCESSING

RVERDF_Y,AX

; DRUM SPEED ERROR AMOUNT

(AFTER FILTER CALCULATION)

MOVW

DE,B_buf+4

;

MULW

SHLW

ROLC

DE

;

DE,1

X,1

A,1

MOVW

RVERDF_bY,DE

RVERDF_bY+2,AX

; (–b)•Y

;

164

CHAPTER 8 PROGRAM LIST

;---------------------------------------------------------------------------------

;

Drum phase error x Loop gain (Kp)

;---------------------------------------------------------------------------------

;

0. Get Kp (Decimal fraction is ignored)

NTSC

PAL

Kp = –3.75

Real number

: 0FC40H

1. Phase error x Loop gain

HL ← HL + AX

;---------------------------------------------------------------------------------

VPT2_200:

;/////Get Kp ///////////

MOV

MOVW

B,NTSC_PAL

AX,tDP_Kp[B]

;

DW

11C2H

;

;/////Error x Kp ////////

MOVW

MULW

DE,RVERDP_Y

DE

; DRUM PHASE ERROR AMOUNT

(AFTER FILTER CALCULATION)

;

CMPW

BNC

AX,#0FF80H

$VPT2_230

; ZERO CHECK

;

CMP

BNC

A,#80H

$VPT2_229

;

; UNDERFLOW

CMPW

BC

AX,#0080H

$VPT2_230

;

MOVW

BR

AX,#7FFFH

VPT2_231

; 7FFFH ← OVERFLOW

;

VPT2_229:

MOVW

BR

AX,#8000H

VPT2_231

; 8000H ← UNDERFLOW

;

VPT2_230:

MOV

A,X

X,D

; A(XD)E

;

VPT2_231:

MOVW

HL,AX

; HL ← DRUM PHASE ERROR AMOUNT

(AFTER GAIN ADDITION)

VPT2_220:

165

CHAPTER 8 PROGRAM LIST

;---------------------------------------------------------------------------------

;

Drum speed error x Loop gain (Kv)

;---------------------------------------------------------------------------------

;

0. Get Kv (Decimal fraction is ignored)

NTSC

PAL

Kv = 17.76

Real number

: 11C2H

: 08E1H

1. Speed error x Loop gain

AX ← AX + DE

;;--------------------------------------------------------------------------------

VPT2_300:;B

;/////Get Kv ///////////

MOV

MOVW

B,NTSC_PAL

AX,tDF_Kv[B]

;

;/////Error x Kv ////////

MOVW

MULW

DE,RVERDF_Y

DE

; DRUM SPEED ERROR AMOUNT

(AFTER FILTER OPERATION)

; AX ← DRUM SPEED ERROR AMOUNT

(AFTER GAIN ADDITION)

MOV

A,X

X,D

; A(XD)E

;

;---------------------------------------------------------------------------------

; Drum speed adjustment + Drum phase adjustment + bias value → PWM 0

;---------------------------------------------------------------------------------

;

VPT2_400:;B

;/////Speed total + bias + phase total gain /////

ADDW

BNV

AX,HL

$VPT2_411

; DRUM PHASE ERROR ADDITION

;

MOVW

ADDC

AX,#07FFFH

X,#0

A,#0

; 7FFFH ← OVERFLOW

;

; 8000H ← UNDERFLOW

VPT2_411:

BT

A.7,$VPT2_412

;

ADDW

BR

AX,RVDBAS

VPT2_420

; BIAS ADDITION (<7FFF)

;

VPT2_412:

ADDW

BC

AX,RVDBAS

$VPT2_420

; BIAS ADDITION (<7FFF)

;

MOVW

AX,#0000H

; 0000H ← OVERFLOW

166

CHAPTER 8 PROGRAM LIST

VPT2_420:;B

;/////PWM 0 Output //////////

;v% PWM limitation items

CMPW

BC

AX,#0100H

$VPT2_421

CMPW

BNH

AX,#0FF00H

$VPT2_422

MOVW

BR

AX,#0FF00H

VPT2_422

VPT2_421:

MOVW

AX,#0100H

VPT2_422:

;^% PWM limitation items

MOVW PWM0,AX

; SET DRUM PWM DATA

;---------------------------------------------------------------------------------

Save capture value (Next CPT2n - 1)

;

;---------------------------------------------------------------------------------

VPT2_500:

;/////Save CPT2 ///////

MOVG

RVCPT2,UUP

;

;---------------------------------------------------------------------------------

Processing after interrupt

;

;---------------------------------------------------------------------------------

VPT2_600:

;///// Multiple interrupt disable /////

DI

POP

MOVW

AX

MK1,AX

; %RETURN MASK REGISTER

; %SET MASK REGISTER

POP

AX

; RETURN MASK REGISTER

MOV1

CY,CRMK02

A.0,CY

; LOAD INTCR0 2 INTERRUPT MASK FLAG

; SAVE INTCR0 2 INTERRUPT MASK FLAG

MOV1

CY,PMK2

A.7,CY

; %LOAD INTP 2 INTERRUPT MASK FLAG

; %SAVE INTP 2 INTERRUPT MASK FLAG

MOVW

MK0,AX

; SET MASK REGISTER

VPT2_EXT:

RETI

EJECT

CSEG

$

VDPGP

UNIT

167

CHAPTER 8 PROGRAM LIST

;---------------------------------------------------------------------------------

;

INTCR10 Drum phase error detection interruption processing

;---------------------------------------------------------------------------------

;

VR10_000 : Interrupt initial processing

VP10_100 : Calculation of phase control target value

VP10_200 : Calculation of drum phase error

VP10_300 : Lag read filter processing

VP10_400 : Processing after interrupt

;---------------------------------------------------------------------------------

Interrupt initial processing

;

;---------------------------------------------------------------------------------

VR10_000:;V

;/////Register setting /////////

SEL

RB2

; HIGH-ORDER INTERRUPT

VR10_010:

;/////Read CPT0 ////

MOVW

MOV

MOVG

AX,CPT0L

HL,AX

A,CPT0H

W,A

;

UUP,WHL

VR10_020:

;/////Drum on check ///

BT

FSDRMON,$VR10_030

RETI

VR10_030:;B

;/////Check speed error /////

BF

RETI

FVDFE10,$VR10_040

; 10% OR MORE DRUM SPEED ERROR? NO

; Yes INTERRUPT END

VR10_040:;B

;/////High-order interrupt enable ///

MOVW

PUSH

MOVW

NOP

AX,MK0

AX

AX,MK1

; SAVE MASK REGISTER

;%SAVE MASK REGISTER

; %%%

;%

PUSH

AX

OR

MK0L,#11101111B

MK0H,#01111100B

MK1L,#11110111B

MK1H,#11111110B

;%INTCR00 ENABLE

;%INTP2, INTCR02, INTCR11 ENABLE

;%INTCR13 ENABLE ;%CTL

;%INTP3 ENABLE

EI

168

CHAPTER 8 PROGRAM LIST

;---------------------------------------------------------------------------------

;

Calculation of phase control target value

;---------------------------------------------------------------------------------

;

<1>Digital value equal to HSW pulse delay amount

CR00 x 4 times (difference between timer 0 and FRC clock frequency)

<2>Delay amount for half cycle of frame

CR10 value

<3>Delay amount for 6.5 Hrs

6.5 Hrs (0.41 msec) ÷ 125 ns (FRC clock) = 616d

<4>Delay amount for Vsync separation

SOFT execution time ÷ 125 ns (FRC clock)

;---------------------------------------------------------------------------------

VR10_100:

;/////Phase target value calculation ///////

; SET MINIMUM UNIT TO 0.500 us

MOVG

MOVW

SHLW

ADDW

WHL,#0

HL,CR00

HL,1

;

; CR00*2

;

; + CR10

HL,CR10

ADDG

MOVG

WHL,#0355H

VVP,WHL

; + (<3> + <4>) 413.14 + 13.5

; = 426.64 µs (853)

; VVP ← PHASE TARGET VALUE

;---------------------------------------------------------------------------------

Drum phase error calculation

;

;---------------------------------------------------------------------------------

;

; 0. Phase error calculation

;

EDP = [(CPT0 value) – (CPT1 value)] – NDPL

EDP

:Drum phase error amount

NDPL

:Phase control target value

MCPT1

MCPT0

:Capture value of internal HSW falling edge only

:Capture at CR10 match

; 1. Check phase error maximum value

;

Assume NTSC error ≥ 06B1H → error = 06B1H (maximum)

Assume PAL error ≥ 06B1H → error = 06B1H (maximum)

;---------------------------------------------------------------------------------

169

CHAPTER 8 PROGRAM LIST

VR10_200:

;/////Phase error calculation /////////

MOVG

SUBG

WHL,UUP

RVCPT0,WHL

WHL,RVCPT1

; (MCPT0 – MCPT1)

;

; DRUM PHASE ERROR

MOV

A,W

; DIVIDE DRUM PHASE ERROR INTO 1/2

AND

SHR

A,#03FH

A,1

;

;%%

MOV

W,A

;

RORC

SHR

MOV

RORC

H,1

L,1

A,1

W,A

H,1

L,1

;

;%%

MOV

MOVW

MOV

B,NTSC_PAL

AX,tDP_MAX[B]

T,#0

; LIMIT MAXIMUM VALUE

;

MOVW

ADDG

DE,AX

TDE,VVP

;

; SET MAXIMUM VALUE TO TARGET +

MAXIMUM LIMITATION VALUE

SUBG

BH

TDE,WHL

$VR10_201

;

ADDG

WHL, TDE

;

VR10_201:

SUBG

BNC

WHL,VVP

; DRUM PHASE ERROR –

; E DP (TARGET VALUE OF DRUM PHASE ERROR)

; IS ERROR AMOUNT NEGATIVE VALUE?

$VR10_220

;/////Check maximum error value ///

; NEGATIVE VALUE

;;

MOV

B,NTSC_PAL

T,#0FFH

;

; LESS THAN MINIMUM VALUE?

MOVW

SUBG

BC

AX,tDP_MIN[B]

DE,AX

TDE,WHL

;

; MINIMUM VALUE – ERROR AMOUNT

;

$VR10_220

MOVW

HL,AX

;

VR10_220:

XCHW

MOVW

HL,RVERDP

RVERDP_1,HL

; RVERDP ← DRUM PHASE ERROR OF THIS TIME

; RVERDP_1 ← DRUM PHASE ERROR OF LAST TIME

170

CHAPTER 8 PROGRAM LIST

;---------------------------------------------------------------------------------

;

Lag read filter processing

;---------------------------------------------------------------------------------

;

0. Set filter coefficient

NTSC:

f1 = 0.013Hz

f2 = 0.25 Hz

DPG = 30Hz

calculation from

MAL a = –0.94897592

MBL b = –0.99728098

MGL g

=

0.05328881

PAL:

f1 = 0.016Hz

f2 = 0.25 Hz

DPG = 25Hz

calculation from

MAL a = –0.93908194

MBL b = –0.99598683

MGL g

=

0.06587816

;;--------------------------------------------------------------------------------

VR10_300:;B

;/////Set filter coefficient ///

MOV

B,NTSC_PAL

;

MOVW

AX,tDP_fG[B]

B_buf,AX

AX,tDP_fAG[B]

B_buf+2,AX

AX,tDP_fB[B]

B_buf+4,AX

;

VR10_310:;B

;/////

Filter calculation processing /////

MOV

MOVW

B,#LOW(B_buf)

C,#LOW(RVERDP)

DE,RVERDP_bY

;

AX,RVERDP_bY+2

MACSW

MOVW

2

;

RVERDP_Y,AX

; DRUM PHASE ERROR AMOUNT

(AFTER FILTER CALCULATION)

MOVW

DE,B_buf+4

;

VR10_YL EQU

13FH

BT

CMPW

BC

MOVW

BR

A.7,$VR10_312

AX,#VR10_YL

$VR10_314

AX,#VR10_YL

VR10_314

;;;;; MAXIMUM LIMITATION PROCESSING Yn – 1

; POSITIVE NUMBER

;

171

CHAPTER 8 PROGRAM LIST

VR10_312:

CMPW

AX,#10000H - VR10_YL

; NEGATIVE NUMBER

BNC

$VR10_314

;

MOVW

AX,#10000H - VR10_YL

;

VR10_314:

;;;;;

MULW

SHLW

ROLC

DE

;

DE,1

X,1

A,1

MOVW

RVERDP_bY,DE

RVERDP_bY+2,AX

; (–b)•Y

;

;---------------------------------------------------------------------------------

CR10 Revision processing

;

;---------------------------------------------------------------------------------

VR10_320:

MOVW

AX,RVBCR10

CR10,AX

; CR10 ← CR10 DATA BUFFER AREA

;

; Note: When write CR10, perform in

;

INTCR10 routine. (Unless, TM1

may overflow depending on timing

of writing!)

;---------------------------------------------------------------------------------

Processing after interrupt

;

;---------------------------------------------------------------------------------

VR10_400:

;/////Multiple interrupt disable /////

DI

POP

MOVW

AX

MK1,AX

; %RETURN MASK REGISTER

; %SET MASK REGISTER

POP

AX

; RETURN MASK REGISTER

MOV1

CY,CRMK02

A.0,CY

; LOAD INTCR02 INTERRUPT MASK FLAG

; SAVE INTCR02 INTERRUPT MASK FLAG

MOV1

CY,PMK2

A.7,CY

; %LOAD INTP2 INTERRUPT MASK FLAG

; %SAVE INTP2 INTERRUPT MASK FLAG

MOVW

MK0,AX

; SET MASK REGISTER

VR10_EXT:

RETI

EJECT

CSEG

$

VCFG

UNIT

172

CHAPTER 8 PROGRAM LIST

;---------------------------------------------------------------------------------

;

INTCPT3 Capstan FG interrupt

;---------------------------------------------------------------------------------

;

VRT3_000 : Interrupt initial processing

VRT3_100 : PBCTL signal missing detection

VRT3_200 : Capstan speed error calculation

VRT3_300 : Error amount calculation special processing

VRT3_400 : Speed error x loop gain (Kv/Kp)

VRT3_500 : Capstan speed adjustment amount + Capstan phase

adjustment amount

VRT3_600 : MIX error amount digital filter processing

VRT3_700 : Capstan speed/phase MIX (Yn) x gain adjustment

VRT3_800 : Capstan speed/phase MIX adjustment value + bias value

VPT3_900 : Capstan PWM output

VRT3_A00 : Processing after interrupt

;---------------------------------------------------------------------------------

Interrupt initial processing

;

;---------------------------------------------------------------------------------

VPT3_000:;V

;/////Register setting /////////

SEL

RB2

; HIGH ORDER INTERRUPT

VPT3_010:

;/////Multiple interrupt enable ////

MOVW

PUSH

MOVW

NOP

AX,MK0

AX

AX,MK1

;%%%

AX

; SAVE MASK REGISTER

;%SAVE MASK REGISTER

;%

PUSH

OR

MK0L,#11101111B

MK0H,#01111100B

MK1L,#11110111B

MK1H,#11111110B

;%INTCR00 ENABLE

;%INTP2,INTCR02, INTCR11 ENABLE

;%INTCR13 ENABLE ;%ctl

;%INTP3 ENABLE

EI

VPT3_015:

;/////Check CFG 90 pulse counter ////

CMP

BZ

RSCFG90C,#00

$VPT3_100

DEC

RSCFG90C

;---------------------------------------------------------------------------------

;

Increment play run mode automatic judgment counter

PBCTL signal missing detection

;---------------------------------------------------------------------------------

VPT3_100:

INC

RVCEVFG

; CFG counter increment @@@ change

173

CHAPTER 8 PROGRAM LIST

VPT3_110:

BT

VPT3_130:

FSMDCHG,$VPT3_200

; AT TRANSITION? Yes

CMP

BC

RVCEVFG,#40

$VPT3_200

; PBCTL SIGNAL MISSING? @@@ CHANGE

; No

VPT3_140:

BT

SET1

VPT3_141:

FVPHFX,$VPT3_141

FVFLCTL

;%PH FIX ON? Yes (FF/REW) ;%ctl

; SET PBCTL SIGNAL MISSING FLAG

;%CTL

MOV

RVCEVFG,#00

; CLEAR PLAY MODE JUDGMENT COUNTER ;@@@

; CHANGE

;%ctl v

;%

;%% CTL AMP GAIN INC(+5)

;% AMPLIFY CTL AMP GAIN BY +5 DURING PBCTL SIGNAL MISSING

MOV

ADD

CMP

BC

A,CTLM

A,#05H

A,#1FH

$VPT3_150

;%

MOV

VPT3_150:;B

MOV

A,#1FH

CTLM.A

;%

;%ctl ^

;-----------------------------------------------------------------------

Calculate capstan speed error

;

;-----------------------------------------------------------------------

;

∆NCF = CPT3n – CPT3n-1

∆NCF: Capture value of this time – capture value of last time

ECV = ∆NCF – NCFL

ECV

NCFL

: Capstan speed error amount

: Capstan speed target value

;-----------------------------------------------------------------------

VPT3_200:;B

MOVW

MOV

MOVG

AX,CPT3L

HL,AX

A,CPT3H

W,A

;

UUP,WHL

SUBG

MOV

WHL,RVCPT3

A,W

; ∆NCF = CPT3n – CPT3n-1

;

AND

MOV

A,#003FH

W,A

;

MOVG

SUBG

BNC

VVP,WHL

WHL,#12C0H

$VPT3_201

;

; Check capstan abnormal high speed rotating

; CFG is within 600 µsec?

174

CHAPTER 8 PROGRAM LIST

MOVW

BR

AX,#1FFFH

VPT3_820

; Yes

; TO AVOID OCCURRING CFG FREQUENT INTERRUPT

; DUE TO MOTOR RUNAWAY,

; AND MICRO CONTROLLER’S RUNAWAY

VPT3_201:;B

MOVG

ADDG

SUBG

BH

WHL,VVP

;

TDE,RVCFRF

TDE,#7FFFH

TDE,WHL

; LIMIT MAXIMUM VALUE

;

; SET MAXIMUM VALUE TO 7FFFH + TARGET VALUE

;

$VPT3_202

ADDG

WHL,TDE

;

VPT3_202:

SUBG

WHL,RVCFRF

; ECV = ∆NCF – NCFL

MOVW

BF

AX,HL

A.7,$VPT3_203

; CALCULATION OF ABSOLUTE VALUE

; NEGATIVE VALUE?

MOVW

SUBW

HL,#0

HL,AX

;

; HL ← ABSOLUTE VALUE

VPT3_203:

MOVW

VP,AX

; VP ← ERROR AMOUNT

;--------------------------------------------------------------------------

Error amount calculation special processing

;

;--------------------------------------------------------------------------

;

When set capstan phase error amount to 0

• When drum speed error amount is more than ± 10%

Flag more than 10%: FSDP10=1

• When capstan speed error amount is more than ± 10%

Error amount is calculated by NTSC/PAL PLAY target value.

NTSC5% : 56CEH x 0.10 = 0458H

PAL 5% : 7BC1H x 0.10 = 0C60H

• When PBCTL signal missing is detected in play

• At FF/REW mode

• When capstan phase servo disabled (during loading)

;--------------------------------------------------------------------------

VPT3_300:;B

MOV

AND

A,RVFSRV_2

A,#00000011b

; READ RUN MODE

;

MOV

B,#MODE NTSC

CMP

BNE

A,#CVPAL

$VPT3_321

; PAL?

; No

175

CHAPTER 8 PROGRAM LIST

MOV

VPT3_321:

B,#MODE PAL

;

MOV

NTSC_PAL,B

MOVW

AX,tCF_MAX[B]

; LESS THAN MAXIMUM VALUE?

;

DW

1E79H

CMPW

BC

HL,AX

; ERROR AMOUNT (ABSOLUTE VALUE):

; MAXIMUM VALUE

$VPT3_320

;

=<

CMPW

BC

VP,#8000H

$VPT3_311

; SIGN

; CY=1 POSITIVE

; CY=0 NEGATIVE

;

MOVW

AX,tCF_MIN[B]

VP,AX

VPT3_311:

MOVW

; SET MAXIMUM VALUE AS SPEED ERROR AMOUNT

VPT3_320:;B

MOVW

RVERCF,VP

AX,tCF_10per[B]

; CAPSTAN SPEED ERROR

;

DW 0458H

DW 0C60H

;

CLR1

FVCFE05

;

CMPW

BNC

AX,HL

$VPT3_330

;

SET1

BR

FVCFE05

;

VPT3_340

VPT3_330:;b

BT

FVPHFX,$VPT3_340

FVDFE10,$VPT3_340

FVFLCTL,$VPT3_400

; PH FIX ON? YES(FF/REW)

BT

BF

; IS DRUM SPEED ERROR MORE THAN 10%? YES

; PBCTL SIGNAL MISSING? NO

VPT3_340:;B

;/////Phase error amount to 0 //////

MOVW

RVERCP_Y,#0

RVERCP,#0

RVERCP_1,#0

RVERCP_bY,#0

RVERCP_bY+2,#0

; CAPSTAN PHASE ERROR ← 0000H

;

; CAPSTAN PHASE FILTER

; CLEAR MEMORY

176

CHAPTER 8 PROGRAM LIST

;----------------------------------------------------------------------

;

Capstan speed error x Loop gain (Kv/Kp)

;----------------------------------------------------------------------

;

AX ← AX + DE

;----------------------------------------------------------------------

VPT3_400:;B

MOVW

AX,RVERCF

DE,RVC_Kvp

; CAPSTAN SPEED ERROR

; SPEED PHASE ERROR MIX RATE

MULW

DE

; A(XD)E

MOV

A,X

X,D

; 8 BITS SHIFT (SET VALID ONLY 16 BITS)

;

;----------------------------------------------------------------------

Capstan speed adjustment amount + Capstan phase adjustment amount

;----------------------------------------------------------------------

;

MOVW

SHLW

DE,RVERCP_Y

DE,2

; CAPSTAN PHASE ERROR

; %%% 3

ADDW

BNV

AX,DE

; CAPSTAN SPEED ERROR AMOUNT + CAPSTAN

; PHASE ERROR

;

$VPT3_511

MOVW

ADDC

AX,#7FFFH

X,#0

A,#0

;

; 7FFFH ← OVERFLOW

; 8000H ← UNDERFLOW

VPT3_511:

XCHW

MOVW

AX,RVERCMX

RVERCMX_1,AX

; CAPSTAN SPEED PHASE MIX ERROR

;

;----------------------------------------------------------------------

Speed/phase MIX error amount digital filter processing

;

;----------------------------------------------------------------------

;

0. Set filter coefficient

NTSC

SP/EP

f1 = 0.45 Hz

f2 = 1.8 Hz

CFG = 360 Hz

calculation from

MAL

MBL

MGL

a = –0.96906992

b = –0.99217674

g = 0.25293372

NTSC

LP

f1 = 0.45 Hz

f2 = 2.5 Hz

CFG = 270 Hz

calculation from

MAL

MBL

a = –0.94346684

b = –0.98958257

177

CHAPTER 8 PROGRAM LIST

;

MGL

g = 0.18427114

SP

PAL

f1 = 0.42 Hz

f2 = 2.7 Hz

CFG = 252.51 Hz

MAL

MBL

MGL

calculation from

a = –0.93499961

b = –0.98960350

g = 0.15994518

VPT3_600:;B

VPT3_610:

;/////Run mode judgment ////////

MOV

B,NTSC_PAL

;

MOV

AND

A,RVFSRV_2

A,#00000011B

; READ RUN MODE

CMP

BNE

A,#CVLP

$CPT3_611

; LP?

;

MOV

B,#MODE LP

;

; B ← NTSC(0)/PAL(2)/LP(4)

CPT3_611:

MOVW

AX,tCMX_fG[B]

B_buf,AX

AX,tCMX_fAG[B]

B_buf+2,AX

AX,tCMX_fB[B]

B_buf+4,AX

;

MOV

MOVW

B,#LOW(B_buf)

C,#LOW(RVERCMX)

DE,RVERCMX_bY

AX,RVERCMX_bY+2

;

MACSW

MOVW

2

;

RVERCMX_Y,AX

DE,B_buf+4

; Y

;

MULW

SHLW

ROLC

DE

;

DE,1

X,1

A,1

MOVW

RVERCMX_bY,DE

RVERCMX_bY+2,AX

; (–b)•Y

;

178

CHAPTER 8 PROGRAM LIST

;----------------------------------------------------------------------

;

Capstan speed/phase mix (Yn) x gain adjustment

;----------------------------------------------------------------------

;

AX ← AX + DE

;----------------------------------------------------------------------

VPT3_700:

MOVW

AX,RVC_Kmp

DE,RVERCMX_Y

;

MULW

DE

; A(XD)E

CMPW

BNC

AX,#0FF80H

$VPT3_730

; ZERO CHECK

;

CMP

BNC

A,#80H

$VPT3_729

;

; UNDERFLOW

CMPW

BC

AX,#0080H

$VPT3_730

;

MOVW

BR

AX,#7FFFH

VPT3_731

; 7FFFH ← OVERFLOW

;

VPT3_729:

MOVW

BR

AX,#8000H

VPT3_731

; 8000H ← UNDERFLOW

;

VPT3_730:

MOV

A,X

X,D

; 8-BIT SHIFT (ONLY FOR 16-BIT)

;

VPT3_731:

;----------------------------------------------------------------------

Capstan speed/phase MIX adjustment value + bias value

;

;----------------------------------------------------------------------

VPT3_800:;B

; swBIAS8

swBIAS8

EQU 0

EQU 1

; BIAS IS LESS THAN 8000H

; BIAS IS 8000H OR MORE

$_IF(swBIAS8)

;

Add processing at bias (=> 8000H)

BF

A.7,$VPT3_812

;

ADDW

BR

AX,RVCBAS

VPT3_820

; NEGATIVE NUMBER BEFORE ADDING

;

VPT3_812:

ADDW

AX,RVCBAS

$VPT3_820

AX,#0FFFFH

; WHEN POSITIVE NUMBER BEFORE ADDING

; OVERFLOW MAY OCCUR

;

BNC

MOVW

; 0FFFFH ← OVERFLOW

179

CHAPTER 8 PROGRAM LIST

$ELSE

;

Add processing at bias (=< 7FFFH)

BF

A.7,$VPT3_812

AX,RVCBAS

;

ADDW

BC

; WHEN NEGATIVE NUMBER BEFORE ADDING

; UNDERFLOW MAY OCCUR

;

$VPT3_820

MOVW

BR

AX,#0000H

VPT3_820

; 0000H ← UNDERFLOW

;

VPT3_812:

ADDW

AX,RVCBAS

; POSITIVE NUMBER BEFORE ADDING

$ENDIF

;---------------------------------------------------------------------------------

Capstan speed level judgment at FF/REW

;

;---------------------------------------------------------------------------------

VPT3_820:;B

MOVW

MOV

AND

CMP

BNE

BC,AX

; SAVE PWM OUTPUT DATA

A,RVSRVCD

A,#11110000B

A,#CVFFREW

$VPT3_830

; CLEAR LOW-ORDER 4 BITS

; FF/REW?

; No

MOV

BT

A,RVERCF

; CAPTURE HIGH-ORDER BYTE OF CAPSTAN

; SPEED ADJUSTMENT

; IS CAPSTAN SPEED ADJUSTMENT AMOUNT (–)?

; No

A.7,$VPT3_823

; %%% MODIFICATION IS REQUIRED

VPT3_821:

CMP

BC

CMP

BC

A,#2

$VPT3_823

A,#6

; C-ERR

0H - 1FFH

$VPT3_822

; C-ERR 200H - 5FFH

; C-ERR 600H - MAX

; LEVEL 0

MOV

BR

A,#0

$VPT3_824

VPT3_822:

MOV

BR

VPT3_823:

MOV

VPT3_824:

A,#1

$VPT3_824

; LEVEL 1

; LEVEL 2

A,#2

MOV

MOVW

RSFRSPED,A

BC,#0FFFFH

; CAPSTAN FF/REW SPEED LEVEL SET

; PWM OUTPUT FULL

VPT3_830:;B

MOVW

AX,BC

; PWM OUTPUT DATA RETURN

180

CHAPTER 8 PROGRAM LIST

;---------------------------------------------------------------------------------

;

Capstan PWM suppression control at PLAY → REVIEW

;---------------------------------------------------------------------------------

VPT3_840:

MOVW

MOV

AND

BC,AX

A,RVSRVCD

A,#11110000B

; SAVE PWM OUTPUT DATA

; CLEAR LOW-ORDER 4 BITS

CMP

BE

A,#CVFR6HVD

$VPT3_841

; 6Hrs PLAY? (AT SPIN OFF RF GEAR)

; Yes

CMP

BNE

A,#CVRVS

$VPT3_842

; RVS PLAY? (AT REVERSE PLAY)

; No

VPT3_841:

MOVW

CMPW

BC

AX,BC

;

AX,#0B333H

$VPT3_842

BC,#0B333H

; CAPSTAN PWM 0B333H (3.5 V) OR HIGHER?

;

; PWM OUTPUT 3.5 V

MOVW

VPT3_842:

MOVW

AX,BC

; PWM OUTPUT DATA RETURN

;---------------------------------------------------------------------------------

Output capstan PWM

;

;---------------------------------------------------------------------------------

VPT3_900:;B

;v%PWM limitations

CMPW

BC

AX,#0100H

$VPT3_901

CMPW

BNH

AX,#0FF00H

$VPT3_902

MOVW

BR

AX,#0FF00H

VPT3_902

VPT3_901:

MOVW

VPT3_902:

;^%PWM limitations

AX,#0100H

MOVW

PWM1,AX

; SET CAPSTAN PWM DATA

;///// SAVE CPT3 ///////

MOVG

RVCPT3,UUP

;

;---------------------------------------------------------------------------------

Multiple interruption prohibited

;

;---------------------------------------------------------------------------------

VPT3_A00:

DI

POP

MOVW

AX

MK1,AX

; %RETURN MASK REGISTER

; %SET MASK REGISTER

181

CHAPTER 8 PROGRAM LIST

POP

AX

; RETURN MASK REGISTER

MOV1

CY,CRMK02

A.0,CY

; LOAD INTCR02 INTERRUPT MASK FLAG

; SAVE INTCR02 INTERRUPT MASK FLAG

MOV1

CY,PMK2

A.7,CY

; %LOAD INTP2 INTERRUPT MASK FLAG

; %SAVE INTP2 INTERRUPT MASK FLAG

MOVW

RETI

MK0,AX

; SET MASK REGISTER

; CAPSTAN FG INTERRUPT PROCESSING END

;%%%ctl

v

$

NOLIST

SUBTITLE(’SRV0.ASM : INTCR13 ROUTINE CTL detection & output interruption’)

$

LIST

EJECT

VCTL

CSEG

UNIT

;---------------------------------------------------------------------------------

INTCR13 CTL detection & output interrupt

;---------------------------------------------------------------------------------

;

VR13_000 : Interrupt initial processing

VR13_100 : CTL detection & output interrupt processing

;---------------------------------------------------------------------------------

Interrupt initial processing

;

;---------------------------------------------------------------------------------

VR13_000:;V

;/////Register setting /////////

SEL

RB3

; HIGHEST-ORDER INTERRUPT!!

VR13_100:

;*********************************************************************************

; GAIN CONTROL

;*********************************************************************************

; REWRITE GAIN AT PLAY and CUE/REV

CALL

!GAINADJ

; CTL AMP GAIN ADJUST

SET1

CRMK13

; INTCR13 INTERRUPT DISABLE

RETI

;

;***************************

; GAIN ADJUST SUBROUTINE

;***************************

GAINADJ

:

MOV

A,AMPMO

;

SET1

MOV1

FLGCLR

CY,A.3

; CTL FLAG CLEAR

182

CHAPTER 8 PROGRAM LIST

XOR1

BC

CY,A.1

$GAIN_E

;

MOV

AND

X,CTLM

X,#00011111B

BF

CMP

BZ

DEC

BR

A.3,$GAIN_UP

X,#0

$GAIN_E

X

;DOWN

;UP

GAINSET

GAIN_UP

:

CMP

BZ

INC

:

X,#1FH

$GAIN_E

X

GAINSET

MOV

CTLM,X

GAIN_E :

RET

;

;%%%CTL ^

$EJECT

VCPG

CSEG

UNIT

;------------------------------------------------------

;

INTCR12 Capstan phase error detection interrupt

At Play: Interrupt by PBCTL signal

;------------------------------------------------------

;

VR12_000 : Interrupt initial processing

VR12_020 : VISS signal detection processing

VR12_200 : Play run mode automatic judgment processing

VR12_300 : Capstan phase error calculation

VR12_400 : Lag read filter processing

VR12_500 : PBCTL signal missing check

VR12_600 : Processing after interrupt

VR12_T00 : Run mode judgment table

;------------------------------------------------------

; Interruption initial processing

;------------------------------------------------------

VR12_000:;V

;///// Register setting /////////

SEL

RB2

; High-order interrupt

VR12_010:

;///// Highest-order interrupt enable ///

MOVW

PUSH

MOVW

NOP

AX,MK0

AX

AX,MK1

; Save mask register

;%Save mask register

; %%%

;%

PUSH

AX

OR MK0L,#11101111B

OR MK0H,#01111100B

;%INTCR00 ENABLE

;%INTP2, INTCR02,

183

CHAPTER 8 PROGRAM LIST

; INTCR11 ENABLE

OR

MK1L,#11110111B

MK1H,#11111110B

;%INTCR13 ENABLE ;%CTL

;%INTP3 ENABLE

EI

;

VR12_020:

;/////Macro service ////////

CMP

BNE

RVMCCR12,#00H

$VR12_032

; IS MSC INTERRUPTING WITH “0”?

; No

CMPW

BE

RVB2CR12,#DT_CMP

$VR12_032

; ARE BUFFER 1 AND 2 COMPARISON AREA

; INFORMATION?

; Yes

MOV

SET1

BR

RVMCCR12,RVCRAM

CRISM12

VR12_120

; SET MACRO SERVICE COUNTER VALUE

; SET INTCR12 MACRO SERVICE INTERRUPT

;%

;

VR12_032:;B

MOV

SET1

RVMCCR12,RVCRAM

CRISM12

; SET MACRO SERVICE COUNTER VALUE

; SET INTCR12 MACRO SERVICE INTERRUPT

VR12_040:

;

/// SEARCH MODE CHECK ///

;%

BF

FSCAPON,$VR12_111

FNSTENA,$VR12_111

; CAPSTAN ON?

; SEARCH DETECT DI? (150 msec)

;

MOV

AND

CMP

BNE

BR

A,RVSRVCD

A,#11110000B

A,#CVFFRW6H

$VR12_045

; CLEAR LOW-ORDER 4 BITS

; AT FF/REW START?

; No

!VR12_111

; DISABLE VISS!

;

VR12_045:;B

CMP

BE

RSNOW,#CSMPLAY

$VR12_050

; DURING PLAY?

; Yes

; No

CMP

BNE

BR

RSNEXT,#CSMPLAY

$VR12_060

VR12_111

;

;%a No

;%a Yes

;

VR12_050:;B

BT

BF

FSVM0FRQ,$VR12_111

PQVD,$VR12_111

; V_MUTE OFF?(”1” PULSE DETECTION?)

;

; No

VR12_060:;B

BT

BF

FSVISSI,$VR12_100

FSVISSO,$VR12_100

FSVISSME,$VR12_111

; INDEX SEARCH MODE?

; ONCE MORE SEARCH MODE?

; MARK/ERASE MODE?

; Yes

VR12_100:;B

;

/// VISS OK ///

;%

SET1

FSVISSOK

; SET VISS SIGNAL DETECTION FLAG!!

VR12_111:;B

;%

/// BUFFER AREA CLEAR ///

;%

184

CHAPTER 8 PROGRAM LIST

MOVW

RVB2CR12,#0FFFFH

;%BUFFER AREA 1,2 CLEAR

; (REVERSE/FORWARD ALL 1 CLEAR)

VR12_120:;B

;

/// COUNTER FLAG CLEAR ///

;%

BF

FSVISTR,$VR12_121

FSVISTR

FSVISSOK

CLR1

MOVW

; CLEAR VISS SIGNAL DETECTION START FLAG!!

; CLEAR VISS SIGNAL DETECTION FLAG!!

;%BUFFER AREA 1,2 CLEAR

RVB2CR12,#0FFFFH

; (REVERSE/FORWARD ALL 1 CLEAR)

;

/// Set coefficient multiplied by CR30 at Macro Service ///

;%

VR12_121:;B

MOV

A,#PTN_REW

;% (REVERSE)

BT

MOV

PCAPFWD,$VR12_122

A,#PTN_FF

;% CAPSTAN FORWARD OR REVERSE ?

;% (FORWARD)

VR12_122:;B

MOV

;%

RVMKEISU,A

;%VISS ^

$

EJECT

;%%%CTL v

;--------------------------------------------------

;-- DETERMINE CTL AMP GAIN SETTING POSITION

;--------------------------------------------------

VR12_A000:

CLR1

INTM1.4

;%a (REVERSE) PBCTL:↓ EDGE

BT

SET1

PCAPFWD,$VR12_A00

INTM1.4

;%a CAPSTAN FORWARD OR REVERSE ?

;%a (FORWARD) PBCTL: ↑ EDGE

VR12_A00:;B

;

BT

FSMDCHG,$VR12_A10

; AT TRANSITION? Yes

MOV

AND

CMP

BNE

A,RVSRVCD

A,#11110000B

A,#CVFFREW

$VR12_A01

; CLEAR LOW-ORDER 4 BITS

; FF/REW ?

; No

;

/// CR13 COMPARATOR UPDATE (FF/REW) /// ;%

MOVW

AX,CPT30

BC,#0133H

; LOAD PBCTL CAPTURE DATA

;%(REVERSE) CPT30 x 1.2

; ...(256 x 1.2)

BT

MOVW

PCAPFWD,$VR12_A05

BC,#01CDH

; CAPSTAN FORWARD OR REVERSE ?

;%(FORWARD) CPT30 x 1.8

; ...(256 x 1.8)

VP12_A05:;B

;

MULUW BC

; CPT30 x ***

MOV

A,X

; AX ← XB

MOV

BR

X,B

VR12_A04

;

185

CHAPTER 8 PROGRAM LIST

;

/// CR13 COMPARATOR UPDATE (PLAY, CUE/REV) ///

VR12_A01:;B

MOVW

AX,CPT30

BC,#4CCDH

; LOAD PBCTL CAPTURE DATA

;%(REVERSE) CPT30 x 0.3

; ...(65536 x 0.3)

MOVW

BT

MOVW

PCAPFWD,$VR12_A02

BC,#0B333H

; CAPSTAN FORWARD OR REVERSE ?

;%(FORWARD) CPT30 x 0.7

; ...(65536 x 0.7)

VR12_A02:;B

MULUW BC

VR12_A04:;B

; CPT30 x ***

ADDW

AX,CR12

; (CPT30 x ***) + CR12

CMPW

BC

SUBW

AX,CR10

$VR12_A03

AX,CR10

;

VR12_A03:

MOVW

CR13,AX

; CR13 UPDATE

CLR1

CRIF13

CRMK13

; CLEAR INTCR13 INTERRUPT REQUEST

; ENABLE INTCR13 INTERRUPT

VR12_A10:;B

;%%%CTL

;--------------------------------------------------

;-- VISS MARK/ERASE

;--------------------------------------------------

CALL

!SR12_000

; VISS MARK/ERASE

;/////Servo mode judgment ///////

MOV

AND

A,RVSRVCD

A,#11110000b

; CLEAR LOW-ORDER 4 BITS

BF

BR

FVPHFX,$VR12_200

VR12_500

; PH FIX ON? No

; Yes (FF/REW)

$

EJECT

;--------------------------------------------------

; PLAY RUN MODE AUTOMATIC JUDGMENT PROCESSING

;--------------------------------------------------

;

Run mode is judged by the count number

of capstan FG signals after the event divider division

that is input into one cycle of PBCTL.

VR12_200:;B

BF

BR

FVCFE05,$VR12_210

VR12_2B0

; CAPSTAN SPEED ERROR IS MORE THAN 5%?

; Yes

VR12_210:;B

MOVG

WHL,#VR12_T00

; %REFER TO TABLE

186

CHAPTER 8 PROGRAM LIST

MOV

MOVW

A,RVCEVFG

BC,#0900H

; RUN MODE JUDGEMENT CFG COUNTER

; COUNTER INITIALIZATION

VR12_220:;B

CMP

BNL

A,[HL]

$VR12_230

; >=

INC

CMP

BNE

A

; +1 CHECK

; NOT MATCH

A,[HL]

$VR12_2B0

VR12_230:;B

BE

$VR12_240

; =

INCW

INC

HL

C

; SET NEXT DATA

; SET PULSE TYPE COUNTER +1

DBNZ

BR

B,$VR12_220

$VR12_2B0

; CHECK COMPLETE? No

; Yes

VR12_240:;B

MOV

AND

A,RVSLPCH

A,#0FH

; JUDGMENT CHATTERING COUNTER

; READ BACK UP DATA

XCH

CMP

BE

A,C

$VR12_250

; MATCH?

; Yes

MOV

BR

RVSLPCH,A

VR12_2C0

; INITIALIZE

VR12_250:;B

ADD

RVSLPCH,#10H

; JUDGMENT CHATTERING COUNTER

; H INCREMENT

CMP

BC

RVSLPCH,#30H

$VR12_2C0

; CHATTERING ABSORPTION COMPLETE?

; No

; Yes

VR12_260:

;//// Run mode set ///////

XCH

A,C

; STORE PULSE TYPE COUNTER

; GET RUN MODE

MOV

AND

A,RVFSRV_2

A,#3

ADD

A,A

MOV

B,A

MOVW

MOV

AX,ttVR12_SPEED[B]

B,#0

ADDW

MOVW

AX,BC

HL,AX

VR12_262:

MOV

CMP

A,[HL]

A,#03

; CHANGE TO PAL MODE

187

CHAPTER 8 PROGRAM LIST

BNE

$VR12_264

; No

BF

BR

FHIFIM,$VR12_264

VR12_2B0

; PAL MODE ? Yes

; NO MODE CHANGE

VR12_264:;J

MOV

AND

OR

A,RVFSRV_2

A,#0FCH

A,[HL]

XCH

A,RVFSRV_2

; SET MODE

XOR

AND

BE

A,RVFSRV_2

A,#03

$VR12_2B0

; NO MODE CHANGE

VR12_270:

CALL

VR12_280:

CALLF !YSA01_R1

!YVTBL_00

; REFER TO SET SERVO CODE & REFER TO TABLE

; 1SEC TIMER START FOR AUTO-TRACKING

CLR1

FSAEND

; ONE AUTO-TRACKING END

; CLEAR FLAG

SET1

VR12_2B0:;B

MOV

VR12_2C0:

FSSPDCHG

; SET MARK/ERASE RELEASE REQUEST FLAG

RVSLPCH,#00H

; RUN MODE JUDGMENT CHATTERING COUNTER

MOV

RVCEVFG,#00H

$VR12_300

; RUN MODE JUDGMENT CFG COUNTER

; INITIALIZE

BR

$

EJECT

;----------------------------------------------------------------------

; Capstan phase error calculation

;----------------------------------------------------------------------

;

Value of CR12

at PLAY

: Capture value of TM1 by PBCTL

at RECORD : Capture value of TM1 by CFG division signal

E CP = (CR12 value) – N CPL

N CPL : Capstan phase target value

NF

: Internal reference timer value (CR10)

;----------------------------------------------------------------------

VR12_300:;B

;/////Internal reference timer value ///////

MOVW

SHRW

DE,CR10

DE,1

; INTERNAL REFERENCE TIMER VALUE

; SET HALF CYCLE

188

CHAPTER 8 PROGRAM LIST

VR12_310:

;/////Phase error calculation ////////

MOVW

SUBW

MOVW

AX,CR12

AX,RVCPRF

HL,AX

; LOAD PHASE CAPTURE DATA

; E CP = NP – N CPL

; HL

BC

$VR12_321

; IS PHASE ERROR (-)?

; WHEN (+),

SUBW

BC

AX,DE

$VR12_322

; SUBTRACT HALF CYCLE

; WHEN WITHOUT CARRY,

; SUBTRACT HALF CYCLE AGAIN

SUBW

MOVW

AX,DE

HL,AX

;

BR

VR12_323

; BECAUSE SIGN IS OPPOSITE,

; COMPARE WITH MINIMUM VALUE

VR12_321:

; WHEN (–),

ADDW

BC

AX,DE

$VR12_323

; ADD HALF CYCLE

; WHEN WITHOUT CARRY,

; ADD HALF CYCLE AGAIN

ADDW

MOVW

AX,DE

HL,AX

;

VR12_322:

MOV

B,NTSC_PAL

AX,tCP_MAX[B]

AX,HL

; (+) → COMPARE WITH MAXIMUM VALUE

MOVW

CMPW

BNC

;

$VR12_325

MOVW

BR

HL,AX

;

$VR12_325

VR12_323:

MOV

B,NTSC_PAL

AX,tCP_MIN[B]

AX,HL

; (–) → COMPARE WITH MINIMUM VALUE

MOVW

CMPW

BNH

;

$VR12_325

MOVW

BR

HL,AX

;

;;

$VR12_325

VR12_325:

XCHW

MOVW

HL,RVERCP

RVERCP_1,HL

; RVERDP ← PHASE ERROR AMOUNT OF THIS TIME

; RVERDP_1 ← PHASE ERROR AMOUNT OF LAST TIME

189

CHAPTER 8 PROGRAM LIST

;---------------------------------------------------------------------------------

;

Lag read filter processing

;---------------------------------------------------------------------------------

;

0. Set filer coefficient

NTSC

f1 = 0.0245 Hz

f2 = 0.180 Hz

DPG = 30 Hz

MAL a = –0.96299834

MBL b = –0.99488186

MGL g = 0.13832185

PAL

f1 = 0.0245 Hz

f2 = 0.190 Hz

DPG = 25 Hz

MAL a = –0.95336134

MBL b = –0.99386137

MGL g = 0.13162089

VR12_400:;B

VR12_410:

; *** Clear filter memory when loading ***

;

* Because of inputting error information at loading

CMP

BNE

RSNEXT,#CSMLOAD

$VR12_420

; LOADING?

; No

MOVW

RVERCP_Y,#0

RVERCP,#0

RVERCP_1,#0

RVERCP_bY,#0

RVERCP_bY+2,#0

;

VR12_420:;B

;/////Run mode judgment ////////

MOV

B,NTSC_PAL

;

MOVW

AX,tCP_fG[B]

B_buf,AX

AX,tCP_fAG[B]

B_buf+2,AX

AX,tCP_fB[B]

B_buf+4,AX

;

VR12_426:;B

MOV

MOVW

B,#LOW(B_buf)

C,#LOW(RVERCP)

DE,RVERCP_bY

;

AX,RVERCP_bY+2

190

CHAPTER 8 PROGRAM LIST

MACSW

MOVW

2

;

RVERCP_Y,AX

; CAPSTAN PHASE ERROR AMOUNT

; (AFTER FILTER OPERATION)

MOVW

DE,B_buf+4

;

MULW

SHLW

ROLC

DE

;

DE,1

X,1

A,1

MOVW

RVERCP_bY,DE

RVERCP_bY+2,AX

;

; (–b)•Y

;---------------------------------------------------------------------------------

; PBCTL signal missing check counter initialize

;---------------------------------------------------------------------------------

VR12_500:;B

MOV

CLR1

RVCEVFG,#00H

FVFLCTL

; Clear CFG counter

; Reset PBCTL missing flag

;---------------------------------------------------------------------------------

Multiple interruption disable

;

;---------------------------------------------------------------------------------

VR12_600:

DI

POP

AX

; %RETURN MASK REGISTER

MOV1

CY,CRMK13

X.3,CY

;% LOAD INTCR13 INTERRUPT MASK FLAG

;%CTL

;% SAVE INTCR13 INTERRUPT MASK FLAG

;%CTL

MOVW

POP

MK1,AX

AX

;%SET MASK REGISTER

; RETURN MASK REGISTER

MOV1

CY,CRMK02

A.0,CY

; LOAD INTCR02 INTERRUPT MASK FLAG

; SAVE INTCR02 INTERRUPT MASK FLAG

MOV1

CY,PMK2

A.7,CY

;%LOAD INTP2 INTERRUPT MASK FLAG

;%SAVE INTP2 INTERRUPT MASK FLAG

MOV1

CY,CRMK11

A.1,CY

; LOAD INTCR11 INTERRUPT MASK FLAG

; SAVE INTCR11 INTERRUPT MASK FLAG

MOVW

RETI

MK0,AX

;

; Vsync OR CR10 match

; INTERRUPT PROCESSING END

191

CHAPTER 8 PROGRAM LIST

;---------------------------------------------------------------------------------

;

Run mode judgment table

;---------------------------------------------------------------------------------

;//// Number of CFG division ////////

VR12_T00:

DB

5,7,9,11,13,16,19,31,37

; PULSE DATA

;//// Run mode conversion table ///

ttVR12_SPEED:

DW

tVR12_T10_SP

tVR12_T10_SLP

tVR12_T10_LP

tVP12_T10_PAL

DW

VR12_T10:

tVR12_T10_SP:

DB

1,2,0,3,0,0,0,0,0

1,1,1,1,1,1,2,3,0

2,1,2,2,2,3,0,2,2

1,2,3,3,0,3,3,3,3

; SP mode

tVR12_T10_SLP:

DB

tVR12_T10_LP:

DB

tVR12_T10_PAL:

DB

; SLP mode

; LP mode

; SP (PAL) mode

$

EJECT

CSEG

VCR00

UNIT

;---------------------------------------------------------------------------------

INTCR00 QUASI Vsync timing setting

;---------------------------------------------------------------------------------

;

VR00_000 : Register setting processing

VR00_100 : RFS level check

VR00_200 : Quasi Vsync rising edge timing setting

VR00_300 : Drum start processing (interrupt enable condition judgment)

;---------------------------------------------------------------------------------

Register setting processing

;

;---------------------------------------------------------------------------------

VR00_000:;V

;/////Register setting /////////

SEL

RB3

; HIGHEST-ORDER INTERRUPT!!

;---------------------------------------------------------------------------------

RFS level check

;

;---------------------------------------------------------------------------------

VR00_100:

BF

ICR.6,$VR00_200

; CAPTURE BY RFS RISING EDGE? No

MOVW

AX,CPT1L

HL,AX

;

192

CHAPTER 8 PROGRAM LIST

MOV

MOVG

A,CPT1H

W,A

RVCPT1,WHL

;

SET1

FSAFRQ

; DOWN EDGE SET FOR AUTO-TRACKING

;---------------------------------------------------------------------------------

Set QUASI Vsync rising timing

;

;---------------------------------------------------------------------------------

; QUASI Vsync outputs during search mode

; (CUE/REV), halt, and V.C mode.

;

Rising timing

;

Fixed value

τd = HSW delay amount + 3

= (CR00 setting value) + 191 µsec

= (CR00 setting value) + 191d

;%

Variable value: CH2 at STILL/FRAME

τd = HSW delay amount + 2H to 4H (initial value) to 6H

= (CR00 setting value) + 128 to 255 to 382 µsec

= (CR00 setting value) + 128d to 255d to 382d

;%

Falling edge timing

4H = 63.55 x 4 = 254.2 µsec

= 254D

;%

1H = 63.55 µsec

* Timing match interrupt → INTCR02

;---------------------------------------------------------------------------------

VR00_200:;B

BF

BT

FVDOUT,$VR00_300

ICR.6,$VR00_230

; QUASI Vsync OUTPUT MODE? No

; RFS RISING EDGE? No

VR00_210:

MOV

AND

CMP

A,RVSRVCD

A,#11110000B

A,#CVSTILL

; CLEAR LOW-ORDER 4 BIT

; SERVO CODE STILL?

BNE

$VR00_230

; No

VR00_220:

;/////Variable value ////////

MOVW

AX,#00

; CLEAR BUFFER

MOV

XCH

A,RVPSVCNT

A,X

; VARIABLE VALUE (00-FEH)

ADDW

MOVW

AX,#128D

AX,CR00

CR02,AX

; %BASIC VALUE

; RISING TIMING

; SET FALLING TIMING

BR

VR00_240

193

CHAPTER 8 PROGRAM LIST

VR00_230:;B

;/////Fixed value ////////

MOVW

ADDW

MOVW

AX,CR00

AX,#191D

CR02,AX

; RISING TIMING

;%SET DATA

;

VR00_240:;B

SET1

P8L.0

;%<DATA OUTPUT TO P80 WITH TRIGGER: “1”>

CLR1

SET1

CRMK02

FVHQVDT

; INTCR02 ENABLE

; SET RISING TIMING FLAG

;------------------------------------------------------------------

Drum rising processing (Interrupt enable conditions judgment)

;

;------------------------------------------------------------------

VR00_300:;B

BF

FSDRMON,$VR00_400

ICR.6,$VR00_400

FSEICPT2

; DRUM ON? No

BF

; RFS FALLING EDGE INPUT? No

CLR1

; CLEAR INTCPT2 INTERRUPT ENABLE

; REQUEST FLAG

;------------------------------------------------------------------

V-MUTE release RFS synchronization processing

;

;------------------------------------------------------------------

VR00_400:;B

BF

FSVM0FRQ,$VR00_500

; V-MUTE RELEASE REQUEST? No

CLR1

SET1

FSVM0FRQ

PQVD

FPQVD

; CLEAR REQUEST

; V-MUTE OFF

; SET PORT REFRESH FLAG

;%P80 PT0 OUTPUT MODE

PMC8.0

;------------------------------------------------------------------

Reverse brake at CUE → PLAY RFS synchronization processing

;

;------------------------------------------------------------------

VR00_500:;B

BF

FSCRRFRQ,$VR00_600

FSCRRFRQ

; REQUEST CAPSTAN REVERSE RFS

; SYNCHRONIZATION?

CLR1

SET1

PCAPFWD

PCAPF_R

FPCAPF_R

; CAPSTAN MOTOR REVERSE START

; SET PORT REFRESH FLAG

MOVG

MOV

WHL,#RNSTIM0

A,RVFSRV_2

;%

AND

A,#00000011B

; READ RUN MODE

; PAL?

CMP

A,#CVPAL

194

CHAPTER 8 PROGRAM LIST

BE

$VR00_510

A,#CVSP

; Yes

CMP

BE

; NTSC SP?

$VR00_510

CMP

BE

A,#CVSLP

$VR00_520

; NTSC SLP?

; NTSC LP

MOV

BR

A,#33H

$VR00_530

; 70 msec TIMER SET

VR00_510:;B

; PAL SP, NTSC SP

MOV

BR

A,#50H

$VR00_530

; 110 msec TIMER SET

VR00_520:;B

MOV

; NTSC SLP

; 60 msec TIMER SET

A,#2CH

VR00_530:;B

MOV

[HL],A

FNSTENO

; TIMER START

;

CLR1

VR00_600:;B

RETI

; INTCR00 INTERRUPT PROCESSING END

$

EJECT

CSEG

VCR02

UNIT

;---------------------------------------------------------------------------------

Set INTCR02 QUASI Vsync timing

;---------------------------------------------------------------------------------

;

VR02_000 : Register set processing

VR02_100 : Set quasi Vsync falling timing

VR02_200 : INTCR02 interrupt disable processing

;---------------------------------------------------------------------------------

Register setting processing

;

;---------------------------------------------------------------------------------

VR02_000:;V

;/////Register setting /////////

SEL

RB3

; Highest-order interrupt!!

;---------------------------------------------------------------------------------

; Set QUASI Vsync falling edge timing

;---------------------------------------------------------------------------------

VR02_100:

BTCLR FVHQVDT,$VR02_110

BR $VR02_200

; Rising timing interrupt?

; No

195

CHAPTER 8 PROGRAM LIST

VR02_110:;B

MOVW

AX,CR02

AX,#254D

CR02,AX

; FALLING EDGE TIMING

;%SET DATA

ADDW

MOVW

CLR1

BR

P8L.0

;%<DATA OUTPUT TO P80 WITH TRIGGER:

; “0” > (Addition)

$VR02_300

;--------------------------------------------------------------------

INTCR02 interrupt disable processing

;

;--------------------------------------------------------------------

VR02_200:

SET1

CRMK02

; INTCR02 disable

VR02_300:

RETI

; INTCR02 interrupt end

$

EJECT

;--------------------------------------------------------------------

SERVO DATA TABLE

;

;--------------------------------------------------------------------

;

; • Table description

;

DB TMC0 (Timer 0 control register setting value)

DB CPTM (Capture mode register setting value)

DB INTM1 (External capture input mode register setting value)

[SP/LP/SLP/PAL]

DB Value of EDVC

DB CR12 Macro service counter

DW REF30Hz

(CR10)

DW Drum speed target value

DB Drum speed target value

DW Drum bias adding value

(CPT2H)

(CPT2L)

DW Capstan speed target value (CPT3)

DW Capstan bias adding value

DW Capstan gain adjustment value

;--------------------------------------------------------------------

;------------------------------

;

PLAY

;------------------------------

SDT_PLAY:

DB

10001001B

00110000B

00010001B

; TMC0

; TM0:CLR

;%CPTM

; CR12-TRG:CTI11,CPT1:↑ ↓ EDGE

;%INTM1 PBCTL:AN_AMP,

COUNT:EN

TM1:CLR

DB

CPT0-TRG:TM1=CR10

; PBCTL:↑ EDGE CFG:↑ EDGE

;

<-(01010001B)

196

CHAPTER 8 PROGRAM LIST

;/////SP /////////////////

SDT_PLS0:

DB

SDT_PLS1:

DB

SDT_PLS2:

DW

SDT_PLS3:

DG

SDT_PLS5:

DW

SDT_PLS6:

DG

SDT_PLS7:

DW

SDT_PLS8:

DW

SDT_PLS9:

DW

SDT_PLSA:

DB

03D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

8256H

2B72H

66F0H

56CEH

85E0H

600H

433H

17H

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

; CTL AMP GAIN

;/////LP /////////////////

SDT_PLL0:

DB

SDT_PLL1:

DB

SDT_PLL2:

DW

SDT_PLL3:

DG

SDT_PLL5:

DW

SDT_PLL6:

DG

SDT_PLL7:

DW

SDT_PLL8:

DW

SDT_PLL9:

DW

SDT_PLLA:

DB

02D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

8256H

2B72H

66FFH

73BDH

8595H

0540H

0159H

1DH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////SLP /////////////////

SDT_PLE0:

DB

SDT_PLE1:

DB

SDT_PLE2:

DW

SDT_PLE3:

DG

SDT_PLE5:

DW

SDT_PLE6:

DG

01D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

8256H

2B72H

66FFH

56CEH

; CPT2

; DRUM BIAS

; CPT3

197

CHAPTER 8 PROGRAM LIST

SDT_PLE7:

DW

SDT_PLE8:

DW

SDT_PLE9:

DW

SDT_PLEA:

DB

86DFH

0420H

0119H

1DH

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////PAL ///////////////

SDT_PLP0:

DB

SDT_PLP1:

DB

SDT_PLP2:

DW

SDT_PLP3:

DG

SDT_PLP5:

DW

SDT_PLP6:

DG

SDT_PLP7:

DW

SDT_PLP8:

DW

SDT_PLP9:

DW

SDT_PLPA:

DB

03D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

9C40H

3415H

66FFH

7BC1H

863FH

0600H

0166H

1DH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;------------------------------

RVS PLAY

;

; SP/LP/SLP/PAL PLAY

;------------------------------

:

SDT_RVS

DB

10001001B

00110000B

; TMC0 COUNT:EN TM1:CLR TM0:CLR

;%CPTM CPT0-TRG:TM1=CR10

; CR12-TRG:CTI11,CPT1:↑ ↓ EDGE

;%INTM1 PBCTL:AN_AMP,PBCTL:↑ EDGE

; CFG:↑ EDGE <-(01010001B)

DB

00010001B

;/////SP ///////////////

SDT_RPS0:

DB

SDT_RPS1:

DB

SDT_RPS2:

DW

SDT_RPS3:

DG

SDT_RPS5:

DW

SDT_RPS6:

DG

SDT_RPS7:

DW

SDT_RPS8:

DW

03D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

83D3H

2BF1H

66FFH

56CEH

8678H

0600H

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

198

CHAPTER 8 PROGRAM LIST

SDT_RPS9:

DW

SDT_RPSA:

DB

0233H

17H

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////LP /////////////////

SDT_RPL0:

DB

SDT_RPL1:

DB

SDT_RPL2:

DW

SDT_RPL3:

DG

SDT_RPL5:

DW

SDT_RPL6:

DG

SDT_RPL7:

DW

SDT_RPL8:

DW

SDT_RPL9:

DW

SDT_RPLA:

DB

02D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

8314H

2BB1H

66FFH

73BDH

8595H

0540H

0159H

1DH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////SLP /////////////////

SDT_RPE0:

DB

SDT_RPE1:

DB

SDT_RPE2:

DW

SDT_RPE3:

DG

SDT_RPE5:

DW

SDT_RPE6:

DG

SDT_RPE7:

DW

SDT_RPE8:

DW

SDT_RPE9:

DW

SDT_RPEA:

DB

01D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

82D5H

2B9CH

66FFH

56CEH

86DFH

0420H

0119H

1DH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////PAL /////////////////

SDT_RPP0:

DB

SDT_RPP1:

DB

SDT_RPP2:

DW

SDT_RPP3:

03D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

9DC0H

199

CHAPTER 8 PROGRAM LIST

DG

SDT_RPP5:

DW

SDT_RPP6:

DG

SDT_RPP7:

DW

SDT_RPP8:

DW

SDT_RPP9:

DW

SDT_RPPA:

DB

3495H

66FFH

7BC1H

863FH

0600H

0166H

1DH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;------------------------------

FF/REW (2H)

;------------------------------

SDT_FR2H:

DB

;

; NTSC PLAY SP

10001001B

00110000B

; TMC0 COUNT:EN TM1:CLR TM0:CLR

;%CPTM CPT0-TRG:TM1=CR10 CR12-TRG:

;CTI11,CPT1;↑ ↓ EDGE

DB

00010001B

;%INTM1 PBCTL:AN_AMP,PBCTL:↑EDGE

; CFG:↑EDGE <-(01010001B)

;/////SP /////////////////

SDT_2HS0:

DB

SDT_2HS1:

DB

SDT_2HS2:

DW

SDT_2HS3:

DG

SDT_2HS5:

DW

SDT_2HS6:

DG

SDT_2HS7:

DW

SDT_2HS8:

DW

SDT_2HS9:

DW

SDT_2HSA:

DB

03D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

8256H

2B72H

66FFH

56CEH

8678H

0600H

0233H

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%%CTL AMP GAIN

;///// LP /////////////////

SDT_2HL0:

DB

SDT_2HL1:

DB

SDT_2HL2:

DW

SDT_2HL3:

DG

SDT_2HL5:

DW

03D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

8256H

2B72H

66FFH

; CPT2

; DRUM BIAS

200

CHAPTER 8 PROGRAM LIST

SDT_2HL6:

DG

SDT_2HL7:

DW

SDT_2HL8:

DW

SDT_2HL9:

DW

SDT_2HLA:

DB

56CEH

8678H

0600H

0233H

0EH

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////SLP /////////////////

SDT_2HE0:

DB

SDT_2HE1:

DB

SDT_2HE2:

DW

SDT_2HE3:

DG

SDT_2HE5:

DW

SDT_2HE6:

DG

03D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

8256H

2B72H

66FFH

56CEH

8678H

0600H

0233H

0EH

; CPT2

; DRUM BIAS

; CPT3

SDT_2H1E7 :

DW

SDT_2HE8:

DW

SDT_2HE9:

DW

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

SDT_2HEA:

DB

;/////PAL /////////////////

SDT_2HP0:

DB

SDT_2HP1:

DB

SDT_2HP2:

DW

SDT_2HP3:

DG

SDT_2HP5:

DW

SDT_2HP6:

DG

SDT_2HP7:

DW

SDT_2HP8:

DW

SDT_2HP9:

DW

SDT_2HPA:

DB

03D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

9C40H

3415H

66FFH

7BC1H

8678H

0600H

0233H

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

201

CHAPTER 8 PROGRAM LIST

;------------------------------

FF/REW (6H)

;------------------------------

SDT_FR6H:

DB

;

; CAPSTAN INITIAL SPEED

10001001B

00110000B

; TMC0 COUNT:EN TM1:CLR TM0:CLR

;%CPTM CPT0-TRG:TM1=CR10 CR12-TRG:

;CTI11,CPT1:↑ ↓ EDGE

DB

00010001B

;%INTM1 PBCTL:AN_AMP, PBCTL:↑ EDGE

; CFG:↑ EDGE <-(01010001B)

;/////SP /////////////////

SDT_6HS0:

DB

SDT_6HS1:

DB

SDT_6HS2:

DW

SDT_6HS3:

DG

SDT_6HS5:

DW

SDT_6HS6:

DG

SDT_6HS7:

DW

SDT_6HS8:

DW

SDT_6HS9:

DW

SDT_6HSA:

DB

01D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

8256H

2B72H

66FFH

56CEH

86DFH

00C0H

0119H

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////LP /////////////////

SDT_6HL0:

DB

SDT_6HL1:

DB

SDT_6HL2:

DW

SDT_6HL3:

DG

SDT_6HL5:

DW

SDT_6HL6:

DG

SDT_6HL7:

DW

SDT_6HL8:

DW

SDT_6HL9:

DW

SDT_6HLA:

DB

01D

; EDVC count

; MACRO count

; CR10

01H

8256H

2B72H

66FFH

56CEH

86DFH

00C0H

0119H

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////SLP /////////////////

SDT_6HE0:

DB

01D

; EDVC COUNT

202

CHAPTER 8 PROGRAM LIST

SDT_6HE1:

DB

SDT_6HE2:

DW

SDT_6HE3:

DG

SDT_6HE5:

DW

SDT_6HE6:

DG

SDT_6HE7:

DW

SDT_6HE8:

DW

SDT_6HE9:

DW

SDT_6HEA:

DB

01H

; MACRO COUNT

; CR10

8256H

2B72H

66FFH

56CEH

86DFH

00C0H

0119H

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////PAL /////////////////

SDT_6HP0:

DB

SDT_6HP1:

DB

SDT_6HP2:

DW

SDT_6HP3:

DG

SDT_6HP5:

DW

SDT_6HP6:

DG

SDT_6HP7:

DW

SDT_6HP8:

DW

SDT_6HP9:

DW

SDT_6HPA:

DB

01D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

9C40H

3415H

66FFH

56CEH

86DFH

00C0H

0119H

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;------------------------------

FF/REW (6H) VD OUT

;------------------------------

SDT_6HVD:

DB

;

; CAPSTAN FG 90 PULSES DRIVE

10001001B

00110000B

; TMC0 COUNT:EN TM1:CLR TM0:CLR

;%CPTM CPT0-TRG:TM1=CR10 CR12-TRG:

; CTI11,CPT1:↑ ↓ EDGE

DB

00010001B

;%INTM1 PBCTL:AN_AMP,PBCTL:↑ EDGE

; CFG:↑ EDGE <-(01010001B)

;/////SP /////////////////

SDT_6VS0:

DB

SDT_6VS1:

DB

SDT_6VS2:

DW

01D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

8315H

203

CHAPTER 8 PROGRAM LIST

SDT_6VS3:

DG

SDT_6VS5:

DW

SDT_6VS6:

DG

SDT_6VS7:

DW

SDT_6VS8:

DW

SDT_6VS9:

DW

SDT_6VSA:

DB

2BB1H

66FFH

56CEH

86DFH

0420H

0119H

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////LP /////////////////

SDT_6VL0:

DB

SDT_6VL1:

DB

SDT_6VL2:

DW

SDT_6VL3:

DG

SDT_6VL5:

DW

SDT_6VL6:

DG

SDT_6VL7:

DW

SDT_6VL8:

DW

SDT_6VL9:

DW

SDT_6VLA:

DB

01D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

82B5H

2B91h

66FFH

56CEH

86DFH

0420H

0119H

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////SLP /////////////////

SDT_6VE0:

DB

SDT_6VE1:

DB

SDT_6VE2:

DW

SDT_6VE3:

DG

SDT_6VE5:

DW

SDT_6VE6:

DG

SDT_6VE7:

DW

SDT_6VE8:

DW

SDT_6VE9:

DW

SDT_6VEA:

DB

01D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

8295H

2B91H

66FFH

56CEH

86DFH

0420H

0119H

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

204

CHAPTER 8 PROGRAM LIST

;/////PAL /////////////////

SDT_6VP0:

DB

SDT_6VP1:

DB

SDT_6VP2:

DW

SDT_6VP3:

DG

SDT_6VP5:

DW

SDT_6VP6:

DG

SDT_6VP7:

DW

SDT_6VP8:

DW

SDT_6VP9:

DW

SDT_6VPA:

DB

01D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

9D00H

3455H

66FFH

56CEH

86DFH

0420H

0119H

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;------------------------------

FF/REW (2H*3)

;------------------------------

SDT_FRX3:

DB

;

; NTSC SLP CUE/REV

10001001B

00110000B

; TMC0 COUNT:EN TM1:CLR TM0:CLR

;%CPTM CPT0-TRG:TM1=CR10 CR12-TRG:

; CTI11,CPT1:↑ ↓ EDGE

DB

00010001B

;%INTM1 PBCTL:AN_AMP,PBCTL:↑ EDGE

; CFG:↑ EDGE <-(01010001B)

;/////SP /////////////////

SDT_X3S0:

DB

SDT_X3S1:

DB

SDT_X3S2:

DW

SDT_X3S3:

DG

SDT_X3S5:

DW

SDT_X3S6:

DG

SDT_X3S7:

DW

SDT_X3S8:

DW

SDT_X3S9:

DW

SDT_X3SA:

DB

03D*3

09D

; EDVC COUNT

; MACRO COUNT

; CR10

8315H

2BB1H

66FFH

56CEH

8678H

0600H

034CH

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

205

CHAPTER 8 PROGRAM LIST

;/////LP /////////////////

SDT_X3L0:

DB

SDT_X3L1:

DB

SDT_X3L2:

DW

SDT_X3L3:

DG

SDT_X3L5:

DW

SDT_X3L6:

DG

SDT_X3L7:

DW

SDT_X3L8:

DW

SDT_X3L9:

DW

SDT_X3LA:

DB

03D*3

09D

; EDVC count

; MACRO count

; CR10

82B5H

2B91H

66FFH

56CEH

8595H

0600H

034CH

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////SLP /////////////////

SDT_X3E0:

DB

SDT_X3E1:

DB

SDT_X3E2:

DW

SDT_X3E3:

DG

SDT_X3E5:

DW

SDT_X3E6:

DG

SDT_X3E7:

DW

SDT_X3E8:

DW

SDT_X3E9:

DW

SDT_X3EA:

DB

03D*3

09D

; EDVC COUNT

; MACRO COUNT

; CR10

8295H

2BB7H

66FFH

56CEH

86DFH

0600H

034CH

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%%CTL AMP GAIN

;/////PAL /////////////////

SDT_X3P0:

DB

SDT_X3P1:

DB

SDT_X3P2:

DW

SDT_X3P3:

DG

SDT_X3P5:

DW

SDT_X3P6:

DG

SDT_X3P7:

DW

03D*3

09D

; EDVC COUNT

; MACRO COUNT

; CR10

9D00H

3455H

66FFH

56CEH

863FH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

206

CHAPTER 8 PROGRAM LIST

SDT_X3P8:

DW

SDT_X3P9:

DW

SDT_X3PA:

DB

0600H

034CH

0EH

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;------------------------------

FF/REW

;------------------------------

SDT_FFRW:

DB

;

; NTSC SP PLAY

10001001B

00110000B

; TMC0 COUNT:EN TM1:CLR TM0:CLR

;%CPTM CPT0-TRG:TM1=CR10 CR12-TRG:

; CTI11,CPT1:↑ ↓ EDGE

DB

00010001B

;%INTM1 PBCTL:AN_AMP,PBCTL:↑ EDGE

; CFG:↑ EDGE <-(01010001B)

;/////SP /////////////////

SDT_FRS0:

DB

SDT_FRS1:

DB

SDT_FRS2:

DW

SDT_FRS3:

DG

SDT_FRS5:

DW

SDT_FRS6:

DG

SDT_FRS7:

DW

SDT_FRS8:

DW

SDT_FRS9:

DW

SDT_FRSA:

DB

40D

; EDVC COUNT

; MACRO COUNT

; CR10

08D

8256H

2B72H

66FFH

56CEH

8678H

0600H

0233H

0EhH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////LP /////////////////

SDT_FRL0:

DB

SDT_FRL1:

DB

SDT_FRL2:

DW

SDT_FRL3:

DG

SDT_FRL5:

DW

SDT_FRL6:

DG

SDT_FRL7:

DW

SDT_FRL8:

DW

SDT_FRL9:

DW

40D

; EDVC COUNT

; MACRO COUNT

; CR10

08D

8256H

2B72H

66FFH

56CEH

8595H

0600H

0233H

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

207

CHAPTER 8 PROGRAM LIST

SDT_FRLA:

DB

0EH

;%% CTL AMP GAIN

;/////SLP /////////////////

SDT_FRE0:

DB

SDT_FRE1:

DB

SDT_FRE2:

DW

SDT_FRE3:

DG

SDT_FRE5:

DW

SDT_FRE6:

DG

SDT_FRE7:

DW

SDT_FRE8:

DW

SDT_FRE9:

DW

SDT_FREA:

DB

40D

; EDVC COUNT

; MACRO COUNT

; CR10

08D

8256H

2B72H

66FFH

56CEH

86DFH

0600H

0233H

0EH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////PAL /////////////////

SDT_FRP0:

DB

SDT_FRP1:

DB

SDT_FRP2:

DW

SDT_FRP3:

DG

SDT_FRP5:

DW

SDT_FRP6:

DG

SDT_FRP7:

DW

SDT_FRP8:

DW

SDT_FRP9:

DW

SDT_FRPA:

DB

40D

; EDVC COUNT

; MACRO COUNT

; CR10

08D

9C40H

3415H

66FFH

7BC1H

863H

0600H

0233H

0EH

; CPT2H

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;------------------------------

CUE

;------------------------------

SDT__CUE:

DB

;

10001001B

00110000B

; TMC0 COUNT:EN TM1:CLR TM0:CLR

;%CPTM CPT0-TRG:TM1=CR10 CR12-TRG:

; CTI11,CPT1:↑ ↓ EDGE

DB

00010001B

;%INTM1 PBCTL:AN_AMP,PBCTL:↑ EDGE

; CFG:↑ EDGE <-(01010001B)

208

CHAPTER 8 PROGRAM LIST

;/////SP /////////////////

SDT_CUS0:

DB

SDT_CUS1:

DB

SDT_CUS2:

DW

SDT_CUS3:

DG

SDT_CUS5:

DW

SDT_CUS6:

DG

SDT_CUS7:

DW

SDT_CUS8:

DW

SDT_CUS9:

DW

SDT_CUSA:

DB

15D

; EDVC COUNT

; MACRO COUNT

; CR10

05D

7F5CH

2A74H

66FFH

54E8H

8678H

0600H

0433H

11H

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////LP /////////////////

SDT_CUL0:

DB

SDT_CUL1:

DB

SDT_CUL2:

DW

SDT_CUL3:

DG

SDT_CUL5:

DW

SDT_CUL6:

DG

SDT_CUL7:

DW

SDT_CUL8:

DW

SDT_CUL9:

DW

SDT_CULA:

DB

09D*2

09D

; EDVC COUNT

; MACRO COUNT

; CR10

7F5EH

2A74H

66FFH

54E9H

8595H

0600H

034CH

12H

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////SLP /////////////////

SDT_CUE0:

DB

SDT_CUE1:

DB

SDT_CUE2:

DW

SDT_CUE3:

DG

SDT_CUE5:

DW

SDT_CUE6:

DG

09D

; EDVC COUNT

; MACRO COUNT

; CR10

09D

805CH

2AC9H

66FFH

5592H

; CPT2

; DRUM BIAS

; CPT3

209

CHAPTER 8 PROGRAM LIST

SDT_CUE7:

DW

SDT_CUE8:

DW

SDT_CUE9:

DW

SDT_CUEA:

DB

86DFH

0600H

034CH

12H

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////PAL /////////////////

SDT_CUP0:

DB

SDT_CUP1:

DB

SDT_CUP2:

DW

SDT_CUP3:

DG

SDT_CUP5:

DW

SDT_CUP6:

DG

SDT_CUP7:

DW

SDT_CUP8:

DW

SDT_CUP9:

DW

SDT_CUPA:

DB

21D

; EDVC COUNT

; MACRO COUNT

; CR10

07D

97C0H

3295H

66FFH

652AH

863FH

0600H

034CH

12H

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;------------------------------

CUE → PLAY

;------------------------------

SDT_CUPL:

DB

;

10001001B

00110000B

; TMC0 COUNT:EN TM1:CLR TM0:CLR

;%CPTM CPT0-TRG:TM1=CR10 CR12-TRG:

; CTI11,CPT1:↑ ↓ EDGE

DB

00010001B

;%INTM1 PBCTL:AN_AMP,PBCTL:↑ EDGE

; CFG:↑ EDGE <-(01010001B)

;/////SP /////////////////

SDT_CPS0:

DB

SDT_CPS1:

DB

SDT_CPS2:

DW

SDT_CPS3:

DG

SDT_CPS5:

DW

SDT_CPS6:

DG

SDT_CPS7:

DW

SDT_CPS8:

DW

15D

; EDVC COUNT

; MACRO COUNT

; CR10

05D

80D9H

2AF3H

66FFH

54E8H

8678H

0600H

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

210

CHAPTER 8 PROGRAM LIST

SDT_CPS9:

DW

SDT_CPSA:

DB

0433H

17H

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////LP /////////////////

SDT_CPL0:

DB

SDT_CPL1:

DB

SDT_CPL2:

DW

SDT_CPL3:

DG

SDT_CPL5:

DW

SDT_CPL6:

DG

SDT_CPL7:

DW

SDT_CPL8:

DW

SDT_CPL9:

DW

SDT_CPLA:

DB

09D*2

09D

; EDVC COUNT

; MACRO COUNT

; CR10

80D9H

2AF3H

66FFH

7137H

8595H

0600H

034CH

1DH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////SLP /////////////////

SDT_CPE0:

DB

SDT_CPE1:

DB

SDT_CPE2:

DW

SDT_CPE3:

DG

SDT_CPE5:

DW

SDT_CPE6:

DG

SDT_CPE7:

DW

SDT_CPE8:

DW

SDT_CPE9:

DW

SDT_CPEA:

DB

09D

; EDVC COUNT

; MACRO COUNT

; CR10

09D

8159H

2B1DH

66FFH

55E7H

86DFH

0600H

034CH

1DH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////PAL /////////////////

SDT_CPP0:

DB

SDT_CPP1:

DB

SDT_CPP2:

DW

SDT_CPP3:

21D

; EDVC COUNT

; MACRO COUNT

; CR10

07D

9940H

211

CHAPTER 8 PROGRAM LIST

DG

SDT_CPP5:

DW

SDT_CPP6:

DG

SDT_CPP7:

DW

SDT_CPP8:

DW

SDT_CPP9:

DW

SDT_CPPA:

DB

3315H

66FFH

652AH

863FH

0600H

034CH

1DH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;------------------------------

REVIEW

;------------------------------

SDT__REV:

DB

;

10001001B

00110000B

; TMC0 COUNT:EN TM1:CLR TM0:CLR

;%CPTM CPT0-TRG:TM1=CR10 CR12-TRG:

; CTI11,CPT1:↑ ↓ EDGE

DB

00010001B

;%INTM1 PBCTL:AN_AMP,PBCTL:↑ EDGE

; CFG:↑ EDGE <-(01010001B)

;/////SP /////////////////

SDT_RVS0:

DB

SDT_RVS1:

DB

SDT_RVS2:

DW

SDT_RVS3:

DG

SDT_RVS5:

DW

SDT_RVS6:

DG

SDT_RVS7:

DW

SDT_RVS8:

DW

SDT_RVS9:

DW

SDT_RVSA:

DB

15D

; EDVC COUNT

; MACRO COUNT

; CR10

05D

86CEH

2CEFH

66FFH

59DFH

8678H

0600H

0433H

11H

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////LP /////////////////

SDT_RVL0:

DB

SDT_RVL1:

DB

SDT_RVL2:

DW

SDT_RVL3:

DG

SDT_RVL5:

DW

09D*2

09D

; EDVC COUNT

; MACRO COUNT

; CR10

860DH

2CAFH

66FFH

; CPT2

; DRUM BIAS

212

CHAPTER 8 PROGRAM LIST

SDT_RVL6:

DG

SDT_RVL7:

DW

SDT_RVL8:

DW

SDT_RVL9:

DW

SDT_RVLA:

DB

7728H

8595H

0600H

034CH

12H

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////SLP ///////////////

SDT_RVE0:

DB

SDT_RVE1:

DB

SDT_RVE2:

DW

SDT_RVE3:

DG

SDT_RVE5:

DW

SDT_RVE6:

DG

SDT_RVE7:

DW

SDT_RVE8:

DW

SDT_RVE9:

DW

SDT_RVEA:

DB

09D

; EDVC COUNT

; MACRO COUNT

; CR10

09D

84CFH

2C45H

66FFH

588AH

86DFH

0600H

034CH

12H

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////PAL ///////////////

SDT_RVP0:

DB

SDT_RVP1:

DB

SDT_RVP2:

DW

SDT_RVP3:

DG

SDT_RVP5:

DW

SDT_RVP6:

DG

SDT_RVP7:

DW

SDT_RVP8:

DW

SDT_RVP9:

DW

SDT_RVPA:

DB

21D

; EDVC COUNT

; MACRO COUNT

; CR10

07D

0A240H

3615H

66FFH

6C2AH

863FH

0600H

034CH

12H

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

213

CHAPTER 8 PROGRAM LIST

;------------------------------

STILL

;------------------------------

SDT_STIL:

DB

;

; SP/LP/SLP/PAL PLAY

10001001B

00110000B

; TMC0 COUNT:EN TM1:CLR TM0:CLR

;%CPTM CPT0-TRG:TM1=CR10 CR12-TRG:

; CTI11,CPT1:↑ ↓ EDGE

DB

00010001B

;%INTM1 PBCTL:AN_AMP,PBCTL:↑ EDGE

; CFG:↑ EDGE <-(01010001B)

;/////SP /////////////////

SDT_STS0:

DB

SDT_STS1:

DB

SDT_STS2:

DW

SDT_STS3:

DG

SDT_STS5:

DW

SDT_STS6:

DG

SDT_STS7:

DW

SDT_STS8:

DW

SDT_STS9:

DW

SDT_STSA:

DB

03D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

8315H

2BB1H

66FFH

56CEH

8678H

0600H

0233H

17H

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////LP /////////////////

SDT_STL0:

DB

SDT_STL1:

DB

SDT_STL2:

DW

SDT_STL3:

DG

SDT_STL5:

DW

SDT_STL6:

DG

SDT_STL7:

DW

SDT_STL8:

DW

SDT_STL9:

DW

SDT_STLA:

DB

02D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

8265H

2B91H

66FFH

73BDH

8595H

0540H

0159H

1DH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////SLP /////////////////

SDT_STE0:

DB

01D

; EDVC COUNT

214

CHAPTER 8 PROGRAM LIST

SDT_STE1:

DB

SDT_STE2:

DW

SDT_STE3:

DG

SDT_STE5:

DW

SDT_STE6:

DG

SDT_STE7:

DW

SDT_STE8:

DW

SDT_STE9:

DW

SDT_STEA:

DB

01H

; MACRO COUNT

; CR10

8295H

2BB7H

66FFH

56CEH

86DFH

0420H

0119H

1DH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

;/////PAL ///////////////

SDT_STP0:

DB

SDT_STP1:

DB

SDT_STP2:

DW

SDT_STP3:

DG

SDT_STP5:

DW

SDT_STP6:

DG

SDT_STP7:

DW

SDT_STP8:

DW

SDT_STP9:

DW

SDT_STPA:

DB

03D

; EDVC COUNT

; MACRO COUNT

; CR10

01H

9D00H

3455H

66FFH

7BC1H

863FH

0600H

0166H

1DH

; CPT2

; DRUM BIAS

; CPT3

; CAPSTAN BIAS

; LOOP GAIN

; CAPSTAN KV/KP

;%% CTL AMP GAIN

$

EJECT

SERVOSUB

CSEG FIXED

;---------------------------------------------------------------------------------

SERVO DATA Setting SUB

;

;---------------------------------------------------------------------------------

;

• TMC0 (Timer 0 Control register)

• CPTM (Capture mode register)

• INTM1 (External capture input mode register)

• EDVC (Event divider control register)

• CR12 Macro service counter

• REF30Hz (CR10)

• Drum speed target value (CPT2H)

• Drum speed target value (CPT2L)

215

CHAPTER 8 PROGRAM LIST

;

• Drum bias adding value

• Capstan speed target value (CPT3)

• Capstan bias adding value

• Loop gain

• Clear filter

• Clear capstan error amount

;---------------------------------------------------------------------------------

YVTBL_00:;C

;/////Interrupt control /////////

DI

; TO BE REFERRED AT SERVO RELATION CONTROL

YVTBL_10:

;///// Address setting /////////

MOV

AND

A,RVSRVCD

A,#0F0H

; SERVO CODE LOW-ORDER MASK

;%SET PLAY

MOVG

WHL,#SDT_PLAY

CMP

BNE

A,#CVFFRW2Hrs

$YVTBL_11

; FF/REW(2Hrs)?

; No

MOVG

WHL,#SDT_FR2Hrs

;% Yes

YVTBL_11:;B

CMP

BNE

A,#CVFFRW6Hrs

$YVTBL_12

; FF/REW(6Hrs)?

; No

MOVG

WHL,#SDT_FR6Hrs

:% Yes

YVTBL_12:;B

CMP

BNE

A,#CVFFRWX3

$YVTBL_13

; FF/REW(2Hrs*3)?

; No

MOVG

WHL,#SDT_FRX3

;% Yes

YVTBL_13:;B

CMP

BNE

A,#CVFFREW

$YVTBL_14

; FF/REW?

; No

MOVG

WHL,#SDT_FFRW

;% Yes

YVTBL_14:;B

CMP

BNE

A,#CVCUE

$YVTBL_15

; CUE?

; No

MOVG

WHL,#SDT__CUE

;% Yes

YVTBL_15:;B

CMP

BNE

A,#CVREV

$YVTBL_16

; REVIEW?

; No

MOVG

WHL,#SDT__REV

;% Yes

YVTBL_16:;B

CMP

BNE

A,#CVSTILL

$YVTBL_17

; STILL?

; No

MOVG

WHL,#SDT_STIL

;% Yes

YVTBL_17:;B

CMP

BNE

A,#CVRVS

$YVTBL_18

; RVS PLAY?

; No

216

CHAPTER 8 PROGRAM LIST

MOVG

YVTBL_18:;B

WHL_#SDT_RVS

;% Yes

CMP

BNE

A,#CVCUPL

$YVTBL_19

: CUE → PLAY?

; No PLAY

MOVG

WHL,#SDT_CUPL

;% Yes

YVTBL_19:;B

CMP

BNE

A,#CVFR6HVD

$YVTBL_20

; 6Hrs PLAY VD OUT ?

; No PLAY

MOVG

WHL,#SDT_6HVD

;% Yes

YVTBL_20:

;/////TMC0 Read /////

MOV

A,[HL+]

TMC0,A

YVTBL_30:

;/////CPTM Read /////

MOV

A,[HL+]

CPTM,A

YVTBL_40:

;/////INTM1 Read /////

MOV

A,[HL+]

INTM1,A

YVTBL_50:

;/////Address adjustment /////////

MOV

AND

A,RVFSRV_2

A,#00000011B

;

; Read running mode

MOVW

BC,#00H

; Set address adding value (SP)

CMP

A,#CVLP

; LP?

BNE

$YVTBL_51

; No

MOVW

BC,#SDT_PLL0-SDT_PLS0

;% Yes (Number of table byte x 1)

YVTBL_51:;B

CMP

A,#CVSLP

; SLP?

BNE

$YVTBL_52

; No

MOVW

BC,#SDT_PLE0-SDT_PLS0

;% Yes (Number of table byte x 2)

YVTBL_52:;B

CMP

A,#CVPAL

; PAL?

BNE

$YVTBL_53

; No

MOVW

BC,#SDT_PLP0-SDT_PLS0

;% Yes (Number of table byte x 3)

YVTBL_53:;B

MOVW

MOV

ADDG

DE,BC

T,#0

WHL,TDE

;% Address adding

;%

217

CHAPTER 8 PROGRAM LIST

YVTBL_60:;B

;/////EDVC /////////////

MOV

DEC

MOV

A,[HL+]

A

EDVC,A

; ;ADD%%

YVTBL_70:

;/////CR12 /////////////

MOV

A,[HL+]

RVMCCR12,A

RVCRAM,A

YVTBL_80:

;/////CR10 /////////////

MOVW

CALL

AX,[HL+]

; WRITE INTO CR10 IS PERFORMED IN

; INTCR10 ROUTINE.

; (TM1 MAY OVERFLOW DEPENDING ON WRITE

; TIMING!)

RVBCR10,AX

!YPGADCHG

; SET PG VALUE

YVTBL_90:

;/////CPT2 ///////////

MOVG

TDE,WHL

WHL,[TDE+]

RVDFRF,WHL

WHL,TDE

YVTBL_B0:

;/////D-BIAS /////////

MOVW

AX,[HL+]

RVDBAS,AX

YVTBL_C0:

;/////CPT3 /////////////

MOVG

TDE,WHL

WHL,[TDE+]

RVCFRF,WHL

WHL,TDE

YVTBL_D0:

;/////C-BIAS /////////

MOVW

AX,[HL+]

RVCBAS,AX

YVTBL_E0:

;/////C-GAIN ADJUSTMENT /////

MOVW

AX,[HL+]

RVC_Kmp,AX

218

CHAPTER 8 PROGRAM LIST

YVTBL_F0:

;///// C-Kv/Kp ///////

MOVW

AX,[HL+]

RVC_Kvp,AX

;

YVTBL_F1:

;/////PB_CTL gain ///////

MOV

A,[HL]

CTLM,A

;

YVTBL_G0:

=

;/////Clear filter /////

; CAPSTAN SPEED/PHASE

MOVW

RVERCMX,#0

;

RVERCMX_1,#0

RVERCMX_bY,#0

RVERCMX_bY+2,#0

MOVW

RVERCP,#0

; CAPSTAN PHASE FILTER

RVERCP_1,#0

RVERCP_bY,#0

RVERCP_bY+2,#0

;

YVTBL_H0:

;/////Clear C-Error ///////

MOVW

RVERCP_Y,#0

RVERCMX_Y+2,#0

; CAPSTAN PHASE ERROR

; CAPSTAN SPEED ERROR

YVTBL_I0:

;/////Interrupt control /////////

EI

RET

END

219

CHAPTER 8 PROGRAM LIST

[MEMO]

220

APPENDIX REVISION HISTORY

The history of revisions hitherto made is shown as follows.

Edition

Second

Revisions

Chapter

Throughout

Addition of µPD784915A

Addition of related document number

The following figures are changed.

Introduction

CHAPTER 3

• Figure 3-4 Use of Event Counter (EC) is corrected.

EXAMPLES OF

• Figure 3-5 Event Counter (EC) Operation Timing is corrected.

• Figure 3-6 Use of Timer 0 is corrected.

STATIONARY TYPE

VCR SERVO CONTROL

• Figure 3-7 Head Switching Signal (V-HSW) Timing (PTO00) is corrected.

• Figure 3-19 Timer 1 Peripheral Circuit is corrected.

• Figure 3-27 Use of Timer for Drum Phase Control (for recording) is corrected.

• Figure 3-28 Drum Phase Control Timing (for recording) is corrected.

Third

The µPD784928, 784928Y Subseries and the µPD784915B, 784916B are added. Throughout

Document numbers of related documents are added or corrected.

Introduction

CHAPTER 1 OUTLINE OF NEC VCR SERVO MICROCONTROLLER

CHAPTER 1

PRODUCTS is added.

OUTLINE OF NEC

VCR SERVO

MICROCONTROLLER

PRODUCTS

Table 2-1 Differences among µPD784915 Subseries Products is added.

CHAPTER 3 OUTLINE OF µPD784928, 784928Y SUBSERIES is added.

CHAPTER 2

OUTLINE OF

µPD784915 SUBSERIES

CHAPTER 3

OUTLINE OF

µPD784928, 784928Y

SUBSERIES

221

APPENDIX REVISION HISTORY

[MEMO]

222

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toensurethatthedocumentationsupplied

to our customers is complete, bug free

and up-to-date, we readily accept that

errorsmayoccur. Despiteallthecareand

precautions we've taken, you may

encounterproblemsinthedocumentation.

Please complete this form whenever

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improvements to us.

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CS 97.8


型号：	UPD78F4928
厂家：	ETC
描述：	UPD784915.784928.784928Y Subseries VCR Servo Basics \| Application Note[03/1998] UPD784915.784928.784928Y子系列录像机伺服基础\|应用指南[ 03/1998 ]\n 录像机光电二极管
文件：	总223页 (文件大小：697K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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