UT621024 [ETC]
128K X 8 BIT LOW POWER CMOS SRAM; 128K ×8位低功耗CMOS SRAM
| 型号： | UT621024 |
| 厂家： | 
ETC |
| 描述： | 128K X 8 BIT LOW POWER CMOS SRAM |
| 文件： | 总12页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
FEATURES
The UT621024 is a 1,048,576-bit low power
CMOS static random access memory
organized as 131,072 words by 8 bits. It is
fabricated using high performance, high
reliability CMOS technology.
Access time : 35/55/70ns (max.)
Low power consumption :
Operating : 60/50/40 mA (typical)
Standby : 2µA (typical) L-version
1µA (typical) LL-version
The UT621024 is designed for low power
application. It is particularly well suited for
battery back-up nonvolatile memory
application.
Single 5V power supply
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage : 2V (min.)
The UT621024 operates from a single 5V
power supply and all inputs and outputs are
fully TTL compatible.
Package : 32-pin 600 mil PDIP
32-pin 450 mil SOP
32-pin 8mmx20mm TSOP-1
32-pin 8mmx13.4mm STSOP
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
NC
A16
Vcc
A15
1
2
32
31
30
29
A16
A15
A13
CE2
A14
A12
3
4
WE
A13
A8
5
28
27
26
25
24
23
22
21
20
19
18
17
A7
A6
.
V
CC
A14
6
MEMORY ARRAY
A5
A4
A9
7
A12
A7
A6
A5
A4
A8
.
.
A11
ROW
8
1024 ROWS × 1024 COLUMNS
A3
9
OE
A10
DECODER
V
SS
A2
10
11
A1
CE1
I/O8
A0
12
13
14
15
16
I/O1
I/O2
I/O3
Vss
I/O7
I/O6
I/O5
I/O4
.
. .
I/O1
.
.
.
I/O
COLUMN I/O
.
.
.
.
.
.
CONTROL
I/O8
PDIP / SOP
COLUMN DECODER
CE1
CE2
WE
OE
A11
A9
1
2
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
OE
A10
LOGIC
A10
A9 A3
CONTROL
A11
A2 A1 A0
A8
3
CE1
I/O8
A13
4
I/O7
I/O6
I/O5
I/O4
Vss
I/O3
I/O2
I/O1
A0
5
WE
CE2
6
PIN DESCRIPTION
A15
Vcc
NC
A16
A14
A12
A7
7
8
UT621024
9
SYMBOL
A0 - A16
I/O1 - I/O8
CE1
WE
OE
VCC
VSS
NC
DESCRIPTION
10
11
12
13
14
15
16
Address Inputs
Data Inputs/Outputs
Chip enable 1,2 Inputs
,CE2
A6
A1
A2
A3
Write Enable Input
Output Enable Input
A5
A4
Power Supply
Ground
TSOP-I/STSOP
No Connection
________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
1
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
ABSOLUTE MAXIMUM RATINGS*
PARAMETER
SYMBOL
VTERM
TA
RATING
-0.5 to +7.0
0 to +70
UNIT
V
Terminal Voltage with Respect to Vss
Operating Temperature
℃
Storage Temperature
TSTG
PD
-65 to +150
℃
Power Dissipation
1
W
DC Output Current
IOUT
Tsolder
50
260
mA
℃
Soldering Temperature (under 10 sec)
*Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This
is a stress rating only and functional operation of the device or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to the absolute maximum rating conditions for extended
period may affect device reliability.
TRUTH TABLE
MODE
I/O OPERATION
SUPPLY CURRENT
CE2
X
L
H
H
H
WE
CE1
H
OE
X
Standby
Standby
Output Disable
Read
X
X
H
H
L
High - Z
High -Z
High - Z
DOUT
ISB,ISB1
ISB,ISB1
ICC
X
X
L
H
L
L
ICC
Write
L
X
DIN
ICC
Note: H = VIH, L=VIL, X = Don't care.
±
℃
℃
DC ELECTRICAL CHARACTERISTICS (VCC = 5V 10%, T = 0 to 70 )
A
MIN. TYP. MAX.
PARAMETER
SYMBOL TEST CONDITION
UNIT
V
V
A
µ
Input High Voltage
Input Low Voltage
Input Leakage Current
VIH
VIL
IIL
2.2
- 0.5
- 1
-
-
-
VCC+0.5
0.8
1
≦ ≦
VSS VIN VCC
Output Leakage Current IOL
≦ ≦
VSS VI/O VCC
=VIH or CE2 = VIL or
A
µ
CE1
- 1
-
1
= VIH or
= VIL
WE
OE
Output High Voltage
Output Low Voltage
Average Operating
Power Supply Courrent
VOH
VOL
ICC
IOH = - 1mA
2.4
-
-
-
V
V
IOL= 4mA
-
-
0.4
100
Cycle time=min, 100% duty,
-35
-55
-70
60
mA
=VIL, CE2 = VIH,
II/O = 0mA
Cycle time=1 s,100% duty,I =0mA
-
-
50
40
85
70
mA
mA
CE1
ICC1
µ
I/O
-
-
10
mA
mA
≦
≧
.
0.2V,CE2 VCC-0.2V,
CE1
other pins at 0.2V or VCC-0.2V,
Standby Power
Supply Current
ISB
=VIH or CE2 = VIL
other pins at 0.2V or VCC-0.2V,
CE1
-
-
-
-
3
ISB1
100
40*
50
≧
VCC-0.2V or
CE1
- L
2
1
A
A
µ
≦
.CE2 0.2V
-
other pins at 0.2V or VCC-0.2V,
µ
LL
15*
℃
*Those parameters are for reference only under 50
________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
2
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
℃
CAPACITANCE (T =25 , f=1.0MHz)
A
PARAMETER
SYMBOL
MIN.
MAX.
8
UNIT
pF
pF
Input Capacitance
Input/Output Capacitance
CIN
-
-
CI/O
10
Note : These parameters are guaranteed by device characterization, but not production tested.
AC TEST CONDITIONS
Input Pulse Levels
0V to 3.0V
5ns
Input Rise and Fall Times
Input and Output Timing Reference Levels
Output Load
1.5V
CL=100pF, IOH/IOL=-1mA/4mA
±
℃
℃
AC ELECTRICAL CHARACTERISTICS (V = 5V 10% , T = 0 to 70 )
CC
A
(1) READ CYCLE
PARAMETER
SYMBOL UT621024-35 UT621024-55 UT621024-70 UNIT
MIN. MAX. MIN. MAX. MIN. MAX.
Read Cycle Time
tRC
35
-
-
55
-
-
70
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Access Time
tAA
35
35
25
-
55
55
30
-
70
70
35
-
Chip Enable Access Time
Output Enable Access Time
Chip Enable to Output in Low-Z
tACE1, tACE2
-
-
-
tOE
-
-
-
tCLZ1*, tCLZ2
*
10
5
-
10
5
-
10
5
-
Output Enable to Output in Low-Z tOLZ
*
-
-
-
Chip Disable to Output in High-Z
tCHZ1*, tCHZ2
*
25
25
-
30
30
-
35
35
-
Output Disable to Output in High-Z tOHZ
*
-
-
-
Output Hold from Address Change tOH
5
5
5
(2) WRITE CYCLE
PARAMETER
SYMBOL UT621024-
35
UT621024-70 UNIT
UT621024-55
MAX. MIN. MAX.
70
MIN.
35
30
30
0
MAX. MIN.
Write Cycle Time
tWC
-
-
55
50
50
0
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Valid to End of Write
Chip Enable to End of Write
Address Set-up Time
Write Pulse Width
tAW
-
60
-
tCW1, tCW2
-
-
-
60
0
-
-
tAS
-
tWP
25
0
-
40
0
-
45
0
-
Write Recovery Time
Data to Write Time Overlap
tWR
-
-
-
tDW
20
0
-
25
0
-
30
0
-
Data Hold from End of Write-Time tDH
-
-
-
Output Active from End of Write
Write to Output in High-Z
tOW
*
5
-
5
-
5
-
tWHZ
*
-
15
-
20
-
25
*These parameters are guaranteed by device characterization, but not production tested.
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
3
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
TIMING WAVEFORMS
READ CYCLE 1 (Address Controlled) (1,2,4)
tRC
Address
tAA
tOH
tOH
DOUT
Data Valid
READ CYCLE 2 (
, CE2 and
Controlled) (1,3,5,6)
OE
CE1
tRC
Address
CE1
tAA
tACE1
CE2
OE
tACE2
tOE
tCHZ1
tCHZ2
tCLZ1
tCLZ2
High-Z
tOHZ
tOH
tOLZ
DOUT
High-Z
Data Valid
Notes :
1.
is HIGH for read cycle.
WE
2. Device is continuously selected
=VIL and CE2=VIH.
CE1
3. Address must be valid prior to or coincident with
and CE2 transition; otherwise tAA is the limiting parameter.
CE1
4.
5.
is low.
OE
t
±
CLZ1, tCLZ2, tOLZ, tCHZ1, tCHZ2 and tOHZ are specified with CL=5pF. Transition is measured 500mV from steady state.
6. At any given temperature and voltage condition, tCHZ1 is less than tCLZ1, tCHZ2 is less than tCLZ2, tOHZ is less than tOLZ.
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
4
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
WRITE CYCLE 1 (
Controlled) (1,2,3,5)
WE
tWC
Address
CE1
tAW
tCW1
tCW2
CE2
tAS
tWP
tWR
WE
tWHZ
tOW
High-Z
(4)
(4)
DOUT
tDW
Data Valid
tDH
DIN
WRITE CYCLE 2 (
and CE2 Controlled) (1,2,5)
CE1
tWC
Address
tAW
CE1
tAS
tCW1
tCW2
tWR
CE2
tWP
WE
tWHZ
(4)
High-Z
DOUT
tDW
Data Valid
tDH
DIN
Notes :
1.
or
must be HIGH or CE2 must be LOW during all address transitions.
CE1
WE
2. A write occurs during the overlap of a low
, a high CE2 and a low
.
CE1
WE
LOW, tWP must be greater than tWHZ+tDW to allow the I/O drivers
OE
3. During a
controlled with write cycle with
WE
to turn off and data to be placed on the bus.
4. During this period, I/O pins are in the output state, and input singals must not be applied.
5. If the
LOW transition occurs simultaneously with or after
LOW transition, the outputs remain in a high
CE1
impedance state.
WE
±
6.
t
OW and tWHZ are specified with CL=5pF. Transition is measured 500mV from steady state.
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
5
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
℃
℃
DATA RETENTION CHARACTERISTICS (T = 0 to 70 )
A
PARAMETER
SYMBOL TEST CONDITION
MIN. TYP. MAX. UNIT
Vcc for Data Retention
VDR
2.0
-
-
V
≧
V
CC-0.2V or
CE1
CE2 ≤ 0.2V
Data Retention Current
IDR
Vcc=3V
- L
-
-
40
20*
20
10*
-
µA
µA
1
- LL
≧
VCC-0.2V or
CE1
0.5
-
CE2 ≤ 0.2V
Chip Disable to Data
Retention Time
tCDR
tR
See Data Retention
Waveforms (below)
0
ns
ns
Recovery Time
tRC*
-
-
tRC* = Read Cycle Time
℃
*Those parameters are for reference only under 50
DATA RETENTION WAVEFORM
Date Retention Mode
VCC
4.5V
4.5V
tR
VDR ≧2.0V
tCDR
CE1
VIH
VIH
≧VCC -0.2V
VSS
CE1
CE2
VIL
VIL
CE2 ≤ 0.2V
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
6
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
PACKAGE OUTLINE DIMENSION
32 pin 600 mil PDIP Package Outline Dimension
UNIT
INCH(BASE)
MM(REF)
SYMBAOL1
A2
B
0.010 (MIN)
0.254 (MIN)
±
±
0.150 0.005 3.810 0.127
±
±
0.018 0.005 0.457 0.127
±
±
B1
c
0.050
0.005 1.270 0.127
±
±
0.010 0.004 0.254 0.102
±
±
D
E
1.650 0.005 41.910 0.127
±
±
0.600 0.010 15.240 0.254
±
±
E1
e
0.544 0.004 13.818 0.102
0.100(TYP)
2.540(TYP)
±
±
eB
L
0.640 0.020 16.256 0.508
±
±
0.130 0.010 3.302 0.254
±
±
S
Q1
0.075 0.010 1.905 0.254
±
±
0.070 0.005 1.778 0.127
Note:
1. D/E1/S DIMENSION DO NOT INCLUDE MOLD FLASH.
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
7
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
32 pin 450mil SOP Package Outline Dimension
UNIT
INCH(BASE)
SYMBOL
MM(REF)
A
0.118 (MAX)
0.004(MIN)
0.111(MAX)
0.015(MIN)
0.020(MAX)
0.008(TYP)
0.817(MAX)
±
2.997 (MAX)
0.102(MIN)
2.82(MAX)
0.38(MIN)
0.50(MAX)
0.203(TYP)
20.75(MAX)
±
A1
A2
b
c
D
E
0.445 0.005 11.303 0.127
A
±
±
E1
e
0.555 0.005 14.097 0.127
0.050(TYP)
1.270(TYP)
±
±
L
0.0347 0.008 0.881 0.203
±
±
L1
S
0.055 0.008 1.397 0.203
0.026(MAX)
0.004(MAX)
0o -10o
0.660 (MAX)
0.101(MAX)
0o -10o
y
Θ
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
8
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
32 pin TSOP-I Package Outline Dimension
UNIT
INCH(BASE)
MM(REF)
SYMBOL
A
0.047 (MAX)
1.20 (MAX)
±
±
A1
A2
0.004 0.002
0.10 0.05
C
±
±
0.039 0.002
1.00 0.05
0.008 + 0.002
- 0.001
0.20 + 0.05
-0.03
b
c
D
E
e
0.005 (TYP)
±
0.127 (TYP)
±
0.724 0.004 18.40 0.10
±
±
0.315 0.004
8.00 0.10
0.020 (TYP)
0.50 (TYP)
±
±
HD
L
0.787 0.008 20.00 0.20
±
±
0.0197 0.004 0.50 0.10
±
±
L1
y
0.0315 0.004 0.08 0.10
0.003 (MAX) 0.076 (MAX)
o
o
o
o
Θ
〜
〜
0
5
0
5
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
9
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
32 pin 8mm x 13.4mm STSOP Package Outline Dimension
Uni
t
MM(REF)
INCH(BASE)
0.047(Max).
Symbol
A
A1
A2
b
±
±
0.10 0.05
0.004 0.002
Note：
±
±
1.00 0.05
0.039 0.002
1.E dinmension is not including end
flash.
c
2.The total of both sides’ end flash Is
not above 0.3mm.
±
±
13.40 0.20
0.526 0.006
D
±
±
11.80 0.10
0.465 0.004
Db
E
±
±
8.000 0.10
0.315 0.004
e
±
±
0.50 0.10
0.020 0.004
L
±
±
0.80 0.10
0.0315 0.004
L1
ꢀ
ꢀ
ꢀ
ꢀ
e
0 ~5
0 ~5
________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
10
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
ORDERING INFORMATION
PART NO.
ACCESS TIME
STANDBY CURRENT
PACKAGE
(ns)
35
35
35
35
35
35
35
35
55
55
55
55
55
55
55
55
70
70
70
70
70
70
70
70
(µA)
100
50
UT621024PC-35L
UT621024PC-35LL
UT621024SC-35L
UT621024SC-35LL
UT621024LC-35L
UT621024LC-35LL
UT621024LS-35L
UT621024LS-35LL
UT621024PC-55L
UT621024PC-55LL
UT621024SC-55L
UT621024SC-55LL
UT621024LC-55L
UT621024LC-55LL
UT621024LS-55L
UT621024LS-55LL
UT621024PC-70L
UT621024PC-70LL
UT621024SC-70L
UT621024SC-70LL
UT621024LC-70L
UT621024LC-70LL
UT621024LS-70L
UT621024LS-70LL
32 PIN PDIP
32 PIN PDIP
32 PIN SOP
100
50
32 PIN SOP
100
50
32 PIN TSOP-I
32 PIN TSOP-I
32 PIN STSOP
32 PIN STSOP
32 PIN PDIP
32 PIN PDIP
32 PIN SOP
100
50
100
50
100
50
32 PIN SOP
100
50
32 PIN TSOP-I
32 PIN TSOP-I
32 PIN STSOP
32 PIN STSOP
32 PIN PDIP
32 PIN PDIP
32 PIN SOP
100
50
100
50
100
50
32 PIN SOP
100
50
32 PIN TSOP-I
32 PIN TSOP-I
32 PIN STSOP
32 PIN STSOP
100
50
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
11
UTRON
UT621024
Rev. 1.5
128K X 8 BIT LOW POWER CMOS SRAM
REVISION HISTORY
REVISION
REV. 1.0
REV. 1.1
REV. 1.2
REV. 1.3
REV. 1.4
DESCRIPTION
DATE
Apr. 05 2000
--
Original.
NA
NA
--
Add STSOP-I Package
Aug. 29.2000
Sep. 01.2000
Jun. 18,2001
Modify the format of power consumption
REV. 1.5
1. Operating : 60/40 -> 60/50/40
2. Standby Current : 10 ->2 (L-version)
3. Add ICC–data as (-55, TYP 50, MAX 85)
4. Revise ISB1 TYP : 10-> 2, MAX : 300/100 ->100/40
5. The symbols CE1# ,OE# & WE# are revised as
,
&
CE1 OE WE
_________________________________________________________________________________________________
UTRON TECHNOLOGY INC.
P80036
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882 FAX: 886-3-5777919
12
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