VMX51C1020-14-Q-C_技术文档

VMX1C1020

Datasheet

Rev 2.12

Versa Mix 8051 Mixed-Signal MCU

Overview

Feature Set

o

8051 Compatible RISC performance Processor.

Integrated Debugger

56KB Flash Program Memory

1280 Bytes of RAM

MULT/ACCU unit including a Barrel Shifter

The VMX51C1020 is a fully integrated mixed-signal

microcontroller that provides a “one-chip solution” for

a broad range of signal conditioning, data acquisition,

processing, and control applications.

The

VMX51C1020 is based on a powerful single-cycle,

RISC-based, 8051 microprocessor with an enhanced

MULT/ACCU unit that can be used to perform

complex mathematical operations.

o

Provides DSP capabilities

o

2 UART Serial Ports

2 Baud Rate Generators for UARTs

Differential Transceiver connected to UART1

J1708/RS-485/RS-422 compatible.

Enhanced SPI interface (Master/Slave)

On-chip analog peripherals such as: an A/D

converter, PWM outputs (that can be used as D/A

converters), a voltage reference, a programmable

current source, an uncommitted operational amplifier,

digital potentiometers and an analog switch makes

the VMX51C1020 ideal for analog data acquisition

applications.

o

Fully Configurable

o

Controls up to 4 slave devices

o

I2C interface

28 General Purpose I/Os

2 External Interrupt Inputs

Interrupt on Port 1 pin change

3, 16-bit Timers/Counters

4 Compare & Capture Units with 3 Capture Inputs

4 PWM outputs, 8-bit / 16-bit resolution

4 ext. + 3 int. Channel 12-bit A/D Converter

The inclusion of a full set of digital interfaces such as

an enhanced fully configurable SPI, an I²C interface,

UARTs and

a J1708/RS-485/RS-422 compatible

differential transceiver, enables total system

integration.

o

Conversion rate up to 10kHz

0-2.7 Volt Input range Continuous /

One-Shot operation

Applications

o

Single or 4-channel automatic

sequential conversions

o

Automotive Applications

Industrial Controls / Instrumentation

Consumer Products

Intelligent Sensors

Medical Devices

o

On-Chip Voltage Reference

Programmable Current Source

Operational Amplifier

2 Digital Potentiometers

1 Digitally Controlled Switch

Power Saving Features + Clock Control

Power-on Reset with Brown-Out Detect

Watchdog Timer

FIGURE 1: VMX51C1020 BLOCK DIAGRAM

8051

µPROCESSOR

SINGLE CYCLE

In-Circuit

Debugging

through UART0

FIGURE 2: VMX51C1020 QFP-64 PACKAGE PINOUT

Programmable

Current Source

2

UARTs

Serial Ports

12-BIT A/D

CONVERTER

56KB

Program FLASH

(In-Circuit Programmable

)

ISRCIN, ISRCOUT, OPOUT are

internally connected to A /D Input

Multiplexer

XTVREF Input

4

8

33

1280 Bytes RAM

32

Band gap

Reference

AGND

49

P1.5

P

G A

(256x 8

& 1k X8)

INT0

PM

P1.4

VDD

RES-

P2.7 – SDI

P2.6 – SDO

P2.5 – SCK

P2.4 – SS-

P2.3 – CS0-

P2.2 – CS1-

P2.1 – CS2-

P2.0 – CS3-

DGND

·

2 Interrupt inputs

28 I/O s,

Interrupt on

Port1 change

4

PWM D /As

4

PWM Outputs

4

PWM D /As

_/4₁₆PWM D /As

ISRCOUT – TA

ISRCIN

8

bit Resolution

(Can be used as /A s)

D

POT2A

·

3

2

Timers,

Baud Rate

POT2B

Operational

Amplifier

VMX51C1020

VDDA

Generators

4 CCU units

ADCI3

ADCI2

·

1

DIGITALLY

ADCI1

[MULT / A C C U]

Unit with

BARREL

CONTROLLED

SWITCH

ADCI0

INT1

XTVREF

AGND

CCU2

SHIFTER

P1.3 PWM3

P1.2 PWM2

OPOUT

64

17

2

DIGITAL

1

16

POTENTIOMETERS

SPI Interface

J1708 /RS485/

RS422

Compatible

Transceiver

I²C Bus

Interface

Power On Reset

Circuit

+

XTAL

Clock Control Unit

WatchDog Timer

Ramtron International Corporation

1850 Ramtron Drive Colorado Springs

Colorado, USA, 80921

http://www.ramtron.com

MCU customer service: 1-800-943-4625, 1-514-871-2447, ext. 208

1-800-545-FRAM, 1-719-481-7000

?

VMX51C1020

39

40

41

NAME

FUNCTION

VMX51C1020 Pins Description

P3.2-T0IN

VDD

I/O - Timer/Counter 0 Input

5V Digital

Table 1: Pin out description

P3.3-

I/O - Capture and Compare Unit 0 Input

CCU0

1

NAME

OPIN-

OPIN+

POT1A

POT1B

SW1A

SW1B

TX1D-

FUNCTION

42

P3.4-

CCU1

I/O - Capture and Compare Unit 1 Input

Inverting Input of the Operational Amplifier

Non-inverting Input of the Operational Amplifier

Digitally Controlled Potentiometer 1A

Digitally Controlled Potentiometer 1B

Digitally Controlled Switch 1A

2

43

44

45

P3.5-T1IN

VPP

I/O - Timer/Counter 1 Input

3

Flash Programming Voltage Input

4

P3.6-SDA

I/O - I2C / Prog. Interface Bi-Directional Data

Bus

5

46

47

48

49

50

NC

Not Connected, leave floating

Not Connected

6

Digitally Controlled Switch 1B

NC

7

RS-485/RS422 compatible differential

Transmitter, Negative side

P3.7-SCL

AGND

INT0

I/O - I2C / Prog. Interface Clock

Analog Ground

8

RX1D-

RS-485/RS422 compatible differential Receiver

Negative side

External interrupt Input (Negative Level or Edge

Triggered)

9

TX1D+

RX1D+

RS-485/RS422 compatible differential

Transmitter, Positive side

51

52

53

PM

Mode Control Input

10

RS-485/RS422 compatible differential Receiver

Positive side

RES-

Hardware Reset Input (Active low)

Programmable Current Source Analog Output

ISRCOUT-

TA

11

12

13

P0.3-RX1

P0.2-TX1

I/O - Asynchronous UART1 Receiver Input

I/O - Asynchronous UART1 Transmitter Output

I/O -Timer/Counter 2 Input

54

55

56

57

58

59

60

61

62

63

64

ISRCIN

POT2A

POT2B

VDDA

Programmable Current Source Input

Digitally Controlled Potentiometer 2A

Digitally Controlled Potentiometer 2B

Analog Supply

P0.1-

T2EX

14

15

P0.0-T2IN

I/O -Timer/Counter 2 Input

P1.0-

I/O - Pulse Width Modulator output 0

ADCI3

ADCI2

ADCI1

ADCI0

XTVREF

AGND

Analog to Digital Converter ext. Input 3

Analog to Digital Converter ext. Input 2

Analog to Digital Converter ext. Input 1

Analog to Digital Converter ext. Input 0

External Reference Voltage Input

Analog Ground

PWM0

16

17

18

P1.1-

I/O - Pulse Width Modulator output 1

I/O - Pulse Width Modulator output 2

I/O - Pulse Width Modulator output 3

PWM1

P1.2-

PWM2

P1.3-

PWM3

OPOUT

Output of the Operational Amplifier

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

CCU2

Capture and Compare Unit 2 Input

Interrupt Input 1

INT1

FIGURE 3: VMX51C1020 PINOUT

DGND

Digital Ground

P2.0-CS3-

P2.1-CS2-

P2.2-CS1-

P2.3-CS0-

P2.4-SS-

P2.5-SCK

P2.6-SDO

P2.7-SDI

VDD

I/O - SPI Chip Enable Output (Master Mode)

I/O - SPI Chip Enable Output (Slave Mode)

I/O - SPI Clock (Input in Slave Mode)

I/O - SPI Data Output Bus

I/O - SPI Data Input Bus

Digital Supply

47 46 45 44 43 42 41 40 39 38 37 36 35 34 33

48

32

31

49

50

51

52

53

AGND

INT0

P1.5

P1.4

30

29

28

27

26

PM

VDD

RES-

P2.7 – SDI

P2.6 – SDO

P2.5 – SCK

P2.4 – SS-

P2.3 – CS0-

P2.2 – CS1-

P2.1 – CS2-

P2.0 – CS3-

DGND

ISRCOUT – TA

ISRCIN

POT2A

POT2B

VDDA

54

55

56

57

25

24

23

22

VMX51C1020

58

59

60

ADCI3

ADCI2

P1.4

I/O

21

20

19

18

ADCI1

61

62

63

64

ADCI0

INT1

P1.5

I/O

XTVREF

AGND

CCU2

P1.3 PWM3

P1.2 PWM2

P1.6

I/O

17

OPOUT

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16

P1.7

I/O

OSC1

Oscillator Crystal Output

OSC0

Oscillator Crystal input/External Clock Source

Input

37

38

P3.0-TX0

P3.1-RX0

I/O - Asynchronous UART0 Transmitter Output

I/O - Asynchronous UART0 Receiver Input

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VMX51C1020

VMX51C1020 Block Diagram

FIGURE 4: VMX51C1020 BLOCK DIAGRAM

8051

µPROCESSOR

SINGLE CYCLE

In-Circuit

Debugging

through UART0

Programmable

Current Source

2 UARTs

Serial Ports

12-BIT A/D

CONVERTER

56KB

Program FLASH

(In-Circuit Programmable)

ISRCIN, ISRCOUT, OPOUT are

internally connected to A/D Input

Multiplexer

XTVREF Input

1280 Bytes RAM

Band gap

Reference

PGA

(256x8 & 1kX8)

·

2 Interrupt inputs

28 I/Os,

Interrupt on

Port1 change

3 Timers,

2 Baud. rate

generators

4 CCU units

4 PWM D/As

4 PWM Outputs

4 PWM D/As

_{8 /}4₁₆P_biW_{t Re}M_solD_uti/_oA_ns

(Can be used as D/As)

·

Operational

Amplifier

·

1 DIGITALLY

CONTROLLED

SWITCH

[MULT / ACCU]

Unit with

BARREL

SHIFTER

2 DIGITAL

POTENTIOMETERS

SPI Interface

J1708/

RS485/RS422

Compatible

I²C Bus

Interface

Transceiver

Power On Reset

Circuit

+

XTAL

Clock Control Unit

WatchDog Timer

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VMX51C1020

Absolute Maximum Ratings

V_DDto DGND

–0.3V, +6V

Digital Output Voltage to

DGND

V_PPto DGND

–0.3V, V_DD+0.3V

+13V

V_DDAto DGND

AGND to DGND

V_DDto V_DDA

-0.3V, +6V

–0.3V, +0.3V

-0.3V, +0.3V

Power Dissipation

§

To +70°C

1000mW

ADCI (0-3) to AGND

XTVREF to AGND

-0.3V, V_DDA+0.3V

Operating Temperature

Range

Storage Temperature Range

0° to +70°C

–65°C to +110°C

+300°C

Digital Input Voltage to

DGND

RS422/485 Minimum and

Maximum Voltages

-0.3V, V_DD+0.3V

-2V, +7V

Lead Temperature

(soldering, 10sec)

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device.

These are stress ratings only and functional operation of the device at these or any other conditions beyond

those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum

rating conditions for extended periods may affect device reliability.

Electrical Characteristics

TABLE 2: ELECTRICAL CHARACTERISTICS

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

GENERAL CHARACTERISTICS (V_DD= +5V, V_DDA= +5V, T_A= +25°C, 14.75MHz input clock, unless otherwise noted.)

Power Supply Voltage

Power Supply Current

V_DD

4.75

4.5

5

5.0

5.5

45*

6*

V

V_DDA

V

I_{DD (14.75MHz)}

I_{DD (1MHz)}

mA

*Depends on clock

speed and peripheral

use and load

0.6

I_DDA

V_PP

0.1

11

5*

Flash Programming Voltage

DIGITAL INPUTS

13

V

Minimum High-Level input

Maximum Low-Level input

Input Current

V_IH

V_IL

I_IN

V_DD= +5V

2.0

0.8

±0.05

5

V

µA

pF

Input Capacitance

C_IN

10

DIGITAL OUTPUTS

Minimum High-Level

Output Voltage

V_OH

V_OL

I_SOURCE= 4mA

I_SINK= 4mA

4.2

0.2

10

V

Maximum Low-Level

Output Voltage

Output Capacitance

C_OUT

I_OZ

15

Pf

Tri-state Output Leakage

Current

0.25

µA

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VMX51C1020

ANALOG INPUTS

ADCI(0-3) Input Voltage Range

ADCI(0-3) Input Resistance

ADCI(0-3) Input Capacitance

V_ADCI

R_ADCI

C_ADCI

I_ADCI

0

2.7

V

100

7

Mohms (design)

pF

nA

ADCI(0-3) Input Leakage

Current

TBD

Channel-to-Channel Crosstalk

-72

dB (design)

(12 bit)

ANALOG OUTPUT

TA Output Drive Capabilities

(Maximum Load Resistance)

V_TA=V_ADCI(0-3)

Others

10

kOhms

Requires buffering

25M

CURRENT SOURCE

ISRC Current Drive REF_ISRC200

ISRC Current Drive REF_ISRC800

ISRC Feedback voltage 200mV

ISRC Feedback voltage 800mV

ISRC Output Resistance

I_ISRC200

I_ISRC800

REF_ISRC200

REF_ISRC800

R_ISRC

33

66

µA (design)

µA

133

500

205

803

195

799

mV

50

25

MOhms

pF

ISRC Output Capacitance

C_ISRC

ISRCIN Input Reference

Resistance

R_RESIN

100

Mohms

ISRCIN Input Reference

Capacitance

C_RESIN

Drift

7

pF

ISRC stability

2.5

%

Allowable sensor capacitance

between ISRCIN & ISRCOUT

1000

PF

Allowable capacitance between

ISRCOUT & GND

100

pF

INTERNAL REFERENCE

Bandgap Reference Voltage

Bandgap Reference Tempco

EXTERNAL REFERENCE

Input Impedance

1.18

1.23V

100

1.28

V

ppm/°C

R_XTVREF

150

kOhms

PGA

PGA Gain adjustment

2.11

-1

2.29

ANALOG TO DIGITAL CONVERTER

External Reference, TA=25C, Fosc = 14.75MHz

ADC Resolution

12

Bits

LSB

Hz

Differential Non linearity

Integral Non linearity

Full-Scale Error (Gain Error)

Offset Error

DNL

INL

±1.5

+4

All channels, ADCI(0-3)

Single Channel

±4

±1

Channel-to-Channel Mismatch

Sampling Rate

1

10k

4 Channels

2.5k

UART1 DIFFERENTIAL TRANSCEIVER COMPATIBLE TO J1708/ RS-485/RS-422

Common mode Input Voltage

Input Impedance

Vc_I

Z_IN

-2

+7

V

1

30

MOhms

mA

Output Drive Current

Differential Input

100mV

mV

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VMX51C1020

OPERATIONAL AMPLIFIER

Output Impedance

Input Resistance

Zout

Zin

20

mOhms

GOhms

dB

36

Voltage Gain

G_v

100

5

Unit Gain Bandwidth

Load Resistance to Ground

Load Capacitance

UGBW

MHz

1

KOhms

pF

40

7

Slew rate

SR

V/µs (Design)

mV

Input Offset Voltage

Input Voltage Range

Common Mode Rejection Ratio

V_IO

+/- 2

V_I®

0

4

V (Design)

dB

CMRRdc

DC

83

99

CMRR1kHz Taken at 1kHz

75

dB Design)

dB (Design)

Power Supply Rejection Ratio

PSRR

Taken at 1kHz

(20dB/decade)

-75

(Vdd)

-94

(Vss)

Output Voltage Swing (RL=10k)

Short Circuit Current to ground

DIGITAL POTENTIOMETERS

V_{O (P-P)}

I_IC

25mV

4.975

V

86

mA (Design)

Number of Steps (8-bit binary

weighted)

256

steps

Maximum Resistance

Minimum Resistance

Step size

28k

485

105

30k

510

115

1

32k

535

130

Ohms

%

Inter channel Matching

Temperature Coefficient

Allowable current (DC)

Inherent Capacitance

DIGITAL SWITCH

0.16

%/°C

mA

5

3

4

pF

Switch on Resistance

Input capacitance

50

0

100

Ohms (+/-10%)

pF

V

Voltage range on Pin

Allowable current (DC)

BROWN OUT / RESET CIRCUIT

Brown-out circuit Threshold

RES- pin internal Pull-Up

5

mA

3.7

4.0

V

20

KOhms

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www.ramtron.com page 6 of 80

VMX51C1020

Memory Organization

Detailed Description

Figure 6 shows the memory organization of the

VMX51C1020.

The following sections will describe the

VMX51C1020’s architecture and peripherals.

At power-up/reset, the code is executed from the

56Kx8 Flash memory mapped into the processor’s

internal Program space.

FIGURE 5: INTERFACE DIAGRAM FOR THE VMX51C1020

VERSA

+5V Digital

+5V Analog

VDD

MIX

T0IN

T1IN

T2IN

T2EX

VDDA

TIMERS

AGND

DGND

A 1KB block of RAM is also mapped into the

external data memory of the VMX51C1020. This

block can be used as general-purpose scratch pad

or storage memory. A 256 byte block of RAM is

mapped to the internal data memory space. This

block of RAM is broken into 2 sub-blocks, with the

upper block accessible via indirect addressing and

the lower block accessible via both direct and

indirect addressing.

UART 0

INTERFACE

UART 0

ADCI0

ADCI1

ADCI2

ADCI3

EXTERNAL A/D

INPUTS

UART 1

INTERFACE

UART 1

UART1 DIFF.

TRANSCEIVER

J1708/RS-485 /

RS422

DIFFERENTIAL

TRANSCEIVER

ISRCOUT

ISRCIN

CURRENT SOURCE

CCU0

CCU1

CCU2

COMPARE AND

CAPTURE UNITS

INPUTS

SW1A

SW1B

DIGITAL

SWITCH

I/O

I/Os

RES-

RESET

The following figure describes the access to the

lower block of 128 bytes.

I2C

INTERFACE

OPOUT

OPIN-

OPIN+

SCL

SDA

OP-AMP

INT0

INT1

EXTERNAL

INTERRUPTS

POT1A

POT1B

POT2A

FIGURE 7: LOWER 128 BYTES BLOCK INTERNAL MEMORY MAP

POTENTIOMETERS

SDI

POT2B

SDO

SCK

SS-

CS0-

CS1-

CS2-

LOWER 128 BYTES OF

INTERNAL DATA MEMORY

SPI

INTERFACE

PWM0

PWM1

PWM

OUTPUTS

7Fh

PWM2

PWM3

DIRECT

RAM

OSC0 OSC1

CS3-

30h

2Fh

REGISTER

BIT-

BANK SELECT

ADDRESSABLE

REGISTERS

20h

1Fh

18h

17h

10h

0Fh

08h

07h

The value of the

RS1, RS0 bits of

PSW SFR

Register (D0h)

defines the

FIGURE 6: MEMORY ORGANIZATION OF THE VMX51C1020

BANK 3

BANK 2

BANK 1

BANK 0

11h

10h

01h

00h

INTERNAL PROGRAM

MEMORY SPACE

selected R0 -R7

Register Bank

DFFFh

56KB

INTERNAL DATA

MEMORY SPACE

00h

FLASH

MEMORY

8051

COMPATIBLE

µ-PROCESSOR

FFh

80h

128 Bytes

RAM

(INDIRECT

ADDRESSING

SFR SPACE -

PERIPHERALS

(DIRECT

The SFR (Special Function Register) space is also

mapped into the upper 128 bytes of internal data

memory space. This SFR space is only accessible

using direct-access. The SFR space provides the

interface to all the on-chip peripherals. This

interfacing is illustrated in Figure 8.

0000h

ADDRESSING)

EXTERNAL DATA

MEMORY SPACE

80h

7Fh

128 Bytes

RAM

(DIRECT &

INDIRECT

ADDRESSING)

03FFh

1KB

SRAM

00h

0000h

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www.ramtron.com page 7 of 80

VMX51C1020

FIGURE 8: SFR ORGANIZATION

TABLE 5: (DPH1) DATA POINTER HIGH 1 - SFR 85H

15

14

13

12

11

10

2

9

1

8

0

ADC

CONTROL

DPH1 [7:0]

TABLE 6: (DPL1) DATA POINTER LOW 1 - SFR 84H

SPI BUS

7

6

5

4

3

DPL1 [7:0]

DIFF

TRANSCEIVER

INTERNAL DATA

MEMORY SPACE

Bit

15-8 DPH1

7-0 DPL1

Mnemonic

Function

Data Pointer 1 MSB.

Data Pointer 1 LSB.

CLOCK

CONTROL

FFH

SFR SPACE

PERIPHERALS

(DIRECT

-

I2C BUS

ADDRESSING)

80H

TABLE 7: (DPS) DATA POINTER SELECT REGISTER - SFR 86H

PERIPHERAL

INTERRUPTS

7

0

6

0

5

0

4

0

3

0

2

0

1

0

SEL

MAC

I/O CONTROL

Bit

Mnemonic

Function

7-1

0

SEL

Always zero

0 = DPTR0 is selected

1 = DPTR1 is selected

8051

PROCESSOR

PERIPHERALS

Used to toggle between both data

pointers

Dual Data Pointers

The VMX51C1020 includes two data pointers.

MPAGE Register

The MPAGE register controls the upper 8 bits of

the targeted address when the MOVX instruction is

used for external RAM data transfer. This allows

access to the entire external RAM content without

using the Data Pointer.

The first data pointer (DPTR0) is mapped into

SFR locations 82h and 83h and the second data

pointer (DPTR1) mapped into SFR locations 84h

and 85h. The SEL bit in the data pointer select

register, DPS (SFR 86h), selects which data

pointer is active. When SEL = 0, instructions that

use the data pointer will use DPL0 and DPH0.

When SEL = 1, instructions that use the DPTR will

use DPL1 and DPH1. SEL is located in bit 0 of the

DPS (SFR location 86h - the remaining bits of SFR

location 86h are un-used.

TABLE 8: (MPAGE) MEMORY PAGE - SFR CFH

7

6

5

4

3

2

1

0

MPAGE [7:0]

User Flags

The VMX51C1020 provides an SFR register that

gives the user the ability to define software flags.

Each bit of this register is individually addressable.

This register may also be used as a general-

purpose storage location. Thus, the user flag

feature allows the VMX51C1020 to better adapt to

each specific application. This register is located at

SFR address F8h

All DPTR-related instructions use the currently

selected data pointer. In order to switch the active

pointer, toggle the SEL bit. The fastest way to do

so is to use the increment instruction (INC DPS).

The use of the two data pointers can significantly

increase the speed of moving large blocks of data

because only one instruction is needed to switch

from a source address and destination address.

TABLE 9: (USERFLAGS) USER FLAG - SFR F8H

7

6

5

4

3

2

1

0

UF7

UF6

UF5

UF4

UF3

UF2

UF1

UF0

The SFR locations and register representations

related to the dual data pointers are outlined as

follows:

TABLE 3: (DPH0) DATA POINTER HIGH 0 - SFR 83H

15

14

13

12

11

10

9

8

DPH0 [7:0]

TABLE 4: (DPL0) DATA POINTER LOW 0 - SFR 82H

7

6

5

4

3

2

1

0

DPL0 [7:0]

Bit

15-8 DPH0

7-0 DPL0

Mnemonic

Function

Data Pointer 0 MSB

Data Pointer LSB.

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VMX51C1020

Size

(bytes)

Instr.

Cycles

Mnemonic

Description

Instruction Set

Data Transfer Instructions

MOV A, Rn

Move register to A

1

2

1

2

1

2

3

2

3

1

2

3

1

2

1

2

1

All VMX51C1020 instructions are function and

binary code compatible with the industry standard

8051. However, the timing of instructions may be

different. The following two tables describe the

instruction set of the VMX51C1020.

MOV A, direct

MOV A, @Ri

MOV A, #data

MOV Rn, A

Move direct byte to A

2

Move data memory to A

2

Move immediate to A

2

Move A to register

2

MOV Rn, direct

MOV Rn, #data

MOV direct, A

MOV direct, Rn

MOV direct, direct

MOV direct, @Ri

MOV direct, #data

MOV @Ri, A

MOV @Ri, direct

MOV @Ri, #data

MOV DPTR, #data16

MOVC A, @A+DPTR

MOVC A, @A+PC

MOVX A, @Ri

MOVX A, @DPTR

MOVX @Ri, A

MOVX @DPTR, A

PUSH direct

POP direct

Move direct byte to register

Move immediate to register

Move A to direct byte

4

2

3

TABLE 10: LEGEND FOR INSTRUCTION SET TABLE

Move register to direct byte

Move direct byte to direct byte

Move data memory to direct byte

Move immediate to direct byte

Move A to data memory

3

Symbol

A

Function

Accumulator

4

Rn

Register R0-R7

3

Direct

@Ri

rel

Internal register address

Internal register pointed to by R0 or R1 (except MOVX)

Two's complement offset byte

Direct bit address

3

Move direct byte to data memory

Move immediate to data memory

Move immediate 16 bit to data pointer

Move code byte relative DPTR to A

Move code byte relative PC to A

Move external data (A8) to A

Move external data (A16) to A

Move A to external data (A8)

Move A to external data (A16)

Push direct byte onto stack

Pop direct byte from stack

Exchange A and register

5

bit

3

#data

#data 16

addr 16

addr 11

8-bit constant

16-bit constant

16-bit destination address

11-bit destination address

3

3-10

4-11

4

TABLE 11: VMX51C1020 INSTRUCTION SET

Size

(bytes)

Instr.

Cycles

Mnemonic

Description

Arithmetic instructions

ADD A, Rn

ADD A, direct

ADD A, @Ri

ADD A, #data

ADDC A, Rn

ADDC A, direct

ADDC A, @Ri

ADDC A, #data

SUBB A, Rn

SUBB A, direct

SUBB A, @Ri

SUBB A, #data

INC A

3

Add register to A

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

1

2

3

1

2

3

1

5

1

XCH A, Rn

2

Add direct byte to A

XCH A, direct

XCH A, @Ri

XCHD A, @Ri

Branching Instructions

ACALL addr 11

LCALL addr 16

RET

Exchange A and direct byte

Exchange A and data memory

Exchange A and data memory nibble

3

Add data memory to A

Add immediate to A

3

Add register to A with carry

Add direct byte to A with carry

Add data memory to A with carry

Add immediate to A with carry

Subtract register from A with borrow

Subtract direct byte from A with borrow

Subtract data mem from A with borrow

Subtract immediate from A with borrow

Increment A

Absolute call to subroutine

Long call to subroutine

2

3

1

2

3

2

3

1

2

3

2

3

6

4

3

4

3

4

2

3

4

3

4

Return from subroutine

RETI

Return from interrupt

AJMP addr 11

LJMP addr 16

SJMP rel

Absolute jump unconditional

Long jump unconditional

Short jump (relative address)

Jump on carry = 1

JC rel

INC Rn

Increment register

JNC rel

Jump on carry = 0

INC direct

Increment direct byte

JB bit, rel

Jump on direct bit = 1

INC @Ri

Increment data memory

Decrement A

JNB bit, rel

Jump on direct bit = 0

DEC A

JBC bit, rel

Jump on direct bit = 1 and clear

Jump indirect relative DPTR

Jump on accumulator = 0

Jump when accumulator not equal to 0

Compare A, direct JNE relative

Compare A, immediate JNE relative

Compare reg, immediate JNE relative

Compare ind, immediate JNE relative

Decrement register, JNZ relative

Decrement direct byte, JNZ relative

DEC Rn

Decrement register

JMP @A+DPTR

JZ rel

DEC direct

DEC @Ri

Decrement direct byte

Decrement data memory

Increment data pointer

Multiply A by B

JNZ rel

INC DPTR

CJNE A, direct, rel

CJNE A, #data, rel

CJNE Rn, #data, rel

CJNE @Ri, #data, rel

DJNZ Rn, rel

DJNZ direct, rel

Bit Operations

CLR C

MUL AB

DIV AB

Divide A by B

DA A

Decimal adjust A

Logical Instructions

ANL A, Rn

ANL A, direct

ANL A, @Ri

ANL A, #data

ANL direct, A

ANL direct, #data

ORL A, Rn

ORL A, direct

ORL A, @Ri

ORL A, #data

ORL direct, A

ORL direct, #data

XRL A, Rn

XRL A, direct

XRL A, @Ri

XRL A, #data

XRL direct, A

XRL direct, #data

CLR A

AND register to A

1

2

1

2

3

1

2

1

2

3

1

2

1

2

3

1

2

3

4

1

2

3

4

1

2

3

4

1

AND direct byte to A

AND data memory to A

AND immediate to A

Clear carry flag

1

2

1

2

1

2

1

3

1

3

1

3

2

3

CLR bit

Clear direct bit

AND A to direct byte

SETB C

Set carry flag

AND immediate data to direct byte

OR register to A

SETB bit

Set direct bit

CPL C

Complement carry Flag

Complement direct bit

OR direct byte to A

CPL bit

OR data memory to A

OR immediate to A

ANL C,bit

Logical AND direct bit to carry flag

Logical AND between /bit and carry flag

Logical OR bit to carry flag

Logical OR /bit to carry flag

Copy direct bit location to carry flag

Copy carry flag to direct bit location

ANL C, /bit

OR A to direct byte

ORL C,bit

OR immediate data to direct byte

Exclusive-OR register to A

Exclusive-OR direct byte to A

Exclusive-OR data memory to A

Exclusive-OR immediate to A

Exclusive-OR A to direct byte

Exclusive-OR immediate to direct byte

Clear A

ORL C, /bit

MOC c,bit

MOV bit,C

Miscellaneous Instruction

NOP

No operation

1

CPL A

Compliment A

SWAP A

Swap nibbles of A

RL A

Rotate A left

RLC A

Rotate A left through carry

Rotate A right

RR A

RRC A

Rotate A right through carry

_________________________________________________________________________________________________

www.ramtron.com page 9 of 80

VMX51C1020

Special Function Registers

The Special Function Registers (SFRs) control several features of the VMX51C1020. Many of the

VMX51C1020 SFRs are identical to the standard 8051 SFRs. However, there are additional SFRs that

control the VMX51C1020’s specific peripheral features that are not available in the standard 8051.

TABLE 12: SPECIAL FUNCTION REGISTERS

SFR

SFR Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Reset Value

Adrs

80h

81h

82h

83h

84h

85h

86h

87h

88h

89h

8Ah

8Bh

8Ch

8Dh

8Eh

8Fh

90h

91h

P0

SP

-

0

-

0

-

TR1

CT1

-

0

-

TF0

M11

-

0

-

TR0

M01

-

0

-

1111 1111b

0000 0111b

0000 0000b

1111 1111b

0000 0000b

DPL0

DPH0

DPL1

DPH1

DPS

PCON

TCON*

TMOD

TL0

TL1

TH0

TH1

Reserved

P1*

0

GF1

IE1

GATE0

0

GF0

IT1

CT0

-

SEL

IDLE

IT0

M00

-

SMOD

TF1

GATE1

STOP

IE0

M10

-

ADCIF/

COMPINT3

MACIF/

COMPINT2

I2CIF/

COMPINT1

SPIRXIF/

COMPINT0

IRCON

T2EXIF

T2IF

SPITXIF

Reserved

ANALOGPWREN

DIGPWREN

CLKDIVCTRL

ADCCLKDIV

S0RELL

S0RELH

S0CON*

S0BUF

IEN2

P0PINCFG

P1PINCFG

P2PINCFG

P3PINCFG

PORTIRQEN

P2*

PORTIRQSTAT A1h

ADCCTRL

ADCCONVRLOW

ADCCONVRMED

ADCCONVRHIGH

92h OPAMPEN DIGPOTEN ISRCSEL

ISRCEN

I2CEN

IRQNORMSPD

TAEN

SPIEN

ADCEN

UART1DIFFEN

PGAEN

UART1EN UART0EN

BGAPEN

0000 0000b

93h

94h

95h

96h

97h

98h

99h

9Ah

9Bh

9Ch

T2CLKEN

SOFTRST

WDOGEN

MACEN

-

MCKDIV_3 MCKDIV_2 MCKDIV_1 MCKDIV_0 0000 0000b

-

0

-

0

-

0000 1100b

11011001b

0000 0011b

0000 0000b

0

S0M0

-

0

S0M1

-

0

MPCE0

-

0

R0EN

-

T0B8

-

R0B8

-

T0I

-

R0I

-

S1IE

-

P0.1/T2EXINE

P07IO

P1.7

P06IO

P1.6

P05IO

P1.5

P04IO

P1.4

P0.3/RX1INE P0.2/TX1OE

P1.3/PWM3OE P1.2/PWM2OE P1.1/PWM1OE P1.0/PWM0OE

P0.0/T2INE 0000 0000b

0000 0000b

9Dh P2.7/SDIEN P2.6/SDOEN P2.5/SCKEN P2.4/SSEN P2.3/CS0EN P2.2/CS1EN P2.1/CS2EN P2.0/CS3EN 0000 0000b

P3.7/MSCLEN P3.6/MSDAEN

P3.5/T1INEN P3.4/CCU1ENP3.3/CCU0EN P3.2/T0INEN P3.1/RX0EN P3.0/TX0EN

P15IEN

9Eh

9Fh

A0h

0000 0000b

1111 1111b

0000 0000b

P17IEN

-

P16IEN

-

P14IEN

P13IEN

P12IEN

P11IEN

P10IEN

-

P17ISTAT

P16ISTAT

P15ISTAT

P14ISTAT

ADCIRQ

P13ISTAT

ADCIE

P12ISTAT

ONECHAN

P11ISTAT

CONT

P10ISTAT

ONESHOT

A2h ADCIRQCLR XVREFCAP

1

-

A3h

A4h

A5h

A6h

A7h

A8h

A9h

AAh

ABh

ACh

ADh

AEh

AFh

B0h

B1h

B2h

B3h

B4h

B5h

B6h

B7h

B8h

B9h

BAh

-

ADCD0LO

ADCD0HI

IEN0*

ADCD0HI_3 ADCD0HI_2 ADCD0HI_1 ADCD0HI_0 0000 0000b

EA

-

WDT

-

T2IE

-

S0IE

-

T1IE

-

INT1IE

-

T0IE

-

INT0IE

-

0000 0000b

ADCD1LO

ADCD1HI

ADCD2LO

ADCD2HI

ADCD3LO

ADCD3HI

Reserved

P3*

Reserved

BGAPCAL

PGACAL

INMUXCTRL

OUTMUXCTRL

SWITCHCTRL

IP0*

ADCD1HI_3 ADCD1HI_2 ADCD1HI_1 ADCD1HI_0 0000 0000b

0000 0000b

ADCD2HI_3 ADCD2HI_2 ADCD2HI_1 ADCD2HI_0 0000 0000b

0000 0000b

-

ADCD3HI_3 ADCD3HI_2 ADCD3HI_1 ADCD3HI_0 0000 0000b

0000 0000b

-

1111 1111b

1101 0001b

0000 0000b

Cal. Vector

0000 0000b

-

ADCINSEL_2 ADCINSEL_1 ADCINSEL_0 AINEN_3

AINEN_2

AINEN_1

AINEN_0

TAOUTSEL_2 TAOUTSEL_1 TAOUTSEL_0

-

SWITCH1_3 SWITCH1_2 SWITCH1_1 SWITCH1_0 0000 0000b

UF8

-

WDTSTAT

IP0.5

IP1.5

-

IP0.4

IP1.4

-

IP0.3

IP1.3

-

IP0.2

IP1.2

-

IP0.1

IP1.1

-

IP0.0

IP1.0

-

0000 0000b

IP1

DIGPOT1

-

_________________________________________________________________________________________________

www.ramtron.com page 10 of 80

VMX51C1020

SFR

Adrs

BBh

SFR Register

Bit 7

-

Bit 6

-

Bit 5

-

Bit 4

-

Bit 3

-

Bit 2

-

Bit 1

-

Bit 0

-

Reset Value

0000 0000b

DIGPOT2

ISRCCAL1

ISRCCAL2

S1RELL

S1RELH

S1CON*

S1BUF

CCL1

CCH1

CCL2

CCH2

CCL3

CCH3

T2CON*

CCEN

CRCL

CRCH

TL2

TH2

Reserved

MPAGE

PSW*

BCh PGACAL0 ISRCCAL1_6ISRCCAL1_5ISRCCAL1_4ISRCCAL1_3ISRCCAL1_2ISRCCAL1_1ISRCCAL1_0 Cal. Vector

BDh

BEh

BFh

C0h

C1h

C2h

C3h

C4h

C5h

C6h

C7h

C8h

C9h

CAh

CBh

CCh

CDh

CEh

CFh

D0h

D1h

To

-

ISRCCAL2_6ISRCCAL2_5ISRCCAL2_4ISRCCAL2_3ISRCCAL2_2ISRCCAL2_1ISRCCAL2_0 Cal. Vector

-

0000 0000b

S1M

-

reserved

MPCE1

R1EN

-

T1B8

-

R1B8

-

T1I

-

R1I

-

T2PS

COCAH3

T2PSM

COCAL3

T2SIZE

COCAH2

T2RM1

COCAL2

T2RM0

COCAH1

T2CM

COCAL1

T2IN1

COCAH0

T2IN0

COCAL0

-

F0

-

P

0000 0000b

0000 0001b

D1h-D4h =FFh

D5h-D7h = 00h

CY

AC

RS1

RS0

OV

reserved

Reserved

D7

U0BAUD

WDTREL

D8h BAUDSRC

D9h PRES

DAh I2CMASKID I2CRXOVIE I2CRXDAVIE I2CTXEMPIE I2CMANACK

-

0000 0000b

WDTREL_6 WDTREL_5 WDTREL_4 WDTREL_3 WDTREL_2 WDTREL_1 WDTREL_0 0000 0000b

I2CACKMODE

I2CCONFIG

I2CCLKCTRL

I2CCHIPID

I2CIRQSTAT

I2CRXTX

Reserved

I2CMSTOP I2CMASTER 0000 0010b

DBh

DCh

DDh

DEh

DFh

E0h

E1h

E2h

E3h

E4h

E5h

E6h

E7h

E8h

E9h

EAh

-

I2CID_5

I2CNOACK

-

0000 0000b

0100 0010b

I2CID_6

I2CGOTSTOP

I2CID_4

I2CSDA

-

I2CID_3

I2CDATACK I2CIDLE

I2CID_2

I2CID_1

I2CRXOV

-

I2CID_0

I2CWID

I2CRXAV I2CTXEMP 0010 1001b

-

0000 0000b

1110 0000b

0000 0000b

0000 0001b

ACC*

-

SPIRX3TX0

SPIRX2TX1

SPIRX1TX2

SPIRX0TX3

SPICTRL

SPICONFIG

SPISIZE

IEN1*

-

SPICK_2

SPICSLO

SPICK_1

SPICK_0

FSONCS3 SPI LOAD

SPICS_1

SPICS_0

-

SPICKPH SPICKPOL SPIMA_SL

SPIRXOVIE SPIRXAVIE SPITXEMPIE 0000 0000b

0000 0111b

SPIRXOVIE

SPIOV

-

T2EXIE

-

SWDT

-

ADCPCIE

SPITXEMPTO SPISLAVESEL

MACOVIE

I2CIE

SPISEL

SPITEIE

SPIRXAV SPITXEMP

reserved

0000 0000b

00011001b

0000 0000b

SPIIRQSTAT

Reserved

MACCTRL1

EBh LOADPREV PREVMODE OVMODE OVRDVAL ADDSRC_1 ADDSRC_0 MULCMD_1 MULCMD_0 0000 0000b

MACC0

MACC1

MACC2

MACC3

ECh

EDh

EEh

EFh

F0h

-

0000 0000b

B*

MACCTRL2

MACA0

MACA1

MACRES0

MACRES1

MACRES2

MACRES3

USERFLAGS*

MACB0

F1h MACCLR2_2 MACCLR2_1 MACCLR2_0 MACOV32IE

MACOV16 MACOV32

F2h

F3h

F4h

F5h

F6h

F7h

F8h

F9h

FAh

FBh

-

UF7

-

UF6

-

UF5

-

UF4

-

UF3

-

UF2

-

UF1

-

UF0

-

MACB1

MACSHIFTCTRL

SHIFTMODE ALSHSTYLE SHIFTAMPL_5 SHIFTAMPL_4 SHIFTAMPL_3 SHIFTAMPL_2 SHIFTAMPL_1 SHIFTAMPL_0

MACPREV0

MACPREV1

MACPREV2

MACPREV3

* Bit addressable

FCh

FDh

FEh

FFh

-

_________________________________________________________________________________________________

www.ramtron.com page 11 of 80

VMX51C1020

Analog Peripheral Power Enable

Peripheral Activation Control

The analog peripherals, specifically, the op-amp

digital potentiometer, current source and analog

to digital converter, have a shared dedicated

register used for enabling and disabling these

peripherals. By default, these peripherals are

powered down when the device is reset.

Digital Peripheral Power Enable

In order to save power upon reset, many of the

digital peripherals of the VMX51C1020 are not

activated. The peripherals affected by this

feature are:

TABLE 14: (ANALOGPWREN) ANALOG PERIPHERALS POWER ENABLE REGISTER -

SFR 92H

o

Timer 2 / Port1

Watchdog Timer

MULT/ACCU unit

I²C interface

SPI interface

UART0

7

6

5

4

OPAMPEN DIGPOTEN

ISRCSEL

ISRCEN

3

2

1

0

TAEN

ADCEN

PGAEN

BGAPEN

UART1

Differential Transceiver

Bit

Mnemonic

Function

1 = User Op-Amp Enable

0 = User Op-Amp Disable

1 = Digital Potentiometer and

Switch Enable

0 = Digital Potentiometer and

Switch Disable

7

OPAMPEN

Before using any of the above-listed peripherals,

they must first be enabled by setting the

corresponding bit of the DIGPWREN SFR

register to 1.

6

DIGPOTEN

0 = ISRC with 200mV feedback

1 = ISRC with 200mV feedback

1 = ISRC Output Enable

0 = ISRC Output Disable

1 = TA Output Enable

0 = TA Output Disable

1 = ADC Enable

0 = ADC Disable

1 = PGA Enable

0 = PGA Disable

1 = Bandgap Enable

0 = Bandgap Disable

5

4

3

2

1

0

ISRCSEL

ISRCEN

TAEN

The same rule applies when accessing a given

peripheral’s SFR register(s).

peripheral must have been powered on

(enabled) first, otherwise the SFR register

content will be ignored

The targeted

ADCEN

PGAEN

BGAPEN

The following table shows the structure of the

DIGPWREN register.

TABLE 13: (DIGPWREN) DIGITAL PERIPHERALS POWER ENABLE REGISTER - SFR

93H

Note: The SFR registers associated with all

analog peripherals are activated when

one or more analog peripherals are

enabled.

7

6

5

4

T2CLKEN

WDOGEN

MACEN

I2CEN

3

2

1

0

SPIEN

UART1DIFFEN

UART1EN

UART0EN

Bit

Mnemonic

Function

Timer 2 / PWM Enable

0 = Timer 2 CLK stopped

1 = Timer 2 CLK Running

Watchdog Enable

0 = Watchdog Disable

1 = Watchdog Enable

7

6

T2CLKEN

WDOGEN

1 = MULT/ACCU Unit Enable

0 = MULT/ACCU Unit Disable

1= I2C Interface Enable

0 = I2C Interface Disable

This bit is merged with CLK STOP bit

5

4

3

MACEN

I2CEN

SPIEN

1 = SPI interface is Enable

0 = SPI interface is Disable

UART1 Differential mode

2

UART1DIFFEN 0 = Disable

1 = Enable

0 = UART1 Disable

1

0

UART1EN

UART0EN

1 = UART1 Enable

0 = UART0 Disable

1 = UART0 Enable

_________________________________________________________________________________________________

www.ramtron.com page 12 of 80

VMX51C1020

General Purpose I/O

FIGURE 10: TYPICAL I/O VOUT VS. SOURCE CURRENT

5.00

The VMX51C1020 provides 28 general-purpose

I/O pins. The I/Os are shared with digital

peripherals and can be configured individually.

4.90

4.80

4.70

4.60

4.50

At Reset, all the VMX51C1020 I/O ports are

configured as Inputs

The I/O Ports are bi-directional and the CPU can

write or read data through any of these ports.

0.0

2.0

4.0

6.0

8.0

10.0

I/O Port Structure

I/O current source (mA)

The VMX51C1020 I/O port structure is shown in

the following figure.

FIGURE 11: TYPICAL I/O VOUT VS. SINK CURRENT

0.50

FIGURE 9 – I/O PORT STRUCTURE

0.40

0.30

0.20

0.10

0.00

VCC

OE

Driver

I/O

Control

logic

I/O

0.0

2.0

4.0

6.0

8.0

10.0

I/O current sink (mA)

TTL

The maximum recommended driving current of a

single I/O on a given port is 10mA. The

recommended limit when more than one I/O on

a given port is driving current is 5mA on each

I/O. The total current drive of all I/O ports should

be limited to 40mA

Each I/O pin includes pull-up circuitry

(represented by the internal pull-up resistor) and

a pair of internal protection diodes connected to

VCC and ground, providing ESD protection.

The following figure shows typical I/O rise time

when driving a 20pF capacitive load. In this

case, rise time is about 14ns.

The I/O operational configuration is defined in

the I/O control logic block.

FIGURE 12: I/O RISE TIME WITH A 20PF LOAD

I/O Port Drive Capability

Each I/O port pin, when configured as an output

is able to source or sink up to 4mA. The

following graphs show typical I/O output voltage

vs. source and I/O output voltage versus sink

current.

_________________________________________________________________________________________________

www.ramtron.com page 13 of 80

VMX51C1020

The following registers are used to configure

each of the ports as either general-purpose

input, output or alternate peripheral function..

Input Voltage vs. Ext. device sink

The I/Os of the VMIX, when configured as

Inputs, include an internal pull-up resistor made

of a transistor that ensures the level present at

the input is stable when the I/O pin is

unconnected.

For example, when bit 5 of Port 2 is configured

as an output, it will output the SCK signal if the

SPI interface is enabled and working.

The only exception to this rule is the I²C Clock

and data bus signals. In these two cases, the

VMX51C1020 configures the pins automatically

as inputs or outputs.

Due to the presence of the pull-up resistor on

the digital inputs, the external device driving the

I/O must be able to sink enough current to bring

the I/O pin low.

The P0PINCFG register controls the I/O access

to UART1, the Timer 2 input and output, as well

as defines the direction of the P0 when used as

general purpose I/O.

The following figure shows the VMX51C1020

Input port voltage vs. external device sink

current.

TABLE 15: (P0PINCFG) PORT 0 PORT CONFIGURATION REGISTER - SFR 9BH

7

6

5

4

P07IO

P06IO

P05IO

P04IO

FIGURE 13: INPUT PORT VOLTAGE VS. EXT DEVICE SINK CURRENT

3

2

1

0

P0.3/RX1INE

P0.2/TX1OE

P0.1/T2EXINE

P0.0/T2INE

5.0

Bit

7:4

3

Mnemonic

P0xIO

P0.3/RX1INE

Function

Unavailable on VMX51C1020

0: General purpose input or

UART1 RX

1: General purpose output

When using UART1 you must

set this bit to 0.

0: General purpose input

1: General purpose output or

UART1 TX

When using UART1 you must

set this bit to 1.

4.0

3.0

2.0

1.0

0.0

2

1

0

P0.2/TX1OE

P0.1/T2EXINE 0: General purpose input or

Timer 2 EX

1: General purpose output

When using Timer 2EX input

you must set this bit to 0.

0: General purpose input or

Timer 2 IN

0

20

40

60

80

100

120

140

160

180

Ext. device sink current (uA)

P0.0/T2INE

1: General purpose output

I/O Port Configuration Registers

When using Timer

2 input

you must set this bit to 0.

The VMX51C1020’s I/O port operation is

controlled by two sets of four registers which

are:

o

The Port Pin Configuration registers

The Port Access registers

The port pin configuration registers combined

with specific peripheral configuration will define if

a given pin acts as a general purpose I/O or if it

provides alternate peripheral functionality.

Before using a peripheral that is shared with

I/Os, the pin corresponding to the peripheral

output must be configured as an output and the

pins that are shared with the peripheral inputs

must be configured as inputs.

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VMX51C1020

The P1PINCFG register controls the access

from the PWM to the I/O pins as well as defines

the direction of the P1 when the PWM’s are not

used.

The P2PINCFG register controls the I/O access

to SPI interface and defines the direction of the

P2 when used as general purpose I/O

TABLE 17: (P2PINCFG) PORT 2 PORT CONFIGURATION REGISTER - SFR 9DH

7

6

5

4

TABLE 16: (P1PINCFG) PORT 1 PORT CONFIGURATION REGISTER - SFR 9CH

P2.7/SDIEN

P2.6/SDOEN

P2.5/SCKEN

P2.4/SSEN

7

6

5

4

P1.7

P1.6

P1.5

P1.4

3

2

1

0

P2.2/CS1EN

P2.3/CS0EN

P2.1/CS2EN

P2.0CS3EN

3

2

1

0

P1.3/PWM3OE

P1.2/PWM2OE

P1.1/PWM1OE

P1.0/PWM0OE

Bit

Mnemonic

P2.7/SDIEN

Function

0: General purpose input or

SDI

Bit

Mnemonic

P1.7

Function

7

6

5

4

3

2

1

0

7

6

5

4

3

0: General purpose input

1: General purpose output

0: General purpose input

1: General purpose output

0: General purpose input

1: General purpose output

0: General purpose input

1: General purpose output

0: General purpose input

1: General purpose output

or PWM bit 3 output

1: General purpose output

P1.6

P1.5

P1.4

When using SPI you must set

this bit to 0.

0: General purpose input

1: General purpose output or

SDO

P2.6/SDOEN

P2.5/SCKEN

P2.4/SSEN

P1.3/PWM3OE

P1.2/PWM2OE

P1.1/PWM1OE

P1.0/PWM0OE

When using SPI you must set

this bit to 1.

0: General purpose input or

SCK

When using PWM you

must set this bit to 1.

0: General purpose input

1: General purpose output

or PWM bit 2 output

1: General purpose output

2

1

0

When using SPI you must set

this bit to 0.

0: General purpose input or

Slave Select

When using PWM you

must set this bit to 1

0: General purpose input

1: General purpose output

or PWM bit 1 output

1: General purpose output

When using SPI SS you must

set this bit to 0.

0: General purpose input

1: General purpose output or

Chip Select bit 0 output

P2.3/CS0EN

P2.2/CS1EN

P2.1/CS2EN

P2.0/CS3EN

When using PWM you

must set this bit to 1

0: General purpose input

1: General purpose output

or PWM bit 0 output

When using SPI CS0 you

must set this bit to 1.

0: General purpose input

1: General purpose output or

Chip Select bit 1 output

When using PWM you

must set this bit to 1

When using SPI CS1 you

must set this bit to 1.

0: General purpose input

1: General purpose output or

Chip Select bit 2 output

When using SPI CS2 you

must set this bit to 1.

0: General purpose input

1: General purpose output or

Chip Select bit 3 output

When using SPI CS3 you

must set this bit to 1.

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VMX51C1020

Using General Purpose I/O Ports

The P3PINCFG register controls I/O access to

UART0, the I2C interface, capture compare

input0 and 1, Timer 0 and Timer 1 inputs as well

as defines the direction of P3 when used as

general purpose I/O

The VMX51C1020’s 28 I/Os are grouped into

four ports. For each port an SFR register

location is defined. Those registers are bit

addressable providing the ability to control the

I/O lines individually.

TABLE 18: (P3PINCFG) PORT 3 PORT CONFIGURATION REGISTER - SFR 9EH

7

6

5

4

When the port pin configuration register value

defines the pin as an output, the value written

into the port register will be reflected at the pin

level.

P3.5/T1INE

N

P3.4/CCU1E

N

P3.7/MSCLEN

P3.6/MSDAEN

3

2

1

0

P3.3/CCU0EN

P3.2/T0INEN

P3.1/RX0EN

P3.0/TX0EN

Reading the I/O pin configured as input is done

by reading the contents of its associated port

register.

Bit

7

Mnemonic

Function

0: General purpose input

1: General purpose output or

Master I2C SCL output

P3.7/MSCLEN

P3.6/MSDAEN

P3.5/T1INEN

TABLE 19:

PORT 0 - SFR 80H

When using the I2C you must

set this bit to 1.

0: General purpose input

1: General purpose output or

Master I2C SDA

7

6

5

4

3

2

1

0

P0 [7:0]

6

5

4

PORT 1 - SFR 90H

7

6

5

4

3

2

1

0

P1 [7:0]

PORT 2 - SFR A0H

When using the I2C you must

set this bit to 1.

0: General purpose input or

Timer1 Input

7

6

4

3

P2 [7:0]

PORT 3 - SFR B0H

7

6

4

3

1: General purpose output

P3 [7:0]

When using Timer 1 you must

set this bit to 0.

0: General purpose input or

CCU1 Input

Bit

7-0

Mnemonic

P0, 1, 2, 3

Function

When the Port is configured as an

output, setting a port pin to 1 will

make the corresponding pin to

output logic high.

1: General purpose output

P3.4/CCU1EN

P3.3/CCU0EN

When set to 0, the corresponding

pin will set a logic low.

When using the Compare and

Capture unit you must set this

bit to 0.

0: General purpose input or

CCU0 Input

I/O usage example

3

The following example demonstrates the configuration of the VMX51C1020 I/Os.

//---------------------------------------------------------------------------

1: General purpose output

//This example continuously reads the P0 and writes its contents into //P1 and it

toggle P2 and P3.

//---------------------------------------------------------------------------

When using the Compare and

Capture unit you must set this

bit to 0.

#pragma TINY

#pragma UNSIGNEDCHAR

2

1

0

0: General purpose input or

Timer 0 Input

1: General purpose output

#include <VMIXReg.h>

at 0x0000 void main (void)

{

DIGPWREN = 0x80;

P3.2/T0INEN

P3.1/RX0EN

P3.0/TX0EN

// Enable Timer 2 to activate P1

//Output

// Configure all P0 as Input

//Configure P1 as Output

//Configure P2 as Output

//Configure P3 as Output

When using Timer 0 you must

set this bit to 0.

0: General purpose input or

UART0 Rx

P1PINCFG = 0x00;

P1PINCFG = 0xFF;

P2PINCFG = 0xFF;

P3PINCFG = 0xFF;

1: General purpose output

while(1)

{

P1 = P0;

P2 = ~P2;

P3 = ~P3;

When using UART0 you must

set this bit to 0.

0: General purpose input

1: General purpose output or

UART0 Tx

//Write P0 into P1

//Toggle P2 & P3

}

}//end of main() function

Using Port1.0-3 as General Purpose

Output

When using UART0 you must

set this bit to 1.

Port1.0-P1.3 can be used as standard digital

outputs. However, in order to do this, the Timer

2 clock must be enabled by setting the

_________________________________________________________________________________________________

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page 16 of 80

VMX51C1020

T2CLKEN bit of the DIGPWREN register. In

addition, the Timer 2 CCEN register must also

have the reset value.

Interrupt on Port1 Change Feature

The VMX51C1020 includes an Interrupt on

Port1 change feature. This feature can be used

to monitor the activity on each I/O Port1 pin

(individually) and trigger an interrupt when the

state of the pin on which this feature has been

activated changes. This is equivalent to having

eight individual external interrupt inputs. The

Interrupt on Port1 change shares the interrupt

vector of the ADC peripheral at address 006Bh.

See the Interrupt section for more details on how

to use this feature.

_________________________________________________________________________________________________

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page 17 of 80

VMX51C1020

MULT/ACCU Control Registers

MULT/ACCU - Multiply

Accumulator Unit

With the exception of the Barrel Shifter, the

MULT/ACCU unit operation is controlled by two

SFR registers:

The VMX51C1020 includes a hardware based

multiply-accumulator unit which provides the

user the ability to perform fast and complex

arithmetic operations.

o

The MACCTRL1

The MACCTRL2

The following two tables describe the details of

these control registers.

MULT/ACCU Features:

o

Hardware Calculation Engine

Calculation result is ready as soon as

the input registers are loaded

Signed mathematical calculations

Unsigned MATH operations are possible

if the MUL engine operands are limited

to 15-bits in size

TABLE 20: (MACCTRL1) MULT/ACCU UNIT CONTROL REGISTER - SFR EBH

7

6

5

4

LOADPREV PREVMODE

OVMODE

OVRDVAL

o

3

2

1

0

ADDSRC [1:0]

MULCMD [1:0]

o

Auto/Manual reload of MAC_RES

Enhanced VMX51C1020 MULT/ACCU

Unit

Easy implementation of complex MATH

operations

Bit

7

Mnemonic

LOADPREV

Function

MACPREV manual Load control

1 = Manual load of the

MACPREV register content if

PREVMODE = 1

o

6

5

PREVMODE

OVMODE

Loading method of MACPREV

register

o

16-bit and 32-bit Overflow Flag

32-bit Overflow can raise an interrupt

MULT/ACCU operand registers can be

cleared individually or all together

Overflow flags can be configured to stay

active until manually cleared

Can store and use results from previous

operations

0 = Automatic load when

MACA0 is written.

1 = Manual Load when 1 is

written into LOADPREV

0 = Once set by math operation,

the OV16 and OV32 flag will

remain set until the overflow

condition is removed.

1= Once set by math operation,

the OV16 and OV32 flag will

stay set until it is cleared

manually.

o

The MULT/ACCU can be configured to perform

the following operations:

FIGURE 13: VMX51C1020 MULT/ACCU OPERATION

4

OVRDVAL

0 = The value on MACRES is

the calculation result.

1 = the value on MACRES is the

32LSB of the MACRES when

the OV32 overflow occurred

32-bit Addition source

B Input

(MACA, MACB) + MACC = MAC_RESULT

(MACA x MACB) + MACC = MAC_RESULT

ADD32 + ADD32

(MACA x MACB) + 0

(MACA x MACB) + MAC_PREV

= MAC_RESULT

3:2

ADDSRC[1:0]

MULT16 + ADD32

(MACA x MACA) + MACC = MAC_RESULT

(MACA x MACA) + 0

= MAC_RESULT

00 = 0 (No Add)

(MACA x MACA) + MAC_PREV

= MAC_RESULT

01 = C (std 32-bit reg)

10 = RES –1

11 = C (std 32-bit reg)

A Input

(MACA x MAC_PREV(16lsb) + MACC

(MACA x MAC_PREV(16lsb) + 0

= MAC_RESULT

(MACA x MAC_PREV(16lsb) + MAC_PREV = MAC_RESULT

00=Multiplication

01=Multiplication

Where MACA (multiplier), MACB (multiplicand),

MACACC (accumulator) and MACRESULT

(result) are 16, 16, 32 and 32 bits, respectively.

10=Multiplication

11= Concatenation of {A, B} for

32-bit addition

Multiplication Command

00 = MACA x MACB

01 = MACA x MACA

10 = MACA x MACPREV (16 LSB)

11 = MACA x MACB

1:0

MULCMD[1:0]

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VMX51C1020

TABLE 21: (MACCTRL2) MULT/ACCU UNIT CONTROL REGISTER 2 -SFR F1H

TABLE 22: (MACA0) MULT/ACCU UNIT A OPERAND, LOW BYTE - SFR F2H

7

6

5

4

3

2

1

0

7

6

5

4

MACA0 [7:0]

MACCLR2 [2:0]

MACOV32IE

Bit

7:0

Mnemonic

MACA0

Function

Lower segment of the MACA

operand

3

-

2

-

1

0

MACOV16

MACOV32

TABLE 23: (MACA1) MULT/ACCU UNIT A OPERAND, HIGH BYTE - SFR F3H

Bit

7:5

Mnemonic

MACCLR[2:0]

Function

MULT/ACCU Register Clear

000 = No Clear

7

6

5

4

3

2

1

0

MACA1 [15:8]

001 = Clear MACA

010 = Clear MACB

011 = Clear MACC

100 = Clear MACPREV

101 = Clear All MAC regs +

Overflow Flags

110 = Clear Overflow Flags only

MULT/ACCU 32-bit Overflow

IRQ Enable

Bit

15:8

Mnemonic

MACA1

Function

Upper segment of the MACA

operand

TABLE 24: (MACB0) MULT/ACCU UNIT B OPERAND, LOW BYTE - SFR F9H

7

6

5

4

3

2

1

0

MACB0 [7:0]

4

MACOV32IE

Bit

7:0

Mnemonic

MACB0

Function

Lower segment of the MACB

operand

3

2

1

-

MACOV16

16-bit Overflow Flag

0 = No 16 overflow

1 = 16-bit MULT/ACCU

Overflow occurred

32-bit Overflow Flag

1 = 32-bit MULT/ACCU

Overflow

TABLE 25: (MACB1) MULT/ACCU UNIT B OPERAND, HIGH BYTE - SFR FAH

7

6

5

4

3

2

1

MACB1 [7:0]

0

MACOV32

Bit

7:0

Mnemonic

Function

Upper segment of the MACB

operand

MACB1

This automatically loads the

MAC32OV register.

The MACOV32 can generate a

MULT/ACCU interrupt when

enabled.

MACC Input Register

The MACC register is a 32-bit register used to

perform 32-bit addition.

MULT/ACCU Unit Data Registers

It’s possible to substitute the MACPREV

Register for the MACC register or 0 in the 32-bit

addition.

The MULT/ACCU Data registers include

operand and result registers that serve to store

the numbers being manipulated in mathematical

operations. Some of these registers are uniquely

for addition (such as MACC) while others can be

used for all operations. The MULT/ACCU

operation registers are represented below.

TABLE 26: (MACC0) MULT/ACCU UNIT C OPERAND, LOW BYTE - SFR ECH

7

6

5

4

3

2

1

0

MACC0 [7:0]

Bit

7:0

Mnemonic

Function

Lower segment of the 32-bit addition

register

MACC0

MACA and MACB Multiplication

(Addition) Input Registers

TABLE 27: (MACC1) MULT/ACCU UNIT C OPERAND, BYTE 1 - SFR EDH

7

6

5

4

3

2

1

0

MACC1 [15:8]

The MACA and MACB register serve as 16-bit

input operands when performing multiplication.

Bit

15:8

Mnemonic

Function

Lower middle segment of the 32-bit

addition register

MACC1

When the MULT/ACCU is configured to perform

32-bit addition, the MACA and the MACB

registers are concatenated to represent a 32-bit

word. In that case the MACA register contains

the upper 16-bit of the 32-bit operand and the

MACB contains the lower 16-bit

TABLE 28: (MACC2) MULT/ACCU UNIT C OPERAND, BYTE 2 - SFR EEH

7

6

5

4

3

2

1

0

MACC2 [23:16]

Bit

23:16

Mnemonic

MACC2

Function

Upper middle segment of the 32-bit

addition register

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VMX51C1020

TABLE 29: (MACC3) MULT/ACCU UNIT C OPERAND, HIGH BYTE - SFR EFH

As mentioned previously, there are two ways to

load the MACPREV register controlled by the

PREVMODE bit value:

7

6

5

4

3

2

1

0

MACC3 [31:24]

Bit

31:24

Mnemonic

MACC3

Function

Upper segment of the 32-bit addition

register

PREVMODE = 0:

Auto MACPREV load, by writing into the MACA0

register. Selected when PREVMODE = 0.

MACRES Result Register

The MACRES register, which is 32-bits wide,

contains the result of the MULT/ACCU

operation. In fact, the MACRES register is the

output of the Barrel Shifter.

PREVMODE = 1:

Manual load of MACPREV when the

LOADPREV bit is set to 1

TABLE 30: (MACRES0) MULT/ACCU UNIT RESULT, LOW BYTE - SFR F4H

A good example using the auto loading of the

MACPREV feature is the implementation of a

FIR Filter. In that specific case, it is possible to

save a total of 8 MOV operations per tap

calculation.

7

6

5

4

3

2

1

0

MACRES0 [7:0]

Bit

7:0

Mnemonic

MACRES0

Function

Lower segment of the 32-bit

MULT/ACCU result register

TABLE 31: (MACRES1) MULT/ACCU UNIT RESULT, BYTE 1 - SFR F5H

7

6

5

4

3

2

1

0

TABLE 34: (MACPREV0) MULT/ACCU UNIT PREVIOUS OPERATION RESULT, LOW

BYTE - SFR FCH

MACRES1 [15:8]

7

6

5

4

3

2

1

0

MACPREV0 [7:0]

Bit

15:8

Mnemonic

MACRES1

Function

Lower middle segment of the 32-bit

MULT/ACCU result register

Bit

7:0

Mnemonic

MACPREV0

Function

Lower segment of 32-bit

MULT/ACCU previous result register

TABLE 32: (MACRES2) MULT/ACCU UNIT RESULT, BYTE 2 - SFR F6H

7

6

5

4

3

2

1

0

MACRES2 [23:16]

TABLE 35: (MACPREV1) MULT/ACCU UNIT PREVIOUS OPERATION RESULT, BYTE

1 - SFR FDH

7

6

5

4

3

2

1

0

Bit

23:16

Mnemonic

MACRES2

Function

MACPREV1 [7:0]

Upper middle segment of the 32-bit

MULT/ACCU result register

Bit

15:8

Mnemonic

MACPREV1

Function

Lower middle segment of 32-bit

MULT/ACCU previous result register

TABLE 33: (MACRES3) MULT/ACCU UNIT RESULT, HIGH BYTE - SFR F7H

7

6

5

4

3

2

1

0

MACRES3 [31:24]

TABLE 36: (MACPREV2) MULT/ACCU UNIT PREVIOUS OPERATION RESULT, BYTE

2 - SFR FEH

Bit

31:24

Mnemonic

MACRES3

Function

Upper segment of the 32-bit

MULT/ACCU result register

7

6

5

4

3

2

1

0

MACPREV2 [15:8]

Bit

23:16

Mnemonic

MACPREV2

Function

MACPREV Register

Upper middle segment of 32-bit

MULT/ACCU previous result register

The MACPREV register provides the ability to

automatically or manually save the contents of

the MACRES register and re-inject it into the

calculation. This feature is especially useful in

TABLE 37: (MACPREV3) MULT/ACCU UNIT PREVIOUS OPERATION RESULT, HIGH

BYTE - SFR FFH

7

6

5

4

3

2

1

0

MACPREV3 [7:0]

applications where the result of

operation serves as one of the operands of the

next one.

a given

Bit

31:24

Mnemonic

MACPREV3

Function

Upper segment of 32-bit

MULT/ACCU previous result register

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VMX51C1020

FIGURE 14: VMX51C1020 MULT/ACCU FUNCTIONAL DIAGRAM

addsrc

SFR registers

Concatenation (A,B)

ov32

SFR registers

shiftmode

B

ADD

MSB

ov16a

MACA1 (MSB)

A

MACA

MACRES3 (MSB)

MACRES2

MACRES

(SFR regs)

MACRES

ov16b

MUL

SHIFT

MACB

MACA0 (LSB)

(Signed)

B

ADD

LSB

A

MACB1 (MSB)

ovrdval

mulcmd

MACRES1

MACC

prevmode

0

MACB0 (LSB)

Maca0 load

loadprev

MACRES0 (LSB)

addsrc

MACC3 (MSB)

MAC32OV3 (MSB)

MAC32OV2

(16 LSB)

MACPREV

MAC32OV

(stored)

MACC2

load

1

ovmode

MACC1

1

rst

MAC32OV1

ov32F

ov32

rst

MACC0 (LSB)

OVCLR

ov32F / IRQ

MAC32OV0 (LSB)

ov32

ovmode

1

rst

Ov16a+b

MAC Control SFR

ov16F

MACCTRL1

MACCTRL2

MACSHIFTCTRL

The above block diagram shows the interaction

between the registers and the other components

that comprise the MULT/ACCU unit on the

VMX51C1020.

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VMX51C1020

// MULT/ACCU example use

MULT/ACCU Barrel Shifter

MACA0 = 0xFF;

MACA1 = 0x7F;

MACB0 = 0xFF;

MACB1 = 0xFF;

MACC0 = 0xFF;

MACC1 = 0xFF;

MACC2 = 0xFF;

MACC3 = 0x7F;

The MULT/ACCU includes a 32-bit Barrel Shifter

at the output of the 32-bit addition unit. The

Barrel Shifter can perform right/left shift

operations in one cycle, which is useful for

scaling the output result of the MULT/ACCU.

The shift range is adjustable from 0 to 16 in both

directions. The “shifted” addition unit output can

be routed to the:

//--- as soon as the MAC input registers are loaded the result is available in the

MACRESx registers.

}//end of main

o

MACRES

MACPREV

MACOV32

//---------------------------------------------------------------------------------

// MAC 32 bit overflow Interrupt Function

void int_5_mac (void) interrupt 12

{

The barrel shifter can perform both arithmetic

and logical shifts: The shift left operation can be

configured as an arithmetic or logical shift. In

the later, the sign bit is discarded.

IEN0 &= 0x7F;

// Disable all interrupts

//Put MAC 32 bit Overflow Interrupt code here.*/

//Note that when a 32bit overflow occurs, the 32 least significant bit of the current

//result are stored into the MAC32OVx registers and can be read at the location

of MACRESx by setting to 1 the OVRDVAL bit of the MACCTRL register

TABLE 38: (MACSHIFTCTRL) MULT/ACCU UNIT BARREL SHIFTER CONTROL

REGISTER - SFR FBH

IRCON &= 0xEF;

IEN0 |= 0x80;

}

// Clear flag (IEX5)

// Enable all interrupts

7

6

5

4

3

2

1

0

SHIFTMODE

ALSHSTYLE

SHIFTAMPL [5:0]

//--------------------------------------------------------------------------------

Bit

7

Mnemonic

SHIFTMODE

Function

0 = Logical SHIFT

1 = Arithmetic SHIFT

Arithmetic Shift Left Style

0= Arithmetic Left Shift: Logical Left

1= Arithmetic Left Shift: Keep sign bit

Shift Amplitude 0 to 16 (5 bits to

provide 16 bits shift range)

Neg. Number = Shift Right

(2 complements)

MULT/ACCU Application Example:

FIR Filter Function

6

ALSHSTYLE

The following ASM code shows the

implementation of a FIR filter computation

function for one iteration, the data shifting

operation and the definition of the FIR filter

coefficient table. The FIR computation is simple

to implement, however, it is quite demanding in

terms of processing power. For each new data

point, the multiplication with associated

5:0

SHIFTAMPL[5:0]

Pos. Number = Shift Left

MULT/ACCU Unit Setup and OV32

Interrupt Example

coefficients

+ addition operation must be

In order to use the MULT/ACCU unit, the user

must first set up and configure the module. The

following provides setup code examples. The

first part of the code is the interrupt setup and

module configuration, whereas the second part

is the interrupt function itself.

performed N times (N=number of filter tapps).

Due to being hardware based and including

features such as automatic reload of the result

of the previous operation, the VMX51C1020

MULT/ACCU unit is very efficient for performing

operations such as FIR filter computation.

Sample C code for MULT/ACCU Unit interrupt

setup and module configuration:

In the code example below, the COMPUTEFIR

loop forms the heart of the FIR computation and

it is clear that use of the MULT/ACCU unit

implies very few instructions being required for

mathematical operations. The net result is a

dramatic performance improvement when

compared with manual calculations done solely

via the standard 8051 instruction set.

//---------------------------------------------------------------------------

// Sample C code to setup the MULT/ACCU unit

//---------------------------------------------------------------------------

//--- Program initialisation omitted…

(…)

void main(void){

// MULT/ACCU setup

IEN0 |= 0x80;

IEN1 |= 0x10;

DIGPWREN |= 0x20;

MACCTRL1 = 0x0C;

MACCTRL2 = 0x10;

// Enable all interrupts

// Enable MULT/ACCU interrupt

// Enable MULT/ACCU unit

// {A,B}+C

// Enable INT overflow_32

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www.ramtron.com page 22 of 80

VMX51C1020

VMX51C1020 FIR Filter Example

MOV

DATAH,MACRES3

DATAL,MACRES2

The example below shows how to use the

MULT/ACCU unit of the VMX51C1020 to

LCALL

MOV

RET

SENDLTC1452

P3,#00

perform FIR filter computing.

In order to

;----------------------------------------------------

;* FIR Filter Coefficients Table

;----------------------------------------------------

minimize the example size, only the FIR

computing function and the coefficient table are

presented.

*

;FSAMPLE 480HZ, N=16, LOW PASS 0.1HZ -78DB @ 60HZ

COEFTABLE:

DW

023DH

049DH

086AH

0D2DH

1263H

1752H

1B30H

1D51H

1B30H

1752H

1263H

0D2DH

086AH

049DH

023DH

DW

;----------------------------------------------------//

;** FIR Filter Computing Function

//

;---------------------------------------------------//

FIRCOMPUTE: MOV R0,#NPOINTSBASEADRS

;INPUT ADC RAW DATA

;AT Xn LOCATIONS...

;Saving acquired data from calling function into RAM for computation

MOV

INC

VARH,DATAH

VARL,DATAL

@R0,VARH

R0

;(MSB)

;(LSB)

MOV

@R0,VARFL

DW

0FFFFH

;END OF TABLE

;** Prepare to compute Yn...

;***Define Base ADRS of input values

MOV

R0,#NPOINTSBASEADRS

;***Define Base Address of coefficients

MOV

R1,#COEFBASEADRS

R7,#NPOINTS

;DEFINE COUNTER

;***Configure the MULT/ACCU unit as Follow:

MOV

MACCTRL,#00001000B

;BIT7 LOADPREV = 0

;BIT6 PREVMODE = 0

;

No manual Previous result

Automatic Previous result save when

MULT/ACCUA0 is loaded

;BIT5 OVMODE = 0

;

Overflow flag remains ON until overflow

condition exist

;BIT4 OVRDVAL = 0

;

The value of MACRES is the calculation

result

;BIT3:2 ADDSRC = 10

;BIT1:0 MULCMD = 00

MACPREV is the Addition Source

Mul Operation = MACAxMACB

;**Clear the MULT/ACCU registers content

MOV

MACCTRL2,#0A0H

;** COMPUTE Yn...

COMPUTEFIR: MOVMACB1,@R1

;Put a given Coefficient into

;MULT/ACCUB

INC

R1

MOV

MACB0,@R1

INC

R1

MOV

INC

MACA1,@R0 ; Put a given Xn Input into

R0

MOV

MACA0,@R0

;This last instruction load the MACPREV register for next Operation

INC

R0

DJNZ

R7,COMPUTEFIR ;Do the Computation for N taps

;*** Second part

;-------------------------------------------------------------------------------------------------------//

;** SHIFT PREVIOUS INPUT VALUES TO LET PLACE FOR NEXT ONE...

;-------------------------------------------------------------------------------------------------------//

SHIFTPAST:

MOV

R7,#(NPOINTS-1)*2

;Define # of datashift

;To perform (N-1)*2

;***COMPUTE FIRST FETCH ADDRESS

MOV R0,#(NPOINTSBASEADRS - 1 + 2*(NPOINTS-1))

;***COMPUTE FIRST DESTINATION ADDRESS

MOV

R1,#(NPOINTSBASEADRS + 1 + 2*(NPOINTS-1))

SHIFTLOOP: MOV

A,@R0

@R1,A

R0

;Shift Given LSB input...

;To next location

;Prepare pointer for moving LSB

MOV

DEC

DJNZ

R1

R7,SHIFTLOOP

;** PERFORM TRANSFORMATION OF Yn HERE AND PUT INTO BINH, BINL

;** IN THIS CASE THE COEFFICIENTS HAVE BEEN MULTIPLIED BY 65536

;** SO THE RESULT IS ON 32-BITS

;** DIVISING YN BY 65536 MEAN ONLY TAKING THE UPPER 16-BITS

_________________________________________________________________________________________________

www.ramtron.com page 23 of 80

VMX51C1020

TABLE 39: (TL0) TIMER 0 LOW BYTE - SFR 8AH

VMX51C1020 Timers

7

6

5

4

3

2

1

0

TL0 [7:0]

The VMX51C1020 includes 3 general-purpose

timer/counters

TABLE 40: (TH0) TIMER 0 HIGH BYTE - SFR 8CH

7

6

5

4

3

TH0 [7:0]

o

Timer0

Timer1

Timer2

TABLE 41: (TL1) TIMER 1 LOW BYTE - SFR 8BH

7

6

5

4

3

TL1 [7:0]

TABLE 42: (TH1) TIMER 1 HIGH BYTE - SFR 8DH

7

6

5

4

3

Timer0 and Timer1 are general purpose timers

that can operate as a timer with a clock rate

based on the system clock, or as an event

counter that monitosr events occurring on an

external timer input pin (T0IN for Timer 0 and

T1IN for Timer 1).

TH1 [7:0]

With the exception of their associated interrupts,

the configuration and control of Timer0 and

Timer1 is performed via the TMOD and TCON

SFR registers.

Timers 0 and Timer 1 are similar to the standard

8051 timers.

The following table shows the TCON special

function register of the VMX51C1020. This

register contains the Timer 0/1 overflow flags,

Timer 0/1 run control bits, interrupt 0/1 edge

flags, and the interrupt 0/1 interrupt type control

Apart from also being capabile of operating as a

timer based on a system clock or as an event

counter, Timer2 is also the heart of the PWM

counter outputs and the Compare and Capture

Units.

bits.

TABLE 43: (TCON) TIMER 0, TIMER 1 TIMER/COUNTER CONTROL - SFR 88H

7

TF1

6

TR1

5

TF0

4

TR0

Each of the VMX51C1020’s timers has a

dedicated interrupt vector which can be

triggered when the Timers overflow.

3

IE1

2

1

0

IT0

IT1

IE0

Bit

7

Mnemonic

TF1

Function

Timer 1 overflow flag.

Set by hardware when Timer 1 overflows.

It is automatically cleared when the

Timer 1 interrupt is serviced.

Timer 0 and Timer 1

This flag can also be cleared by software.

Timer 1 Run control bit.

TR1 = 0, Stop Timer 1

TR1 = 1, Start Timer 1

Timer 0 overflow flag.

Set by hardware when Timer 0 overflows.

It is automatically cleared when the

Timer 0 interrupt is serviced.

This flag can also be cleared by software.

Timer 0 Run control bit.

TR0 = 0, Stop Timer 0

TR0 = 1, Start Timer 0

Interrupt 1 edge flag.

This flag is set by hardware when falling

edge on external INT1 is observed.

It is cleared when interrupt is processed.

INT1 interrupt event type control bit.

The VMX51C1020’s Timer0 and Timer1 are very

similar in their structure and operation. The

main difference being that Timer1 serves as a

baud rate generator for UART0 and it shares

some of its resources when Timer0 is used in

mode 3.

6

5

TR1

TF0

4

3

TR0

IE1

Timer0 and Timer1 each consist of a 16-bit

register for which the content is accessible as

two independent SFR registers: TLx and THx.

2

IT1

IT1 = 0,

interrupt will be caused by

a Low Level on INT1

IT1 = 1,

Interrupt will be caused by a

High to Low transition on INT1.

1

0

IE0

IT0

INT0 edge flag configuration

Set by hardware when falling edge on

external pin INT0 is observed.

It is cleared when interrupt is processed.

INT0 interrupt event type control bit.

IT0 = 0,

IT0 = 1,

interrupt will be caused by

a Low Level on INT0

Interrupt will be caused by a

High to Low transition on INT0.

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VMX51C1020

The TMOD register is mainly used to set the

operating mode of the timers and it allows the

user to enable the external gate control as well

as select timer or counter operation.

Low transitions on the TxIN pin of the

VMX51C1020 increments the timer value.

Note that when Timer0 and Timer1 operate in

Timer mode, they use the System Clock as their

source. Therefore configuring the CLKDIVCTRL

register will affect the Timer’s operation.

TABLE 44: (TMOD) TIMER MODE CONTROL - SFR 89H

7

6

CT1

5

M11

4

M01

GATE1

3

2

CT0

1

M10

0

M00

GATE0

Timer0 & Timer1 Gate Control

Bit

7

Mnemonic

GATE1

Function

GATE1 = 0,

The level present on the INT1 pin has

no effect on Timer1 operation.

The Gate control makes it possible for an

external device to control Timer0 and Timer1

operation through the interrupt (INTx) pins.

GATE1 = 1,

The level of INT1 pin serves as a Gate

control on to Timer/Counter operation

provided the TR1 bit is set. Applying a

Low Level on the INT1 pin makes the

Timer stop.

Selects TIMER1 Operation.

CT1 = 0, Sets the Timer 1 as a Timer

which value is incremented

by SYSCLK events.

When the GATEx and TRx bits of the TMOD

register are set to 1:

o

INTx = Logic LOW, The Timer x Stops

INTx = Logic High, The Timer x Runs

CT1

When the Gate bit equals 0, then the logic level

present at the INTx pin have no effect on the

Timer Operation.

CT1 = 1, The Timer 1 operates as a

counter which counts the

High to Low transition on

that occurs on the T1IN

input.

5

4

3

M11

M01

GATE0

Selects mode for Timer/Counter 1, as

shown in the Table below.

FIGURE 15: TIMER 0, TIMER 1 CTX & GATE CONTROL

GATE0 = 0,

SYSCLK

÷12

The level present on the INT0 pin has

no effect on Timer1 operation.

0

1

CTx=0

CTx=1

CLK

GATE0 = 1,

The level of INT0 pin serves as a Gate

control on to Timer/Counter operation

provided the TR0 bit is set. Applying a

Low Level on the INT0 pin makes the

Timer stop.

TxIN

TRx

2

CT0

Selects Timer 0 Operation.

CT1 = 0, Sets the Timer 0 as a Timer

which value is incremented

by SYSCLK events.

GATEx

INTx

CT1 = 1, The Timer 0 operates as a

counter which counts the

High to Low transition on

that occurs on the T1IN

input.

1

0

M10

M00

Selects mode for Timer/Counter 0, as

shown in the Table below.

Timer0/Timer1/Counter Operation

The CT0 and CT1 bits of the TMOD register

control the Clock source for Timer0 and Timer1,

respectively. When the CT bit is set to 0 (Timer

mode) the Timer is sourced from the system

clock divided by 12.

Setting the CTx bit to 1 sets the Timer to operate

in event counter mode. In this mode, High to

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VMX51C1020

Timer0, Timer1 Operation Modes

Timer 0, Timer 1: Mode 0 - Overflow Rate (Hz)

CTx = 0

The operating mode of Timer0 and Timer1 is

determined by the M1x and M0x bits in the

TMOD register. The following summarizes the

four modes of operation for Timers0 and 1.

Timer overflow rate (Hz) =

f_SYSCLK_________

12 x [8192-(THx, TLx)]

CTx = 1

TABLE 45: TIMER/COUNTER MODE DESCRIPTION SUMMARY

Timer overflow rate (Hz) =

f_TxIN_________

[8192-(THx,TLx)]

M1 M0

Mode

Function

0

Mode 0

13-bit Timer / Counter, with 5

lower bits in TL0 or TL1 register

and bits in TH0 or TH1 register

Mode 1 (16-bit)

(for timer

0

and timer 1,

respectively). The 3 high order

bits of TL0 and TL1 are held at

0.

Mode 1 operation is the same for Timer0 and

Timer1. In Mode 1, the timer is configured as a

16-bit counter. Other than rollover at FFFFh,

Mode 1 operation is the same as Mode 0.

0

1

0

Mode 1

Mode 2

16-bit Timer / Counter

8-bit auto reload Timer /

Counter. The reload value is

kept in TH0 or TH1, while TL0

or TL1 is incremented every

machine cycle. When TLx

overflows, a value from THx is

copied to TLx.

If Timer 1 M1 and M0 bits are

set to 1, Timer 1 stops. If Timer

0 M1 and M0 bits are set to 1,

FIGURE 16 : TIMER 0 MODE 0 & MODE 1

SYSCLK

÷12

TH0

4

1

Mode 3

0

1

CT0=0

CT0=1

0

7

CLK

Mode = 0

P3.2-T0IN

Timer

0

acts

as

two

/

Mode = 1

independent 8-bit Timers

Counters.

TR0

TL0

GATE0

0

7

Mode 0, 13-bit Timer/Counter

INT0

TF0

INT

Mode 0 operation is the same for Timer0 and

Timer1.

FIGURE 17: TIMER 1 MODE 0 & MODE 1

SYSCLK

÷12

In Mode 0, the timer is configured as a 13-bit

counter that uses bits 0-4 of the TLx register and

all 8-bits of the THx register. The Timer Run bit

(TRx) of the TCON SFR starts the timer. The

value of the CTx bit defines if the Timer will

operate as a Timer (CTx = 0), deriving its source

from the System Clock, or count the High to Low

Transitions (CTx = 1) that occurs on the External

Timer input pin (TxIN). When the 13-bit count

increments from 1FFFh (all ones) to all zeros,

the TF0 (or TF1) bit will be set in the TCON

SFR.

TH1

4

0

1

CT1=0

CT1=1

0

7

CLK

Mode = 0

P3.5-T1IN

Mode = 1

0

TL1

TR1

7

GATE1

INT1

TF1

INT

To UART0

The Timer0 and Timer1 overflow rate in mode 1

can be calculated using the following equations:

Timer 0, Timer 1: Mode 1 - Overflow Rate (Hz)

CTx = 0

The state of the upper 3-bits of the TLx register

is indeterminate in Mode 0 and must be masked

when the software evaluates the register’s

contents.

Timer overflow rate (Hz) =

CTx = 1

f_SYSCLK_________

12 x [65536-(THx, TLx)]

Timer overflow rate (Hz) =

f_TxIN_________

[65536-(THx, TLx)]

Mode 2 (8-bit)

The operation of Mode2 is the same for Timer0

and Timer1. In Mode 2, the timer is configured

_________________________________________________________________________________________________

www.ramtron.com

page 26 of 80

VMX51C1020

as an 8-bit counter, with automatic reload of the

start value. The LSB of the Timer register, TLx,

is the counter itself and the MSB portion of the

Timer, THx, stores the timer reload value.

Using Timer1 in mode 2 is recommended as the

best approach when using Timer1 as the

UART0 baud rate generator.

Mode 3 (2 x 8-bit)

Mode 2’s counter control is the same as for

Mode 0 and Mode 1. However, in Mode 2, when

TLx rolls over from FFh, the value stored in THx

is reloaded into TLx.

In Mode 3, Timer0 operates as two 8-bit

counters and Timer1 stops counting and holds

its value.

FIGURE 20: TIMER0, TIMER 1 STRUCTURE IN MODE 3

FIGURE 18 : TIMER 0 MODE 2

TH0

0

7

CLK

SYSCLK

÷12

TL0

0

1

CT0 = 0

CT0 = 1

0

7

TR1

TF1

INT

P3.2 - T0IN

To UART0

SYSCLK

÷12

0

7

CT0 = 0

CT0 = 1

0

1

TH0

TF0

TL0

0

7

CLK

TR0

P3.2-T0IN

GATE0

INT

INT0

TR0

GATE0

INT0

TF0

INT

The Timer0 overflow rate in Mode 3 can be

calculated by using following equations:

FIGURE 19: TIMER 1 MODE 2

SYSCLK

÷12

Timer 0, Timer 1: Mode 3 - Overflow Rate (Hz)

TH0, CTx = 0 or 1

TL1

0

1

CT1 = 0

CT1 = 1

0

7

P3.5 - T1IN

Timer overflow rate (Hz) =

f_SYSCLK_____

12 x 256

0

7

TH1

TF1

TL0, CTx = 0

TR1

GATE1

INT

Timer overflow rate (Hz) =

f_SYSCLK_____

12 x 256

INT1

To UART0

TL0, CTx = 1

The Timer0 and Timer1 overflow rate in Mode 2

can be calculated using the following equations:

Timer overflow rate (Hz) =

__

f

_TxIN_____

256

Timer 0, Timer 1: Mode 2 - Overflow Rate (Hz)

CTx = 0

In Mode 3, the values present in the TH1 and

TL1 registers, as well as the value of the GATE1

and CT1 control bits, have no impact on the

Timer operation.

Timer overflow rate (Hz) =

f_SYSCLK_________

12 x [256-(THx)]

CTx = 1

Timer0 & Timer1 Interrupts

Timer overflow rate (Hz) =

__ f_TxIN________

[256--(THx)]

Timer0 and Timer1 have a dedicated interrupt

vectors located at:

o

000Bh for the Timer 0

001Bh for the Timer 1

Using Timer1 as Baud Rate generator

The natural priority of Timer0 is higher than that

of Timer1.

_________________________________________________________________________________________________

www.ramtron.com page 27 of 80

VMX51C1020

The following table provides a summary of the

Interrupt control and Flag bits associated with

the Timer0 and Timer1 interrupts.

Setting Up Timer1 Example

The following code provides an example of how

to configure Timer1 (first part of the code is the

interrupt setup and module configuration

whereas the second part is the interrupt

function).

Bit Name

Location

Description

EA

IEN0.7

General interrupt control bit

0, Interrupt Disabled

1, Enabled Interrupt active

Timer 0 Overflow Interrupt

1 = Enable

0 = Disable

Timer 1 Overflow Interrupt

1 = Enable

0 = Disable

TF0 Flag is set when Timer 0

Overflow occurs.

T0IE

T1IE

TF0

IEN0.1

IEN0.3

TCON.5

Example1: Delay function

//-------------------------------------------------------------------------

// Sample C code using the Timer 1: Delay function

//-------------------------------------------------------------------------

VOID DELAY1MS(UNSIGNED CHAR DLAIS) {

IDATA UNSIGNED CHAR X=0;

TMOD = 0X10;

TL1 = 0X33;

TH1 = 0XFB;

;//TIMER1 RELOAD VALUE FOR

Automatically cleared when

Timer 0 interrupt is serviced.

This flag can also be cleared

by software

TCON = 0X40;

WHILE (DLAIS > 0)

{

DO{

TF1

TCON.7

TF1 Flag is set when Timer 1

Overflow occurs.

X=TCON;

X= X&0X80;

}WHILE(X==0);

Automatically cleared when

Timer 1 interrupt is serviced.

This flag can also be cleared

by software

TCON = TCON&0X7F;

TL1 = 0X33;

TH1 = 0XFB;

;//TIMER1 RELOAD VALUE FOR

DLAIS = DLAIS-1;

}

}//END OF DELAY 1MS

Setting Up Timer0 Example

Example 2: Timer1 interrupt example

In order to use Timer0, the first step is to setup

the interrupt and then configure the module and

this is described in the following code example.

//-------------------------------------------------------------------------

// Sample C code using the Timer 1: Interrupt

//-------------------------------------------------------------------------

// (…) PROGRAM INITIALIZATION OMITTED

at 0xo100 void main(void){

Sample C code to set up Timer 0:

//---------------------------------------------------------------------------

// TIMER 1 setup

// Sample C code to setup Timer 0

IEN0 |= 0x80;

IEN0 |= 0x08;

TMOD = 0x20;

TCON = 0x40;

TL1 = 0xFC;

// Enable all interrupts

// Enable interrupt Timer1

// Timer 1 mode 2

// Start Timer 1

//---------------------------------------------------------------------------

// (…) PROGRAM INITIALIZATION OMITTED

AT 0X0100 VOID MAIN(VOID){

// Timer1 offset

// INTERRUPT + TIMER 0 SETUP

do {

IEN0 |= 0X80;

IEN0 |= 0X02;

TMOD = 0X02;

TCON = 0X10;

// ENABLE ALL INTERRUPTS

// ENABLE INTERRUPT TIMER 0

// TIMER 0 MODE 2

}while(1);

//Wait Timer 1 interrupt

}//end of main() function

//----------------------------------------

// Timer 1 Interrupt function

//----------------------------------------

void int_timer_1 (void) interrupt 3

{

// START TIMER 0

DO{}WHILE(1);

//WAIT FOR TIMER 0 INTERRUPT

}//END OF MAIN()

IEN0 &= 0x7F;

// Disable all interrupts

// Enable all interrupts

//---------------------------------------------------------------------------

// INTERRUPT FUNCTION

/* Put Interrupt code here*/

VOID INT_TIMER_0 (VOID) INTERRUPT 1

{

IEN0 |= 0x80;

}

IEN0 &= 0X7F;

/*------------------------*/

// DISABLE ALL INTERRUPTS

/*Put Interrupt code here*/

/*------------------------*/

IEN0 |= 0x80;

}

// Enable all interrupts

//---------------------------------------------------------------------------

_________________________________________________________________________________________________

www.ramtron.com page 28 of 80

VMX51C1020

The T2CON register controls:

Timer2

o

T2 clock source Prescaler

T2 count size (8/16-bits)

T2 reload mode

The VMX51C1020 Timer2 and associated

peripherals include the following capabilities:

T2 Input selection

o

16-Bit Timer

16-Bit Auto-Reload Timer

Compare and Capture units

8 / 16 PWM outputs

TABLE 50: (T2CON) TIMER 2 CONTROL REGISTER -SFR C8H

7

6

5

4

T2PS

T2PSM

T2SIZE

T2RM1

3

2

1

0

T2RM0

T2CM

T2IN1

T2IN0

TABLE 46: (TL2) TIMER 2, LOW BYTE - SFR CCH

7

6

5

4

3

2

1

0

Bit

7

Mnemonic Function

TL2 [7:0]

T2PS

Prescaler select bit:

0 = Timer 2 is clocked with 1/12 of

the oscillatory frequency

1 = Timer 2 is clocked with 1/24 of

the oscillatory frequency

0 = Prescaler

1 = clock/2

Timer 2 Size

TABLE 47: (TH2) TIMER 2, HIGH BYTE - SFR CDH

7

6

5

4

3

TH2 [7:0]

6

5

T2PSM

T2SIZE

Figure 21 shows the Timer2 Compare/Capture

unit block diagram. The following paragraphs

will describe describe how these blocks work.

0 = 16-bit

1 = 8-bit

4

3

T2RM1

T2RM0

Timer 2 reload mode selection

0X = Reload disabled

10 = Mode 0

Timer2 Registers

11 = Mode 1

Timer 2 compare mode selection

0 = Mode 0

1 = Mode 1

Timer 2 input selection

00 = Timer 2 stops

01 = Input frequency f/2, f/12 or f/24

10 = Timer 2 is incremented by

external signal at pin T2IN

11 = Internal clock is gated to the

T2IN input.

Timer2 constists of a 16-bit register, whose

upper and lower bytes are accessible via two

independent SFR registers (TL2, TH2).

2

T2CM

1

0

T2IN1

T2IN0

TABLE 48: (TL2) TIMER 2 LOW BYTE - SFR CCH

7

6

5

4

3

2

1

0

TL2 [7:0]

TABLE 49: (TH2) TIMER 2 HIGH BYTE - SFR CDH

7

6

5

4

3

2

1

0

TH2 [7:0]

Timer2 Control Register

Most of Timer2’s control is accomplished via the

T2CON register located at SFR address C8h.

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www.ramtron.com page 29 of 80

VMX51C1020

FIGURE 21: TIMER 2 AND COMPARE/CAPTURE UNIT

CCH3

COCAH3

Capture

10

COCAH3

Enable

Capture

Sync

T2IN

Data

Latch

Comp

_CaptureCOCAH3

CCL3

CCH2

Compare

16-bit

Comparator

11

01

COCAH2

Enable

Capture

Comp

Data

Latch

_CaptureCOCAH2

Compare

Capture

÷2

16-bit

Comparator

1

0

T2INxx

CCL2

CCH1

SYSCLK

T2EX

COCAH1

Enable

Capture

Comp

Data

Latch

÷2

1

0

_CaptureCOCAH1

CCaappttuurree

÷12

16-bit

Comparator

T2SIZE

00

Compare

COCAH0

Enable

COCAH1

Capture

Comp

T2PSM

Sync

Data

Latch

Timer 2

CCL1

CRCH

_CaptureCOCAH0

T2PS

COCAH0

Compare

Capture

16-bit

Comparator

TL2

TH2

Reload

Compare

Capture

COCAH0

Data

Latch

Reload

CRCL

INPUT/OUTPUT Control

T2IF

T2EXIF

T2EXIE

INTCOMP3

P1.0-PWM0

P1.1-PWM1

P1.2-PWM2

P1.3-PWM3

CCU0

CCU1

CCU2

INTCOMP2

INTCOMP1

INTCOMP0

Interrupt Request

Timer2 Clock Sources

Timer2 Operating Modes

As previously stated, Timer2 can operate in

Timer mode, in which case it derives its source

from the System Clock (SYSCLK) or it can be

configured as an event counter where the High

to Low transition on the T2IN input makes the

Timer 2 to increment.

When the T2IN1 bit is set to 0 and the T2IN0 bit

is set to 1, Timer2 derives its source from the

internal pre-scaled clock or not, depending on

the T2PSM bit value.

Event Counter Mode

When operating in the Event Counter Mode, the

timer is incremented as soon as the external

The T2IN0 and T2IN1 bits of the T2CON register

serve to define the selected Timer2 input and

the operating mode of Timer2 (see following

table).

signal T2IN transitions from a 1 to a 0.

A

sample of the T2IN input is taken at every

machine cycle. Timer 2 is incremented in the

cycle following the one in which the transition

was detected.

TIMER 2 CLOCK SOURCE

T2IN1 T2IN0

Selected Timer 2 input

Timer 2 Stop

0

1

Gated Timer Mode

Standard Timer mode using internal

clock with or without prescaler

In the Gated Timer Mode, the internal clock,

which serves as the Timer2 clock source, is

gated by the external signal T2IN. In other

words, when T2IN is high, the internal clock is

allowed to pass through the AND gate. A low

value of T2IN will diable the clock pulse. This

provides the ability for an external device to

control Timer2’s operation or to use Timer2 to

monitor the duration of an event.

1

0

1

External T2IN pin clock Timer2

Internal Clock is gated by the T2IN input

When T2IN = 0, the Timer2 stop

When in Timer mode, Timer2 derives its source

from the System Clock and the CLKDIVCTRL

register will affect Timer 2’s operation.

Timer 2 Stop

When both T2IN1 and T2IN0 bit are set to 0,

Timer2 is in STOP mode.

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VMX51C1020

Timer2 Mode 1

Timer2 Clock Prescaler

In Mode 1, a 16-bit reload from the CRCx

register on the falling edge of T2EX occurs. This

transition will set T2EXIF if T2EXIE is set. This

action will cause an interrupt (providing that the

Timer2 interrupt is enabled) and the T2IF flag

value will not be affected.

When Timer2 is configured so that it derives its

clock source from the System Clock, the Clock

prescaling value can be controlled by software

using the T2PSM and the T2PS bit of the

T2CON register.

The different system clock prescaling values are

shown in the following table:

The value of the T2SIZE does not affect the

Reload in Mode 1. Also, the reload operation is

performed independently of the state of the

T2EXIE bit.

T2PSM

T2PS

Timer 2 input clock

SYSCLK / 2

1

0

X

0

1

SYSCLK / 12

SYSCLK / 24

FIGURE 22: TIMER 2 RELOAD MODE

T2EX

Timer2 Count Size

Reload Mode 1

Reload Mode 0

T2EXIE

Timer2 can be configured to operate in 8-bit or

16-bit formats. The T2SIZE bit of the T2CON

register selects the Timer2 count size.

TL2

CRCL

Input

Clock

Data Bus

Data Latch

Reload

o

If T2SIZE = 0, Timer2 size is 16-bits

If T2SIZE = 1, Timer2 size is 8-bits

Data Bus

TH2

Data Bus

CRCH

EXF2

Timer2 Reload Modes

T2IF

The Timer2 reload mode is selected by the

T2RM1 and T2RM0 bits of the T2CON register.

The following figure shows the reload operation.

Timer 2 interrupt

request

Timer2 Overflows and Interrupts

Timer2 must be configured as

a

16-bit

Timer/Counter for the reload modes to be

operational by clearing the T2SIZE bit.

Timer2’s interrupt is enabled when the Timer2

counter, the T2IF flag is set, and a Timer 2

interrupt occurs.

Timer 2 Mode 0

A Timer2 interrupt may also be raised from

T2EX if the T2EXIE bit of the IEN1 register is

set.

When the timer overflows, the T2IF overflow flag

is set. Concurrently, this overflow causes Timer2

to be reloaded with the 16-bit value contained in

the CRCx register, (which has been preset by

software). This reload operation will occur during

the same clock cycle in which T2IF was set.

Finding the exact source of a Timer2 interrupt

can be verified by checking the value of the T2IF

and the T2EXIF bits of the IRCON register.

Timer2’s interrupt vector is located at address

002Bh

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VMX51C1020

Timer2 Setup Example

Bit

Mnemonic Mnemonic

Function

Compare and Capture mode

for CRC register

Compare/capture disabled

Capture on a falling edge at

pin CCU0 (1 cycle)

In order to use Timer2, one must first set up and

configure the module (see following code

example).

COCAH0

COCAL0

0

1

//---------------------------------------------------------------------------

1

0

1

Compare enabled (PWM0)

Capture on write operation

into register CRC1

// Sample C code to setup Timer 2

//---------------------------------------------------------------------------

// (…) PROGRAM INITIALIZATION OMITTED

COCAH1

COCAL1

Compare/capture mode for

CC register 1

at 0x100 void main(void){

0

1

Compare/capture disabled

Capture on a rising edge at

pin CCU1 (2 cycles)

Compare enabled (PWM1)

Capture on write operation

into register CCL1

Compare/capture mode for

CC register 2

Compare/Capture disabled

Capture on a rising edge at

pin CCU2 (2 cycles)

Compare enabled (PWM2)

Capture on write operation

into register CCL2

Compare/Capture mode for

CC register 3

Compare/capture disabled

N/A - CCU3 not pinned out

Compare enabled (PWM)

Capture on write operation

into register CCL3

// TIMER 2 & Interrupt setup

DIGPWREN = 0x80;

// Enable Timer2,

T2CON = 0x01;

TL2 = 0xE0;

TH2 = 0xFF;

// Set timer 2 to OSC/12

1

0

1

IEN0 |= 0x80;

IEN0 |= 0x20;

// Enable all interrupts

// Enable interrupt Timer 2

COCAH2

COCAL2

do{

}while(1);

//wait for Timer 2 interrupt

0

1

}//end of main()

//---------------------------------------------------------------------------

// Timer 2 Interrupt Function

//---------------------------------------------------------------------------

void int_timer_2 (void) interrupt 5

{

1

0

1

COCAH3

COCAL3

IEN0 &= 0x7F;

// Disable all interrupts

/*------------------------*/

/*Interrupt code here*/

/*------------------------*/

0

1

0

1

0

1

IEN0 |= 0x80;

}

// Enable all interrupts

Timer2 Special Modes

This allows individual configuration and

operation of each Compare and Capture Unit.

For general timing/counting operations, the

VMX51C1020’s Timer2 includes 4 Compare and

Capture units that can be used to monitor

specific events and serve to drive PWM outputs.

Each Compare and Capture unit provides three

specific operating modes that are controlled by

the CCEN register. These 3 modes are:

Compare/Capture & Reload Registers

Each Compare and Capture Unit has a specific

16-bit register accessible via two SFR

addresses.

o

Compare Modes Enable.

Note that the CRCHx/CRCLx registers

associated with Compare/Capture Unit 0 are the

only ones that can be used to perform a reload

of Timer2 operation.

Capture on write into CRCL/CCLx registers.

Capture on transitions at CCU input pins

level.

TABLE 51: (CCEN) COMPARE/CAPTURE ENABLE REGISTER -SFR C9H

The following tables describe the different

registers that may be captured or compared to

the value of Timer2.

7

6

5

4

COCAH3

COCAL3

COCAH2

COCAL2

3

2

1

0

TABLE 52: (CRCL) COMPARE/RELOAD/CAPTURE REGISTER, LOW BYTE - SFR CAH

COCAH1

COCAL1

COCAH0

COCAL0

7

6

5

4

3

2

1

0

CRCL [7:0]

The CCEN register bits are grouped in pairs of

COCAHx/COCALx bits. Each pair corresponds

TABLE 53: (CRCH) COMPARE/RELOAD/CAPTURE REGISTER, HIGH BYTE - SFR CBH

to one Compare and Capture Unit.

The

7

6

5

4

3

2

1

0

CRCH [7:0]

Compare and Compare unit operating mode vs.

the configuration bit is described in the following

table.

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VMX51C1020

TABLE 54: (CCL1) COMPARE/CAPTURE REGISTER 1, LOW BYTE - SFR C2H

Capture Mode 0

7

6

5

4

3

2

1

0

CCL1 [7:0]

In Capture Mode 0, a transition on a given CCU

pin triggers the latching of Timer2 data into the

associated Compare/Capture register.

TABLE 55: (CCH1) COMPARE/CAPTURE REGISTER 1, HIGH BYTE - SFR C3H

7

6

5

4

3

2

1

0

CCH1 [7:0]

Capture Mode 1

TABLE 56: (CCL2) COMPARE/CAPTURE REGISTER 2, LOW BYTE - SFR C4H

In Capture Mode 1, a capture of the Timer2

value will occur upon writing to the Low Byte of

the chosen capture register.

7

6

5

4

3

2

1

0

CCL2 [7:0]

TABLE 57: (CCH2) COMPARE/CAPTURE REGISTER 2, HIGH BYTE - SFR C5H

7

6

5

4

3

2

1

Note: On the VMX51C1020, the CCU3 input is

NOT pinned out.

CCH2 [7:0]

TABLE 58: (CCL3) COMPARE/CAPTURE REGISTER 3, LOW BYTE - SFR C6H

7

6

5

4

3

2

1

CCL3 [7:0]

FIGURE 23: TIMER 2 CAPTURE MODE 0 FOR CRCL AND CRCH BLOCK DIAGRAM

Write to CRCL, CCLx

CCUx Pin

TABLE 59: (CCH3) COMPARE/CAPTURE REGISTER 3, HIGH BYTE - SFR C7H

Capture

Mode 0

Capture

Mode

1

7

6

5

4

3

2

1

TL2

CRCL / CCLx

CCH3 [7:0]

Data Bus

Input

Clock

Data Latch

Compare/Capture Data Line Width

Reload

Data Latch

The VMX51C1020 is capable of comparing and

capturing data using data lines up to 16 bits

wide. When comparing 2 registers or capturing

1 register, it is required to set the T2SIZE bit of

the T2CON register to 1. This adjusts the line

width to 8-bits.

Data Bus

TH2

Data Bus

T2IF

Timer 2 interrupt

request

CRCH / CCHx

The Capture modes can be especially useful for

external event duration calculation with the

ability to latch the timer value at a given time

(computation can then be performed at a later

time).

When comparing two pairs of registers, for

example, CCH1 and CCL1 to TH2 and TL2, the

T2SIZE bit must be set to 0. This adjusts the line

width to 16 bits.

When operating in Capture Modes, the Compare

and Capture units don’t affect the VMX51C1020

Interrupts.

Timer2 Capture Modes

The Timer2 Capture Modes allow acquiring and

storing the 16-bit contents of Timer2 into a

Capture/Compare register following a MOV SFR

operation or the occurrence of an external event

on one of the CCU pins (described in the

following table).

Timer2 Compare Modes

In Compare Mode, a Timer2 count value is

compared to a value that is stored in the

CCHxx/CCLx or CRCHx/CRCLx registers. If the

values compared match (i.e. when the pulse

changes state), a Compare/Capture interrupt is

generated, if enabled. Varying the value of the

Capture input

CCU0

Timer 2 Capture triggering event

High to Low Transition on CCU0

Low to High Transition on CCU1

Low to High Transition on CCU2

CCHx/CCLx or CRCHx/CRCLx allows

variation of the rectangular pulse generated at

a

CCU1

CCU2

the output. This variation can be used to perform

Timer2 capture is done without affecting Timer2

operation.

pulse width modulation.

following section.

See PWM in the

Each individual Compare and Capture Unit can

be configured for Capture Mode by configuring

the appropriate bit pair of the CCEN register.

The two Capture modes are Mode 0 and Mode

1.

In order to activate the Compare Mode on one of

the four Compare Capture Units, the associated

COCAHx and COCALx bits must be set to 1 and

0, respectively

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VMX51C1020

When the Compare Mode is enabled, the

corresponding output pin value is under the

control of the internal timer circuitry.

(x=0 to3) will not appear on the physical port pin

until the next compare match occurs.

As is the case in Compare Mode 0, the

Compare signal in Mode 1 can also generate an

interrupt (if enabled).

On the VMX51C1020, two Compare Modes are

possible. In both modes, the new value arrives

at port pin 1 in the same clock cycle as the

internal compare signal is activated. The T2CM

of the T2CON register defines the Compare

Mode and is described in the following

paragraphs.

The figure below shows the operating structure

of a given Capture Compare unit operating in

Compare Mode 1.

FIGURE 25: TIMER 2 COMPARE MODE 1 BLOCK DIAGRAM

Compare Mode 0

CRCL,

CCLX

CRCH,

CCHX

A functional diagram of Compare Mode 0 is

shown below. A comparison is made between

the 16-bit value of the Compare/Capture

registers and the TH2, TL2 registers. When the

Timer2 value exceeds the value stored in the

CRCH, CRCL / CCHx, CCLx registers, a high

Compare

Signal

COMPxINT

Interrupt

Comparator

compare

signal

is

generated

and

a

Shadow Register

Compare/Capture interrupt is activated if

enabled. If T2SIZE = 1, the comparison is made

between the TL2 and CRCL/CCLx register.

Port Register

Circuit

Data

Latch

TH2

TL2

Timer 2

Output Register

Overflow

Timer 2

Interrupt

P1.0-

PWM0

P1.1-

PWM1 PWM2

P1.2-

P1.3-

PWM3

This compare signal is then propagated to the

pin corresponding P1.x Pin(s) and to the

associated COMPINTx interrupt (if enabled).

The corresponding P1.x pin is reset when a

Timer2 overflow occurs.

Timer 2 Compare Mode Interrupt

Configuration of the Compare and Capture Units

for the “Compare Mode” through the CCEN

register has an impact on the Interrupt structure

FIGURE 24: TIMER 2 COMPARE MODE 0 BLOCK DIAGRAM

of the VMX51C1020.

In that specific mode

each Compare Capture Unit takes control of one

interrupt line.

CRCH,

CCHX

CRCL,

CCLX

When using the PWM output device, some care

must be excercised to avoid other peripheral

interrupts from being blocked by this

mechanism.

Compare

Signal

COMPxINT

Interrupt

Comparator

Set

Register

TH2

TL2

Timer 2

Overflow

Reset

Register

Timer 2

Interrupt

P1.1-

PWM1

P1.2-

PWM0 PWM0

P1.3-

P1.0-

PWM0

Compare Mode 1

When given Compare Capture unit is

a

operating in Mode 1, any write operations to the

corresponding output register of the port P1.x

_________________________________________________________________________________________________

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VMX51C1020

Mode). As long as the value present in the

Compare and Capture register is greater than

the Timer2 value, the Compare unit will output a

logic low.

FIGURE 26: COMPARE AND CAPTURE UNIT INTERRUPT CONTROL

COMPINT0

Interrupt

1

Interrupt Vector

0053h

SPI Rx &

RxOV INT

0

CCEN(1,0)

= 1,0

When the value of Timer2 equals the value of

the Compare and Capture register, the Compare

unit will change from a logic Low to a logic High.

COMPINT1

Interrupt

1

0

Interrupt Vector

005Bh

I2C INT

CCEN(3,2)

= 1,0

COMPINT2

Interrupt

1

Interrupt Vector

0063h

The clock source for the PWM is derived from

Timer2; which is incremented at every signal

pulse of the appropriate source. The source is

selected by the T2IN1 and T2IN0 bits of the

T2CON register

MAC

Overflow INT

0

CCEN(5,4)

= 1,0

COMPINT3

Interrupt

1

Interrupt Vector

006Bh

ADC & Port

Change INT

0

The T2SIZE bit of the T2CON register allows

configuring the PWM output for 8 or 16-bit

operation. The Timer2 Size affects all the PWM

outputs.

CCEN(7,6)

= 1,0

Using Timer 2 for PWM Outputs

When the Timer2 Size is 8-bits, the comparison

is performed between Timer2 and the LSB of the

Compare and Capture Unit register. The

resulting PWM resolution is 8-bit.

Configuring the Compare and Capture Units in

Compare Mode 0 allows PWM output generation

on the Port1 I/O pins. This mode can be used

for PWM applications such as:

When the Timer2 Size is configured for 16-bit

operation, the comparison is performed between

Timer2 and the contents of the whole Compare

and Capture Unit register. The resulting PWM

resolution is 16-bits but the PWM frequency is

consequently low.

o

D/A conversion

Motor control

Light control

Etc.

When one specific Compare and Capture unit is

configured for this mode, its associated I/O pin is

reserved for this operation only and any write

operation to the associated I/O pin of the P1

register will have no effect on it.

When the System clock is used as the Timer2

clock source, the PWM output frequency equals

the Timer2 overflow rate.

Note that the

CLKDIVCTRL register contents affects Timer2

operation and thus, PWM output frequency.

The following table shows the association

between the Compare and Capture Units,

associated registers and I/O pin

T2CON

T2PSM

T2CON

T2PS

X

T2CON

T2SIZE

0

1

1-8

0-16

1-8

0-16

Freq

PWM

Fosc

14.74MHz

1

0

112.5Hz

28.8KHz

4.8KHz

18.8Hz

2.4KHz

9.38Hz

TABLE 60: COMPARE AND CAPTURE UNIT PWM ASSOCIATION

x

Compare

Capture

Registers

I/O pin

0-12

1-24

Unit

0

1

2

3

CRCH / CRCL

CCH1 / CCL1

CCH2 / CCL2

CCH3 / CCL3

P1.0

P1.1

P1.2

P1.3

The duty cycle of the PWM output is proportional

to the ratio of the Compare and Capture Unit

register’s content versus the Maximum Timer2

number of cycles before overflow: 256 or 65536,

depending on the T2SIZE bit value

PWM signal generation is derived from the

comparison result between the values stored

into the capture compare registers and the

Timer2 value.

When a digital value is written into one of the

Compare and Capture registers, a comparison is

performed between this register and the Timer2

value (providing that Timer2 is in Compare

_________________________________________________________________________________________________

www.ramtron.com page 35 of 80

VMX51C1020

PWM Duty Cycle Calculation: 8-bit

Using the PWM as a D/A Converter

PWM duty cycle CCU0 (%) = 100% x

(256-CRCL)_

256

One of the popular uses of the PWM is to

perform D/A conversion by low pass filtering its’

modulated square wave output. The greater the

duty cycle of the square wave, the greater the

DC value is at the output of the low pass filter

and vice versa.

PWM duty cycle CCU1-3 (%) = 100% x

(256-CCLx)_

256

Variations in the duty cycle of the PWM when

filtered can therefore generate arbitrary

waveforms.

PWM Duty Cycle Calculation: 16-bit

PWM duty cycle CCU0 (%) = 100% x 65536–(CRCH, CRCL)

(CRCH, CRCL)

PWM duty cycle CCU1-3 (%) = 100% x 65536–(CRCH, CRCL)

(CRCH, CRCL)

PWM Configuration Example

The following example shows how to configure

the Timer2 based PWM in 8-bit mode.

(…)

DIGPWREN = 0x80;

T2CON = 0x61;

//ENABLE TIMER 2 MODULE

//BIT 7 - Select 0=1/12, 1=1/24 of Fosc

//BIT 6 - T2 clk source: 0 = Presc,

1=clk/2

//BIT 5 - T2 size: 0=16-bit, 1=8-bit

//BIT 4,3 - T2 Reload mode:

//BIT 2 - T2 Compare mode

//BIT 1,0 - T2 input select: 01= input

derived from osc.

//WHEN THE PWM IS CONFIGURED IN 16-BIT FORMAT, THE PWM OUTPUT

FREQUENCY IS GIVEN BY //THE FOLLOWING EXPRESSION:

// PWM Freq = [(FOSC/2)] / 65536

// WITH A 14.7456MHZ CRYSTAL PWM FREQUENCY = 112.5HZ

//When the PWM is configured in 8-bit its output freq = [(Fosc/2)] / 256

//USING A 14.7456MHZ CRYSTAL PWM FREQUENCY = 28.8KHZ

CCEN = 0x0AA;

//Enable Compare on 4 PWM outputs

// In 16-bit PWM resolution both LSB and MSB of compare unit are used

//In 8-bit PWM Resolution, only the LSB of compare units are used

// and MSB is kept to 00h

CRCL = 0x0E6;

x100%

//PWM0 duty = [(256-CRCL)/256]

CRCH = 0x000;

CCL1 = 0x0C0;

x100%

//E6h => 10.1%

//PWM1 duty = [(256-CCL1)/256]

CCH1 = 0x000;

CCL2 = 0x080;

CCH2 = 0x000;

CCL3 = 0x033;

CCH3 = 0x000;

P1PINCFG = 0x0F;

//C0h => 25%

//PWM2 duty = [(256-CCL2)/256] x100%

//80h => 50%

//PWM3 duty = [(256-CCL3)/256] x100%

//33h => 80%

//Configure P1 LSQ as output to enable

PWM

(…)

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www.ramtron.com page 36 of 80

VMX51C1020

UART0 Control Register

Serial UART Interfaces

UART0 configuration is performed mostly via the

S0CON SFR register located at address 98h.

The VMX51C1020 includes two serial UART

interface ports (UART0 and UART1). Each

serial port has a 10-bit timer devoted to baud

rate generation.

TABLE 62: (S0CON) SERIAL PORT 0, CONTROL REGISTER - SFR 98H

7

6

5

4

Both serial ports can operate in full duplex

S0M0

S0M1

MPCE0

R0EN

mode.

The VMX51C1020 also includes a

double buffer, enabling the UART to accept an

incoming word before the software has read the

previous value.

3

2

1

T0I

0

R0I

T0B8

R0B8

Bit

7

6

Mnemonic Function

S0M0

S0M1

MPCE

Sets Serial Port Operating Mode

See Table

1 = Enables the multiprocessor

communication feature.

UART0 Serial Interface

5

4

3

R0EN

T0B8

1 = Enables serial reception.

Cleared by software to disable

reception.

The operation of UART0 of the VMX51C1020 is

similar to the standard 8051 UART.

The 9^thtransmitted data bit in Modes

2 and 3. Set or cleared by the CPU,

depending on the function it

performs (parity check,

UART0 can derive its clock source from a 10-bit

dedicated baud rate generator or from the

Timer1 overflow.

multiprocessor communication etc.)

In Modes 2 and 3, it is the 9^thdata bit

received. In Mode 1, if sm20 is 0,

RB80 is the stop bit. In Mode 0, this

bit is not used. Must be cleared by

software.

2

R0B8

UART0’s Transmit and Receive buffers are

accessed through a unique SFR register named

S0BUF.

1

0

T0I

R0I

Transmit interrupt flag set by

hardware after completion of a serial

reception. Must be cleared by

software.

Receive interrupt flag set by

hardware after completion of a serial

reception. Must be cleared by

software.

The UART0 S0BUF has a double buffering

feature on reception which allows accepting an

incoming word before the software has read the

previous value from the S0BUF.

TABLE 61: (S0BUF) SERIAL PORT 0, DATA BUFFER - SFR 99H

7

6

5

4

3

2

1

0

UART0 Operating Modes

S0BUF [7:0]

UART0 can operate in four distinct modes,

which are defined by the SM0 and SM1 bits of

the S0CON register (see following table).

TABLE 63: SERIAL PORT 0 MODES

SM0 SM1 MODE

DESCRIPTION BAUD RATE

0

1

0

1

0

1

0

1

2

3

Shift Register

8-bit UART

9-bit UART

Fosc/12

Variable

Fclk/32 or /64

Variable

**Note that the speed in mode 2 depends on SMOD bit in the Special

Function Register PCON when SMOD = 1 fclk/32

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VMX51C1020

UART0 - Mode 0

UART0 - Mode 3

In this Mode, pin RX0 is used as an input and an

output, while TX0 is used only to output the shift

clock. For an operation in this mode, 8 bits are

transmitted with the LSB as the first bit.

Additionally, the baud rate is fixed at 1/12 of the

crystal oscillator frequency. In order to initialize

reception in this mode, the user must set bits

R0I and R0EN in the S0CON register to 0 and 1,

respectively. Note that in other Modes, when

R0EN=1, the interface begins to receive data.

Mode 3 is essentially identical to Mode 2, with

the difference being that the internal baud rate

generator or Timer1 can be used to set the

baud rate.

UART0 - Baud Rate Generator Source

As mentioned previously, the UART0 baud rate

clock can be sourced from either Timer 1 or the

dedicated 10-bit baud rate generator.

UART0 - Mode 1

Selection between these sources is enabled via

the BAUDSRC bit of the U0BAUD register (see

following table).

In this Mode, the RX0 pin serves as an input and

the TX0 pin as a serial output and no external

shift clock is used. In Mode 0, 10-bits are

transmitted:

TABLE 64: (U0BAUD) UART0 BAUD RATE SOURCE SELECT - SFR D8H

7

6

-

5

-

4

-

3

-

2

-

1

-

0

-

o

Start bit (logic low);

8-bits of data (LSB first);

A stop bit (logic high).

BAUDSRC

7

BAUDSRC Baud rate generator clock source

0 = Timer 1

1 = Use UART0 dedicated Baud

rate generator

-

The start bit synchronizes data reception, with

the 8-bits of received data then being available

in the S0BUF register. Reception is completed

once the stop bit sets the R0B8 flag in the

S0CON register.

6:0

-

UART0 - Mode 2

In this Mode the RX0 pin is used as an input and

an output while TX0 is used to output the shift

clock.

In

Mode

2,

11

bits

are

transmitted/received. hese 11-bits consist of:

o

Start bit (logic low)

8 bits of data (LSB first),

One programmable 9^thbit,

Stop bit (logic high).

The 9^thbit is used for parity. In the data

transmission case, bit TB80 of the S0CON is

output as the 9^thbit. For reception, the 9^thbit will

be stored captured in the RB80 bit of the

S0CON register.

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VMX51C1020

Using the UART0 dedicated baud rate

generator, frees up Timer 1 for other uses.

Timer1 can also be used as the baud rate

generator for the UART0. Set BAUDSRC to 0

and assign Timer1’s output to UART0.

The S0RELH and S0REL registers are used to

store the 10-bit reload value of the UART0 baud

rate generator.

When the baud rate clock source is derived from

Timer1, the baud rate and timer reload values

can be calculated using the following formulas

(examples follow).

TABLE 65: (S0RELL) SERIAL PORT 0, RELOAD REGISTER, LOW BYTE - SFR 96H

7

6

5

4

3

2

1

0

S0RELL [7:0]

TABLE 69: EQUATION TO CALCULATE BAUD RATE FOR SERIAL 0

Serial 0: mode 1 and 3

Mode 1: ForU0BAUD.7=0 (standard mode)

TABLE 66: (S0RELH) SERIAL PORT 0, RELOAD REGISTER, HIGH BYTE - SFR 97H

7

6

5

4

3

2

1

0

2^SMODx f_clk

S0RELH [15:8]

Baud Rate =

_

32 x 12 x (256-TH1)

The following equations should be used to

calculate the reload value for the SOREL

register (examples follow).

TH1 = 256 -

2^SMODx f_{clk____}

32x12x Baud Rate

Mode 3: For BAUDSRC=1

SOREL = 1024 –

2^SMODx f_{clk_______}

64 x Baud Rate

TABLE 70: UART 0 BAUD RATE SAMPLE VALUES BAUDSRC =0, SMOD = 1

Desired

Baud Rate

TH1 @ f_clk

11.059 MHz

=

TH1 @ f_clk

14.75 MHz

=

Baud Rate =

2^SMODx f_{clk____}

64 x (1024 – S0REL)

115.2 kbps

57.6 kbps

19.2 kbps

9.6 kbps

2.4 kbps

1.2 kbps

300 bps

-

FFh

FDh

FAh

E8h

D0h

40h

FCh

F8h

E0h

C0h

-

TABLE 67: SERIAL 0 BAUD RATE SAMPLE VALUES BAUDSRC = 1, SMOD = 1

Desired

Baud Rate

S0REL @ f_clk

11.059 MHz

=

S0REL @ f_clk

14.75 MHz

=

500.0 kbps

460.8 kbps

230.4 kbps

115.2 kbps

57.6 kbps

19.2 kbps

9.6 kbps

2.4 kbps

1.2 kbps

300 bps

-

3FFh

3FEh

3FCh

3F8h

3E8h

3D0h

340h

280h

-

TABLE 71:UART 0 BAUD RATE SAMPLE VALUES BAUDSRC =0, SMOD = 0

Desired

Baud Rate

3FDh

3FAh

3EEh

3DCh

370h

2E0h

-

TH1 @ f_clk

=

TH1 @ f_clk

14.75 MHz

=

11.059 MHz

115.2 kbps

57.6 kbps

19.2 kbps

9.6 kbps

2.4 kbps

1.2 kbps

300 bps

-

FEh

FCh

F0h

E0h

80h

FDh

F4h

E8h

A0h

TABLE 68: SERIAL 0 BAUD RATE SAMPLE VALUES BAUDSRC =1, SMOD = 0

Desired

Baud Rate

S0REL @ f_clk

11.059 MHz

=

S0REL @ f_clk

14.75 MHz

=

115.2 kbps

57.6 kbps

19.2 kbps

9.6 kbps

2.4 kbps

1.2 kbps

300 bps

-

3FEh

3FCh

3F4h

3E8h

3A0h

340h

100

3FDh

3F7h

3EEh

3B8h

370h

1C0h

_________________________________________________________________________________________________

www.ramtron.com page 39 of 80

VMX51C1020

Example of UART0 Setup and Use

In order to use UART0, the following operations

must be performed:

o

Enable the UART0 Interface

Set I/O Pad direction TX= output, RX=Input

Enable Reception (if required)

o

Configure the Uart0 controller S0CON

The following are configuration and transmission

code examples for UART0.

//----------------------------------------------------------------------------------------//

// UART0 CONFIG with S0REL

//

// Configure the UART0 to operate in RS232 mode at 19200bps

// with a crystal of 14.7456MHz

//

//----------------------------------------------------------------------------------------//

void uart0ws0relcfg()

{

P3PINCFG |= 0x01;

DIGPWREN |= 0x01;

S0RELL = 0xF4;

S0RELH = 0x03;

S0CON = 0x50;

// pads for uart 0

// enable uart0/timer1

//com speed = 19200bps

// Uart0 in mode1, 8 bit, var. baud rate

//Set S0REL is source for UART0

//Baud rate clock

U0BAUD = 0x80;

}//end of uart0ws0relcfg() function

//----------------------------------------------------------------------------------------//

// UART0 CONFIG with Timer 1

//

// Configure the UART0 to operate in RS232 mode at 19200bps

// with a crystal of 14.7456MHz

//

//----------------------------------------------------------------------------------------//

void uart0wTimer1cfg()

{

P3PINCFG |= 0x01;

DIGPWREN |= 0x01;

TMOD &= 0x0F;

TMOD =0x20;

// pads for uart0

// enable uart0/timer1

//Set Timer 1, Gate 0, Mode 2

//Com Speed = 19200bps

TH1 = 0xFE;

TCON &= 0x0F;

TCON =0x40;

//Start Timer 1

U0BAUD = 0x00;

//Set Timer 1 Baud rate

//generator for UART0

PCON = 0x00;

S0CON = 0x50;

//Set SMOD = 0

// Config Uart0 in mode 1,

//8 bit, variable baud rate

}//end of uart1Config() function

//----------------------------------------------------------------------------------------//

// Txmit0()

//

// One Byte transmission on UART0

//----------------------------------------------------------------------------------------//

// - Constants definition

sbit UART_TX_EMPTY = USERFLAGS^1;

void txmit0( unsigned char charact){

S0BUF = charact;

USERFLAGS = S0CON;

//Wait TX EMPTY flag to be raised

while (!UART_TX_EMPTY) {USERFLAGS = S0CON;}S0CON =

//clear both R0I & T0I bits

S0CON & 0xFD;

}//end of txmit0() function

See the Interrupt section for example of setup of

UART0 interrupts

_________________________________________________________________________________________________

www.ramtron.com

page 40 of 80

VMX51C1020

UART1: Operating Modes

UART1 Serial Interface

The VMX51C1020 UART1 has two operating

Modes, A and B, which provide 9 or 8-bit

operation, respectively (see following table).

The UART1 serial interface is based on a subset

of UART0. It provides two operating modes and

its clock source is derived exclusively from a

dedicated 10-bit baud rate generator.

TABLE 74: UART1 MODES

SM

MODE

DESCRIPTION

9-bit UART

8-bit UART

BAUD RATE

Variable

The UART1 Transmit and Receive buffers are

accessed via SFR register S1BUF.

0

1

A

B

TABLE 72: (S1BUF) SERIAL PORT 1, DATA BUFFER - SFR C1H

7

6

5

4

3

2

1

0

UART1 - Mode A

S1BUF [7:0]

In this Mode, 11 bits are transmitted or received.

These 11 bits are composed of:

As is the case with UART0, UART1 includes a

double buffering feature in order to avoid

overwriting of the receive register.

o

A start bit (logic low),

8 bits of data (LSB first),

A programmable 9^thbit,

Stop bit (logic high).

UART1 Control Register

UART1 is controlled by the S1CON register. The

following table provides a description of the

UART1 Control Register.

As in Mode 2 and 3 of UART0, the 9^thbit is used

for parity. For data transmission, the TB81 bit of

the S1CON register holds the 9^thbit. In the case

of reception, the 9^thbit will be captured into the

R1B8 bit of the S1CON register.

TABLE 73: (S1CON) SERIAL PORT 1, CONTROL REGISTER - SFR C0H

7

6

5

4

S1M

Reserved

MPCE1

R1EN

UART1 - Mode B

3

2

1

0

T1B8

R1B8

T1I

R1I

In this Mode, 10 bits are transmitted and consist

of:

Bit

7

6

Mnemonic Function

S1M

Reserved

MPCE1

Operation mode Select

-

o

A start bit (logic low)

8 bits of data (LSB first);

A stop bit (logic high).

5

1 = Enables multiprocessor

communication feature.

4

3

R1EN

T1B8

If set, enables serial reception.

Cleared by software to disable

reception.

Received data (8-bit) is read via the S1BUF

register. Reception is completed once the stop

bit sets the R1B8 flag in the S1CON register.

The 9^thtransmitted data bit in mode

A. Set or cleared by the CPU,

depending on the function it performs

(parity check, multiprocessor

communication, etc.)

UART1 - Baud Rate Generator

2

R1B8

In Mode A, it is the 9^thdata bit

received. In Mode B, if SM21 is 0,

RB81 is the stop bit. Must be cleared

by software.

As previously mentioned, UART1’s clock source

is derived from a dedicated 10-bit baud rate

generator module.

1

0

T1I

R1I

Transmit interrupt flag, set by

hardware after completion of a serial

transfer. Must be cleared by software

Receive interrupt flag, set by

hardware after completion of a serial

reception. Must be cleared by

software

The S1REL registers are used to adjust the

baud rate of UART1.

TABLE 75: (S1RELL) UART1, RELOAD REGISTER, LOW BYTE - SFR BEH

7

6

5

4

3

2

1

0

S1RELL [7:0]

TABLE 76: (S1RELH) UART 1, RELOAD REGISTER, HIGH BYTE - SFR BFH

7

6

5

4

3

2

1

0

S1RELH [7:0]

_________________________________________________________________________________________________

www.ramtron.com page 41 of 80

VMX51C1020

The following formulas are used to calculate the

baud Rate, S1RELL and S1RELH values.

Example of UART1 Setup and Use

Serial 1

The following are C code examples of UART1

configuration, serial byte transmission and

interrupt usage.

Baud Rate=

f_{clk__________}

32 x (1024-S1REL)

Note: S1REL.9-0 = S1RELH.1-0 + S1RELL.7-0

//----------------------------------------------------------------------------------------//

// UART1 CONFIG

//

S1REL = 1024 -

f_{clk__________}

// Configure the UART1 to operate in RS232 mode at 115200bps

32 x Baud Rate

// with a crystal of 14.7456MHz

//----------------------------------------------------------------------------------------//

void uart1Config(void)

{

P0PINCFG |= 0x04;

DIGPWREN |= 0x02;

S1RELL = 0xFC;

S1RELH = 0x03;

S1CON = 0x90;

// pads for uart 1

// enable uart1

// Set com speed = 115200bps

TABLE 77: SERIAL 1 BAUD RATE SAMPLE VALUES

Desired

S1REL @

f_clk= 11.0592

MHz

S1REL @

f_clk= 14.746

MHz

Baud Rate

// Mode B, receive enable

500.0 kbps

460.8 kbps

230.4 kbps

115.2 kbps

57.6 kbps

19.2 kbps

9.6 kbps

-

}//end of uart1Config() function

3FFh

3FEh

3FCh

3F8h

3E8h

3D0h

34Fh

280h

//----------------------------------------------------------------------------------------//

// TXMIT1 -- Transmit one byte on the UART1

//----------------------------------------------------------------------------------------//

void txmit1( unsigned char charact){

3FDh

3FAh

3EEh

3DCh

370h

2E0h

S1BUF = charact;

USERFLAGS = S1CON;

while (!UART_TX_EMPTY) {USERFLAGS = S1CON;}

2.4 kbps

1.2 kbps

//Wait TX EMPTY flag

//clear both R1I & T1I bits

S1CON = S1CON & 0xFD;

}//end of txmit1() function

//----------------------------------------------------------------------------------------//

// Interrupt configuration

//---------------------------------------------------------------------------------------//

Setting Up and Using UART1

IEN0 |= 0x80;

IEN2 |= 0x01;

// Enable all interrupts

// Enable interrupt UART 1

In order to use UART1, the following operations

must be performed:

//----------------------------------------------------------------------------------------//

// Interrupt function

//----------------------------------------------------------------------------------------//

o

Enable the UART1 Interface

Set I/O Pad direction TX= output, RX=Input

Enable Reception (if required)

o

void int_serial_1 (void) interrupt 16

{

Configure the UART1 controller S1CON

IEN0 &= 0x7F;

// Disable all interrupts

/*------------------------*/

/*Interrupt code here*/

/*------------------------*/

if (S1CON&0x01==0x01)

{

S1CON &= 0xFE;

// Clear RI (it comes

// before T1I)

}

else

{

S1CON &= 0xFD;

// Clear T1I

}

IEN0 |= 0x80;}

// Enable all interrupts

}

/-----------------------------------------------------------------------

_________________________________________________________________________________________________

www.ramtron.com page 42 of 80

VMX51C1020

From the software point of view, the differential

transceiver is viewed as differential UART.

UART1 Driven Differential

Transceiver

The differential transceiver I/Os are connected

to UART1 of the VMX51C1020, therefore

communication parameters such as the data

length, speed, etc are managed by the UART1

peripheral interface/registers.

The VMX51C1020 includes

a

differential

transceiver compatible with the J1708/RS-

485/RS-422 standards. These are driven by

UART1.

The Transceiver’s signals are differential which

provide high electrical noise immunity. The

Using the UART1 Differential

Transceiver

differential

interface

is

capable

of

transferring/recieving data over hundreds of feet

of twisted pair wire.

In order to use the Differential Transceiver

interface, one must perform the following

operations:

A number of devices can be connected in

parallel to the differential bus in order to

implement a multi-drop network. The number of

devices that can be networked depends on the

bus length and configuration.

o

Enable UART1 and the differential

interface by setting bits 1 and 2 of the

DIGPWREN register.

The admissible common mode voltage range of

the differential interface is –2.0 V to +7.0 V.

When implementing this type of transmission

network over long distances in noisy

o

Configure UART1’s operating mode via

the S1CON register.

environments,

appropriate

protection

is

Set the baud rate via the S1RELH and

S1RELL registers.

recommended in order to prevent the common

mode voltage from causing any damage to the

VMX51C1020.

Enable UART1’s interrupt, if required

Use UART1’s S1BUF register to transmit and

receive data through the differential transceiver.

If the P0.2 pin is configured as an output, the

signal corresponding to the TX1 signal of

UART1 will appear on this pin (note that the

P0.3-RX1 pin can be used as regular digital

output).

FIGURE 27: DIFFERENTIAL INTERFACE (J1708 CONFIG)

+5V

Versa Mix

TX1D+

TX1D-

+5V

RX1D+

RX1D-

When the transceiver is connected in Half-

Duplex mode (RX1D+ connected to TX1D+ and

RX1D- connected to TX1D-) and UART1’s

interrupts are enabled, careful management of

the UART1 interrupts will be required as every

byte transmitted will generate a local Rx

interrupt.

FIGURE 28: DIFFERENTIAL INTERFACE (RS485 CONFIG)

+5V

Versa Mix

TX1D+

TX1D-

RX1D+

RX1D-

_________________________________________________________________________________________________

www.ramtron.com page 43 of 80

VMX51C1020

Differential Interface Use Example

//---------------------------------------------------------------------------------------------//

// EXT INT0 interrupt

//

// when the External interrupt 0 is triggered A Message string is sent over the

// the serial UART1

//---------------------------------------------------------------------------------------------//

The following code provides and an example of

configuration and use of the VMX51C1020

Differential Interface.

void int_ext_0 (void) interrupt 0 {

#pragma SMALL

#pragma UNSIGNEDCHAR

#include <vmixreg.h>

int x=0;

idata unsigned char

cptr=0x01;

// --- function prototypes

void txmit1( unsigned char charact);

IEN0 &= 0x7F;

//disable ext0 interrupt

void uart1differential(void);

cptr = cptr-1;

while( irq0msg[cptr] != '\n')

// - global variables

//Send a text string over the differential interface

// - Constants definition

sbit UART_TX_EMPTY = USERFLAGS^1;

{

txmit1( irq0msg[cptr]);

cptr = cptr +1;

}

code char irq0msg[]="Ramtron inc”;

//---------------------------------------------------------------------------------------------//

IEN0 = 0x81;

//

MAIN FUNCTION

//Enable all interrupts + int_0

//---------------------------------------------------------------------------------------------//

//----------------------------------------------------------------------------------------------------//

//------------------------------- Individual Functions ----------------------------------------//

//----------------------------------------------------------------------------------------------------//

at 0x0100 void main (void) {

// Enable and configure the UART1

uart1differential();

//Config UART1 diff interface

//----------------------------------------------------------------------------------------------------//

// UART1 DIFFERENTIAL CONFIG

//

// Configure the UART1 differential interface to operate in

// Warning: The Clock Control circuit does affect the dedicated baud rate

// generator S0REL, S1REL and Timer1 operation

// RS232 mode at 115200bps with a crystal of 14.7456MHz

//

//*** Configure the interrupts

IEN0 |= 0x81;

//----------------------------------------------------------------------------------------------------//

void uart1differential(void)

{

//Enable interrupts + Ext. 0 interrupt

//Enable UART1 Interrupt

IEN2 |= 0x01;

DIGPWREN |= 0x06;

P0PINCFG |= 0x04;

P0PINCFG = 0x00;

// enable uart1 & differential transceiver

// pads for uart1

Txmit1(“A’);

//Transmit one character on UART1

do

{

S1RELL = 0xFC;

S1RELH = 0x03;

S1CON = 0x90;

// Set com speed = 115200bps

// Mode B, receive enable

}while(1);

//Wait for UART1 Rx interrupt

}//end of uart1differential() function

}// End of main()...

//-----------------------------------------------------------------------------------------------//

// TXMIT1

//

//---------------------------------------------------------------------------------------------//

// UART1 Differential interface interrupt

//

// In this example, the source of UART1 interrupt would be caused

// by bytes reception on the differential interface

//----------------------------------------------------------------------------------------------//

void int_uart1 (void) interrupt 16 {

// Transmit one byte on the UART1 Differential interface

//

//-----------------------------------------------------------------------------------------------//

void txmit1( unsigned char charact){

S1BUF = charact;

USERFLAGS = S1CON;

unsigned char charact;

//Wait TX EMPTY flag to be raised

IEN0 &= 0x7F;

while (!UART_TX_EMPTY) {USERFLAGS = S1CON;}

// -- Put you code here…

S1CON = S1CON & 0xFD;

}//end of txmit1() function

//clear both R1I & T1I bits

S1CON = S1CON & 0xFC;

IEN0 |= 0x80;

//clear both R1I & T1I bits

// enable all interrupts

}// end of uart1 INTERRUPT

_________________________________________________________________________________________________

www.ramtron.com page 44 of 80

VMX51C1020

FIGURE 29: SPI INTERFACE BLOCK DIAGRAM

SPI Interface

VERSA MIX SPI

INTERFACE

Serial Data IN

SDI

SPI SFRs

Serial Data OUT

SDO

SCK

CS0

CS1

CS2

CS3

SS

The VMX51C1020’s SPI peripheral is a highly

configurable and powerful interface enabling

high speed serial data exchange with external

devices such as A/Ds, D/Aa, EEPROMs, etc.

Serial Clock IN/OUT

Chip Select Output

To Slave Device #1

To Slave Device #2

To Slave Device #3

To Slave Device #4

From Master Device

The SPI interface can operate as either a master

or a slave device. In master mode, it can control

up to 4 slave devices connected to the SPI bus.

Processor

Chip Select Output

Slave Select Input

SPI IRQs

The following lists

a

number of the

VMX51C1020’s SPI features.

SPI Transmit/Receive Buffer

Structure

o

Allows synchronous serial data transfers

Transaction size is configurable from 1-

32-bits and more.

Full duplex support

SPI Modes 0, 1, 2, 3 and 4 supported

(Full clock polarity and phase control)

Up to four slave devices can be

connected to the SPI bus when it is

configured in master mode

When receiving data, the first byte received is

stored in the SPIRX0 Buffer. As bits continue to

arrive, the data already present in the buffer is

shifted towards the least significant byte end of

the receive registers (see following figure).

o

For example (see following figure), assume the

SPI is about to receive 4 consecutive bytes of

data: W, X, Y and Z, where the first byte

received is byte W, The first received byte (W)

will be placed in the SPIRX0 register. Upon

reception of the next byte (X), the contents of

SPIRX0 will be shifted into SFR register SPIRX1

and byte X will be placed in the SPIRX0

registers. Following this same procedure, we

bytes W, X, Y and Z will end up in RX data

buffer registers SPIRX0, SPIRX1, SPIRX2 and

SPIRX3, respectively.

o

Slave mode operation

Data transmission speed is configurable

Double 32-bit buffers in transmission

and reception

o

3 dedicated interrupt flags

o

TX-Empty

RX Data Available

RX Overrun

o

Automatic/Manual control of the chip

selects lines.

SPI operation is not affected by the

clock control unit

The case where the SDO and SDI pins are

shorted together is represented in the following

diagram.

The following provides a block diagram view of

the SPI Interface.

_________________________________________________________________________________________________

www.ramtron.com page 45 of 80

VMX51C1020

FIGURE 30 : SPI INTERFACE RECEIVE TRANSMIT SCHEMATIC

TABLE 80: (SPIRX1TX2) SPI DATA BUFFER, BYTE 2 - SFR E3H

BEFORE A RECEPTION

7

6

5

4

3

2

1

0

SPIRX1TX2 [23:16]

First Byte to be

Transmitted

LSBit

0

MSBit

7

1

2 3 4 5 6

Bit

Mnemonic Function

22:16 SPITX2

SPIRX1

SPI Transmit Data Bits 23:16

SPI Receive Data Bits 15:8

lsb

SPITX3

W

SPITX2

X

SPITX1

Y

SPITX0

Z

msb

lsb

TX Data Buffer

RX Data Buffer

TABLE 81: (SPIRX0TX3) SPI DATA BUFFER, HIGH BYTE - SFR E4H

msb

7

6

5

4

3

2

1

SPIRX3

SPIRX2

SPIRX1

SPIRX0

SPIRX0TX3 [31:24]

First Byte Received is

Placed in the least

significant byte register

Bit

Mnemonic Function

31:24 SPITX3

SPIRX0

SPI Transmit Data Bits 31:24

SPI Receive Data Bits 7:0

AFTER A RECEPTION

SPI Control Registers

lsb SPITX3

SPITX2

SPITX1

SPITX0 msb

The SPI Control registers are used to define:

TX Data Buffer

RX Data Buffer

msb

lsb

W

o

SPI operating speed (Master mode)

Active Chip Select output (Master mode)

SPI clock Phase (Master/Slave modes).

SPI clock Polarity (Master/Slave modes).

Z

Y

X

SPIRX2

SPIRX1

SPIRX3

SPIRX0

Bytes are Shifted 1 byte position

at a time each time a new byte is

received

MSBit

LSBit

TABLE 82: (SPICTRL) SPI CONTROL REGISTER - SFR E5H

7

6 5 4 3 2 1 0

7

6

5

4

SPICK [2:0]

SPICS_1

Close-Up View of how the bits within

the byte is placed after it has been

received

3

2

1

0

SPICS_0

SPICKPH

SPICKPOL

SPIMA_SL

When using the SPI Interface, it is important to

keep in mind that a transmission is started when

the SPIRX3TX0 register is written to.

Bit

7:5

Mnemonic

SPICK[2:0]

Function

SPI Clock control

000 = OSC Ck Div 2

001 = OSC Ck Div 4

010 = OSC Ck Div 8

011 = OSC Ck Div 16

100 = OSC Ck Div 32

101 = OSC Ck Div 64

110 = OSC Ck Div 128

111 = OSC Ck Div 256

Active CS line in Master Mode

00 = CS0- Active

01 = CS1- Active

10 = CS2- Active

11 = CS3- Active

SPI Clock Phase

From an SFR point of view, the transmission

and reception buffers of the SPI interface

occupy the following addresses.

TABLE 78: (SPIRX3TX0) SPI DATA BUFFER, LOW BYTE - SFR E1H

7

6

5

4

3

2

1

0

4:3

SPICS[1:0]

SPIRX3TX0 [7:0]

Bit

7-0

Mnemonic

SPITX0

SPIRX3

Function

SPI Transmit Data Bits 7:0

SPI Receive Data Bits 31:24

2

1

SPICKPH

SPICKPOL

SPI Clock Polarity

0 – CK Polarity is Low

1 – CK Polarity is High

Master / -Slave

TABLE 79: (SPIRX2TX1) SPI DATA BUFFER, BYTE 1 - SFR E2H

7

6

5

4

3

2

1

SPIRX2TX1 [15:8]

0

SPIMA_SL

1 = Master

0 = Slave

Bit

Mnemonic Function

15:8 SPITX1

SPIRX2

SPI 1 Transmit Data Bits 15:8

SPI Receive 1 Data Bits 23:16

_________________________________________________________________________________________________

www.ramtron.com page 46 of 80

VMX51C1020

SPI MODE 0: SPICKPOL =0,SPICKPH =0

SPI Operating Speed

Three bit in the SPICTRL register serve to adjust

the communication speed of the SPI interface.

CS_X

SCK

SPICK[2:0]

Div Ratio

Clk Div 2

Fosc =

14.74MHz

Fosc =

SDO

11.059MHz

5.53 MHz

2.76 MHz

1.38 MHz

691 kHz

346 kHz

173 kHz

86 kHz

MSB

LSB

7.37 MHz

Clk Div 4

Clk Div 8

3.68 MHz

1.84 MHz

922 kHz

461 kHz

230 kHz

115 kHz

57.6 kHz

SDI

*Arrows indicate the edge where the data acquisition occurs

Clk Div 16

Clk Div 32

Clk Div 64

Clk Div 128

Clk Div 256

SPI Mode 1

43.2 kHz

o

Data is placed on the SDO pin at the

falling edge of the clock.

Data is sampled on the SDI pin at the

rising edge of the clock.

SPI Master Chip Select Control

When the SPI is configured in Master mode, the

value of the SPICS[1:0] bits will define which

Chip select pins will be active during the

transaction.

FIGURE 32: SPI MODE 1

SPI MODE 1: SPICKPOL =0,SPICKPH =1

CS_X

SCK

The following sections will describe how the SPI

Clock Polarity and Phase affects the read and

write operations of the SPI interface.

SDO

MSB

LSB

SDI

SPI Operating Modes

*Arrows indicate the edge where the data acquisition occurs

The SPI interface can operate in four distinct

modes defined by the SPICKPH and SPICKPOL

bits of the SPICTRL register.

SPICKPH defines the SPI clock phase and

SPICKPOL defines the Clock polarity for data

exchange.

SPICKPOL SPICKPH

SPI Operating Mode

bit value

0

1

0

1

0

1

SPI Mode 0

SPI Mode 1

SPI Mode 2

SPI Mode 3

SPI Mode 0

o

Data is placed on the SDO pin at the

rising edge of the clock.

Data is sampled on the SDI pin at the

falling edge of the clock.

FIGURE 31 : SPI MODE 0

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VMX51C1020

SPI Mode 2

SPI Transaction Size

o

Data is placed on the SDO pin at the

falling edge of the clock.

Data is sampled on the SDI pin at the

rising edge of the clock.

Many SPI based microcontrollers only allow a

fixed SPI transaction size of 8-bits. However,

most devices requiring SPI control require

transactions of more than 8-bits, giving way to

alternate inefficient means of dealing with SPI

transactions.

FIGURE 33: SPI MODE 2

SPI MODE 2: SPICKPOL =1,SPICKPH =0

The VMX51C1020 SPI interface includes a

transaction size control register, SPISIZE that

enables different sized transaction to be

performed. The SPI interface also automatically

controls the Chip select line.

CS_X

SCK

SDO

MSB

LSB

SDI

The following table describes the SPISIZE

register.

*Arrows indicate the edge where the data acquisition occurs

TABLE 83: (SPISIZE) SPI SIZE CONTROL REGISTER - SFR E7H

SPI Mode 3

7

6

5

4

3

2

1

0

SPISIZE[7:0]

o

Data is placed on the SDO pin at the

rising edge of the clock.

Data is sampled on the SDI pin at the

falling edge of the clock.

Bit

7:0

Mnemonic

SPISIZE[7:0]

Function

Value of the SPI packet size

The following formula is used to calculate the

transaction size.

FIGURE 34: SPI MODE 3

SPI MODE 3: SPICKPOL =1,SPICKPH =1

For SPISIZE from 0 to 31:

CS_X

SCK

SPI Transaction Size = [SPISIZE + 1]

SDO

MSB

LSB

For SPISIZE from 32 to 255*:

SDI

*Arrows indicate the edge where the data acquisition occurs

SPI Transaction Size = [SPISIZE*8 - 216]

An SPI transaction size greater than 32 bits is

possible when using the VMX51C1020 SPI

interface, however, large data packets of this

size require

careful management of the

associated interrupts in order to avoid buffer

overwrites.

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VMX51C1020

TABLE 85: (SPIIRQSTAT) SPI INTERRUPT STATUS REGISTER - SFR E9H

SPI Interrupts

7

-

6

-

5

4

SPISLAVESEL

SPITXEMPTO

The SPI interface has three associated

interrupts.

3

2

1

0

SPISEL

SPIOV

SPIRXAV

SPITXEMP

o

SPI RX Overrun

SPI RX Data Available

SPI TX Empty

Bit

7:6

Mnemonic

Function

-

Flag that indicates that we have

not reloaded the transmit buffer

fast enough (only used for

5

4

SPITXEMPTO

The SPIRXOVIE, SPIRXAVIE and SPITXEMPIE

bits of the SPICONFIG register allow individual

enabling of the above interrupt sources at the

SPI interface level.

packets greater than 32 bits.).

SPISLAVESEL Slave Select “NOT” (SSN)

This bit is the result of the

logical AND operation between

3

SPISEL

CS0, CS1, CS2 and CS3.

(Indicates if one chip is

selected.)

At the processor level, two interrupt vectors are

dedicated to the SPI interface:

2

1

SPIOV

SPIRXAV

SPI Receiver overrun

SPI Receiver available

SPI Transmit buffer is ready to

receive mode data. It does not

flag that the transmission is

completed.

o

SPI RX data available and Overrun

interrupt

SPI TX empty interrupt

0

SPITXEMP

In order to have the processor jump to the

associated interrupt routine, you must also

enable one or both of these interrupts in the

IEN1 register as well as set the EA bit of the

IEN0 register (see interrupt section).

SPI Manual Chip Select Control

In some applications, manual control of the

active select line can be useful. Setting the

SPICSLO bit of the SPICONFIG register forces

the active chip select line to stay low when the

SPI transaction is completed in Master mode.

When the SPICSLO bit is cleared, the Chip

select line returns to its inactive state.

TABLE 84: (SPICONFIG) SPI CONFIG REGISTER - SFR E6H

7

6

-

5

4

SPICSLO

FSONCS3

SPILOAD

3

-

2

1

0

SPIRXOVIE

SPIRXAVIE

SPITXEMPIE

Bit

7

Mnemonic

SPICSLO

Function

Manual CS up (Master mode)

0 = The CSx goes low when

transmission begins and returns

to high when it ends.

SPI Manual Load Control

The SPI can generate a LOAD pulse on the CS3

pin when the SPILOAD bit is set. This is useful

for some D/A converters and avoids having to

use a separate I/O pin for this purpose.

1 = The CSx stays low after

transmission ends. The user

must clear this bit for the CSx

line to return high.

-

6

5

-

FSONCS3

This bit sends the frame select

pulse on CS3.

4

SPILOAD

This bit sends load pulse on

CS3.

3

2

-

SPIRXOVIE

SPI Receiver overrun interrupt

enable.

1

0

SPIRXAVIE

SPI Receiver available interrupt

enable.

SPI Transmitter empty interrupt

enable.

SPITXEMPIE

The SPIIRQSTAT register contains the

interrupts flags associated with the SPI

interface.

Monitoring these bits allows polling the control of

the SPI interface.

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VMX51C1020

do{

SPI Frame Select Control

dacvall = dacvall + 1;

if( dacvall==0xff)

{

It’s also possible to generate a positive pulse on

the CS3 pin of the SPI interface by setting the

FSONCS3 bit of the SPICONFIG register. This

feature can be used to generate a Frame Select

signal required by some DSP compatible

devices without requiring the use of a separate

I/O pin.

dacvalh = dacvalh +1;

dacvall = 0x00;

}

send16-bitdac( dacvalh, dacvall);

}while( (dacvall != 0xff) && (dacvalh != 0xff) );

do{

dacvall = dacvall - 1;

if( dacvall==0x00)

{

dacvalh = dacvalh - 1;

dacvall = 0xff;

}

send16-bitdac( dacvalh, dacvall);

}while( (dacvall != 0x00) && (dacvalh != 0x00) );

};

Note that when both the SPILOAD and

FSONCS3 are selected, the internal logic give

priority to the Frame Select pulse.

}// End of main()...

SPI Interface to 16-bit D/A Example

//-----------------------------------------------------------------------//

// Send16-bitdac - Send data to 16 bit D/A Converter //

//-----------------------------------------------------------------------//

void send16-bitdac( unsigned char valhigh, unsigned char vallow){

The following is a code example for doing 16-bit

transfers over the the SPI interface.

//

USERFLAGS = 0x00;

while(!SPI_TX_EMPTY){USERFLAGS = SPIIRQSTAT;}

//---------------------------------------------//

// VMIX_SPI_to_dac_interface. c //

//---------------------------------------------//

//

// This demonstration program show the how to interface a 16-bit D/A

// to the VMX51C1020 SPI interface.

SPIRX2TX1 = vallow;

SPIRX3TX0 = valhigh;

//Put LSB of value in SPI transmit buffer

//-> trigger transmission

//Put MSB of value in SPI transmit buffer

//-> trigger transmission

//

#pragma SMALL

#include <vmixreg.h>

do{

//Wait SPI TX empty flag to be activated

USERFLAGS = P2;

USERFLAGS &= 0x08;

// --- function prototypes

}while( USERFLAGS == 0);

}//end of send16-bitdac

//Function Prototype: Send Data to the 16 bit D/A

void send16bitdac( unsigned char valhigh, unsigned char vallow);

// Bit definition

sbit SPI_TX_EMPTY = USERFLAGS^0;

//------------------------------------------------------------------------------//

//

MAIN FUNCTION

//

//-----------------------------------------------------------------------------//

at 0x0100 main (void) {

unsigned char dacvall=0;

unsigned char dacvalh=0;

DIGPWREN |= 0x08;

//LSB of current DAC value

//MSB of current DAC value

//ENABLE SPI INTERFACE

//*** Initialise the SPI interface ****

P2PINCFG |= 0x68;

// config I/O port to allow the SPI

//interface to access the pins

// In this application we only need to configure the 5 upper bit of P2PINCFG

// P2PINCFG bit 7 - SDIEN = 0 -> INPUT (NOT USED)

// P2PINCFG bit 6 - SDOEN = 1 -> OUTPUT TO DAC SDI PIN

// P2PINCFG bit 5 - SCKEN = 1 -> OUTPUT TO DAC SCK PIN

// P2PINCFG bit 4 - SSEN = 0 -> INPUT (NOT USED)

// P2PINCFG bit 3 - CS0EN = 1 -> OUTPUT TO DAC CS PIN

// P2PINCFG bit 2 - CS1EN = 0 -> INPUT (NOT USED)

// P2PINCFG bit 1 - CS2EN = 0 -> INPUT (NOT USED)

// P2PINCFG bit 0 - CS3EN = 0 -> INPUT (NOT USED)

SPICTRL = 0x25;

// SPI ctrl: OSC/16, CS0, phase=0, pol=0, master

// SPICK BIT 7:5 = 001 -> SPI CLK SPEED = OSC/2

// SPICS BIT 4:3 = 00 -> CS0 LINE IS ACTIVE

// SPICKPH BIT 2 = 1 SPI CLK PHASE

// SPICKPOL BIT 1 = 0 SPI CLOCK POLARITY

// SPIMA_SL BIT 0 = 1 -> SET SPI IN MASTER MODE

SPICONFIG = 0x00;

// SPI CONFIG: auto CSLO, no FS, NO Load, clear IRQ flags

// SPICSLO BIT 7 = 0 AUTOMATIC CHIP SELECT CONTROL

// UNSUSED BIT 6 = 0

// FSONCS3 BIT 5 = 0 Do not send FrameSelect Signal on CS3

// SPILOAD BIT 4 = 0 do not Sen the Low pulse on CS3

// UNUSED BIT 3 = 0

// SPIRXOVIE BIT 2 = 0 Dont enable SPI RX Overrun IRQ

// SPIRXAVIE BIT 1 = 0 Dont enable SPI RX AVAILLABLE IRQ

// SPITXEMPIE BIT 0 = 0 Dont Enable SPI TX EMPTY IRQ

SPISIZE = 0x0F;

// SPI SIZE: 16-bits

// GENERATE A TRIANGLE WAVE ON THE DAC OUTPUT

while(1){

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VMX51C1020

The SPI also includes double buffering for data

reception. Once a data reception is completed,

the RX interrupt is activated and the data is

transferred into the SPI RX buffer. At this point,

the SPI interface can receive more data.

However, the processor must have retrieved the

first data stream before the second data stream

reception is complete, otherwise a data overrun

will occur and the SPI RX overrun interrupt will

be activated, if enabled.

SPI Interrupt Example

The following provides an example of basic SPI

configuration and Interrupt handling.

//-------------------------------------------------------------------------------//

// Sample C code for SPI RX & TX interrupt set-up

//-------------------------------------------------------------------------------//

//

#pragma SMALL

#include <vmixreg.h>

at 0x0100 main (void) {

DIGPWREN = 0x08;

P2PINCFG = 0x4F;

SPICONFIG = 0x03;

SPISIZE = 0x07;

// Enable SPI

// Set pads direction

// Enable Rx_avail + TX_empty

// SPI SIZE: 8 bits

IEN0 |= 0x80;

IEN1 |= 0x06;

// Enable all interrupts

// Enable SPI Txempty + RXavail interrupt

SPIRX3TX0 = valhigh;

//Put MSB of value in SPI transmit buffer

//-> trigger transmission

Do{

}while(1)

}//end of main()

//---------------------------------------------------------------------------//

// SPI TX Empty Interrupt function

//---------------------------------------------------------------------------//

void int_2_spi_tx (void) interrupt 9

{

IEN0 &= 0x7F;

// Disable all interrupts

/*-------------------------*/

/* Interrupt code here*/

/*-------------------------*/

IRCON &= 0xFD;

IEN0 |= 0x80;

}

// Clear flag SPITXIF

// Enable all interrupts

//---------------------------------------------------------------------------//

// SPI RX availlable function

//---------------------------------------------------------------------------//

void int_2_spi_rx (void) interrupt 10

{

IEN0 &= 0x7F;

// Disable all interrupts

/*-------------------------*/

/* Interrupt code here*/

/*-------------------------*/

IRCON &= 0xFB;

IEN0 |= 0x80;

}

// Clear flag SPIRXIF

// Enable all interrupts

//---------------------------------------------------------------------------//

Due to the double buffering of the SPI interface,

an SPI TX empty interrupt will be activated as

soon as the data to be transmitted is written into

the SPI interface transmit buffer. If data is

subsequently written into the SPI transmit buffer

before the original data has been transmitted,

the TX empty interrupt will only be activated

when the original data has been fully

transmitted.

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VMX51C1020

The I2CIRQSTAT register provides the status of

the I²C interface operation and monitors the I²C

bus status.

I²C Interface

The VMX51C1020 includes an I²C compatible

communication interface that can be configured

in Master mode or in Slave mode.

TABLE 88: (I2CIRQSTAT) I2C INTERRUPT STATUS - SFR DDH

7

6

5

4

I2CGOTSTOP

I2CNOACK

I2CSDA

I2CDATACK

I²C Control Registers

3

2

1

0

I2CIDLE

I2CRXOV

I2CRXAV

I2CTXEMP

The I2CRXTX SFR register is used to retrieve

and transmit data on the I²C interface.

Bit

7

Mnemonic

Function

This means that the slave

has received a stop (this bit is

read only). Reset only when

the master begins a new

transmission.

Flag that indicates that no

acknowledge has been

received. Is reset at the start

of the next transaction

TABLE86: (I2CRXTX) I2C DATA BUFFER - SFR DEH

7

6

5

4

3

2

1

0

I2CSGOTSTOP

I2CNOACK

I2CRXTX [7:0]

Bit

Mnemonic

Function

I2C Data Receiver / Transmitter

buffer

7:0

I2CRXTX[7:0]

6

The I2CCONFIG register serves to configure the

operation of the VMX51C1020 I²C interface.

The following table describes the I2CCONFIG

register bits.

5

4

3

I2CSDA

I2CDATACK

I2CIDLE

Value of SDA line.

Data acknowledge phase.

Indicates that I2C is idle

2

1

0

I2CRXOV

I2CRXAV

I2CTXEMP

I2C Receiver overrun

I2C Receiver available

I2C Transmitter empty

TABLE 87: (I2CCONFIG) I2C CONFIGURATION - SFR DAH

7

6

5

4

I2CMASKID

I2CRXOVIE

I2CRXDAVIE

I2CTXEMPIE

The I2CCHIPID register holds the VMX51C1020

I²C interface ID as well as the status bit that

indicates if the last byte monitored on the I²C

interface was destined for the VMX51C1020 or

not.

3

2

1

0

I2CMANACK

I2CACKMODE

I2CMSTOP

I2CMASTER

Bit

Mnemonic

Function

7

This is used to mask the chip ID

when you have only two devices.

Therefore in a transaction, rather

that receiving the chip ID first,

you will receive the first packet of

data.

I2CMASKID

6

5

4

3

I2C Receiver overrun interrupt

enable

I2C Receiver available interrupt

enable

I2C Transmitter empty interrupt

enable

1= Manual acknowledge line

goes to 0

I2CRXOVIE

I2CRXDAVIE

I2CTXEMPIE

I2CMANACK

0= Manual acknowledge line

goes to 1

2

I2CACKMODE Used only with Master Rx, Master

Tx, and Slave Rx.

1= Manual Acknowledge on

0= Manual Acknowledge off

1

0

I2CMSTOP

I2C Master receiver stops at next

acknowledge phase. (read during

data phase)

I2C Master mode enable

1= I2C interface is Master

0= I2C interface is Slave

I2CMASTER

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VMX51C1020

The reset value of this register is 0x42,

corresponding to an I²C Chip ID of 0x21. The

chip ID value of the VMX51C1020 can be

dynamically changed by writing the desired ID

into the I2CCHIPID register (see following table).

formula is used to calculate the I²C clock

frequency in Master mode.

I²C Clk =

________f_osc__________

[8 x (I2CCLKCTRL)]

TABLE 89: (I2CCHIPID) I2C CHIP ID - SFR DCH

7

6

5

4

3

2

1

0

I2CID [6:0]

I2CWID

The following table provides examples of I²C

clock (on SCL pin) speeds for various setting of

Bit

7:1

Mnemonic

I2CID[6:0]

Function

The value of this chip’s ID

Read Only and is used only in

slave mode.

the I2CCLKCTRL register when using

14.75MHz oscillator to drive the VMX51C1020.

a

0:The .ID received corresponds

to the I2CID

1: The ID received do not

correspond to the I2CID

0

I2WID

I2CCLKCTRL Value

I2C Clock (SCL Value)

920kHz

01h

03h

07h

13h

27h

C7h

461KHz

230KHz

92KHz

46KHz

The I2WID bit is “read only” and used only in

Slave mode and is an indicator of whether the

transaction is targeted to the VMX1020 device.

9.2KHz

When the I²C interface is configured for slave

modethe I2CCLKCTRL is not used

If the device ID sent by the Master device

corresponds to the I2CID value stored in the

I2CCHIPID, the I2WID bit will be cleared to 0 by

the I2C module. If the transaction was destined

for another I2C slave device, the I2WID bit will

be set to 1.

TABLE 90: (I2CCLKCTRL) I2C CLOCK CONTROL - SFR DBH

7

6

5

4

3

2

1

0

I2CCLKCTRL [7:0]

Bit

Mnemonic

Function

7:0

I2CCLKCTRL

I2C Clock speed control

The I2WID value is valid at the moment the

device ID transmission from the master device

on the I²C bus has completee.

In the case where the I²C RX available interrupt

is activated, once the device ID is received, an

I²C RX available interrupt will be triggered. The

interrupt service routine should then monitor the

I2WID bit in order to establish if the transaction

is destined for this VMX1020 device.

If the I2WID bit is set to 1, the I²C interrupt

service routine can be terminated and there

won’t be another I²C Rx available interrupt until

the next I²C transaction.

If the I2WID bit is cleared, the RX Available

interrupt, if enabled, will be triggered for each

data byte received.

I²C Clock Speed

The VMX51C1020’s I²C communication speed is

fully configurable.

Control of the I²C communication speed enabled

via the I2CCLKCTRL register. The following

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page 53 of 80

VMX51C1020

I²C Interface Interrupts

Reading the value of the I2CRXTX register

resets the I2CRXAV bit. Once started, the I²C

byte read process will continue until the Master

generates a STOP condition.

The I²C interface has a dedicated interrupt

vector located at address 0x5B. Three flags

(see below) share the I²C interrupt vector and

can be used to monitor the I²C interface status

making it possible to activate the I²C interrupt.

When the I²C interface is configured as a

Master, setting the I2CMSTOP bit of the

I2CCONFIG register to a 1 will result in the I²C

interface generating a STOP condition after the

reception of the next byte.

I2CTXEMP:

I2CRXAV:

I2CRXOV:

Is set to 1 when the transmit buffer is

empty

Is set to 1 when data byte reception

completes.

Is set to 1 if a new byte reception

completes before the previous data in

the reception buffer is read, resulting in

a data collision.

In Master Mode, it’s possible to manually control

the operation of the acknowledged timing when

receiving data. To do this, you must first set the

I2CMANACK bit of the I2CCONFIG register to 1.

Then, once you have received a byte, you can

manually control the acknowledge level by

clearing or setting the I2CMANACK bit.

These flags can all trigger the I²C interrupt if

their corresponding bit in the I2CCONFIG

register is set to one.

Note: The VMX51C1020 I²C Interface is not

compatible with the I²C multi-master

mode.

In the case where more than one of these flags

can activate an I²C interrupt, the interrupt

service routine is left to figure out which

condition generated the interrupt.

Slave I²C Operation

The VMX51C1020 I²C interface can be

Note that the I2CRXAV, I2CTXEMP and

I2CRXOV flags can still be polled if their

corresponding interrupt enable flag is cleared.

Therefore they can still be used to monitor

status.

configured as

a

Slave by clearing the

I2CMASTER bit of the I2CCONFIG register.

In Slave mode, the VMX51C1020 has no control

over the rate or timing of the data exchange that

occurs on the I²C bus. Therefore, in Slave

mode, it is preferable to manage the

transactions using the I²C interrupts.

Master I²C Operation

In Master mode, the VMX51C1020 I²C interface

controls the I²C bus transfers.

In order to

configure the I²C interface as a Master, the

I2CMASTER bit of the I2CCONFIG register

must be set to one.

The I2CMASKID bit, when set, will configure the

Slave device to mask the received ID byte and

receive the data directly. This is useful when

only two devices are present on the I²C bus.

Once the I²C interface is configured, sending

data to a Slave device connected to the bus is

done by writing the data into the I2CRXTX

register.

Note: When

the

VMX51C1020

starts

transmitting data in Slave mode, it will

continually transmit the value present in

the I²C transmit register as long as the

Master provides the clock signal or until

the Master device generates a STOP

condition

Before sending data to a Slave device, a byte

containing the target device’s chip ID and

Read/Write bit must be sent to it.

A master mode data read is triggered by reading

the I2CRXAV (bit 1) of the I2CIRQSTAT

register. The data is present on the I2CRXTX

register when the I2CRXAV bit is set.

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VMX51C1020

Errata:

I²C EEPROM Interface Example

Program

The VMX1020 I²C Interface has a critical timing

issue when the device is configured as a Slave

and transmits multiple data bytes. Single byte

transmission in slave mode is not effected.

The following provides an example program

using the VMX51C1020 I²C interface for

performing read and write operations to an

externally connected EEPROM device.

The condition arises if the Master device

releases the SDA line at the same time it brings

the SCL line low for the Acknowledge phase.

#pragma SMALL

#include <vmixreg.h>

// --- Function prototypes

unsigned char eeread(idata unsigned char, idata unsigned char);

void eewrite(idata unsigned char, idata unsigned char, unsigned char);

In order for the VMX1020 I²C Slave transmission

to work properly for multiple bytes, the Master

device MUST release the SDA line AFTER the

SCL negative edge.

// - Global variables

idata unsigned char

irqcptr=0x00;

sbit I2C_TX_EMPTY = USERFLAGS^0;

sbit I2C_RX_AVAIL = USERFLAGS^1;

sbit I2C_IS_IDLE = USERFLAGS^3;

sbit I2C_NO_ACK = USERFLAGS^6;

For this reason it is not possible to have a

VMX1020 device configured as an I²C Master

and VMX1020 devices configured as I²C Slaves

on the same I²C bus. Unless data transmitted

from VMX1020 I²C Slaves to the I²C Master is

done one byte at a time.

//-------------------------------------------------------------------------------//

//

MAIN FUNCTION

//

//------------------------------------------------------------------------------//

void main (void){

unsigned char x=0;

DIGPWREN = 0x13;

//Enable the I2C peripheral

//…To about 100KHZ...

//*** configure I2C Speed.

I2CCLKCTRL = 0x013;

//*** Configure the interrupts

IEN0 |= 0x81;

//Enable Ext INT0 interrupt + main

//*** infinite loop waiting for ext IRQ

while(1){

};

}// End of main()...

//-------------------------------------------------------------------------------//

// EXT INT0 interrupt

//

// When the External interrupt 0 is triggered read and write

// operations are performed on the EEPROM

//-------------------------------------------------------------------------------//

void int_ext_0 (void) interrupt 0 {

// Local variables declaration

idata unsigned char eedata;

idata unsigned char adrsh =0;

idata unsigned char adrsl =0;

idata int adrs =0;

//

IEN0 &= 0x7F;

//disable ext0 interrupt

//(Masked for debugger compatibility)

//Write irqcptr into the EEPROM at adrs 0x0100

eewrite( 0x01,0x00,irqcptr);

irqcptr = irqcptr + 1;

//Increment the Interrupt counter

//Perform an EEPROM read at address 0x100

eedata = eeread(0x01, 0x00);

delay1ms(100);

IEN0 = 0x81;

//Debo delay for the switch on INT0

// enable all interrupts + int_0 (Removed

//for debugger compatibility)

//

}// end of EXT INT 0

//---------------------------------------------------------------------------------//

// INDIVIDUALS FUNCTIONS //

//--------------------------------------------------------------------------------//

//-----------------------------------------------------------------//

// EEREAD - EEPROM Random Read //

//----------------------------------------------------------------//

unsigned char eeread(idata unsigned char adrsh, idata unsigned char adrsl)

{

idata unsigned char x=0;

idata unsigned char readvalue=0;

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VMX51C1020

I2CCONFIG = 0x03;

//I2C MASTER MODE NO INTERRUPT

I2CRXTX = 0xA8;

//SEND 24LC64 ADRS + write COMMAND

USERFLAGS = 0x00;

while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}

I2CRXTX = adrsh;

//SEND 24LC64 ADRSH

USERFLAGS = 0x00;

while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}

I2CRXTX = adrsl;

//SEND 24LC64 ADRSL

USERFLAGS = 0x00;

while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}

USERFLAGS = 0x00;

//wait for I2C interface to be idle

while(!I2C_IS_IDLE){USERFLAGS = I2CIRQSTAT;}

I2CCONFIG &= 0xFD;

I2CCONFIG |= 0x02;

I2CRXTX = 0xA9;

//set Master Rx Stop, only 1 byte to receive

// Chip ID read

USERFLAGS = 0x00;

while(!I2C_RX_AVAIL){USERFLAGS = I2CIRQSTAT;}

readvalue = I2CRXTX;

USERFLAGS = 0x00;

while(!I2C_IS_IDLE){USERFLAGS = I2CIRQSTAT;}

//Wait for I2C IDLE

return

readvalue;

}//End of EEREAD

//----------------------------------------------------------------//

// EEWRITE - EEPROM Random WRITE //

//----------------------------------------------------------------//

void eewrite(idata unsigned char adrsh, idata unsigned char adrsl, unsigned char

eedata)

{

idata unsigned char x;

I2CCONFIG = 0x01;

I2CRXTX = 0xA8;

//I2C MASTER MODE NO INTERRUPT

//SEND EEPROM ADRS + READ

//COMMAND

USERFLAGS = 0x00;

while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}

I2CRXTX = adrsh;

//SEND ADRSH

USERFLAGS = 0x00;

while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}

I2CRXTX = adrsl;

//SEND ADRSL

USERFLAGS = 0x00;

while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}

I2CRXTX = eedata;

//SEND 24LC64 DATA and wait

//for I2C bus IDLE

USERFLAGS = 0x00;

while(!I2C_IS_IDLE){USERFLAGS = I2CIRQSTAT;}

///--Wait Write operation to end

I2CCONFIG = 0x01;

//I2C Master Mode no Interrupt

do{

I2CRXTX = 0xA8;

USERFLAGS = 0x00;

//Send 24LC64 Adrs +read Command

while(!I2C_TX_EMPTY){USERFLAGS = I2CIRQSTAT;}

USERFLAGS = I2CIRQSTAT;

}while(I2C_NO_ACK);

delay1ms(5);

//5ms delay for EEPROM write

}// End of EEPROM Write

_________________________________________________________________________________________________

www.ramtron.com page 56 of 80

VMX51C1020

Analog Signal Path

Internal Reference and PGA

The VMX51C1020 implements a complete

single chip acquisition system by integrating the

following analog peripherals:

The VMX51C1020 provides a temperature

calibrated internal bandgap reference coupled

with a programmable gain amplifier.

o

12-bit A/D converter having 4 external

inputs as well as 3 internal connections

to the Operational amplifier and Current

source input and output for a total of 7

inputs. The ADC conversion rate is

programmable up to 10KHz

Internal Bandgap reference and PGA

1 Programmable current source

2 Digital potentiometers

The programmable gain amplifier’s role is to

amplify the bandgap output to 2.7 volts and

provide the drive required for the ADC reference

input and current source.

Both the bandgap and the PGA are calibrated

during production and their associated

calibration registers are automatically loaded

with the appropriate calibration vectors when the

device is reset.

o

1 Digital switch

The following figure provides a block diagram of

the VMX51C1020’s analog peripherals and their

connection.

The bandgap and PGA calibration vectors are

stored into the BGAPCAL and PGACAL SFR

registers when a reset occurs. It is possible for

the user program to overwrite the contents of

those registers.

FIGURE 35: ANALOG SIGNAL PATH OF THE VMX51C1020

TABLE 91: (BGAPCAL) BAND-GAP CALIBRATION VECTOR REGISTER - SFR B3H

AIN0

AIN1

AIN2

AIN3

VBGAP

7

6

5

4

3

2

1

0

ISRCOUT/TA

BANDGAP

PGA

BGAPCAL [7:0]

Reserved

unused

Bit

7:0

Mnemonic

BGAPCAL

Function

Band-gap data calibration

200mV

800mV

XTVREF

TABLE 92: (PGACAL) PGA CALIBRATION VECTOR REGISTER - SFR B4H

AIN0

AIN1

AIN2

AIN3

ISRCIN

OPOUT

7

6

5

4

3

2

1

0

PGACAL [7:0]

A/D

Bit

7:0

Mnemonic

PGACAL

Function

OPOUT

RESERVED

ISRCIN

8

MSBs of PGA Calibration

Vector (LSBit is on ISRCCAL1)

ISRCOUT

Using the VMX51C1020 Internal

Reference

POT1

POT2

SW1

The on-chip calibrated bandgap or the external

reference provides the basis for all derived on-

chip voltages. These signals serve as reference

for the ADC and the current source.

The configuration and setup up of the

VMX51C1020’s internal reference is done by

setting bits 0 and 1 of the ANALOGPWREN

register to 1. This powers on the bandgap and

the PGA, respectively.

Analog Peripheral Power Control

Selection of the internal/ external reference, the

multiplexer’s current source drive, ADC control,

and the respective power downs for these

peripherals

are

controlled

via

the

ANALOGPWREN SFR registers.

_________________________________________________________________________________________________

www.ramtron.com page 57 of 80

VMX51C1020

Use of the internal reference requires the

addition of two external tank capacitors on the

XTVREF pin.

The external reference voltage source can be

set from 0.5 to 3.5 volts and must provide

sufficient drive to operate the ADC load.

These capacitors consist of one 4.7uF to 10uF

Tantalum capacitor in parallel with one 0.1uF

Ceramic capacitor.

FIGURE 38: EXTERNAL REFERENCE CONNECTION TO THE XTVREF PIN

XTVREF

The following shows the connection of the tank

capacitors to the XTVREF pin

4.7uF

to

10uF

V

0.1uF

FIGURE 36: TANK CAPACITORS CONNECTION TO THE XTVREF PIN

2.7V

XTVREF

4.7uF

Warning:

0.1uF

to

10uF

When an external reference source is

applied to the XTVREF pin, it is

mandatory not to power-on the PGA.

The internal bandgap reference should

also be kept de-activated.

The VMX51C1020 internal reference can also

be used as an external reference provided that

the load on the XTVREF pin is kept to a

minimum. The following table shows the typical

effect of loading on the XTVREF voltage.

Reference Impact on the

Programmable Current Source

FIGURE 37: TANK CAPACITORS CONNECTION TO THE XTVREF PIN

The Programmable Current Source uses the

same reference as the ADC for its operation,

therefore, using an external reference will have

a direct impact on the current source output.

2.75

2.70

The 200/800mV current source reference

voltage, calibrated at 2.7V will change in a linear

fashion according to the voltage present on the

XTVREF pin.

2.65

0.0

1.0

2.0

3.0

4.0

5.0

Load current on XTVREF (mA)

It is recommended that the external load on the

XTVREF pin be less than 1mA.

For example, in the case where the reference

voltage applied to the XTVREF pin is 3V, the

current source reference voltage will be scaled

up by a factor of [VXTVREF/2.7V] to 222mV and

889mV respectively.

Note: A stabilization delay of more than 1ms

should be provided between the activation of the

bandgap, the PGA and the first A/D conversion

or measurement made on the programmable

current source.

A/D Converter

The VMX51C1020 includes a feature rich, highly

configurable on-chip 12-bit A/D converter.

Using an External Reference

An external reference can be used to drive the

VMX51C1020 ADC and the programmable

current source instead of the internal reference.

The A/D conversion data is output as unsigned

12-bit binary, with 1 LSB = Full Scale/4096. The

following figure describes the ideal transfer

function for the ADC.

_________________________________________________________________________________________________

www.ramtron.com page 58 of 80

VMX51C1020

FIGURE 39: IDEAL A/D CONVERTER TRANSFER FUNCTION

OUTPUT

CODE

TABLE 93: (ADCD0LO) ADC CHANNEL 0 DATA REGISTER, LOW BYTE - SFR A6H

1111_1111_1111

1111_1111_1110

1111_1111_1101

Bit

Mnemonic

ADCD0LO

Function

1111_1111_1100

1 LSB = XTVREF / 4096

7:0

ADC channel 0 low

TABLE 94: (ADCD0HI) ADC CHANNEL 0 DATA REGISTER, HIGH BYTE - SFR A7H

Bit

3:0

Mnemonic

ADCD0HI

Function

ADC channel 0 high

0000_0000_0011

0000_0000_0010

0000_0000_0001

0000_0000_0000

TABLE 95: (ADCD1LO) ADC CHANNEL 1 DATA REGISTER, LOW BYTE - SFR A9H

7

6

5

4

3

2

1

0

XTVREF

ADCD1LO [7:0]

0V

The A/D converter includes a system that

provides the ability to trigger automatic periodic

conversions of up to 10kHz without processor

intervention.

Bit

7:0

Mnemonic

ADCD1LO

Function

ADC channel 1 low

TABLE 96: (ADCD1HI) ADC CHANNEL 1 DATA REGISTER, HIGH BYTE - SFR AAH

7

-

6

-

5

-

4

-

3

2

1

0

ADCD1HI [3:0]

Once the conversion is complete, the A/D

system can activate an interrupt that can wake-

up the processor (assuming it has been put into

idle mode) or automatically throttle the

processor clock to full speed.

Bit

3:0

Mnemonic

ADCD1HI

Function

ADC channel 1 high

TABLE 97: (ADCD2LO) ADC CHANNEL 2 DATA REGISTER, LOW BYTE - SFR ABH

7

6

5

4

3

2

1

0

ADCD2LO [7:0]

The VMX51C1020 A/D converter can also be

configured to perform the conversion on one

specific channel or on four consecutive channels

(in round-robin fashion).

Bit

7:0

Mnemonic

ADCD2LO

Function

ADC channel 2 low

TABLE 98: (ADCD2HI) ADC CHANNEL 2 DATA REGISTER, HIGH BYTE - SFR ACH

7

-

6

-

5

-

4

-

3

2

1

0

ADCD2HI [3:0]

These features make the A/D adaptable for

many applications.

Bit

7:4

3:0

Mnemonic

-

ADCD2HI

Function

-

ADC channel 2 high

The following paragraphs describe the

VMX51C1020’s A/D converter register features.

TABLE 99: (ADCD3LO) ADC CHANNEL 3 DATA REGISTER, LOW BYTE - SFR ADH

7

6

5

4

3

2

1

0

ADCD3LO [7:0]

ADC Data Registers

Bit

7:0

Mnemonic

ADCD3LO

Function

ADC channel 3 low

The ADC data registers hold the ADC

conversion results. The ADCDxLO register(s)

hold the 8 Least Significant Bits (LSBs) of the

conversion results while the ADCDxHI

register(s) hold the 4 Most Significant Bits (MSB)

of the conversion results.

TABLE 100: (ADCD3HI) ADC CHANNEL 3 DATA REGISTER, HIGH BYTE - SFR AEH

7

-

6

-

5

-

4

-

3

2

1

0

ADCD3HI [3:0]

Bit

7:4

3:0

Mnemonic

-

ADCD3HI

Function

-

ADC channel 3 high

ADC Input Selection

A/D conversions can be performed on a single

channel, sequentially on the four lower

channels, or sequentially on the four upper

channels of the ADC input multiplexer.

An input buffer is present on each of the four

external ADC inputs (ADIN0 to AIN3)

These buffers must be enabled before a

conversion can take place on the ADC AIN0-

_________________________________________________________________________________________________

www.ramtron.com page 59 of 80

VMX51C1020

AIN3 inputs. These buffers are enabling by

setting the corresponding bits of the lower nibble

(AIEN [3:0]) of the INMUXCTRL register to 1.

implement continuous conversions at a rate

defined by the Conversion Rate register.

When the CONT bit is set to 0, the A/D operates

in “One Shot” mode, initiating a conversion when

the ONESHOT bit of the ADCCONTRL register

is set.

TABLE 101: (INMUXCTRL) ANALOG INPUT MULTIPLEXER CONTROL REGISTER -

SFR B5H

7

-

6

5

4

3

2

1

0

ADCINSEL [2:0]

AINEN [3:0]

Bit

7

Mnemonic

-

Function

ADC One Channel/ Four Channel Conversion

-

6:4

ADCINSEL[2:0] ADC Input Select

000 - AIN0

The VMX51C1020’s ADC includes a feature that

renders it possible to perform a conversion on

one specific channel or on four consecutive

channels.

001 - AIN1

010 - AIN2

011 - AIN3

100 - OPOUT

101 - VSR

110 - ISRCIN

111 - ISRCOUT

Analog Input Enable

This feature minimizes the load on the processor

when reading more than one ADC input is

required.

3:0

AINEN[3:0]

The upper four bits of the INMUXCTRL register

are used to define the channel on which the

conversion will take place when the ADC is set

to perform the conversion on one specific

channel.

The ONECHAN bit of the ADCCTRL register

controls this feature. When the ONECHAN is

set to 1, the conversion will take place on the

channel selected by the INMUXCTRL register.

Once the conversion is completed, the result will

be put into the ADCD0LO and ADCD0HI

registers

ADC Control Register

The ADCCTRL register is the main register used

for control and operation of the ADC.

When the ONECHAN bit is set to 0, the

conversion, once triggered, will be done

sequentially on four channels and the

conversion results will be placed into the

ADCDxLO and ADCDxHI registers.

TABLE 102: (ADCCTRL) ADC CONTROL REGISTER - SFR A2H

7

6

5

1

4

ADCIRQCLR XVREFCAP

ADCIRQ

3

2

1

0

Bit 6 of the INMUXCTRL register controls

whether the conversion will take place on the

four upper channels of the input multiplexer or

the 4 lower channels.

ADCIE

ONECHAN

CONT

ONESHOT

Bit

7

Mnemonic

Function

ADC interrupt clear

Writing 1 Clears interrupt

Always keep this bit at 1

Keep this bit = 1

Read ADC Interrupt Flag

Write 1 generate ADC IRQ

ADC interrupt enable

1 = Conversion is performed on

one channel

ADCIRQCLR

6

5

4

XVREFCAP

Reserved = 1

ADCIRQ

3

2

ADCIE

ONECHAN

Specified ADCINSEL

0 = Conversion is performed on

4 ADC channels

1

0

CONT

1 = Enable ADC continuous

conversion

1 = Force a single conversion

on 1 or 4 channels

ONESHOT

ADC Continuous/One Shot Conversion

The CONT bit sets the ADC conversion mode.

When the CONT bit is set to 1, the ADC will

_________________________________________________________________________________________________

www.ramtron.com page 60 of 80

VMX51C1020

ADC Clock Source Configuration

ADC Conversion Rate Configuration

A/D converter derives its clock source from the

main VMX51C1020 clock. The frequency of the

ADC clock should be set between 250kHz to

1.25MHz

The VMX51C1020’s ADC conversion rate, when

configured in continuous mode is defined by the

24-bit A/D Conversion Rate register that serves

as the time base for triggering the ADC

conversion process.

Configuration of the ADC clock source

frequency is done by adjusting the value of the

ADCCLKDIV register. The following equation is

used to calculate the ADC reference clock value.

The following equation is used to calculate the

value of the conversion rate.

Conversion Rate Equation:

ADC Clock Reference Equation:

Conversion rate registers value (24-bit) =

f_OSC

Conv_Rate

ADC Clk ref =

f_OSC

4x (ADCCDIV +1)

The conversion rate register is accessible using

three SFR registers as follows:

The ADC conversion requires 111 ADC clock

cycles to perform the conversion on one

channel.

TABLE 104: (ADCCONVRLOW)ADC CONVERSION RATE REGISTER LOW BYTE -

SFR A3H

Bit

Mnemonic

Function

7:0

ADCCONVRLOW Conversion rate low byte

The following table provides recommended

ADCCLKDIV register values versus conversion

rate. The numbers given are conservative

figures and derived from a 14.74MHz clock

TABLE 105: (ADCCONVRMED) ADC CONVERSION RATE REGISTER MED BYTE -

SFR A4H

Bit

7:0

Mnemonic

Function

ADCCONVRMED Conversion rate medium byte

TABLE 106: (ADCCONVRHIGH) ADC CONVERSION RATE REGISTER HIGH BYTE -

SFR A5H

ADCCLKDIV

Maximum Conv. Rate*

10500 Hz

8000 Hz

0x02

0x03

Bit

Mnemonic

Function

7:0

ADCCONVRHIGH Conversion rate high byte

0x05

5000 Hz

0x07

0x08

0x09

4000 Hz

3500 Hz

3200 Hz

The following table provides examples of typical

values versus conversion rate.

0x0B

0x0D, 0x0E, 0x0F

2500 Hz

2200 Hz

Conversion

Rate

1Hz

ADC conv. rate register value.

Fosc= 14.74MHz

E10000h

10Hz

100Hz

1kHz

168000h

024000h

003999h

* The maximum conversion rate is for the single

channel condition. If the conversion is

performed on 4 channels, divide the maximum

conversion rate by 4. For example to perform

the conversion at 2.5KHz on four channels, the

ADCCLKDIV register should be set to 0x02 (4x

2500Hz =10KHz)

2.5kHz

5kHz

8kHz

00170Ah

000B85h

000733h

0005C2h

10kHz

TABLE 103: (ADCCLKDIV) ADC CLOCK DIVISION CONTROL REGISTER - SFR 95H

7

6

5

4

3

2

1

0

ADCCLKDIV [7:0]

Bit

7:0

Mnemonic

ADCCLKDIV[7:0]

Function

ADC clock divider

_________________________________________________________________________________________________

www.ramtron.com page 61 of 80

VMX51C1020

//*** Configure the interrupts

IEN0 |= 0x80;

ADC Status Register

//enable main interrupt

IEN1 |= 0x020;

//Enable ADC Interrupt

while(1);

}// End of main()...

//Infinite loop waiting ADC interrupts

The ADC shares interrupt vector 0x6B with the

Interrupt on Port 1 Change and the Compare

//-----------------------------------------------------------------------//

// ADC INTERRUPT ROUTINE

and Capture Unit 3.

To enable the ADC

//-----------------------------------------------------------------------//

void int_adc (void) interrupt 13 {

idata int value = 0;

interrupt, the ADCIE bit of the ADCCTRL

register must be set. Before or at the same time

this bit is set, the ADCIRQCLR and the ADCIRQ

bits must be cleared. The ADCPCIE bit of the

IEN1 register must also be set, as well as the

EA bit of the IEN0 register.

IEN0 &= 0x7F;

//disable ext0 interrupts

ADCCTRL |=0x80;

//Clear ADC interrupt

// Read ADC channel 0

value = ADCD0HI;

value = valeur*256;

value = valeur + ADCD0LO;

(…)

Once the ADC interrupt occurs, ADC Interrupt

must be cleared by writing a ‘1’ into the

ADCINTCLR bit of the ADCCTRL register. The

ADCIF flag in the IRCON register must also be

cleared.

// Read ADC channel 3

value = ADCD3HI;

value = valeur*256;

value = valeur + ADCD3LO;

(…)

IRCON &= 0xDF;

ADCCTRL |=0xFA;

IEN0 |= 0x80;

//Clear adc irq flag

//prepare adc for next acquisition

// enable all interrupts

}// End of ADC IRQ

(…)

A/D Converter Example

The following provides example code for the A/D

converter. The first section of the code covers

interrupt setup/module configuration whereas

the second section is the interrupt function itself.

Warning:

When using the ADC, make sure the

output multiplexer controlled by the

TAEN bit of the ANALOGPWREN

register (92h) is powered down at all

times, otherwise, the signal present on

the ISRCOUT can be routed back to the

selected ADC input, causing conversion

errors.

Sample C code to setup the A/D converter:

//-----------------------------------------------------------------------//

//

MAIN FUNCTION

//-----------------------------------------------------------------------//

(…)

at 0x0100 void main (void) {

//*** Initialize the Analog Peripherals ***

ANALOGPWREN = 0x07;

//Enable the following analog

//peripherals: ISRC, ADC, PGA,

// BGAP. TA = OFF (mandatory)

//Configure the ADC and Start it

ADCCLKDIV=0x0F;

ADCCONVRLOW=0x00;

ADCCONVRMED=0x40;

ADCCONVRHIGH =0x02;

//SET ADC CLOCK SOURCE

//CONFIGURE CONVERSION RATE

//= 100Hz @ 14.74 MHz

INMUXCTRL=0x0F;

ADCCTRL=0xEA;

//Enable All ADC External inputs

//buffers and select ADCI0

//Configure the ADC as follow:

//bit 7: =1 ADCIRQ Clear

//Bit 6: =1 XVREFCAP (always)

//Bit 5: =1 (always)

//Bit 4: =0 = ADCIRQ (don’t care)

//Bit 3: =1 = ADC IRQ enable

//Bit 2: =0 conversion on 4

//channels

//Bit 1: =1 Continuous conversion

//Bit 0: =0 No single shot mode

_________________________________________________________________________________________________

www.ramtron.com page 62 of 80

VMX51C1020

Programmable Current Source

TABLE 108: (ISRCCAL2) CURRENT SOURCE CALIBRATION VECTOR FOR 800MV

FEEDBACK VALUE - SFR BDH

7

-

6

5

4

3

2

1

0

The VMX51C1020 includes a programmable

current source used to drive external devices

such as resistive sensors connected between

the ISRCOUT and ISRCIN pins

ISRCCAL2 [6:0]

Bit

7

Mnemonic

-

Function

-

Calibration Value for ISRC

feedback of 800mV

6:0

ISRCCAL2[6:0]

To ensure current output stability, the current

source provides a feedback input, ISRCIN. The

feedback is voltage controlled and can be

dynamically set to either 200mV or 800mV.

Placing a resistor between the ISRC pin and the

ground defines the output current of the current

source.

Current Source Setup Example

The following provides setup examples for the

current source.

Enabling the Current Source using the 200mV

reference:

The VMX51C1020 current Source can drive

currents up to 500µA when the reference is set

to 800mV.

MOV

ANALOGPWREN,#00110011B

;Enable Analog peripherals

;Bit 7: OPAMPEN = 0 Op-Amp OFF

;Bit 6: DIGPOTEN= 0 Dig Pot OFF

;Bit 5: ISRCSEL = 1 ISRC 800mV

;Bit 4: ISRCEN = 1 ISRC ON

;Bit 3: TAEN = 0 TA output OFF

;Bit 2: ADCEN = 0 ADC OFF

;Bit 1: PGAEN = 1 PGA ON

FIGURE 40: PROGRAMMABLE CURRENT SOURCE TO EXCITE SENSOR

To A/D

;Bit 0: BGAPEN = 1 BandGap ON

ISRCOUT

Enabling the Current Source using the 200mV

reference:

Sensor

ISRCIN

;MOV

ANALOGPWREN,#00010011B

Rref

;Enable Analog peripherals

;Bit 7: OPAMPEN = 0 Op-Amp OFF

;Bit 6: DIGPOTEN= 0 Dig Pot OFF

;Bit 5: ISRCSEL = 0 ISRC 200mV

;Bit 4: ISRCEN = 1 ISRC ON

;Bit 3: TAEN = 0 TA output OFF

;Bit 2: ADCEN = 0 ADC OFF

;Bit 1: PGAEN = 1 PGA ON

200 mV

800 mV

;Bit 0: BGAPEN = 1 BandGap ON

As shown above, a resistive device (sensor)

must be connected between the ISRCOUT and

the ISRCIN.

In order to perform A/D conversion of the

voltage present at the terminal of the current

source, there is an internal link between each of

the ISRCOUT and ISRCIN pins as well as the

Input multiplexer of the A/D converter.

TABLE 107: (ISRCCAL1) CURRENT SOURCE CALIBRATION VECTOR FOR 200MV

FEEDBACK VALUE - SFR BCH

7

6

5

4

3

2

1

0

PGACAL0

ISRCCAL1 [6:0]

Bit

7

Mnemonic

PGACAL0

Function

Bit 0 of PGACAL

Calibration Value for ISRC

feedback of 200mV

6:0

ISRCCAL1[6:0]

_________________________________________________________________________________________________

www.ramtron.com page 63 of 80

VMX51C1020

Digital Potentiometers

R_{potentiometer *}= [ 256 - DIGPOTx[7:0] ] x 30k

The

VMX51C1020

has

two

digital

256

*Potentiometer value

potentiometers that are controlled by DIGPOTx

registers (DIGPOT1, DIGPOT2) that can be

used in applications such as:

Digital Potentiometer Setup Example

Only two instructions are required to enable and

configure the digital Potentiometers of the

VMX51C1020:

o

Gain control

Offset adjustment

A/D input attenuation

Digitally controlled filter

MOV

ANALOGPWREN,#01000000B

DIGPOT1,#0C0h

DIGPOT2,#040h

;SET POT1 to 25% of Max Pot value

;SET POT2 to 75% of Max Pot value

FIGURE 41: DIGITAL POTENTIOMETER FUNCTIONAL DIAGRAM

POTx

A

POTx

B

Operational Amplifier

The VMX51C1020 is equipped with an

operational amplifier. This op-amp can be used

for a wide array of analog applications such as:

o

Gain control

Offset Control

Reference buffering

Integrator

Other standard op amp applications

DIGPOTx register

TABLE 109: (DIGPOT1) DIG. POTENTIOMETER 1 CONTROL REGISTER - SFR BAH

7

6

5

4

3

2

1

0

DIGPOT1 [7:0]

The op-amp on the VMX51C1020 has an open-

loop gain of 100dB; a unity gain bandwidth of

5MHz and it is able to drive a 1kO and 40pf load.

The slew rate of the Op-Amp is 7V/µs and the

output voltage can swing between 25mV and

4.975 Volts (10kO load).

Bit

7-0

Mnemonic

DIGPOT1

Function

Potentiometer 1 Value

TABLE 110: (DIGPOT2) DIG. POTENTIOMETER 2 CONTROL REGISTER - SFR BBH

7

6

5

4

3

2

1

0

DIGPOT2 [7:0]

Bit

7-0

Mnemonic

DIGPOT2

Function

Potentiometer 2 Value

To activate the Operational Amplifier, the

OPAMPEN bit (bit 7) of the ANALOGPWREN

register (SFR 92h) must be set to 1.

The digital potentiometers are floating devices,

meaning that there are no restrictions on the

voltage present on their terminals as long as

they are kept within the nominal operating range

of the VMX51C1020.

Warning:

If the VMX51C1020 Op-Amp inputs are

left floating, it should be kept in power

down to prevent risk of oscillation.

The current flow through the potentiometers

should be limited to 5mA max.

The digital potentiometer maximum nominal

resistance is 30k +/- 2Kohms from device to

device. On a given device the two digital

potentiometer values usually match within 1%.

Before using the digital potentiometers, they

must first be enabled by setting bit 6 of the

ANALOGPWREN register (92h) to 1. The

potentiometer value is governed by the following

equation.

_________________________________________________________________________________________________

www.ramtron.com page 64 of 80

VMX51C1020

Analog Output Multiplexer

Digitally Controlled Switches

The VMX51C1020’s analog output multiplexer is

used for production test purposes and provides

access to internal test points of the analog signal

path.. It can however, be used in applications,

but due to its high intrinsic impedance, care

must be taken with respect to loading.

The VMX51C1020 include a digital switch

composed of 4 sub-switches connected in

parallel. These sub-switches can be individually

controlled by writing to the SFR register at B7h.

FIGURE 42: SWITCH FUNCTIONAL DIAGRAM

The analog output multiplexer shares its output

with the current source output and therefore

must be disabled when the current source or the

ADC is used.

SW1A

SW1B

Inversely, when the analog output multiplexer is

used, the current source must be powered

down.

sw1d sw1c sw1b sw1a

x

SWITCHCTRL register

The following table summarizes the analog

output multiplexer select line settings.

The switch “ON” resistance is between 50 and

100 Ohms depending on the number of sub-

switches being used. If, for example, one sub-

switch is closed, the switch resistance will be

about 100 Ohms, and if all 4 switches are

closed, the switch resistance will go down to

about 50 Ohms.

TABLE 112: (OUTMUXCTRL) ANALOG OUTPUT MULTIPLEXER CONTROL REGISTER

- SFR B6H

7

-

6

-

5

-

4

-

3

-

2

1

0

TAOUTSEL [2:0]

Bit

7:3

2:0

Mnemonic

Unused

TAOUTSEL[2:0] Signal output on TA

Function

Unused

TABLE 111: (SWITCHCTRL) USER SWITCHES CONTROL REGISTERS - SFR B7H

7

6

5

4

3

2

1

0

000 – AIN0

001 – AIN1

Not Used but implemented

SWTCH1 [3:0]

010 – AIN2

011 – AIN3

100 – VBGAP

101 – reserved

110 – unused

111 – unused

Bit

7:4

Mnemonic

User Flags

Function

Not used but implemented bits

Can be used as general

purpose storage

Switch 1 control (composed of 4

3:0

SWITCH1[3:0] individual switches each bit

controlled)

The upper 4 bits of the SWITCHCTRL register

can be used as general purpose flags.

_________________________________________________________________________________________________

www.ramtron.com page 65 of 80

VMX51C1020

VMX51C1020 Interrupts

Interrupt Enable Registers

The VMX51C1020 is a highly integrated device

incorporating a vast number of peripherals for

which a comprehensive set of 29 interrupt

sources sharing 12 interrupt vectors is available.

Most of the VMX51C1020 peripherals can

generate an interrupt, providing feedback to the

MCU core that an event has occurred or a task

has been completed.

The following tables describe the interrupt

enable registers their associated bit functions:

TABLE 114: (IEN0) INTERRUPT ENABLE REGISTER 0 - SFR A8H

7

6

5

4

EA

WDT

T2IE

S0IE

3

2

1

0

T1IE

INT1IE

T0IE

INT0IE

Bit

7

Mnemonic Function

The following features are key VMX51C1020

interrupt features.

EA

General Interrupt control

0 = Disable all Enabled interrupts

1 = Authorize all Enabled interrupts

Watchdog timer refresh flag. This bit

is used to initiate a refresh of the

watchdog timer. In order to prevent

an unintentional reset, the watchdog

timer the user must set this bit

directly before SWDT.

Timer 2 Overflow / external Reload

interrupt

6

WDT

o

Each

digital

peripheral

on

the

VMX51C1020 has an interrupt channel.

The SPI, UARTs and I²C all have event

specific flag bits.

When the processor is in IDLE mode, an

interrupt may be used to wake it up.

The processor can run at full speed

during interrupt routines.

5

T2IE

0 = Disable

1 = Enable

4

3

2

1

0

S0IE

Uart0 interrupt.

0 = Disable

1 = Enable

The following table summarizes the interrupt

sources, natural priority and the associated

interrupt vector addresses of the VMX51C1020.

T1IE

Timer 1 overflow interrupt

0 = Disable

1 = Enable

INT1IE

T0IE

External Interrupt 1

0 = Disable

1 = Enable

Timer 0 overflow interrupt

0 = Disable

TABLE 113: INTERRUPT SOURCES AND NATURAL PRIORITY

Interrupt

Reserved

Interrupt Vector

0E43h

INT0

0003h

UART1

0083h

1 = Enable

TIMER 0

000Bh

INT0IE

External Interrupt 0

0 = Disable

SPI Tx

004Bh

INT1

0013h

1 = Enable

SPI RX & SPI RX OVERRUN

/ COMPINT0

TIMER 1

I2C (Tx, Rx, Rx Overrun)

/ COMPINT1

UART0

MULT/ACCU 32bit Overflow /

COMPINT2

TIMER 2: T2 Overflow, T2EX

ADC and interrupt on Port 1

change (8 int.) / COMPINT3

0053h

001Bh

005Bh

0023h

0063h

002Bh

006Bh

It is also possible to program the interrupts to

wake-up the processor from an IDLE condition

or force its clock to throttle up to full speed when

an interrupt condition occurs.

_________________________________________________________________________________________________

www.ramtron.com page 66 of 80

VMX51C1020

Timer2 Compare Mode Impact on

Interrupts

The SPI RX (and RXOV), I²C, MULT/ACCU and

ADC Interrupts are shared with the four Timer2

Compare and Capture Unit interrupts.

TABLE 115: (IEN1) INTERRUPT ENABLE 1 REGISTER -SFR E8H

7

6

5

4

T2EXIE

SWDT

ADCPCIE

MACOVIE

3

2

1

0

I2CIE

SPIRXOVIE

SPITEIE

reserved

Bit

7

Mnemonic

T2EXIE

Function

T2EX interrupt Enable

0 = Disable

When the Compare and Capture Units of Timer2

are configured in Compare Mode via CCEN

register, the Compare and Capture unit takes

control of one interrupt vector as shown below.

1 = Enable

6

SWDT

Watchdog timer start/refresh flag.

Set to activate/refresh the watchdog

timer. When directly set after setting

WDT, a watchdog timer refresh is

performed. Bit SWDT is reset.

ADC and Port change interrupt

0 = Disable

1 = Enable

MULT/ACCU Overflow 32 bits

interrupt

FIGURE 43: COMPARE CAPTURE INTERRUPT STRUCUTRE

COMPINT0

1

Interrupt

5

4

ADCPCIE

MACOVIE

Interrupt Vector

0053h

SPI Rx &

RxOV INT

0

CCEN(1,0) = 1,0

COMPINT1

1

Interrupt

0 = Disable

1 = Enable

I2C Interrupt

0 = Disable

Interrupt Vector

005Bh

I2C INT

0

3

2

1

0

I2CIE

CCEN(3,2) = 1,0

COMPINT2

1 = Enable

1

SPIRXOVIE SPI Rx avail + Overrun

0 = Disable

Interrupt

Interrupt Vector

0063h

MAC

Overflow INT

1 = Enable

SPI Tx Empty interrupt

0 = Disable

0

SPITEIE

reserved

CCEN(5,4) = 1,0

COMPINT3

1 = Enable

1

Interrupt

Interrupt Vector

006Bh

ADC & Port

Change INT

0

TABLE 116: (IEN2) INTERRUPT ENABLE 2 REGISTER - SFR 9AH

CCEN(7,6) = 1,0

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

S1IE

The impact of this is that the corresponding

peripheral interrupt, if enabled, will be blocked.

The output signal from the comparison module

will be routed to the Interrupt system and the

control lines will be dedicated to the Compare

and Capture unit.

Bit

7-1

0

Mnemonic Function

-

S1IE

-

UART 1 Interrupt

0 = Disable UART 1 Interrupt

1 = Enable UART 1 Interrupt

This interrupt control “take over” is specific to

each individual Compare and Capture unit. For

example if Compare and Capture Unit number 2

is configured to generate a PWM signal on P1.2,

the MULT/ACCU overflow interrupt, if enabled,

will be dedicated to the Compare and Capture

Unit number 2 and the SPI, I²C and ADC

interrupts won’t be affected.

_________________________________________________________________________________________________

www.ramtron.com page 67 of 80

VMX51C1020

TABLE 118: (IP0) INTERRUPT PRIORITY REGISTER 0 - SFR B8H

Interrupt Status Flags

7

6

5

4

3

2

1

0

The IRCON register is used to identify the

UF8

WDTSTAT

IP0 [5:0]

source of an interrupt.

Before exitingthe

Bit

7

6

Mnemonic

UF8

Function

User Flag bit

interrupt service routine, the IRCON register bit

that corresponds with the serviced interrupt

should be cleared.

WDTSTAT Watchdog timer status flag. Set to 1

by hardware when the watchdog

timer overflows. Must be cleared

manually

TABLE 117: (IRCON) INTERRUPT REQUEST CONTROL REGISTER - SFR 91H

7

6

5

4

5

IP0.5

Port1

Change

Timer 2

ADC

T2EXIF

T2IF

ADCIF

MACIF

4

3

2

IP0.4

IP0.3

IP0.2

UART0

Timer 1

External

INT1

Timer 0

Interrupt

External

INT0

-

MULT/ACCU

I2C

SPI RX

available

SPI TX

Empty

3

2

1

0

I2CIF

SPIRXIF

SPITXIF

Reserved

-

Bit

7

Mnemonic

T2EXIF

Function

1

0

IP0.1

IP0.0

Timer 2 external reload flag

This bit informs the user

whether an interrupt has been

generated from T2EX, if the

T2EXIE is enabled.

Timer 2 interrupt flag

A/D converter interrupt request

flag/ port 0 change.

External

INT 0

UART1

Table 119: (IP1) Interrupt Priority Register 1 - SFR B9h

6

5

T2IF

ADCIF /

COMPINT3

7

-

6

-

5

4

3

2

1

0

IP1 [5:0]

/ COMPINT3

Bit

Mnemonic

Function

4

3

2

MACIF /

COMPINT2

I2CIF /

COMPINT1

SPIRXIF /

COMPINT0

SPITXIF

MULT/ACCU unit interrupt

request flag / COMPINT2

I²C interrupt request flag

/ COMPINT1

RX available flag SPI + RX

Overrun / / COMPINT0

TX empty flag SPI

7

6

5

-

IP1.5

Port1

Change

Timer 2

ADC

4

3

2

IP1.4

IP1.3

IP1.2

UART0

Timer 1

External

INT1

Timer 0

Interrupt

External

INT0

-

MULT/ACCU

I2C

SPI RX

available

SPI TX

Empty

1

0

-

Reserved

1

0

IP1.1

IP1.0

External

INT 0

Interrupt Priority Register

UART1

All of the VMX51C1020’s interrupt sources are

combined into groups with four levels of priority.

Configuring the IP0 and IP1 registers makes it

possible to change the priority order of the

peripheral interrupts in order give higher priority

to a given interrupt that belongs to a given

group.

These groups can be programmed individually

to one of the four priority levels: from Level0 to

Level3 with Level3 being the highest priority.

TABLE 120: INTERRUPT GROUPS

The IP0 and IP1 registers serve to define the

specific priority of each of the interrupt groups.

By default, when the IP0 and IP1 registers are at

reset state 00h, the natural priority order of the

interrupts shown previously are in force.

Bit

IP1.5, IP0.5

Interrupt Group

Port1

Change

Timer 2

ADC

IP1.4, IP0.4

IP1.3, IP0.3

IP1.2, IP0.2

UART0

Timer 1

External

INT1

-

MULT/ACCU

I2C

SPI RX

available

SPI TX

Empty

-

IP1.1, IP0.1

IP1.0, IP0.0

Timer 0

Interrupt

External

INT0

External

INT 0

UART1

_________________________________________________________________________________________________

www.ramtron.com page 68 of 80

VMX51C1020

The respective values of the IP1.x and IP0.x bits

define the priority level of the interrupt group vs.

the other interrupt groups as follows.

TABLE 121: INTERRUPT PRIORITY LEVEL

IP1.x

IP0.x

Priority Level

Level 0 (Low)

Level 1

Level 2

Level 3 (High)

0

1

0

1

0

1

The WDTSTAT bit of the IP0 register is the

Watchdog status flag and is set to 1 by the

hardware whenever a Watchdog Timer overflow

occurs. This bit must be cleared manually.

Finally, bit 7 of the IP0 register can be used as a

general purpose user flag.

_________________________________________________________________________________________________

www.ramtron.com

page 69 of 80

VMX51C1020

Setting up INT0 and INT1 Interrupts

INT0 example

The following provides example code for

interrupt setup and module configuration.

The IT0 and IT1 bits of the TCON register define

whether external interrupts 0 and 1 will be edge

or level triggered.

//---------------------------------------------------------------------------

// Sample C code to setup INT0

//---------------------------------------------------------------------------

#pragma TINY

#include <vmixreg.h>

When an interrupt condition occurs on INT0 or

INT1, the associated interrupt flag IE0 or IE1 will

at 0x0100 void main (void) {

// INT0 Config

be set.

The interrupt flag is automatically

cleared when the interrupt is serviced.

TCON |= 0x01; //Interrupt on INT0 will be caused by a High->Low

//edge on the pin

// Enable INT0 interrupts

TABLE 122: (TCON) TIMER 0, TIMER 1 TIMER/COUNTER CONTROL - SFR 88H

IEN0 |= 0x80;

IEN0 |= 0x01;

// Enable all interrupts

// Enable interrupt INT0

7

6

TR1

5

TF0

4

TR0

TF1

// Wait for INT0…

3

2

1

0

do

IE1

IT1

IE0

IT0

{

}while(1);

//Wait for INT0 interrupts

Bit

7

Mnemonic

TF1

Function

}//end of main function

Timer 1 overflow flag set by hardware

when Timer 1 overflows. This flag can be

cleared by software and is automatically

cleared when interrupt is processed.

Timer 1 Run control bit. If cleared Timer 1

stops.

Timer 0 overflows flag set by hardware

when Timer 0 overflows. This flag can be

cleared by software and is automatically

cleared when interrupt is processed.

Timer 0 Run control bit. If cleared timer 0

stops.

Interrupt 1 edge flag. Set by hardware

when falling edge on external INT1 is

observed. Cleared when interrupt is

processed.

Interrupt 1 type control bit. Selects falling

edge or low level on input pin to cause

interrupt.

//---------------------------------------------------------------------------

// Interrupt Function

void int_ext_0 (void) interrupt 0

{

IEN0 &= 0x7F;

6

5

TR1

TF0

// Disable all interrupts

// Enable all interrupts

/* Put the Interrupt code here*/

IEN0 |= 0x80;

}

4

3

TR0

IE1

//---------------------------------------------------------------------------

INT1 example

The following code example shows the INT1

interrupt setup and module configuration:

2

1

IT1

IE0

//-------------------------------------------------------------------------

// Sample C code to setup INT1

//-------------------------------------------------------------------------

#pragma TINY

Interrupt 0 edge flag. Set by hardware

when falling edge on external pin INT0 is

observed. Cleared when interrupt is

processed.

#include <vmixreg.h>

0

IT0

Interrupt 0 type control bit. Selects falling

edge or low level on input pin to cause

interrupt.

at 0x0100 void main (void) {

// INT1 Config

TCON |= 0x04; //Interrupt on INT1 will be caused by a High->Low

//edge on the pin

// Enable INT1 interrupts

IEN0 |= 0x80;

IEN0 |= 0x04;

// Enable all interrupts

// Enable interrupt INT1

// Wait for INT1…

do

{

}while(1);

//Wait for INT1 interrupts

// Interrupt function

void int_ext_1 (void) interrupt 2

{

IEN0 &= 0x7F;

// Disable all interrupts

/* Put the Interrupt code here*/

IEN0 |= 0x80;

}

// Enable all interrupts

_________________________________________________________________________________________________

www.ramtron.com page 70 of 80

VMX51C1020

UART0 and UART1 Interrupt Example

Interrupt on P1 Change

The following program examples demonstrate

how to initialization the UART0 and UART1

interrupts.

The VMX51C1020 includes an Interrupt on Port

change feature, which is available on the Port1

pins of the VMX51C1020.

//-------------------------------------------------------------------------------

// Sample C code for UART0 and UART1 interrupt example

//-------------------------------------------------------------------------------

#pragma TINY

This feature is like having eight extra external

interrupt inputs sharing the ADC interrupt vector

at address 006Bh and can be very useful for

applications such as switches, keypads, etc.

#include <vmixreg.h>

// --- function prototypes

void txmit0( unsigned char charact);

void txmit1( unsigned char charact);

void uart1Config(void);

To activate this interrupt, the bits corresponding

to the pins being monitored must be set in the

PORTIRQEN register. The ADCPCIE bit in the

IEN1 register must be set as well as the EA bit

of the IEN0 register.

void uart0ws0relcfg(void);

// - Constants definition

sbit UART_TX_EMPTY = USERFLAGS^1;

//---------------------------------------------------------------------------

//

MAIN FUNCTION

//---------------------------------------------------------------------------

at 0x0100 void main (void) {

TABLE 123: (PORTIRQEN) PORT CHANGE IRQ CONFIGURATION - SFR 9FH

// Enable and configure the UART0 & UART1

7

6

5

4

uart0ws0relcfg();

//Configure UART0

P17IEN

P16IEN

P15IEN

P4IEN

uart1Config();

//Configure UART1

3

2

1

0

//*** Configure the interrupts

P13IEN

P12IEN

P11IEN

P10IEN

IEN0 |= 0x91;

IEN2 |= 0x01;

//Enable UART0 Int + enable all int

//Enable UART1 Interrupt

do

Bit

Mnemonic

P17IEN

Function

Port 1.7 IRQ on change enable

0 = Disable

1 = Enable

Port 1.6 IRQ on change enable

0 = Disable

1 = Enable

Port 1.5 IRQ on change enable

0 = Disable

1 = Enable

Port 1.4 IRQ on change enable

0 = Disable

1 = Enable

Port 1.3 IRQ on change enable

0 = Disable

1 = Enable

Port 1.2 IRQ on change enable

0 = Disable

1 = Enable

Port 1.1 IRQ on change enable

0 = Disable

1 = Enable

Port 1.0 IRQ on change enable

0 = Disable

{

}while(1);

// End of main()...

7

6

5

4

3

2

1

0

//Wait for UARTs interrupts

//---------------------------------------------------------------------------

// INTERRUPT ROUTINES

//---------------------------------------------------------------------------

P16IEN

P15IEN

P14IEN

P13IEN

P12IEN

P11IEN

P10IEN

//---------------------------------------------------------------------------

// UART0 interrupt

//

// Retrieve character received in S0BUF and transmit it

// back on UART0

// //-------------------------------------------------------------------------

void int_uart0 (void) interrupt 4 {

IEN0 &= 0x7F;

//disable All interrupts

//--- The only UART0 interrupt source is Rx...

txmit0(S0BUF);

// Return the character

//received on UART0

S0CON = S0CON & 0xFC;

IEN0 |= 0x80;

}// end of UART0 interrupt

//clear R0I & T0I bits

// enable all interrupts

//---------------------------------------------------------------------------

// UART1 interrupt

//

// Retrieve character received in S1BUF and transmit it

// back on UART1

// //---------------------------------------------------------------------------

void int_uart1 (void) interrupt 16 {

1 = Enable

IEN0 &= 0x7F;

//disable All interrupts

The PORTIRQSTAT register monitors the

occurrence of the Interrupt on port change.

This register serves to define which P1 pin has

changed when an interrupt occurs.

//--- The only UART1 interrupt source is Rx...

txmit1(S1BUF);

// Return the character

// received on UART1

// clear both R1I & T1I bits

// enable all interrupts

S1CON = S1CON & 0xFC;

IEN0 |= 0x80;

}// end of UART1 interrupt

Note:

See UART0 / UART1 section for configuration examples and

TXMITx functions

_________________________________________________________________________________________________

www.ramtron.com page 71 of 80

VMX51C1020

TABLE 124: (PORTIRQSTAT) PORT CHANGE IRQ STATUS - SFR A1H

The following provides an assembler example

for configuration of the Interrupt on Port1 pin

change and how it is shared with the ADC

interrupt.

7

6

5

4

P17ISTAT

P16ISTAT

P15ISTAT

P14ISTAT

3

2

1

0

P13ISTAT

P12ISTAT

P11ISTAT

P10ISTAT

include VMIXreg.INC

;*** INTERRUPT VECTORS JUMP TABLE *

Bit

Mnemonic

P17ISTAT

Function

Port 1.7 changed

0 = No

1 = Yes

Port 1.6 changed

0 = No

1 = Yes

Port 1.5 changed

0 = No

1 = Yes

Port 1.4 changed

0 = No

1 = Yes

Port 1.3 changed

0 = No

1 = Yes

Port 1.2 changed

0 = No

1 = Yes

Port 1.1 changed

0 = No

1 = Yes

Port 1.0 changed

0 = No

7

6

5

4

3

2

1

0

ORG 0000H

ORG 006BH

;BOOT ORIGIN VECTOR

START

;INT ADC and P1 change interrupt

INT_ADC_P1

LJMP

P16ISTAT

P15ISTAT

P14ISTAT

P13ISTAT

P12ISTAT

P11ISTAT

P10ISTAT

;*** MAIN PROGRAM

ORG 0100h

START:

MOV

DIGPWREN,#01H

P2PINCFG,#0FFH

;ENABLE TIMER 2

;*** Initialise Port change interrupt on P1.0 - P1.7

MOV

PORTIRQSTAT,#00H

PORTIRQEN,#11111111B

;*** Initialise the ADC, BGAP, PGA Operation

MOV ANALOGPWREN,#07h

;Select CH0 as ADC input + Enable input buffer + Adc clk

MOV

INMUXCTRL,#0Fh

ADCCLKDIV,#0Fh

ADCCONVRLOW,#000h

;*** configure ADC Conversion Rate

MOV

ADCCONVRMED,#080h

ADCCONVRHIGH,#016h

ADCCTRL,#11111010b

;***Activate All interrupts + (serial port for debugger support)

MOV

;*** Enable ADC interrupt

MOV

IEN0,#090H

IEN1,#020H

1 = Yes

;***Wait IRQ…

WAITIRQ: LJMP

WAITIRQ

FIGURE 44: APPLICATION EXAMPLE OF PORT CHANGE INTERRUPT

ORG 0200h

;************************************************************************

Numeric Keypad

;* IRQ ROUTINE: IRQADC + P1Change

;************************************************************************

INT_ADC_P1:

1

4

7

*

2

5

8

0

3

6

9

#

;MOV

IEN0,#00h ;DISABLE ALL INTERRUPT

P1.4

P1.5

;***Check if IRQ was caused by Port Change

;***If PORTIRQSTAT = 00h -> IRQ comes from ADC

MOV

JZ

A,PORTIRQSTAT

CASE_ADC

P1.6

;*** If interrupt was caused by Port 1, change

CASE_P0CHG:

VMX51C1020

P1.7

MOV

PORTIRQSTAT,#00H

;*** Perform other instructions related to Port1 change IRQ

;(...)

;*** Jump to Interrupt end

AJMP

ENDADCP1INT

P1.3

P1.2

P1.1

;*** If interrupt was caused by ADC

CASE_ADC:

ANL

ADCCTRL,#11110011b

;***Reset ADC interrupt flags & Reset ADC for next acquisition

ORL

ADCCTRL,#080h

ADCCTRL,#11111010b

;*** Perform other instructions related to Port1 change IRQ

;(...)

;** End of ADC and Port 1 Change interrupt

ENDADCP0INT:

ANL

IRCON,#11011111b

;***Enable All interrupts before exiting

; MOV

RETI

IEN0,#080H

END

_________________________________________________________________________________________________

www.ramtron.com page 72 of 80

VMX51C1020

The Clock Control Circuit

FIGURE 45: CLOCK TIMING WHEN AN INTERRUPT OCCURS

The VMX51C1020’s clock control circuit allows

dynamic adjustment of the clock from which the

processor and the peripherals derive their clock

source. This allows reduction of overall power

consumption by modulating the operating

frequency according to processing requirements

or peripheral use.

INTERNAL

CLOCK

INTERRUPT

SET

INTERRUPT

CLEARED

Once the interrupt is cleared, the VMX51C1020

returns to the selected operating speed as

defined by the MCKDIV [3:0] bits of the

CLKDIVCTRL register.

A typical application for this can be portable

acquisition systems in which significant power

savings can be achieved by lowering the

operating frequency between A/D conversions

and automatically throttling it back to full speed

when an A/D interrupt is generated. Note that

A/D converter operation is not affected by the

Clock Control Unit.

When the IRQNORMSPD bit is set, the

VMX51C1020 will continue to operate at the

selected speed as defined by the MCKDIV [3:0]

bits of the CLKDIVCTRL register.

Note: With the exception of the A/D converter

and analog only peripherals such as the

current source, potentiometers and op-

amp, all the peripheral operating speeds

are affected by the Clock Control circuit

The clock control circuit allows adjusting the

System clock from [Fosc/1] (full speed) down to

[Fosc/512]. The clock division control is done

via the CLKDIVCTRL register located at address

94h of the SFR register area.

TABLE 125: (CLKDIVCTRL) CLOCK DIVISION CONTROL REGISTER -SFR 94H

Software Reset

7

6

-

5

-

4

SOFTRST

IRQNORMSPD

Software reset can be generated by setting the

SOFTRST bit of the CLKDIVCTRL register to 1.

3

2

1

0

MCKDIV [3:0]

Bit

Mnemonic

SOFTRST

Function

Writing 1 into this bit location

provokes a reset. Read as a 0

-

7

6:5

-

0 = Full Speed in IRQ

4

IRQNORMSPD 1 = Selected speed during

IRQs

Master Clock Divisor

0000 – Sys CLK

0001 = SYS /2

0010 = SYS /4

0011 = SYS /8

0100 = SYS /16

3:0

MCKDIV [3:0]

0101 = SYS /32

0110 = SYS /64

0111 = SYS /128

1000 = SYS /256

1001 = SYS /512

(…)

1111 = SYS /512

The value written into the lower nibble of the

CLKDIVCTRL register, MCKDIV[3:0], defines

the clock division ratio.

When the IRQNORMSPD bit is cleared, the

VMX51C1020 will run at the maximum operating

speed when an interrupt occurs (see following

figure).

_________________________________________________________________________________________________

www.ramtron.com

page 73 of 80

VMX51C1020

STOP Mode

Power-on/Brown-Out Reset

In this mode, in contrast to IDLE mode, all

internal clocking shuts down. In order to enter

STOP mode, the user must set the STOP bit of

the PCON register. The CPU will exit this state

only when a non-clocked external interrupt or

reset occurs (internal interrupts are not possible

because they require clocking activity).

The VMX51C1020 includes

a

Power-On-

Reset/Brown-Out detector circuit that ensures

the VMX51C1020 enters and stays in the reset

state as long as the supply voltage is below the

reset threshold voltage (order of 3.7 – 4.0 Volts).

In most applications, the VMX51C1020 requires

no external components to perform a Power-on

Reset when the device is powered on.

The following interrupts can restart the

processor from STOP mode: Reset, INT0, INT1,

SPI Rx/Rx Overrun, and the I²C interface.

The VMX51C1020 includes a RESET input for

applications in which external Reset control is

required. The reset pin includes an internal pull-

up resistor. When a Power-on reset occurs, all

SFR locations return to their default values and

peripherals are disabled.

FIGURE 46: POWER MANAGEMENT ON THE VMX51C1020

IDLE

CLKCPU

GATE

STOP

CLK FOR

CPU

INTERRUPT

REQUEST

CLKPER

GATE

CLK FOR

Errata Note:

PERIPHERALS

CLK

The VMX51C1020 may fail to exit the reset state if the

supply voltage drops below the reset threshold, but

not below 3V. For applications where this condition

can occur, use an external supply monitoring circuit to

reset the device.

The following table describes the power control

register of the VMX51C1020.

TABLE 126: (PCON) POWER CONTROL (CPU) - SFR 87H

7

6

-

5

-

4

-

3

GF1

2

GF0

1

0

SMOD

STOP

IDLE

Processor Power Control

Bit

7

Mnemonic

SMOD

Function

The speed in Mode 2 of Serial Port 0

is controlled by this bit. When

SMOD= 1, f_clk/32. This bit is also

significant in Mode 1 and 3, as it

adds a factor of 2 to the baud rate.

The processor power management unit has two

modes of operation: IDLE and STOP mode.

6

5

4

3

2

1

-

IDLE Mode

GF1

GF0

STOP

Not used for power management

When the VMX51C1020 is in IDLE mode, the

processor clock is halted. However, the internal

clock and peripherals continue to run. The

power consumption drops because the CPU is

not active. As soon as an interrupt or reset

occurs, the CPU exits the IDLE mode.

Not used for power management

Stop mode control bit. Setting this bit

turns on the STOP Mode. STOP bit

is always read as 0.

IDLE mode control bit. Setting this bit

turns on the IDLE mode. IDLE bit is

always read as 0.

0

IDLE

In order to enter IDLE mode, the user must set

the IDLE bit of the PCON register. Any enabled

interrupts will force the processor to exit IDLE

mode

_________________________________________________________________________________________________

www.ramtron.com page 74 of 80

VMX51C1020

Watchdog Timer

TABLE 128: (IP0) INTERRUPT PRIORITY REGISTER 0 - SFR B8H

7

6

5

4

3

2

1

0

UF8

WDTSTAT

IP0 [5:0]

The VMX51C1020’s Watchdog Timer is used to

monitor program operation and reset the

processor in the case where the program code

would not be able to refresh the Watchdog

before its timeout period has lapsed. This can

come about from an event that results in the

Program Counter executing faulty or incorrect

code and inhibiting the device from doing its

intended job.

Bit

Mnemonic

UF8

Function

User Flag bit

7

6

WDTSTAT Watchdog timer status flag. Set to 1

by hardware when the watchdog

timer overflows. Must be cleared

manually

5

IP0.5

Port1

Change

Timer 2

ADC

4

3

2

IP0.4

IP0.3

IP0.2

UART0

Timer 1

External

INT1

-

MULT/ACCU

I2C

SPI RX

availlable

SPI TX

Empty

The Watchdog Timer consists of a 15-bit counter

composed of two registers (WDTL and WDTH)

and a reload register (WDTREL). See following

figure.

-

1

0

IP0.1

IP0.0

Timer 0

Interrupt

External

INT0

External

INT 0

UART1

FIGURE 47: WATCH DOG TIMER

The WDTSTAT bit of the IP0 register is the

Watchdog status flag. This bit is set to 1 by the

hardware whenever a Watchdog Timer overflow

occurs. This bit must be cleared manually.

SYSCLK ÷ 12

÷2

0

WDTL

7

8

WDTH

14

WDTR

Setting-up the Watchdog Timer

÷16

Control of the Watchdog Timer’s is enabled by

the following bits:

0

WDTREL

7

Control Logic

Bit

Location

DIGPWREN.6

IEN0.6

Role

WDTR

(Refresh)

WDTS

(Start)

WDOGEN

WDTR

WDTS

Watchdog timer Enable

Watchdog timer refresh flag

Watchdog Timer Start bit

IEN1.6

The WDTL and WDTH registers are not

accessible from the SFR register. However the

WDTREL register makes it possible to load the

upper 6 bits of the WDTH register.

In order for the Watchdog to begin counting, the

user must set the WDOGEN bit (bit 6) of

DIGPWREN register, as follows:

The PRES bit of the WDTREL register selects

the Clock prescaler that is fed into the Watchdog

Timer.

MOV

DIGPWREN,#x1xxxxxxB

;x=0 or 1 depending

;of other peripherals

;to enable

When PRES = 0, the clock prescaler = 24

When PRES = 1, the clock prescaler = 384

TABLE 127: (WDTREL) WATCHDOG TIMER RELOAD REGISTER - SFR D9H

7

6

5

4

3

2

1

0

PRES

WDTREL [6:0]

Bit

7

Mnemonic

PRES

Function

Pre-scaler select bit. When set, the

Watchdog is clocked through an

additional divide-by-16 pre-scaler.

7-bit reload value for the high-byte

of the Watchdog timer. This value

is loaded into the WDT when a

refresh is triggered by a

6-0

WDTREL

consecutive setting of bits WDT

and SWDT.

_________________________________________________________________________________________________

www.ramtron.com page 75 of 80

VMX51C1020

The value written into the WDTREL register

defines the Delay Time of the Watchdog Timer

asfollows:

*** The Simple way ***

MOV

IEN0,#x1xxxxxxB

IEN1,#x1xxxxxxB

;DIRECT WRITE THAT SET BIT

;WDTR (x = 0 or 1)

;DIRECT WRITE THAT SET BIT

;WDTS (x = 0 or 1)

WDT delay when the WDTREL bit 7 is cleared

In the case where the program makes use of the

interrupts, it is recommended to deactivate

interrupts before the Watch Dog refresh is

performed and reactivate them afterwards.

WDT Delay =

24*[ 32768–(WDTREL(6:0) x 256)]

Fosc

WDT delay when the WDTREL bit 7 is set

b) Watch Dog Timer refresh example 2:

WDT Delay =

384*[ 32768–(WDTREL(6:0) x 256)]

Fosc

*** If Interrupts are used: ***

CLR

MOV

ORL

XCH

MOV

ORL

MOV

SETB

IEN0.7

A,IEN0

A,#01000000B

A,R1

A,IEN1

A,#01000000B

IEN0,R1

IEN1,A

;Deactivate the interrupt

;Retrieve IEN0 content

;set the bit 6 (WDTR)

;Store IENO New Value

;Retrieve IEN1 content

;Set bit 6, (WDTS)

; Set WDTR BIT

;Set WDTS BIT

;Reactivate the Interrupts

The following table provides WDT reload values

and their corresponding delay times

IEN0.7

Fosc

WDTREL

00h

WDT Delay

53.3ms

14.74MHz

Watchdog Timer Reset

4Fh

20.4ms

CCh

347ms

To determine whether the Reset condition was

caused by the Watchdog Timer, the state of the

WDTSTAT bit of the IP0 register should be

monitored. On a standard power on reset

condition, this bit is cleared.

Note: The value present in the CLKDIVCTRL

Register affects the Watchdog Timer Delay time.

The above equations and examples assume that

the CLKDIVCTRL register content is 00h

Starting the Watchdog Timer

To start the Watchdog timer using the hardware

automatic start procedure, the WDTS (IEN1)

and WDTR (IEN0) bits must be set. The

Watchdog will begin to run with default settings,

i.e. all registers will be set to zero.

;*** Do a Watchdog Timer Refresh / Start sequence

SETB

IEN0.6

IEN1.6

;Set the WDTR bit first

;Then without delay set the

;WDTS bit

When the WDT registers enter the state 7FFFh,

the asynchronous signal, WDTS will become

active. This signal will set bit 6 in the IP0 register

and trigger a reset.

To prevent the Watchdog Timer from resetting

the VMX51C1020, you must reset it periodically

by clearing the WDTR and, immediately

afterwards, clear the WDTS bit.

As a security feature to prevent inadvertent

clearing of the Watchdog timer, no delay

(instruction) is allowed between the clearing of

the WDTR and the WDTS bits.

a) Watchdog Timer refresh example 1:

_________________________________________________________________________________________________

www.ramtron.com

page 76 of 80

VMX51C1020

WDT Initialization and Use Example

Program

VMX51C1020 Programming

When the PM pin is set to 1, the I²C interface

becomes the programming interface for the

VMX51C1020’s Flash memory.

ORG 0000H

LJMP

;RESET & WD IRQ VECTOR

START

;*************************************

;* MAIN PROGRAM BEGINNING *

;*************************************

An In-circuit programming interface is easy to

implement at the board level. See VMIX APP-

Note001.

ORG 0100h

;*** Initialize WDT and other peripherals***

MOV

DIGPWREN,#40H

;ENABLE WDT OPERATION

;*** INITIALIZE WATCHDOG TIMER RELOAD VALUE

MOV

WDTREL,#04FH

;The WDTREL register is used to

;define the Delay Time WDT.

Erasing and programming the VMX51C1020’s

;Bit

7

of WDTREL define clock

Flash

programming voltage of 12V. This programming

voltage is supplied/controlled by the

programming hardware/tools.

memory

requires

an

external

;prescalng value

;Bit 6:0 of WDTREL defines the

;upper 7 bits reload value of the

;watchdog Timer 15-bit timer

;*** PERFORM A WDT REFRESH/START SEQUENCE

SETB

IEN0.6

IEN1.6

;Set the WDTR bit first

;Then without delay (instruction)

;set the WDTS bit right after.

;No Delays are permitted between

;setting of the WDTR bit and

;setting of the WDTS bit.

;This is a security feature to

;prevent inadvertent reset/start of

;the WDT

The VMX51C1020 can be programmed using

the Ramtron In-Circuit Programmer.

FIGURE 48: VMX51C1020 PROGRAMMING

;IF other interrupt are enabled,

;It is recommended to disable

;interrupts before refreshing the

;WDT and reactivate them after

;*** Wait WDT Interrupt

WAITWDT:

NOP

;*** If the two following code lines below are put "in-comment", the ;***WDT will

trigger a reset, and the program will restart.

;*** PERFORM A WATCHDOG TIMER REFRESH/START SEQUENCE

;SETB

LJMP

IEN0.6

IEN1.6

WAITWDT

;Set the WDTR bit first

;Then without delay (instruction)

;set the WDTS bit right after.

;No Delays are permitted between

;setting of the WDTR bit and

;setting of WDTS bit.

;This is a security feature to

;prevent inadvertent reset/start of

;the WDT

Target PC Board

5V (optional)

SCL

SDA

VPP 12V

VERSA-ICP

PM

RES - (RESET)

GND

;It is recommended to disable

;interrupts before refreshing the ;WDT

and reactivate them after

_________________________________________________________________________________________________

www.ramtron.com page 77 of 80

VMX51C1020

FIGURE 49: VMX51C1020 DEBUGGER HARDWARE INTERFACE

VMX51C1020 Debugger

VERSA Ware

VMX

Software

The

VMX51C1020

includes

hardware

Debugging features that speed-up embedded

software development time.

Debugger Features

The

VMX51C1020

Debugger

supports

breakpoints and single-stepping of the user

program. It supports retrieval and editing of the

contents of the SFR Registers and RAM

memory contents when a breakpoint is reached

or when the device operates in single-step

mode. Unlike ROM monitor programs that

execute user program instruction at a much

lower speed, the VMX51C1020 Debugger does

not affect program operating speed when in

“Run Mode” before encountering a breakpoint.

To UART0

RS232

Transceiver

VERSA-ICP

Target PC Board

Debugger Software Interface

Debugger Hardware Interface

The VERSA WARE VMX51C1020 / VERSA1

Windows^™software provides an easy to use

user interface for In-Circuit Debugging

The VMX51C1020’s Development System

provides the ideal platform for running the

Debugger. Interfacing to the VMX51C1020’s

Debugger is done via the UART0 serial

interface.

For more details on the VMX51C1020

Debugger,

see

the

“VERSA

WARE

VMX51C1020 - V1 Software User Guide.pdf”

It is possible to run the VMX51C1020 Debugger

on the end user PCB provided that access to the

VMX51C1020’s UART0 is available. However,

a connection to a stand alone In-Circuit

Programmer (ICP) will be required to perform

Flash programming, control of the Reset line,

and to activate the Debugger on the target

VMX51C1020 device.

All documents are accessible on the Ramtron

Inc. website at www.ramtron.com

_________________________________________________________________________________________________

www.ramtron.com page 78 of 80

VMX51C1020

VMX51C1020 64 pin Quad Flat Package

E

E1

10

A2

D

D1

A

VMX51C1020

QFP-64

A1

e

10

64

1

0.30 RAD. TYP.

6

4

A

STANDOFF

0.25

A1

SEATING

PLANE

L

0.20 RAD. TYP.

0.17 MAX

b

BODY +3.20mm Footprint

NOTES:

PACKAGE THICKNESS

2.00

64L

LEADS

Dims.

TOLS.

1) ALL DIMENSIONS ARE IN MILLIMETERS

A

A1

A2

D

MAX.

2.35

0.25MAX

2.00

+.10/-.05

±.25

2) DIMENSIONS SHOWN ARE NOMINAL

WITH TOLERANCES AS INDICATED.

17.20

14.00

17.20

14.00

.88

D1

E

±.10

±.25

3) FOOT LENGTH "L" IS MEASURED AT

GAGE PLANE, 0.25 ABOVE SEATING

PLANE

E1

L

±.10

+.15/-.10

BASIC

±.05

e

.80

b

.35

0º-7º

_________________________________________________________________________________________________

www.ramtron.com page 79 of 80

VMX51C1020

Ordering Information

Device Number Structure

VMX51C1020 Ordering Options

Device Number

Package

Option

QFP-64

Operating

Voltage

4.75V to 5.5V

Temperature

Frequency

VMX51C1020-14-QC

VMX51C1020-14-QCG

*See Errata information below

0°C to +70°C

14.75MHz

4.75V to 5.5V

VMX51C1020 Errata

The VMX51C1020 operating frequency and temperature range have been revised with more conservative values.

The maximum operating frequency specifications of the VMX51C1020 has been revised to 14.75MHz and its operating

temperature range to 0ºC to 70ºC.

These new specifications affect all the VMX51C1020 devices with the markings of VMX51C1020-QAI16.

In order to reflect the specification updates of the VMX51C1020, the new VMX51C1020 devices that have the same silicon

version, features and performances as the VMX51C1020-QAI16 will now be marked VMX51C1020-QAC14.

Disclaimer

Right to make changes - Ramtron reserves the right to make changes to its products - including circuitry, software and services -

without notice at any time. Customers should obtain the most current and relevant information before placing orders.

Use in applications - Ramtron assumes no responsibility or liability for the use of any of its products, and conveys no license or

title under any patent, copyright or mask work right to these products and makes no representations or warranties that these

products are free from patent, copyright or mask work right infringement unless otherwise specified. Customers are responsible

for product design and applications using Ramtron parts. Ramtron assumes no liability for applications assistance or customer

product design.

Life support – Ramtron products are not designed for use in life support systems or devices. Ramtron customers using or selling

Ramtron products for use in such applications do so at their own risk and agree to fully indemnify Ramtron for any damages

resulting from such applications.

Note:

PC is a registered trademark of IBM Corp. Windows is a registered trademark of Microsoft Corp.

I2C is a registered trademark of Philips Corporation. SPI is a registered trademark of Motorola Inc.

All other trademarks are the property of their respective owners.

_________________________________________________________________________________________________

www.ramtron.com page 80 of 80


型号：	VMX51C1020-14-Q-C
厂家：	ETC
描述：	Versa Mix 8051 Mixed-Signal MCU 反之亦然混合8051混合信号MCU
文件：	总80页 (文件大小：3640K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VMX51C1020-14-Q-C [ETC]

相关型号：

VMX51C1020-14-Q-C-G

VMX51C1020-14-Q-C-X

VMX51C1020-14-QC

VMX51C1020-14-QCG

VMX51C900

VMX51C900-25-L

VMX51C900-25-L-G

VMX51C900-25-LG

VMX51C900-25-P

VMX51C900-25-P-G

VMX51C900-25-PG

VMX51C900-25-Q