VPX3224D_技术文档

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

Contents

Page

Section

Title

6

1.

Introduction

7

1.1.

System Architecture

8

2.

Functional Description

Analog Front-End

8

2.1.

8

2.1.1.

2.1.2.

2.1.3.

2.1.4.

2.1.5.

2.1.6.

2.2.

Input Selector

8

Clamping

8

Automatic Gain Control

Analog-to-Digital Converters

ADC Range

8

Digitally Controlled Clock Oscillator

Color Decoder

10

11

12

13

14

15

16

17

18

20

21

22

23

25

2.2.1.

2.2.2.

2.2.3.

2.2.4.

2.2.5.

2.2.6.

2.2.7.

2.2.8.

2.3.

IF-Compensation

Demodulator

Chrominance Filter

Frequency Demodulator

Burst Detection

Color Killer Operation

PAL Compensation/1-H Comb Filter

Luminance Notch Filter

Video Sync Processing

Macrovision Detection (version D4 only)

Component Processing

Horizontal Resizer

2.4.

2.5.

2.5.1.

2.5.2.

2.5.3.

2.5.4.

2.5.5.

2.6.

Skew Correction

Peaking and Coring

YCbCr Color Space

Video Adjustments

Video Output Interface

Output Formats

2.6.1.

2.6.1.1.

2.6.1.2.

2.6.1.3.

2.6.2.

2.6.3.

2.6.4.

2.7.

YUV 4:2:2 with Separate Syncs/ITU-R601

Embedded Reference Headers/ITU-R656

Embedded Timing Codes (BStream)

Bus Shuffler

Output Multiplexer

Output Ports

Video Data Transfer

Single and Double Clock Mode

Half Clock Mode

2.7.1.

2.7.2.

2.8.

Video Reference Signals

HREF

2.8.1.

2.8.2.

2.8.3.

2.8.4.

VREF

Odd/Even Information (FIELD)

VACT

2

Micronas

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

Contents, continued

Page

Section

Title

26

28

29

30

31

33

34

35

36

37

38

39

40

44

2.9.

Operational Modes

Open Mode

2.9.1.

2.9.2.

Scan Mode

2.10.

Windowing the Video Field

Temporal Decimation

Data Slicer

2.11.

2.12.

2.12.1.

2.12.2.

2.12.3.

2.12.3.1.

2.12.3.2.

2.12.3.3.

2.12.3.4.

2.13.

Slicer Features

Data Broadcast Systems

Slicer Functions

Input

Automatic Adaptation

Standard Selection

Output

VBI Data Acquisition

Raw VBI Data

2.13.1.

2.13.2.

2.14.

Sliced VBI Data

Control Interface

Overview

2.14.1.

2.14.2.

2.14.3.

2.14.4.

2.14.5.

2.15.

2

I C-Bus Interface

2

Reset and I C Device Address Selection

Protocol Description

FP Control and Status Registers

Initialization of the VPX

Power-on-Reset

2.15.1.

2.15.2.

2.15.3.

2.16.

Software Reset

Low Power Mode

JTAG Boundary-Scan, Test Access Port (TAP)

General Description

2.16.1.

2.16.2.

2.16.2.1.

2.16.2.2.

2.16.2.3.

2.16.2.4.

2.16.2.5.

2.16.2.6.

2.16.3.

2.16.4.

2.16.4.1.

2.16.4.2.

2.16.4.3.

2.16.4.4.

2.16.4.5.

2.16.4.6.

2.16.4.7.

2.17.

TAP Architecture

TAP Controller

Instruction Register

Boundary Scan Register

Bypass Register

Device Identification Register

Master Mode Data Register

Exception to IEEE 1149.1

IEEE 1149.1–1990 Spec Adherence

Instruction Register

Public Instructions

Self-Test Operation

Test Data Registers

Boundary-Scan Register

Device Identification Register

Performance

Enable/Disable of Output Signals

Micronas

3

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

Contents, continued

Page

Section

Title

45

48

45

47

48

3.

Specifications

3.1.

3.2.

3.3.

3.4.

3.5.

Outline Dimensions

Pin Connections and Short Descriptions

Pin Descriptions

Pin Configuration

Pin Circuits

50

51

52

53

54

55

56

57

58

59

4.

Electrical Characteristics

4.1.

Absolute Maximum Ratings

4.2.

Recommended Operating Conditions

Recommended Analog Video Input Conditions

4.2.1.

4.2.2.

4.2.3.

4.2.4.

4.3.

2

Recommended I C Conditions

Recommended Digital Inputs Levels of RES, OE, TCK, TMS, TDI

Recommended Crystal Characteristics

Characteristics

4.3.1.

4.3.2.

4.3.3.

4.3.4.

4.3.5.

4.3.6.

4.3.7.

4.3.8.

4.3.9.

4.3.10.

4.3.10.1.

Current Consumption

Characteristics, Reset

XTAL Input Characteristics

Characteristics, Analog Front-End and ADCs

Characteristics, Control Bus Interface

Characteristics, JTAG Interface (Test Access Port TAP)

Characteristics, Digital Inputs/Outputs

Clock Signals PIXCLK, LLC, and LLC2

Digital Video Interface

Characteristics, TTL Output Driver

TTL Output Driver Description

60

61

62

63

64

5.

Timing Diagrams

5.1.

5.2.

5.3.

5.4.

5.5.

5.6.

5.7.

5.7.1.

Power-up Sequence

Default Wake-up Selection

Control Bus Timing Diagram

Output Enable by Pin OE

Timing of the Test Access Port TAP

Timing of all Pins connected to the Boundary-Scan-Register-Chain

Timing Diagram of the Digital Video Interface

Characteristics, Clock Signals

65

68

72

6.

Control and Status Registers

6.1.

Overview

2

6.1.1.

6.1.2.

Description of I C Control and Status Registers

Description of FP Control and Status Registers

4

Micronas

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

Contents, continued

Page

Section

Title

83

84

85

7.

Application Notes

7.1.

Differences between VPX 3220A and VPX 322xD

Impact to Signal to Noise Ratio

Control Interface

7.2.

7.3.

7.3.1.

7.3.2.

7.3.3.

7.3.4.

7.3.5.

7.3.6.

7.4.

Symbols

2

Write Data into I C Register

2

Read Data from I C Register

Write Data into FP Register

Read Data from FP Register

Sample Control Code

Xtal Supplier

7.5.

Typical Application

88

8.

Data Sheet History

Micronas

5

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

Video Pixel Decoder

Video Interfacing

– YC C 4:2:2 format

b

r

Release Note: This data sheet describes functions

and characteristics of VPX 322xD–C3 and D4. Revi-

sion bars indicate significant changes to the pre-

vious edition.

– ITU-R 601 compliant output format

– ITU-R 656 compliant output format

– BStream compliant output format

– square pixel format (640 or 768 pixel/line)

– 8-bit or 16-bit synchronous output mode

– 13.5 MHz/16-bit and 27 MHz/8-bit output rate

– VBI bypass and raw ADC data output

1. Introduction

The Video Pixel Decoders VPX 3225D and VPX 3224D

are the second generation of full feature video acquisi-

tion ICs for consumer video and multimedia applica-

tions. All of the processing necessary to convert an ana-

log video signal into a digital component stream have

been integrated onto a single 44-pin IC. Moreover, the

VPX 3225D provides text slicing for intercast, teletext,

and closed caption. Both chips are pin compatible to

VPX 3220A, VPX 3216B, and VPX 3214C. Notable fea-

tures include:

Data Broadcast Support (VPX 3225D only)

– high-performance data slicing in hardware

– multistandard data slicer

• NABTS, WST

• CAPTION (1x,2x), VPS, WSS, Antiope

– full support for

• teletext, intercast, wavetop,

• WebTV for windows, EPG services

Video Decoding

– multistandard color decoding:

• NTSC-M, NTSC-443

• PAL-BGHI, PAL-M, PAL-N, PAL-60

• SECAM

2

– programmable to new standards via I C

– automatic slice level adaptation

– VBI and Full-Field mode

• S-VHS

– NTSC with Y/C comb filter

– data insertion into video stream

– two8-bitvideoA/Dconverterswithclampingandauto-

matic gain control (AGC)

– simultaneous acquisition of teletext, VPS, WSS, and

caption

– four analog inputs with integrated selector for:

• 3 composite video sources (CVBS), or

• 2 Y/C sources (S-VHS), or

Miscellaneous

– 44-pin PLCC package

• 2 composite video sources and one Y/C source.

– total power consumption of below 1 W

– horizontal and vertical sync detection for all standards

2

– I C serial control, 2 different device addresses

– decodes and detects Macrovision 7.1 protected video

(version D4 only)

– singleon-chipclockgeneration, onlyonecrystalneed-

ed for all standards

Video Processing

– user programmable output pins

– power-down mode

– hue, brightness, contrast, and saturation control

– dual window cropping and scaling

– horizontal resizing between 32 and 864 pixels/line

– vertical resizing by line dropping

– high-quality anti-aliasing filter

– IEEE 1149.1 (JTAG) boundary scan interface

Software Support

– MediaCVR Software Suite

• Video for Windows driver

• TV viewer applet, teletext browser

• intercast/wavetop browser

– scaling controlled peaking and coring

– WebTV for Windows

• Video capture and VBI services

6

Micronas

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

1.1. System Architecture

The block diagram (Fig. 1–1) illustrates the signal flow

through the VPX. A sampling stage performs 8-bit A/D

conversion, clamping, andAGC. Thecolordecodersep-

arates the luma and chroma signals, demodulates the

chroma, and filters the luminance. A sync slicer detects

the sync edge and computes the skew relative to the

sample clock. The video processing stage resizes the

YCbCr samples, adjusts the contrast and brightness,

and interpolates the chroma. The text slicer extracts

lines with text information and delivers decoded data

bytes to the video interface.

Note: The VPX 3225D and VPX 3224D are not register

compatible with the VPX 3220A, VPX 3216B, and

VPX 3214C family.

HREF

VREF

FIELD

Sync Processing

Clock Gen.

DCO

Text Slicer

(VPX 3225D only)

A[7:0]

Y

CVBS/Y

Luma Filter

ADC

OEQ

Video Decoder

C C

b

C C

b r

r

Chroma

Demodulator

B[7:0]

Chroma

PIXCLK

LLC

VACT

Line Store

SDA

SCL

I2C

JTAG

Fig. 1–1: Block diagram of the VPX 3224D, VPX 3225D

Micronas

7

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2. Functional Description

pacitors and is generated by digitally controlled current

sources. The clamping level is the back porch of the vid-

eo signal. S-VHS chroma is AC coupled. The input pin

is internally biased to the center of the ADC input range.

The following sections provide an overview of the differ-

ent functional blocks within the VPX. Most of them are

controlled by the Fast Processor (‘FP’) embedded in the

decoder. For controlling, there are two classes of regis-

2

ters: I C registers (directly addressable via I C bus) and

FP-RAM registers (ram memory of the FP; indirectly ad-

2.1.3. Automatic Gain Control

2

dressable via I C bus). For further information, see sec-

A digitally working automatic gain control adjusts the

magnitude of the selected baseband by +6/–4.5 dB in 64

logarithmic steps to the optimal range of the ADC. The

gain of the video input stage including the ADC is 213

steps/V with the AGC set to 0 dB.

tion 2.14.1.

2.1. Analog Front-End

This block provides the analog interfaces to all video in-

puts and mainly carries out analog-to-digital conversion

for the following digital video processing. A block dia-

gram is given in Fig. 2–1.

2.1.4. Analog-to-Digital Converters

Two ADCs are provided to digitize the input signals.

Each converter runs with 20.25 MHz and has 8-bit reso-

lution. An integrated bandgap circuit generates the re-

quired reference voltages for the converters. The two

ADCs are of a 2-stage subranging type.

Clamping, AGC, and clock DCO are digitally controlled.

The control loops are closed by the embedded proces-

sor.

2.1.1. Input Selector

2.1.5. ADC Range

Up to four analog inputs can be connected. Three inputs

(VIN1–3)areforinputofcompositevideoorS-VHSluma

signal. These inputs are clamped to the sync back porch

and are amplified by a variable gain amplifier. Two in-

puts, one dedicated (CIN) and one shared (VIN1), are

for connection of S-VHS carrier-chrominance signal.

The chrominance input is internally biased and has a

fixed gain amplifier.

The ADC input range for the various input signals and

the digital representation is given in Table 2–1 and Fig.

2–2. The corresponding output signal levels of the

VPX 32xx are also shown.

2.1.6. Digitally Controlled Clock Oscillator

The clock generation is also a part of the analog front

end. The crystal oscillator is controlled digitally by the

FP; the clock frequency can be adjusted within

±150 ppm.

2.1.2. Clamping

The composite video input signals are AC coupled to the

IC. The clamping voltage is stored on the coupling ca-

AGC

+6/–4.5 dB

VIN3

CVBS/Y

VIN2

digital CVBS or Luma

CVBS/Y

clamp

bias

ADC

VIN1

CIN

CVBS/Y/C

gain

digital Chroma

system clocks

Chroma

input mux

DCVO

±150

ppm

reference

generation

frequency

20.25 MHz

Fig. 2–1: Analog front-end

8

Micronas

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

Table 2–1: ADC input range for PAL input signal and corresponding output signal ranges

Signal

Input Level [mV

]

pp

ADC

Range

YC C

r b

Output

Range

–6 dB

667

0 dB

1333

1000

700

+4.5 dB

2238

1679

1175

504

[steps]

252

213

149

64

[steps]

CVBS

100% CVBS

–

75% CVBS

video (luma)

sync height

clamp level

burst

500

–

350

224

150

300

–

68

16

Chroma

300

890

670

64

–

100% Chroma

75% Chroma

bias level

190

143

128

128$112

128$84

128

CVBS/Y

Chroma

upper headroom = 38 steps = 1.4 dB = 25 IRE

headroom = 56 steps = 2.1 dB

255

228

192

217

192

white

video = 100 IRE

128

68

128

80

black

= clamp

level

sync = 41 IRE

32

0

32

lower headroom = 4 steps = 0.2 dB

Fig. 2–2: ADC ranges for CVBS/Luma and Chroma, PAL input signal

Micronas

9

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

dB

2.2. Color Decoder

10

5

In this block, the standard luma/chroma separation and

multi-standard color demodulation is carried out. The

color demodulation uses an asynchronous clock, thus

allowing a unified architecture for all color standards.

0

–5

A block diagram of the color decoder is shown in Fig.

2–4. The luma, as well as the chroma processing, is

shown here. The color decoder also provides several

special modes; for example, wide band chroma format

which is intended for S-VHS wide bandwidth chroma.

–10

–15

–20

The output of the color decoder is YC C in a 4:2:2 for-

r

b

3.5

3.75

4

4.25

4.5

4.75

5

MHz

mat.

Fig. 2–3: Freq. response of chroma IF-compensation

2.2.1. IF-Compensation

2.2.2. Demodulator

With off-air or mistuned reception, any attenuation at

higher frequencies or asymmetry around the color sub-

carrier is compensated. Four different settings of the IF-

compensation are possible:

The entire signal (which might still contain luma) is now

quadrature-mixed to the baseband. The mixing frequen-

cy is equal to the subcarrier for PAL and NTSC, thus

achieving the chroma demodulation. For SECAM, the

mixing frequency is 4.286 MHz giving the quadrature

baseband components of the FM modulated chroma.

After the mixer, a lowpass filter selects the chroma com-

ponents; a downsampling stage converts the color dif-

ference signals to a multiplexed half rate data stream.

– flat (no compensation)

– 6 dB/octave

– 12 dB/octave

– 10 dB/MHz

The last setting gives a very large boost to high frequen-

cies. It is provided for SECAM signals that are decoded

using a SAW filter specified originally for the PAL stan-

dard.

The subcarrier frequency in the demodulator is gener-

ated by direct digital synthesis; therefore, substandards

such as PAL 3.58 or NTSC 4.43 can also be demodu-

lated.

Luma

Notch

Filter

Luma / CVBS

Chroma

Cross-

Switch

1 H Delay

ACC

Lowpass Filter

Phase/Freq.

Demodulator

IF Compensation

DC-Reject

Chroma

MIXER

Color-PLL/Color-ACC

Fig. 2–4: Color decoder

10

Micronas

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.2.3. Chrominance Filter

2.2.4. Frequency Demodulator

The demodulation is followed by a lowpass filter for the

color difference signals for PAL/NTSC. SECAM requires

amodifiedlowpassfunctionwithbell-filtercharacteristic.

At the output of the lowpass filter, all luma information is

eliminated.

The frequency demodulator for demodulating the SE-

CAM signal is implemented as a CORDIC-structure. It

calculates the phase and magnitude of the quadrature

components by coordinate rotation.

The phase output of the CORDIC processor is differen-

tiated to obtain the demodulated frequency. After a pro-

grammable deemphasis filter, the Dr and Db signals are

The lowpass filters are calculated in time multiplex for

the two color signals. Four bandwidth settings (narrow,

normal, broad, wide) are available for each standard.

The filter passband can be shaped with an extra peaking

term at 1.25 MHz. For PAL/NTSC, a wide band chroma

filter can be selected. This filter is intended for high

bandwidth chroma signals; for example, a nonstandard

wide bandwidth S-VHS signal.

scaled to standard C C amplitudesandfedtothecross-

r

b

over-switch.

2.2.5. Burst Detection

In the PAL/NTSC-system, the burst is the reference for

the color signal. The phase and magnitude outputs of

the CORDIC are gated with the color key and used for

controlling the phase-lock-loop (APC) of the demodula-

tor and the automatic color control (ACC) in PAL/NTSC.

The ACC has a control range of +30...–6 dB.

dB

0

–10

–20

–30

–40

–50

ForSECAMdecoding, thefrequencyoftheburstismea-

sured. Thus, the current chroma carrier frequency can

be identified and is used to control the SECAM proces-

sing. The burst measurements also control the color kill-

er operation; they can be used for automatic standard

detection as well.

2.2.6. Color Killer Operation

0

1

2

3

4

5

MHz

PAL/NTSC

The color killer uses the burst-phase/burst-frequency

measurement to identify a PAL/NTSC or SECAM color

signal. For PAL/NTSC, the color is switched off (killed)

as long as the color subcarrier PLL is not locked. For SE-

CAM, the killer is controlled by the toggle of the burst fre-

quency. The burst amplitude measurement is used to

switch off the color if the burst amplitude is below a pro-

grammable threshold. Thus, color will be killed for very

noisy signals. The color amplitude killer has a program-

mable hysteresis.

dB

0

–10

–20

–30

–40

2.2.7. PAL Compensation/1-H Comb Filter

–50

0

The color decoder uses one fully integrated delay line.

Only active video is stored.

1

2

3

4

5

MHz

SECAM

The delay line application depends on the color stan-

dard:

Fig. 2–5: Frequency response of chroma filters

– NTSC:

– PAL:

1-H comb filter or color compensation

color compensation

– SECAM: crossover-switch

Micronas

11

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

CVBS

Luma

In the NTSC compensated mode, Fig. 2–7 c), the color

signal is averaged for two adjacent lines. Thus, cross-

color distortion and chroma noise is reduced. In the

NTSC combfilter mode, Fig. 2–7 d), the delay line is in

the composite signal path, thus allowing reduction of

cross-color components, as well as cross-luminance.

The loss of vertical resolution in the luminance channel

is compensated by adding the vertical detail signal with

removed color information.

Notch

filter

Y

8

Chroma

Process.

Chroma

Process.

C C

r

C C

r

b

8

a) conventional

b) S-VHS

CVBS

Notch

filter

Y

8

2.2.8. Luminance Notch Filter

1 H

Delay

Chroma

Process.

C C

r

b

If a composite video signal is applied, the color informa-

tion is suppressed by a programmable notch filter. The

position of the filter center frequency depends on the

subcarrier frequency for PAL/NTSC. For SECAM, the

notch is directly controlled by the chroma carrier fre-

quency. This considerably reduces the cross-lumi-

nance. The frequency responses for all three systems

are shown in Fig. 2–6. In S-VHS mode, this filter is by-

passed.

c) compensated

Notch

filter

Y

CVBS

1 H

Delay

8

Chroma

Process.

C C

r

b

dB

10

d) comb filter

Fig. 2–7: NTSCcolor decoding options

0

–10

–20

–30

–40

CVBS

Notch

Y

filter

8

1 H

Delay

Chroma

Process.

C C

r

b

0

2

4

6

8

10 MHz

PAL/NTSC notch filter

a) conventional

Luma

dB

10

Y

8

0

Chroma

1 H

Delay

Chroma

Process.

C C

r

b

8

–10

b) S-VHS

–20

–30

–40

Fig. 2–8: PAL color decoding options

0

2

4

6

8

10 MHz

SECAM notch filter

CVBS

Notch

filter

Y

8

Fig. 2–6: Frequency responses of the luma

notch filter for PAL, NTSC, SECAM

MUX

1 H

Delay

Chroma

Process.

C C

r

b

Fig. 2–9: SECAM color decoding

12

Micronas

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.3. Video Sync Processing

2.4. Macrovision Detection (version D4 only)

Video signals from Macrovision encoded VCR tapes are

decodedwithoutlossofpicturequality. However, itmight

be necessary in some applications to detect the pres-

ence of Macrovision encoded video signals. This is pos-

sible by reading a set of I C registers (FP-RAM

0x170–0x179) in the video front-end.

Fig. 2–10 shows a block diagram of the front-end sync

processing. To extract the sync information from the

video signal, a linear phase lowpass filter eliminates all

noise and video contents above 1 MHz. The sync is sep-

arated by a slicer; the sync phase is measured. The in-

ternal controller can select variable windows to improve

the noise immunity of the slicer. The phase comparator

measures the falling edge of sync, as well as the inte-

grated sync pulse.

2

Macrovision encoded video signals typically have AGC

pulses and pseudo sync pulses added during VBI. The

amplitude of the AGC pulses is modulated in time. The

Macrovision detection logic measures the VBI lines and

compares the signal against programmable thresholds.

The sync phase error is filtered by a phase-locked loop

that is computed by the FP. All timing in the front-end is

derived from a counter that is part of this PLL, and it thus

counts synchronously to the video signal.

The window in which the video lines are checked for Ma-

crovisionpulsescanbedefinedintermsofstartandstop

line (e.g. 6–15 for NTSC).

A separate hardware block measures the signal back

porch and also allows gathering the maximum/minimum

of the video signal. This information is processed by the

FP and used for gain control and clamping.

For vertical sync separation, the sliced video signal is in-

tegrated. The FP uses the integrator value to derive ver-

tical sync and field information.

Frequency and phase characteristics of the analog vid-

eo signal are derived from PLL1. The results are fed to

the rest of the video processing system in the backend.

The resizer unit uses them for data interpolation and

orthogonalization. A separate timing block derives the

timing reference signals HREF and VREF from the hori-

zontal sync.

PLL1

lowpass

front sync

skew

vblank

field

horizontal

phase

comparator

& lowpass

front

1 MHz &

sync

counter

sync

separation

generator

video

slicer

input

clock

synthesizer

syncs

clamp &

clock

H/V syncs

front-end

timing

signal

measurement

clamping color key FIFO_write

Fig. 2–10: Sync separation block diagram

Micronas

13

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.5. Component Processing

path. The Luma Filtering block applies anti-aliasing low-

pass filters with cutoff frequencies adapted to the num-

ber of samples after scaling, as well as peaking and cor-

ing. The Resize and Skew blocks alter the effective

sampling rate and compensate for horizontal line skew.

The YCbCr samples are buffered in a FIFO for continu-

ous burst at a fixed clock rate. For luminance samples,

the contrast and brightness can be adjusted and noise

shaping applied. In the chrominance path, Cb and Cr

samples can be swapped. Without swapping, the first

valid video sample is a Cb sample. Chrominance gain

can be adjusted in the color decoder.

Recovery of the YCbCr components by the decoder is

followed by horizontal resizing and skew compensation.

Contrast enhancement with noise shaping can also be

applied to the luminance signal. Vertical resizing is sup-

ported via line dropping.

Fig. 2–11 illustrates the signal flow through the compo-

nent processing stage. The YCbCr 4:2:2 samples are

separated into a luminance path and a chrominance

Contrast,

Brightness &

Noise shaping

Resize

Y_in

Y_out

Luma Filter

with peaking

& coring

Skew

Luma

Phase Shift

F

I

F

O

Active Video

Reference

Sequence

Control

Latch

Chroma

Phase Shift

16 bit

Resize

Cb/Cr-

swapping

Cr_out

CbCr_in

Skew

Fig. 2–11: Component processing stage

Table 2–2: Several rasters supported by the resizer

NTSC

PAL/SECAM

768 x 576

704 x 576

384 x 288

352 x 288

192 x 144

176 x 144

32 x 24

Format Name

640 x 480

704 x 480

320 x 240

352 x 240

160 x 120

176 x 120

32 x 24

Square pixels for broadcast TV (4:3)

Input Raster for MPEG-2

Square pixels for TV (quarter resolution)

CIF – Input raster for MPEG-1, H.261

Square pixels for TV (1/16 resolution), H.324, H.323

QCIF – Input raster for H.261

Video icons for graphical interfaces (square)

14

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

dB

0

2.5.1. Horizontal Resizer

The operating range of the horizontal resizer was cho-

sen to serve the widest possible range of applications

andsourceformats(numberoflines, aspectratio, etc...).

Table 2–2 lists several examples for video sourced from

525/625 line TV systems.

–10

–20

–30

–40

The horizontal resizer alters the sampling raster of the

videosignal, therebyvaryingthenumberofpixels(NPix)

in the active portion of the video line. The number of pix-

els per line is selectable within a range from 32 to 864

in increments of 2 pixels (see section 2.10.: Windowing

the Video Field). Table 2–2 gives an overview of several

supported video rasters. The visual quality of a sampling

rate conversion operation depends on two factors:

– the frequency response of the individual filters, and

– the number of available filters from which to choose.

0

10

20

30

40

MHz

The VPX is equipped with a battery of FIR filters to cover

the five octave operating range of the resizer. Fig. 2–12

shows the magnitude response of five example filters

corresponding to 1054, 526, 262, 130, and 32 pixels.

Fig. 2–12: Freq. response of 5 widely spaced filters

dB

0

The density of the filter array can be seen in Fig. 2–13.

The magnitude response of 50 filters lying next to each

other are shown. Nevertheless, these are only 10% of all

filters shown. As a whole, the VPX comes with a battery

of 512 FIR filters. Showing these 512 Filters in Fig. 2–12

would result in a large black area. This dense array of fil-

ters is necessary in order to maintain constant visual

quality over the range of allowable picture sizes. The al-

ternative would be to use a small number of filters whose

cutoff frequencies are regularly spaced over the spec-

trum. However, it has been found that using few filters

leads to visually annoying threshold behavior. These ef-

fects occur when the filters are changed in response to

variations in the picture size.

–2

–4

–6

–8

–10

–12

Filterselectionisperformedautomaticallybytheinternal

processor based on the selected resizing factor (NPix).

This automated selection is optimized for best visual

performance.

0

0.5

1

1.5

2

2.5

3

MHz

Fig. 2–13: Freq. response of 50 neighbored filters

Micronas

15

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.5.2. Skew Correction

2.5.4. YCbCr Color Space

The VPX delivers orthogonal pixels with a fixed clock

even in the case of non-broadcast signals with substan-

tial horizontal jitter (VCRs, laser disks, certain portions

of the 6 o’clock news...).

The color decoder outputs luminance and one multi-

plexed chrominance signal at a sample clock of

20.25 MHz. Activevideosamplesareflaggedbyasepa-

rate reference signal. Internally, the number of active

samples is 1080 for all standards (525 lines and 625

lines). The representation of the chroma signals is the

ITU-R 601 digital studio standard.

This is achieved by highly accurate sync slicing com-

bined with post correction. Immediately after the analog

input is sampled, a horizontal sync slicer tracks the posi-

tion of sync. This slicer evaluates, to within 1.6 ns, the

skew between the sync edge and the edge of the pixel-

clock. This value is passed as a skew on to the phase

shift filter in the resizer. The skew is then treated as a

fixed initial offset during the resizing operation.

In the color decoder, the weighting for both color differ-

ence signals is adjusted individually. The default format

has the following specification:

– Y = 224*Y + 16 (pure binary),

– C = 224*(0.713*(R–Y)) + 128 (offset binary),

The skew block in the resizer performs programmable

phase shifting with subpixel accuracy. In the luminance

path, a linear interpolation filter provides a phase shift

between 0 and 31/32 in steps of 1/32. This corresponds

to an accuracy of 1.6 ns. The chrominance signal can be

shifted between 0 and 7/8 in steps of 1/8.

r

– C = 224*(0.564*(B–Y)) + 128 (offset binary).

b

2.5.5. Video Adjustments

The VPX provides a selectable gain (contrast) and offset

(brightness) for the luminance samples, as well as addi-

tional noise shaping. Both the contrast and brightness

2.5.3. Peaking and Coring

The horizontal resizer comes with an extra peaking filter

for sharpness control. The center frequency of the peak-

ing filter is automatically adjusted to the image size in

512 steps. The peaking value to each center frequency

can be controlled by the user with up to eight steps via

FP-RAM 0x126/130. Fig. 2–14 shows the magnitude re-

sponse of the eight steps of the peaking filter corre-

sponding to an image size of 320 pixels.

2

factors can be set externally via I C serial control of FP-

RAM 0x127,128,131, and 132. Fig. 2–15 gives a func-

tional description of this circuit. First, a gain is applied,

yielding a 10-bit luminance value. The conversion back

to 8-bit is done using one of four selectable techniques:

simple rounding, truncation,1-bit error diffusion, or 2-bit

error diffusion. Bit[8] in the ‘contrast’-register selects be-

tween the clamping levels 16 and 32.

After the peaking filter, an additional coring filter is imple-

mented to the horizontal resizer. The coring filter sub-

tracts 0, 1/2, 1, or 2 LSBs of the higher frequency part of

the signal. Note, that coring can be performed indepen-

dently of the peaking value adjustment.

I

= c * I + b

c = 0...63/32 in 64 steps

b = –127...128 in 256 steps

out

in

In the chrominance path, Cb and Cr samples can be

swapped with bit[8] in FP-RAM 0x126 or 130. Adjust-

ment of color saturation and gain is provided via FP-

RAM 0x30–33 (see section 2.2.5.).

dB

10

0

–10

–20

Rounding

Truncation

1 bit

Err. Diff.

2 bit

Err. Diff.

–30

FP-RAM

Registers

Contrast

Select

Brightness

0

1

2

3

4

5

6

MHz

Fig. 2–15: Contrast and brightness adjustment

Fig. 2–14: Frequency response of peaking filter

16

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

2.6. Video Output Interface

2.6.1. Output Formats

The VPX supports the YUV 4:2:2 video format only. Dur-

ing normal operation, all reference signals are output

separately. To provide a reduced video interface, the

VPX offers two possibilities for encoding timing refer-

ences into the video data stream: an ITU-R656 com-

pliant output format with embedded timing reference

headers and a second format with single timing control

codes in the video stream. The active output format can

be selected via FP-RAM 0x150 [format].

Contrary to the component processing stage running at

a clock rate of 20.25 MHz, the output formatting stage

(Fig. 2–16) receives the video samples at a pixel trans-

port rate of 13.5 MHz. It supports 8 or 16-bit video for-

mats with separate or embedded reference signals, pro-

vides bus shuffling, and channels the output via one or

both 8-bit ports. Data transfer is synchronous to the in-

ternally generated 13.5 MHz pixel clock.

The format of the output data depends on three parame-

ters:

2.6.1.1. YUV 4:2:2 with Separate Syncs/ITU-R601

– the selected output format

The default output format of the VPX is a synchronous

16-bit YUV 4:2:2 data stream with separate reference

signals. Port A is used for luminance and Port B for chro-

minance-information. Video data is compliant to ITU-

R601. Bit[1:0] of FP-RAM 0x150 has to be set to 00. Fig-

ure 2–17 shows the timing of the data ports and the

reference signals in this mode.

S YUV 4:2:2, separate syncs

S YUV 4:2:2, ITU-R656

S YUV 4:2:2, embedded reference codes (BStream)

– the number of active ports (A only, or both A and B)

– clock speed (single, double, half).

In 8-bit modes using only Port A for video data, Port B

can be used as programmable output.

Video

Samples

16

8

Port A

OE

8

Port B

PIXCLK

LLC

LLC2

Clock

Generation

HREF

VREF

VACT

Reference

Signals

Fig. 2–16: Output format stage

Luminance

(Port A)

Y

1

Y

n–1

Y

n

Chrominance

(Port B)

C

n

1

n–1

VACT

PIXCLK

LLC

Fig. 2–17: Detailed data output (single clock mode)

Micronas

17

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.6.1.2. Embedded Reference Headers/ITU-R656

– Ancillarydatablocksmaybelongerthan255bytes(for

raw data) and are transmitted without checksum. The

secondary data ID is used as high byte of the data

count (DC1; see Table 2–5).

The VPX supports an output format which is designed to

be compliant with the ITU-R656 recommendation. It is

activated by setting Bit[1:0] of FP-RAM 0x150 to 01. The

16-bit video data must be multiplexed to 8 bit at the

double clock frequency (27 MHz) via FP-RAM 0x154, bit

9 set to 1 (see also section 2.6.3.: Output Multiplexer).

– Ancillary data packets must not follow immediately af-

ter EAV or SAV.

– The total number of clock cycles per line, as well as

valid cycles between EAV and SAV may vary.

In this mode, video samples are in the following order:

Cb, Y, Cr, Y, ... The data words 0 and 255 are protected

since they are used for identification of reference head-

ers. This is assured by limitation of the video data. Tim-

ing reference codes are inserted into the data stream at

the beginning and the end of each video line in the fol-

lowing way: A ‘Start of active video’-Header (SAV) is in-

serted before the first active video sample. The ‘end of

active video’-code (EAV) is inserted after the last active

video sample. They both contain information about the

field type and field blanking. The data words occurring

during the horizontal blanking interval between EAV and

SAV are filled with 0x10 for luminance and 0x80 for chro-

minance information. Table 2–3 shows the format of the

SAV and EAV header.

Table 2–3: Coding of the SAV/EAV-header

Bit No.

Word

MSB

7

LSB

0

6

1

0

F

5

1

0

V

4

1

0

H

3

1

2

1

First

1

0

1

Second

Third

0

Fourth

P3

P2

P1

P0

F = 0 during field 1,

V = 0 during active lines

H = 0 in SAV,

F = 1 during field 2

V = 1 during vertical field blanking

H = 1 in EAV

Note that the following changes and extensions to the

ITU-R656 standard have been included to support hori-

zontal and vertical scaling, transmission of VBI-data,

etc.:

The bits P0, P1, P2, and P3 are protection bits. Their

states are dependent on the states of F, V, and H as

shown in Table 2–4.

– Both the length and the number of active video lines

varies with the selected window parameters. For com-

pliance with the ITU-R656 recommendation, a size of

720 samples per line must be selected for each win-

dow. To enable a constant line length even in the case

of different scaling values for the video windows, the

VPX provides a programmable ‘active video’ signal

(see section 2.8.4.).

Table 2–4: Coding of the protection bits

Bit No.

Code

(hex)

MSB

LSB

F

0

1

V

0

1

0

1

H

0

1

0

1

0

1

0

1

P3

0

P2

0

P1

0

P0

0

– During blanked lines, the VACT signal is suppressed.

VBI-lines can be marked as blanked or active, thus al-

lowingthechoiceofenabledorsuppressedVACTdur-

ing the VBI-window. The vertical field blanking flag (V)

in the SAV/EAV header is set to zero in any line with

enabled VACT signal (valid VBI or video lines).

80

9D

AB

B6

C7

DA

EC

F1

1

0

1

0

1

0

1

0

– During blanked lines, SAV/EAV headers can be sup-

pressed in pairs with FP-RAM 0x150, bit9. To assure

vertical sync detection, some SAV/EAV headers are

inserted during field blanking.

0

1

0

1

0

1

0

– The flags F, V, and H encoded in the SAV/EAVheaders

change on SAV. With FP-RAM 0x150, bit10 set to 1,

they change onEAV. The programmed windows, how-

ever, are delayed by one line. Header suppression is

applied for EAV/SAV pairs.

0

1

The VPX also supports the transmission of VBI-data as

vertical ancillary data during blanked lines in the interval

starting with the end of the SAV and terminating with the

beginning of EAV. In this case, an additional header is in-

serted directly before the valid active data. In this mode,

the position of SAV and EAV depends on the settings for

the programmable VACT signal. These parameters will

– For data within the VBI-window (e.g. sliced or raw tele-

text data), the user can select between limitation or re-

duction to 7-bit resolution with an additional LSB as-

suring odd parity (0 and 255 never occur). This option

can be selected via FP-RAM 0x150 [range].

18

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

be checked and corrected if necessary to assure an ap-

propriate size of VACT for both data and ancillary header.

Table 2–5: Coding of the ancillary header information

Bit No.

Word

MSB

7

LSB

0

Table 2–5 shows the coding of the ancillary header in-

formation. The word I[2:0] contains a value for data type

identification (1 for sliced and 3 for raw data during odd

fields, 5 for sliced and 7 for raw data during even fields).

M[5:0] contains the MSBs and L[5:0] the LSBs of the

number of following D-words (32 for sliced data, 285 for

raw data). DC1 is normally used as secondary data ID.

The value 0 for M[5:0] in the case of sliced data marks

an undefined format. Bit 6 is even parity for bit5 to bit0.

Bit 7 is the inverted parity flag. Note that the following

user data words (video data) are either limited or have

odd parity to assure that 0 and 255 will not occur. Bit 3

in RAM 0x150 selects between these two options.

6

0

5

4

3

2

1

Pream1

Pream2

Pream3

DID

0

1

NP

P

0

1

0

I2

M2

L2

I1

M1

L1

I0

M0

L0

DC1

M5

L5

M4

L4

M3

L3

DC2

current line length

dependent on window size

Y C Y ...

Digital

Video Output

C

C Y C Y ...

B R

B

R

constant during

horizontal blanking

SAV: “start of active video” header

EAV: “end of active video” header

Y = 10 ; C = C = 80

hex

R

B

hex

VACT

Fig. 2–18: Output of video or VBI data with embedded reference headers (according to ITU-R656)

DATA

(Port A)

80h

10h

SAV

C

Y

C

Y

C

Y

C

Y

EAV

4

80h

10h

1

2

3

4

B1

1

R1

2

Bn–1

n–1

Rn–1

n

1

2

3

VACT

PIXCLK

LLC

Fig. 2–19: Detailed data output (double clock mode)

current line length

size of programmable VACT

dependent on VBI-window size

Digital

Video Output

D D D D ...

C Y C Y ...

B R

1

2

3

4

constant during

horizontal blanking

SAV: “start of active video” header

EAV: “end of active video” header

Y = 10 ; C = C = 80

hex

R

B

hex

VACT

Fig. 2–20: Output of VBI-data as ancillary data

Micronas

19

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.6.1.3. Embedded Timing Codes (BStream)

Table 2–6: Chrominance control codes

In this mode, several event words are inserted into the

pixel stream for timing information. It is activated by set-

ting Bit[1:0] of FP-RAM 0x150 to 10. Each event word

consists of a chrominance code value containing the

phase of the color-multiplex followed by a luminance

code value signalling a specific event. The allowed con-

trol codes are listed in table 2–6 and 2–7.

Chroma Value

Phase Information

Cr pixel

FE

FF

Cb pixel

2.6.2. Bus Shuffler

At the beginning and the end of each active video line,

timing reference codes (start of active video: SAV; end

of active video: EAV) are inserted with the beginning and

the end of VACT. Since VACT is suppressed during

blanked lines, video data and SAV/EAV codes are pres-

ent during active lines only. If raw/sliced data should be

output, VACT has to be enabled during the VBI window

with bit 2 of FP-RAM 0x138! In the case of several win-

dows per field, the length of the active data stream per

line can vary. Since the qualifiers for active video (SAV/

EAV) are independent of the other reference codes,

there is no influence on horizontal or vertical syncs, and

sync generation can be performed even with several dif-

ferent windows. For full compliance with applications re-

quiring data streams of a constant size, the VPX pro-

vides a mode with programmable ‘video active’ signal

VACT which can be selected via bit 2 of FP-RAM 0x140.

The start and end positions of VACT relative to HREF is

determined by FP-RAM 0x151 and 0x152. The delay of

valid data relative to the leading edge of HREF is calcu-

lated with the formulas given in table 2–8 and 2–9. The

result can be read in FP-RAM 0x10f (for window 1) and

0x11f (for window 2). Be aware that the largest window

defines the size of the needed memory. In the case of

1140 raw VBI-samples and only 32 scaled video sam-

ples, the graphics controller needs 570 words for each

line (the VBI-samples are multiplexed to luminance and

chrominance paths).

In the YUV 4:2:2 mode, the output of luminance data is

on port A and chrominance data on Port B. With the bus

shuffler, luminance can be switched to Port B and chro-

minance to port A. In 8-bit double clock mode, shuffling

can be used to swap the Y and C components. It is se-

lected with FP-RAM 0x150.

2.6.3. Output Multiplexer

During normaloperation, a16-bitYUV4:2:2datastream

is transferred synchronous to an internally generated

PIXCLK at a rate of 13.5 MHz. Data can be latched onto

the falling edge of PIXCLK or onto the rising edge of LLC

during high PIXCLK. In the double clock mode, lumi-

nanceandchrominancedataaremultiplexedto8bitand

transferred at the double clock frequency of 27 MHz in

the order Cb, Y, Cr, Y...; the first valid chrominance value

being a Cb sample. With shuffling switched on, Y and C

components are swapped. Data can be latched with the

rising edge of LLC or alternating edges of PIXCLK. This

mode is selected with bit 9 of FP-RAM 0x154. All 8-bit

modes use Port A only. In this case, Port B can be acti-

vated as programmable output with bit 8 of FP-RAM

0x154. Bit 0–7 determine the state of Port B.

video data

The leading edge of HREF indicates the beginning of a

new video line. Depending on the type of the current line

(active or blanked), the corresponding horizontal refer-

ence code is inserted. For big window sizes, the leading

edge of HREF can arrive before the end of the active

data. In this case, hardware assures that the control

code for HREF is delayed and inserted after EAV only.

The VREF control code is inserted at the falling edge of

VREF. The state of HREF at this moment indicates the

current field type (HREF = 0: odd field; HREF = 1: even

field).

8

=0

8

B[7:0]

video port

=1

8

7:0

8

FP-RAM 0x154 [outmux]

Fig. 2–21: Programmable output port

In this mode, the words 0,1,254, and 255 are reserved

for data identifications. This is assured by limitation of

the video data.

2.6.4. Output Ports

The two 8-bit ports produce TTL level signals coded in

binary offset. The Ports can be tristated either via the

2

outputenablepin(OE)orviaI C register 0xF2. For more

information, seesection2.17. “Enable/DisableofOutput

Signals”.

20

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

Table 2–7: Luminance control codes

Luma Value

Video Event

VACT end

Video Event

Phase Information

01

02

03

04

05

06

last pixel was the last active pixel

next pixel is the first active pixel

begin of an active video line

begin of a blank line

refers to the last pixel

VACT begin

HREF active line

HREF blank line

VREF even

refers to the next pixel

refers to the current pixel

begin of an even field

VREF odd

begin of an odd field

DATA

(Port A)

FFh

03h

FFh

02h

C

Y

C

Y

C

Y

C

Y

n

FEh

01h

B1

1

R1

2

Bn–1

n–1

Rn–1

VACT

HREF

PIXCLK

LLC

Fig. 2–22: Detailed data output with timing event codes (double clock mode)

2.7. Video Data Transfer

2.7.1. Single and Double Clock Mode

The VPX supports a synchronous video interface. Video

data arrives to each line at the output in an uninterrupted

burst with a fixed transport rate of 13.5 MHz. The dura-

tionoftheburstismeasuredinclockperiodsofthetrans-

port clock and is equal to the number of pixels per output

line.

Data is transferred synchronous to the internally gener-

ated PIXCLK. The frequency of PIXCLK is 13.5 MHz.

The LLC signal is provided as an additional support for

both the 13.5 MHz and the 27 MHz double clock mode.

The LLC consists of a doubled PIXCLK signal (27 MHz)

for interface to external components which rely on the

Philips transfer protocols. In the single clock mode, data

can be latched onto the falling edge of PIXCLK or at the

rising edge of LLC during high PIXCLK. In double clock

mode, output data can be latched onto both clock edges

of PIXCLK or onto every rising edge of LLC. Combined

with the half-clock mode, the available transfer band-

widths at the ports are therefore 6.75 MHz, 13.5 MHz,

and 27.0 MHz.

The data transfer is controlled via the signals: PIXCLK,

VACT, and LLC. An additional clock signal LLC2 can be

switched to the TDO output pin to support different tim-

ings.

The VACT signal flags the presence of valid output data.

Fig. 2–23, 2–24, and 2–25 illustrate the relationship be-

tween the video port data, VACT, PIXCLK, and LLC.

Whenever a line of video data should be suppressed

(line dropping, switching between analog inputs), it is

done by suppression of VACT.

Micronas

21

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.7.2. Half Clock Mode

For applications demanding a low bandwidth for the

transmission between video decoder and graphics con-

troller, the clock signal qualifying the output pixels

(PIXCLK) can be divided by 2. This mode is enabled by

setting Bit 5 of the FP-RAM 0x150 [halfclk]. Note that the

output format ITU-R601 must be selected. The timing of

thedataandclocksignalsinthiscaseisdescribedinFig-

ure 2–25.

If the half-clock mode is enabled, each second pulse of

PIXCLK is gated. PIXCLK can be used as a qualifier for

valid data. To ensure that the video data stream can be

spread, the selected number of valid output samples

should not exceed 400.

Luminance

(Port A)

Y

1

Y

n–1

Y

n

Chrominance

(Port B)

C

n

1

n–1

VACT

PIXCLK

LLC

Fig. 2–23: Output timing in single clock mode

Video

(Port A)

C

Y

1

C

Y

n–1

C

Y

n

1

n–1

n

VACT

PIXCLK

LLC

Fig. 2–24: Output timing in double clock mode

Luminance

(Port A)

Y

1

Y

n

Chrominance

(Port B)

C

n

1

VACT

PIXCLK

LLC

Fig. 2–25: Output timing in half clock mode

22

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

2.8. Video Reference Signals

2.8.2. VREF

The complete video interface of the VPX runs at a clock

rate of 13.5 MHz. It mainly generates two reference sig-

nals for the video timing: a horizontal reference (HREF)

and a vertical reference (VREF). These two signals are

generated by programmable hardware and can be ei-

ther free running or synchronous to the analog input vid-

eo. The video line standard (625/50 or 525/60) depends

on the TV-standard selected with FP-RAM 0x20 [sdt].

The polarity of both signals is individually selectable via

FP-RAM 0x153.

Figs. 2–27 and 2–28 illustrate the timing of the VREF

signal relative to field boundaries of the two TV stan-

dards. The start of the VREF pulse is fixed, while the

length is programmable in the range between 2 and 9

video lines via FP-RAM 0x153 [vlen].

2.8.3. Odd/Even Information (FIELD)

Information on whether the current field is odd or even

is supplied through the relationship between the edge

(either leading or trailing) of VREF and level of HREF.

This relationship is fixed and shown in Figs. 2–27 and

2–28. The same information can be supplied to the

FIELD pin, which can be enabled/disabled as output in

FP-RAM 0x153 [enfieldq]. FP-RAM 0x153 [oepol] pro-

grams the polarity of this signal.

The circuitry which produces the VREF and HREF sig-

nals has been designed to provide a stable, robust set

of timing signals, even in the case of erratic behavior at

the analog video input. Depending on the selected oper-

ating mode given in FP-RAM 0x140 [settm], the period

of the HREF and VREF signals are guaranteed to re-

main within a fixed range. These video reference signals

can therefore be used to synchronize the external com-

ponents of a video subsystem (for example the ICs of a

PC add-in card).

During normal operation the FIELD flag is filtered since

most applications need interlaced signals. After filtering,

the field type is synchronized to the input signal only if

the last 8 fields have been alternating; otherwise, it al-

ways toggles. This filtering can be disabled with FP-

RAM 0x140 [disoef]. In this case, the field information

follows the odd/even property of the input video signal.

In addition to the timing references, valid video samples

are marked with the ‘video active’ qualifier (VACT). In or-

der to reduce the signal number of the video interface,

several 8-bit modes have been implemented, where the

reference signals are multiplexed into the data stream

(see section 2.6.1.).

2.8.1. HREF

Fig. 2–26 illustrates the timing of the HREF signal rela-

tive to the analog input. The inactive period of HREF has

a fixed length of 64 periods of the 13.5 MHz output clock

rate. The total period of the HREF signal is expressed as

F

and depends on the video line standard.

nominal

Analog

Video

Input

VPX

Delay

HREF

4.7 µs (64 cycles)

F

nominal

Fig. 2–26: HREF relative to input video

Micronas

23

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

625

1

2

3

4

5

8

6

7

Input CVBS

(50 Hz), PAL

3

4

5

6

7

9

10

Input CVBS

(60 Hz), NTSC

HREF

VREF

361 t

CLK13.5

2 .. 9 H

> 1 t

CLK13.5

FIELD

Fig. 2–27: VREF timing for ODD fields

312

265

313

266

314

315

268

316

269

317

270

318

319

272

320

Input CVBS

(50 Hz), PAL

267

271

273

Input CVBS

(60 Hz), NTSC

HREF

VREF

46 t

CLK13.5

2 .. 9 H

> 1 t

CLK13.5

FIELD

Fig. 2–28: VREF timing for EVEN fields

24

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

2.8.4. VACT

supported [FP-RAM 0x140, vactmode]. The start and

end position for the VACT signal relative to the trailing

edge of HREF can be programmed within a range of 0

to 864 [FP-RAM 0x151, 0x152]. In this case, VACT no

longer marks valid samples only.

The ‘video active’ signal is a qualifier for valid video sam-

ples. Since scaled video data is stored internally, there

are no invalid pixel within the VACT interval. VACT has

a defined position relative to HREF depending on the

window settings (see section 2.10.). The maximal win-

dow length depends on the minimal line length of the in-

put signal. It is recommended to choose window sizes of

less than 800 pixels. Sizes up to 864 are possible, but for

non-standard input lines, VACT is forced inactive 4

PIXCLK cycles before the next trailing edge of HREF.

The position of the valid data depends on the window

definitions. It is calculated from the internal processor.

ThecalculateddelayofVACTrelativetothetrailingedge

of HREF can be read via FP-RAM 0x10f (window 1) or

0x11f(window2). Tables2–8and2–9showtheformulas

for the position of valid data samples relative to the trail-

ing edge of HREF.

During the VBI-window, VACT can be enabled or sup-

pressed with FP-RAM 0x138. Within this window, the

VPX can deliver either sliced text data with a constant

length of 64 samples or 1140 raw input samples. For ap-

plications that request a uniform window size over the

whole field, a mode with a free programmable VACT is

Fig. 2–29 illustrates the temporal relationship between

the VACT and the HREF signals as a function of the

number of pixels per output line and the horizontal di-

mensions of the window. The duration of the inactive pe-

riod of the HREF is fixed to 64 clock cycles.

Table 2–8: Delay of valid output data relative to the trailing edge of HREF (single clock mode)

Mode

Data Delay

Data End

Video data

(HBeg+HLen)*(720/NPix)–Hlen

HBeg*(720/NPix)

for NPix < 720

for NPix ≥ 720

DataDelay + HLen

Raw VBI data

150

726

720

790

Sliced VBI data

Table 2–9: Delay of valid output data relative to the trailing edge of HREF (half clock mode)

Mode

Data Delay

Data End

Video data

(HBeg+HLen)*(720/NPix)–2*Hlen for NPix < 360

DataDelay + 2*HLen

HBeg*(720/NPix)

not possible!

662

for NPix ≥ 360

Raw VBI data

not possible!

790

Sliced VBI data

DATA

(Port A or B)

D

1

n–1

n

VACT

data end

data delay

64 cycles

HREF

PIXCLK

LLC

Fig. 2–29: Relationship between HREF and VACT signals (single clock mode)

Micronas

25

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.9. Operational Modes

2.9.2. Scan Mode

In the Scan Mode, the HREF and VREF signals are al-

ways generated by free running hardware. They are

therefore completely decoupled from the analog input.

The output video data is always suppressed.

The relationship between the video timing signals

(HREF and VREF) and the analog input video is deter-

mined by the selected operational mode. Three such

modes are available: the Open Mode, the Forced

Mode, and the Scan Mode. These modes are selected

2

The purpose of the Scan Mode is to allow the external

controller to freely switch between the analog inputs

while searching for the presence of a video signal. In-

formation regarding the video (standard, source, etc...)

via I C commands [FP-RAM 0x140, settm, lattm].

2.9.1. Open Mode

2

can be queried via I C read.

In the Open Mode, both the HREF and the VREF signal

track the analog video input. In the case of a change in

the line standard (i.e. switching between the video input

ports), HREF and VREF automatically synchronize to

thenewinput. Whennovideoispresent, bothHREFand

VREF float to the idling frequency of their respective

PLLs. During changes in the video input (drop-out,

switching between inputs), the performance of the

HREF and VREF signals is not guaranteed.

In the Scan Mode, the video line standard of the VREF

and HREF signals can be changed via I C command.

2

The transition always occurs at the first frame boundary

2

after the I C command is received. Fig. 2–30, below,

demonstrates the behavior of the VREF signal during

the transition from the 525/60 system to the 625/50 sys-

tem (the width of the vertical reference pulse is exagger-

ated for illustration).

2

I C Command to

Selected timing standard

becomes active

switch video timing standard

time

VREF

f

odd

even

odd

even

16.683 ms

20.0 ms

33.367 ms

40.0 ms

(525/60)

(625/50)

Fig. 2–30: Transition between timing standards

26

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

Table 2–10: Transition behavior as a function of operating mode

Transition Behavior as a Function of Operating Mode

Mode Behavior

Transition

Power up/Reset

(no video)

Open

VREF, HREF: floats to steady state frequency of internal PLL

no video → video

video → no video

video → video

Open

Scan

VREF, HREF: track the input signal

no visible effect on any data or control signals

– timing signals continue unchanged in free running mode

– VACT signal is suppressed

Open

Scan

VREF, HREF: floats to steady state frequency of internal PLL

no visible effect on any data or control signals

– timing signals continue unchanged in free running mode

– VACT signal is suppressed

Open

Scan

VREF, HREF: track the input video immediately

Data:

available immediately after color decoder locks to input.

no outwardly visible effect on any data or control signals.

– timing signals continue unchanged in free running mode

– VACT signal is suppressed

Micronas

27

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.10. Windowing the Video Field

The option, to separately specify the number of input

lines and the number of output lines, enables vertical

compression. In the VPX, vertical compression is per-

formed via simple line dropping. A nearest neighbor al-

gorithm selects the subset of the lines for output. The

presence of a valid line is signalled by the ‘video active’

qualifier (or the corresponding SAV/EAV code in em-

bedded sync modes).

For each input video field, two non-overlapping video

windows can be defined. The dimensions of these win-

2

dows are supplied via I C commands. The presence of

two windows allows separate processing parameters

suchasfilterresponsesandthenumberofpixelsperline

to be selected.

The numbering of the lines in a field of interlace video is

dependent on the line standard. Figs. 2–33 and 2–34 il-

lustrate the mapping of the window dimensions to the

actual video lines. The indices on the left are the line

numbers relative to the beginning of the frame. The in-

dices on the right show the numbering used by the VPX.

Asseenhere, theverticalboundariesofwindowsarede-

fined relative to the field boundary. Spatially, the lines

from field #1 are displayed above identically numbered

from field #2. For example: On an interlace monitor, line

#23 from field #1 is displayed directly above line #23

from field #2. There are a few restrictions to the vertical

definition of the windows. Windows must not overlap

vertically but can be adjacent. The first allowed line with-

in a field is line #10 for 525/60 standards and line #7 for

625/50 standards. The number of output lines cannot be

greater than the number of input lines (no vertical zoom-

ing). The combined height of the two windows cannot

exceed the number of lines in the input field.

External control over the dimensions of the windows is

performed by I C writes to a window-load-table (Win-

2

LoadTab). For each window, a corresponding WinLoad-

Tab is defined in a table of registers in the FP-RAM [win-

dow1: 0x120–128; window2: 0x12a–132]. Data written

to these tables does not become active until the cor-

responding latch bit is set in the control register FP-

RAM 0x140. A 2-bit flag specifies the field polarity over

which the window is active [vlinei1,2].

Vertically, as can be seen in Fig. 2–31, each window is

definedbyabeginninglinegiveninFP-RAM0x120/12A,

a number of lines to be read-in (FP-RAM 0x121/12B),

and a number of lines to be output (FP-RAM

0x122/12C). Each of these values is specified in units of

video lines.

Line 1

Horizontally, the windows are defined by a starting point

defined in FP-RAM 0x123/12D and the length in FP-

RAM 0x124/12E. They are both given relative to the

number of pixels (NPix) in the active portion of the line

(Fig. 2–32) selected in FP-RAM 0x125/12F. The scaling

factor is calculated internally from NPix.

begin

# lines in,

# lines out

Window 1

begin

53.33 msec

64 msec

# lines in,

# lines out

Window 2

Window

Fig. 2–31: Vertical dimensions of windows

H Begin

H Length

N Pix

Fig. 2–32: Horizontal dimensions of sampling window

28

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

4

5

4

5

4

5

1

2

1

2

1

2

267

268

314

315

6

7

6

7

6

7

3

4

3

4

3

4

269

270

316

317

D

18

19

20

18

19

20

22

23

24

25

18

19

20

22

23

24

25

281

282

283

22

23

24

25

335

336

337

21

284

338

D

260

523

524

525

308

309

308

309

310

311

621

622

623

624

625

261

262

263

261

262

263

261

262

263

309

310

311

310

311

312

1

2

3

264

265

264

265

264

265

312

313

312

313

266

Field 1

Field 2

Field 1

Field 2

Fig. 2–34: Mapping for 625/50 line systems

Fig. 2–33: Mapping for 525/60 line systems

2.11. Temporal Decimation

There are some restrictions in the horizontal window

definition. The total number of active pixels (NPix) must

beanevennumber. ThemaximumvalueforNPixshould

be 800. Values up to 864 are possible, but for short input

lines, video data is not guaranteed at the end of the line

since VACT will be interrupted at the beginning of the

next line. HLength should also be an even number. Ob-

viously, the sum of HBegin and HLength may not be

greater than NPix.

To cope with bandwidth restrictions in a system, theVPX

supports temporal dropping of video frames via sup-

pression of the VACT signal. Dropping will be applied for

video windows only. There is no influence on the state

of the VBI-window. This mode can be activated for each

video window by setting the enable flag in the corre-

sponding WinLoadTab (FP-RAM 0x121/12B). The

selection in FP-RAM 0x157 determines how many

frames will be output within an interval of 3000 frames.

Note that this selection is applied for both video win-

dows, but decimation can be enabled for each window

separately. The number of valid frames is updated only

ifthecorrespondinglatchflaginFP-RAM0x140[lattdec]

is set. Frame dropping with temporal decimation can be

combined with the field disable flags (FP-RAM

0x121/12B). Within valid video frames, each field type

can be disabled separately.

Window boundaries are defined by writing the dimen-

sions into the associated WinLoadTab and then setting

the corresponding latch bit in the control word FP-RAM

0x140 [latwin]. Window definition data is latched at the

beginning of the next video frame. Once the WinLoad-

Tab data has been latched, the latch bit in the Control

word is reset. By polling the Infoword (FP-RAM 0x141),

the external controller can know when the window

boundary data has been read. Window definition data

can be changed only once per frame. Multiple window

definitions within a single frame time are ignored and

can lead to error.

Micronas

29

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.12. Data Slicer

2.12.2. Data Broadcast Systems

The data slicer is only available on VPX 3225D. Soft-

ware drivers accessing the slicer I C registers should

therefore check the VPX part number.

Table 2–11 gives an overview of the most popular data

broadcast systems throughout the world. The data slicer

oftheVPX3225Dcanbeprogrammedtoacquirethedif-

2

ferent data systems via a set of I C registers.

2.12.1. Slicer Features

The various data broadcast systems are specified by a

limited set of parameters:

– 8-bit digital FBAS input

– line multiplex (VBI)

– bit rate

– 8-bit unbuffered ascii data output

– internal sync separation

– modulation

– PAL and NTSC operation

– VBI and full-field mode

– start timing

– clock run-in (CRI)

– framing code (FRC)

– number of data bytes

– automatic slicer adaptation

– text reception down to 30% eyeheight

– soft error correction

– simultaneous decoding of 4 different text services

• main service: programmable

• side service: VPS in line 16

• side service: CAPTION in line 21

• side service: WSS in line 23

– programmable text parameters for main service

• bit rate

• clock run-in

• framing code

• error tolerance

• number of data bytes

2

– operation controlled by I C registers

Table 2–11: Data Broadcast Systems

Text

System

TV

Standard

TV

Lines

Bitrate

Modulation

Timing

CRI

FRC

No.

Bytes

WST

PAL

6–22

16

6.937500Mbit/s

2.500000Mbit/s

0.833333Mbit/s

1.006993Mbit/s

1.812500Mbit/s

6.203125Mbit/s

5.727272Mbit/s

1.006993Mbit/s

1.812500Mbit/s

0.450450Mbit/s

NRZ

10.3 µs

12.5 µs

11.0 µs

10.5 µs

11.2 µs

10.5 µs

9.6 µs

’5555’x

’3c78’x

’aaa0’x

?

’27’x

’51’x

’f8’x

’c2’x

?

42

13

11

4

VPS

PAL

Bi-Phase

NRZ

WSS

PAL

23

Caption

VITC

PAL

21

PAL

6–22

10–21

21

NRZ

9

Antiope

WST

SECAM

NTSC

NRZ

’5555’x

’aaa0’x

’2aa0’x

?

’e7’x

’27’x

’e7’x

’c2’x

’b7’x

?

37

34

33

4

NRZ

NABTS

Caption

2xCaption

VITC

NRZ

10.5 µs

11.2 µs

11 µs

NRZ

10–21

20

NRZ

4

NRZ

9

CGMS

NRZ

’10’b

–

3

30

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

2.12.3. Slicer Functions

during framing code and clock run-in. The increment of

the phase accumulator is programmable and can be

used to set up any bit rate with the formula:

The data slicer is inserted between the video ADC and

the video output interface (see Fig. 1–1). It operates

completely independent of the video front-end proces-

sing and has its own sync separator and a separate set

increment = 2048 * bit rate/20.25 MHz

2

of I C registers. Figure 2–35 shows a more detailed

block diagram of the digital data slicer.

2.12.3.3. Standard Selection

The main teletext service can be received in VBI lines

only or in every line of each field (full-field mode). All

parameters needed to identify a teletext service are

programmable.

DIN

8

20.25 MHz

The slicer uses a reference of 24 bits to identify a teletext

service. This reference is compared with the first

received teletext bits which are often named clock run-in

(CRI) and framing code (FRC). If there is a match, the

slicer will start signal adaptation and write the following

data to the output stage. The reference can be reduced

in length by setting a mask for services which do not

have a 16-bit clock run-in. Bit errors can be allowed by

setting a tolerance level for every byte of the reference.

Filter

Sync

Digital

Text

Slicer

Bit Slicer

Formatter

2

I C Register

8

Additionally, the slicer can switch to other teletext

services during dedicated lines of the VBI. These can be

line 16 for VPS, line 21 for CAPTION, or line 23 for WSS.

In this case, the parameters are hard wired. Table 2–13

2

Dout

Dval

I C Bus

2

shows with which I C registers the text parameters are

programmed and what the fixed settings for the side ser-

vices are.

Fig. 2–35: Slicer block diagram

2.12.3.4. Output

2.12.3.1. Input

The slicer delivers a synchronous burst of decoded

teletext data bytes together with a data valid signal. This

data stream is fed into the video FIFO of the VPX back-

end. The data rate depends on the teletext bit rate

(divided by 8), the length of the burst is programmable.

The burst can optionally be extended to 64 bytes inde-

pendently of the selected teletext service (fill64 mode).

The dummy bytes needed to fill the burst to 64 bytes are

delivered at a rate of 20.25 MHz. Normally, there is no

output during lines without text transmission or unknown

text signals. For some applications, it is necessary to

have constant memory mapping. Therefore, the slicer

can be forced to output 64 bytes per line even if no text

is detected (dump mode).

The slicer receives an 8-bit digitized FBAS signal which

is clamped to the back porch level. The teletext signal

amplitude can vary to a certain degree (±3 dB), as the

slicer will adapt its internal slice level.

2.12.3.2. Automatic Adaptation

TheslicermeasurescertainsignalcharacteristicsasDC

offset, level, bandwith, and phase error. A digital filter at

the input stage is used to compensate bandwith effects

of the transmission channel. A DC shifter generates a

DC free text signal even in case of co-channel interfer-

ence. The internal slice level is adapted to the teletext

signal level.

The first 3 bytes of the data burst carry information to

identify the received teletext service. The 2 byte line

numbercontainsafreerunningframecounterwhichcan

be used to identify data loss in the framebuffer of a cap-

ture application. The field bit can be used to identify field

dependent services such as CAPTION. The 10-bit line

number corresponds to the standard line counting

scheme of a PAL composite video signal; in case of

NTSC, the value “3” is subtracted.

The adaption algorithm is designed for the signal char-

acteristics of a WST or NABTS transmission. For text

systems with significantly different signal characteristics

(like CAPTION), the adaption should be disabled.

Theteletextsamplingrateisgeneratedbyaphaseaccu-

mulator running at 20.25 MHz, which is synchronized

Micronas

31

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

The number of useful data bytes at the output is pro-

grammable and should be set accordingly to the se-

lected teletext standard. To get “n” data bytes, the value

“n+1” has to be programmed, because of the additional

framing code byte.

Table 2–12: Slicer Output Format

Byte

Number

Byte

Format

Bit

Format

1

line number

high

b[7:3] frame counter

b[2] odd field

In case of dump mode, byte numbers “1” and “2” are also

valid for lines without detected text data. They are then

followed by 62 dummy bytes.

b[1:0] line number[9:8]

2

3

4

.

line number low

framing code

1st data byte

...

b[7:0] line number[7:0]

b[7:0] as transmitted

...

byte_cnt+2 last data byte

b[7:0] as transmitted

b[7:0] 00000000

...

.

dummy byte

...

.

64

dummy byte

b[7:0] 00000000

Table 2–13: Slicer Programming (shaded values are hard wired)

Programmable

Parameter

I2C Register

(hex)

Main Service

e.g. WST

on/off

Side Services

VPS

WSS

CAPTION

on/off

ntsc

text reception

TV standard

TV lines

C9

on/off

pal

on/off

pal

C9

pal/ntsc

vbi/full field

702

C9

16

23

21

bitrate

C1, C2

506

102

reference

BB, BC, BD

27 55 55

00 00 03

01 01 01

43

51 55 55

00 00 00

01 01 01

28

f8 3c 78

00 00 00

01 01 01

14

c2 aa a0

00 00 1f

01 01 01

5

mask

B8, B9, BA

tolerance

CE

CF

C7

byte_cnt

64 byte mode

dump mode

adaption

on/off

off

soft error correction

32

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

2.13. VBI Data Acquisition

2.13.1. Raw VBI Data

The VPX supports two different data acquisition modes

for the vertical blanking interval: a bypass mode for raw

data of the vertical blanking interval and a data slicer

mode in which dedicated hardware provides constant

packets of already decoded VBI-data. The data slicer

mode is only available on VPX 3225D.

The raw data mode is enabled with bit[1] of FP-RAM

0x138 (vbimode). This mode bypasses the luminance

processing of the video front-end and delivers unmodi-

fied video samples from the ADC to the output ports.

During lines within the VBI-window, specified by the

user settings in the corresponding Load-Table, the VPX

internally acquires 1140 raw data bytes of the luminance

input at a rate of 20.25 MHz corresponding to 56.296 µs

of the analog video (see Fig. 2–37). Chrominance data

is not valid. The raw data samples are multiplexed inter-

nally to 570x16 bit on the luminance and chrominance

port. The external timing corresponds to the video mode

with 570 output samples for an uncropped window.

Figure 2–36 shows the timing of both data ports and the

necessary reference signals in this mode.

For both services, the start and end line of a vertical

blanking interval (VBI) window can be defined for each

field with FP-RAM 0x134–137. Teletext data can occur

between lines 6 and 23 of each field. However, the VBI-

window is freely programmable. It is possible to select

the whole field (beginning with line #3). If video windows

are enabled, the VBI-window should end two lines be-

fore the first valid line of the next video window. The VBI-

window can be activated via bit[0] in FP-RAM 0x138.

The identification of valid VBI-lines is possible with the

VACT-signal (or the ‘active line’-flags in the modes with

embedded syncs) or a special ‘data active’ signal on the

TDO pin. Bit[10] of FP-RAM 0x154 selects between

these two cases. In the default mode, VACT is used. The

output of both signals can be suppressed optionally with

bit[2]ofFP-RAM0x138. Inthiscase, thegraphiccontrol-

ler has to use only the HREF signal to mask the active

video data.

1140 samples (56.296 ms)

64 ms

In the ITU-R656 mode, VBI-data can be transmitted as

vertical ancillary data (with 7 bit resolution + odd parity).

The selections for the VBI-window will be updated by

setting bit[11] in FP-RAM 0x138.

53.33 ms

active video

Fig. 2–37: Horizontal dimensions of the window

for raw VBI-data

Luminance

(Port A)

D

2

1

1138

1137

1140

1139

Chrominance

(Port B)

VACT or TDO*

PIXCLK

LLC

* depending on bit[10] of FP-RAM 0x154

Fig. 2–36: Timing during lines with raw VBI-data (single clock mode)

Micronas

33

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.13.2. Sliced VBI Data

Table 2–14: Splitting of sliced data to luminance and

chrominance output

The sliced data mode is enabled with bit[1] of the

FP-RAM 0x138 (vbimode). This mode uses the inte-

grated data slicer (available only on VPX 3225D) and

delivers decoded data samples to the output ports.

Bit No.

Word

MSB

7

LSB

0

6

5

4

3

2

1

The data slicer provides data packets of a constant size

(filled with dummy bytes). The data packets have a de-

fault size of 64 bytes. To reduce the data rate for text sys-

tems with a smaller number of data bytes, the packet

size can be reduced via FP-RAM 0x139.

Slicer

Data

S7

S3

S6

S5

S4

S3

S2

S1

S0

S4

S0

Chroma

Output

S6

S2

S5

S1

S4

S0

S7

S3

S6

S2

S5

S1

Luma

Output

DuringlineswithintheVBI-window, specifiedbytheuser

settings in the corresponding Load-Table, the VPX inter-

nally multiplexes the data slicer packets onto the lumi-

nance and chrominance outputs. Since the values 0,

254, and 255 are protected in the 8-bit output modes

(ITU-R656, BStream), each slicer sample is separated

into two nibbles for transmission. Table 2–14 shows the

implemented data formats.

The splitting described above can be disabled by setting

bit6inthe‘format_select’register. Inthiscase, thesliced

samples will be transmitted in the luminance path only.

To avoid modification of valid data, the limitation of lumi-

nance data in the 8-bit output modes should be sup-

pressed with bit 8 in the same register (note that lumi-

nance codes will not be protected).

In each path, one nibble is transmitted twice. The LSB

is inverted for odd parity. This assures that the values 0

and 255 will not occur (for the detection of embedded

syncs). In the mode with embedded timing event codes,

chrominance data will be limited additionally. No signifi-

cant information will be lost since only Bit 0 and 1 will be

modified. Figure 2–38 shows the timing of data and ref-

erence signals in this mode.

Luminance

(Port A)

D

1 (LSBs)

1 (MSBs)

63 (LSBs)

63 (MSBs)

64 (LSBs)

64 (MSBs)

Chrominance

(Port B)

VACT

PIXCLK

LLC

Fig. 2–38: Timing during lines with sliced VBI-data (single clock mode)

34

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

2

2.14. Control Interface

The I C interface of the VPX conforms to the I C bus

specification for the fast-mode. It incorporates slope

control for the falling edges of the SDA and SCL signals.

If the power supply of the VPX is switched off, both pins

SCL and SDA float. External pull-up devices must be

adapted to fulfill the required rise time for the fast-mode.

For bus loads up to 200 pF, the pull-up device could be

a resistor; for bus loads between 200 pF and 400 pF, the

pull-up device can be a current source (3 mA max.) or

a switched resistor circuit.

2.14.1. Overview

Communication between the VPX and the external con-

troller is performed serially via the I C bus (pins SCL and

SDA).

2

There are basically two classes of registers in the VPX.

The first class of registers are the directly addressable

2

I C registers. These are registers embedded directly in

the hardware. Data written to these registers is inter-

preted combinatorially directly by the hardware. These

registers are all a maximum of 8-bits wide.

2

2.14.3. Reset and I C Device Address Selection

The VPX can respond to one of two possible chip ad-

dresses. The address selection is made at reset by an

externally supplied level on the OE pin. This level is

latched on the inactive going edge of RES.

The second class of registers are the ‘FP-RAM regis-

ters’, the memory of the onboard microcontroller (Micro-

nas Fast Processor). Data written into this class of regis-

ters is read and interpreted by the FP’s micro-code.

Internally, these registers are 12 bits wide. Communica-

2

tions with these registers require I C packets with 16-bit

data payloads.

2

Table 2–15: I C bus device addresses

OE

0

A6

1

A5

0

A4

0

A3

0

A2

0

A1

1

A0 R/W

hex

1/0 86/87

1/0 8e/8f

2

Communication with both classes of registers (I C and

2

FP-RAM) is performed via I C. The format of the I C

telegram depends on which type of register is being ad-

dressed.

1

0

1

2

2.14.2. I C Bus Interface

2.14.4. Protocol Description

2

The VPX has an I C bus slave interface and uses I C

clock synchronization to slow down the interface if re-

2

Once the reset is complete, the IC is selected by assert-

ing the device address in the address part of a I C trans-

quired. The I C bus interface uses one level of subad-

dressing. First, the bus address selects the IC, then a

subaddress selects one of the internal registers.

2

mission. A device address pair is defined as a write ad-

dress (86 hex or 8e hex) and a read address (87 hex or

8f hex). Writing is done by sending the device write ad-

dress first, followed by the subaddress byte and one or

two data bytes. For reading, the read subaddress has to

be transmitted, first, by sending the device write address

(86 hex or 8e hex) followed by the subaddress, a second

start condition with the device read address (87 hex or

8f hex), and reading one or two bytes of data. It is not al-

lowed to send a stop condition in between. This will re-

sult in reading erratic data.

I²C

subaddress

space

FP-RAM

0

Read Address

Write Address

The registers of the VPX have 8 or 16 bit data size; 16-bit

registers are accessed by reading/writing two 8-bit data

bytes with the high byte first. The order of the bits in a

data/address/subaddress byte is always MSB first.

FP

mcontroller

Data

Status

2

Figure 2–40 shows I C bus protocols for read and write

operations of the interface; the read operation requires

an extra start condition after the subaddress and repeti-

tion of the read chip address, followed by the read data

bytes. The following protocol examples use device ad-

dress hex 86/87.

ff

17f

Fig. 2–39: FP register addressing

Micronas

35

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

Write to Hardware Control Registers

S

1 0 0 0 0 1 1 0

ACK

sub-addr

ACK

send data-byte

ACK

P

Read from Hardware Control Registers

S

1 0 0 0 0 1 1 0

ACK

sub-addr

ACK

S

1 0 0 0 0 1 1 1

ACK

receive data-byte

NAK

P

2

Note:

S =

P =

I C-Bus Start Condition

2

I C-Bus Stop Condition

ACK = Acknowledge-Bit (active low on SDA from receiving device)

NAK = No Acknowledge-Bit (inactive high on SDA from receiving device)

1

0

SDA

SCL

S

P

2

Fig. 2–40: I C bus protocol

(MSB first)

2.14.5. FP Control and Status Registers

rent transmission into a wait state called clock synchro-

nization. After a certain period of time, the VPX releases

the clock and the interrupted transmission is carried on.

DuetotheinternalarchitectureoftheVPX, theICcannot

2

react immediately to all I C requests which interact with

Before accessing the address or data registers for the

FP interface (FPRD, FPWR, FPDAT), make sure that

the busy bit of FP is cleared (FPSTA).

the embedded processor (FP). The maximum response

timing is appr. 20 ms (one TV field) for the FP processor

if TV standard switching is active. If the addressed pro-

2

cessor is not ready for further transmissions on the I C

bus, the clock line SCL is pulled low. This puts the cur-

Write to FP

S

1 0 0 0 0 1 1 0

ACK

FPWR

FPDAT

ACK send FP-address- ACK send FP-address- ACK

P

byte high

byte low

ACK

send data-byte

high

ACK

send data-byte

low

ACK

Read from FP

S

1 0 0 0 0 1 1 0

ACK

FPRD

ACK send FP-address- ACK send FP-address- ACK

byte high byte low

P

1 0 0 0 0 1 1 0

FPDAT

ACK

S

1 0 0 0 0 1 1 1

ACK receive data-byte ACK receive data-byte NAK

high low

P

36

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

2.15. Initialization of the VPX

Table 2–16: State of the pins during and after reset

2.15.1. Power-on-Reset

Pins

Reset

Active

Inactive

Setup

Active

Setup

(FIELD=0) (FIELD=1)

In order to completely specify the operational mode of

the VPX, appropriate values must be loaded into the I C

2

Port A

Port B

HREF

VREF

FIELD

VACT

Tri-State

active (OE=0)

active

and FP registers. After powering the VPX, an internal

power-on-reset clears all the FP/I C-Registers. An ini-

2

tialization routine loads the default values for both the

2

I C and FP registers from internal program ROM. The

externalRES pin forces all outputs to be tri-stated. At the

inactive going edge of the RES pin, OE and FIELD are

read in for configuration. The FIELD pin is internally

pulled down, an external pull-up resistor could be used

to define a different power-on configuration. The power-

onconfigurationisreadoneveryrisingedgeoftheexter-

nal RES pin.

active

pull down Tri-State

active

Tri-State

active

PIXCLK Tri-State

active

13.5 MHz

Either inactive (tri-state) or active output pins could be

chosen with the FIELD pin at the inactive going edge of

RES. In the inactive state, all relevant output pins are tri-

stated, thisincludesPortA, PortB, HREF, VREF, FIELD,

VACT, PIXCLK, LLC, and LLC2. In the active setup, all

of these pins are driven. Table 2–16 gives an overview

of the different setups. Additionally, the data ports A and

B can be tri-stated with an external pullup resistor at the

output enable pin OE. The ports can be reactivated ei-

LLC

Tri-State

active

27 MHz

TDO/

LLC2

active

program-

mable output

2

ther by the OE pin or via setting bit 7 in I C register 0xF2

(”oeq_dis”).

With the FIELD pin pulled down at the inactive going

edge of RES, the VPX comes up in the low power mode.

This mode is introduced for power consumption critical

applications. It can be turned on and off with bit[1:0] in

The VPX always comes up in NTSC square pixel mode

(640x240, both fields). In the case of inactive low power

mode, the internal H-Sync scheduler is switched off, as

in normal low power mode. After enabling the chip via

2

the I C register 0xAA (”lowpow”). There are three levels

of low power mode. When any of them is turned on, the

VPXwaits for at least one complete video scan line in or-

der to complete all internal tasks and then goes into tris-

tate mode. The exact moment is not precisely defined,

so care should be taken to deactivate the system using

VPX data before the end of the video scan line in which

theVPXisswitchedintolowpowermode. Duringthelow

2

I C Interface, the H-Sync scheduler is enabled and the

chips goes into a normal active NTSC operation condi-

tion.

2.15.2. Software Reset

2

power mode, all the I C and FP registers are preserved,

TheVPXprovidesthepossibilityofasoftwareresetgen-

so that the VPX restores its normal operation as soon as

low power mode is turned off, without need for any re-ini-

2

erated via I C command (I C register 0xAA, bit 2). Be

aware that this software reset does not activate the con-

figuration read-in during power-on reset.

2

tialization. On the other hand, all the I C and FP regis-

ters can be read/written as usual. The only exception is

2

the third level (value of 3 in I C register 0xAA) of low

2

power. In that mode, I C speeds above 100 kbit/sec are

2.15.3. Low Power Mode

2

not allowed. In modes 1 and 2, I C can be used up to the

full speed of 400 kbit/s.

The VPX goes into low power mode, if the inactive mode

has been chosen. This is equal to the manual chosen

low-power mode. Note, that every manual selection of

the power mode (full or low-power) overwrites (resets!)

the power-up configuration. However, the current con-

2

figuration cannot be read via the corresponding I C reg-

ister. Other restrictions are that the selection of the low-

2

power mode limits the rate of the I C-interface to

100 kHz, and that the IC comes up with full power con-

sumption until the low-power circuit becomes active.

Micronas

37

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.16. JTAG Boundary-Scan, Test Access Port (TAP)

2.16.2.2. Instruction Register

The instruction register chooses which one of the data

registers is placed between the TDI and TDO pins when

the select data register state is entered in the TAP con-

troller. When the select instruction register state is ac-

tive, the instruction register is placed between the TDI

and TDO.

The design of the Test Access Port, which is used for

Boundary-Scan Test, conforms to standard IEEE

1149.1-1990, with one exception. Also included is a list

of the mandatory instructions supported, as well as the

optional instructions. The following comprises a brief

overview of some of the basics, as well as any optional

features which are incorporated. The IEEE 1149.1 docu-

ment may be necessary for a more concise description.

Finally, an adherence section goes through a checklist

of topics and describes how the design conforms to the

standard.

Instructions

The following instructions are incorporated:

– bypass

– sample/preload

– extest

The implementation of the instructions HIGHZ and

CLAMP conforms to the supplement P1149.1/D11 (Oc-

tober 1992) to the standard 1149.1-1990.

– master mode

– ID code

2.16.1. General Description

– HIGHZ

– CLAMP

The TAP in the VPX is incorporated using the four signal

interface. The interface includes TCK, TMS, TDI, and

TDO. The optional TRESET signal is not used. This is

not needed because the chip has an internal power-on-

reset which will automatically steer the chip into the

TEST-LOGIC-RESET state. The goal of the interface is

to provide a means to test the boundary of the chip.

There is no support for internal or BIST(built-in self test).

The one exception to IEEE 1149.1 is that the TDO output

is shared with the LLC2 signal. This was necessitated

due to I/O restrictions on the chip (see section 2.16.3.

“Exceptions to IEEE 1149.1” for more information).

2.16.2.3. Boundary Scan Register

The boundary scan register (BSR) consists of boundary

scan cells (BSCs) which are distributed throughout the

chip. These cells are located at or near the I/O pad. It al-

lows sampling of inputs, controlling of outputs, and shift-

ingbetweeneachcellinaserialfashiontoformtheBSR.

This register is used to verify board interconnect.

Input Cell

The input cell is constructed to achieve capture only.

This is the minimal cell necessary since Internal Test

(INTEST) is not supported. The cell captures either the

system input in the CAPTURE-DR state or the previous

cells output in the SHIFT-DR state. The captured data is

then available to the next cell. No action is taken in the

UPDATE-DR state. See Figure 10–11ofIEEE1149.1for

reference.

2.16.2. TAP Architecture

The TAP function consists of the following blocks: TAP-

controller, instruction register, boundary-scan register,

bypass register, optional device identification register,

and master mode register.

2.16.2.1. TAP Controller

Output Cell

The TAP controller is responsible for responding to the

TCK and TMS signals. It controls the transition between

states of this device. These states control selection of

the data or instruction registers, and the actions which

occur in these registers. These include capture, shifting,

and update. See Fig. 5–1 of IEEE 1149.1 for TAP state

diagram.

The output cell will allow both capture and update. The

capture flop will obtain system information in the CAP-

TURE-DR state or previous cells information in the

SHIFT-DR state. The captured data is available to the

next cell. The captured or shifted data is downloaded to

the update flop during the UPDATE-DR state. The data

from the update flop is then multiplexed to the system

outputpinwhentheEXTESTinstructionisactive. Other-

wise, the normal system path exists where the signal

fromthesystemlogicflowstothesystemoutputpin. See

Fig. 10–12 of IEEE 1149.1 for reference.

38

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

Tristate Cell

2.16.4. IEEE 1149.1-1990 Spec Adherence

Each group of output signals, which are tristatable, is

controlled by a boundary scan cell (output cell type).

This allows either the normal system signal or the

scanned signal to control the tristate control. In the VPX,

there are four such tristate control cells which control

groupsofoutputsignals(seesection“OutputDriverTris-

tate Control” for further information).

This section defines the details of the IEEE1149.1 de-

sign for the VPX. It describes the function as outlined by

IEEE1149.1, section 12.3.1. The section of that docu-

ment is referenced in the description of each function.

2.16.4.1. Instruction Register

Bidirect Cell

(Section 12.3.1.b.i of IEEE 1149.1-1990)

The bidirect cell is comprised of an input cell and a tris-

tate cell as described in the IEEE standard. The signal

PIXCLK is a bidirectional signal.

The instruction register is three bits long. No parity bit is

included. The pattern loaded in the instruction register

during CAPTURE-IR is binary “101” (MSB to LSB). The

two LSBs are defined by the spec to be “01” (bit 1 and

bit 0) while the MSB (bit 2) is set to “1”.

2.16.2.4. Bypass Register

This register provides a minimal path between TDI and

TDO. This is required for complicated boards where

many chips may be connected in serial.

2.16.4.2. Public Instructions

(Section 12.3.1.b.ii of IEEE 1149.1-1990)

A list of the public instructions is as follows:

2.16.2.5. Device Identification Register

This is an optional 32-bit register which contains the

Micronas identification code (JEDEC controlled), part

and revision number. This is useful in providing the tes-

ter with assurance that the correct part and revision are

inserted into a PCB.

Instruction

EXTEST

Code (MSB to LSB)

000

SAMPLE/PRELOAD

ID CODE

001

2.16.2.6. Master Mode Data Register

010

MASTER MODE

HIGHZ

011

This is an optional register used to control an 8-bit test

register in the chip. This register supports shift and up-

date. No capture is supported. This was done so the last

word can be shifted out for verification.

100

CLAMP

110

BYPASS

100 – 111

2.16.3. Exception to IEEE 1149.1

There is one exception to IEEE 1149.1. The exception

is to paragraphs 3.1.1.c., 3.5.1.b, and 5.2.1.d (TEST-

LOGIC-RESET state). Because of pin limitations on the

chip, a pin is shared for two functions. When the circuit

is in the TEST-LOGIC-RESET state, the LLC2 signal is

driven out the TDO/LLC2 pin. When the circuit leaves

theTEST-LOGIC-RESETstate, theTDOsignalisdriven

onthisline. AslongasthecircuitisnotintheTEST-LOG-

IC-RESET state, all the rules for application of the TDO

signal adhere to the IEEE1149.1 spec.

The EXTEST and SAMPLE/PRELOAD instructions

both apply the boundary scan chain to the serial path.

The ID CODE instruction applies the ID register to the

serial chain. The BYPASS, the HIGHZ, and the CLAMP

instructions apply the bypass register to the serial chain.

TheMASTERMODEinstructionisatestdatainstruction

for public use. It provides the ability to control an 8-bit

test register in the chip.

Since the VPX uses the JTAG function as a boundary-

scantool, theVPXdoesnotsacrificetestofthispinsince

it is verified by exercising JTAG function. The designer

of the PCB must make careful note of this fact, since he

will not be able to scan into chips receiving the LLC2 sig-

nal via the VPX. The PCB designer may want to put this

chip at the end of the chain or bring the VPX TDO out

separately and not have it feed another chip in a chain.

Micronas

39

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2.16.4.3. Self-Test Operation

2.16.4.5. Boundary Scan Register

(Section 12.3.1.b.iii of IEEE 1149.1-1990).

(Section 12.3.1.b.v of IEEE 1149.1-1990)

There is no self-test operation included in the VPX de-

sign which is accessible via the TAP.

The boundary scan chain has a length of 38 shift regis-

ters. The scan chain order is specified in the section “Pin

Connections”.

2.16.4.4. Test Data Registers

2.16.4.6. Device Identification Register

(Section 12.3.1.b.iv of IEEE 1149.1-1990).

(Section 12.3.1.b.vi of IEEE 1149.1-1990)

The VPX includes the use of four test data registers.

They are the required bypass and boundary scan regis-

ters, the optional ID code register, and the master mode

register.

The manufacturer’s identification code is “6C”

Micronas. The general implementation scheme uses

only the 7 LSBs and excludes the MSB, which is the par-

for

(hex)

ity bit. The part number is “7230”

. in case of

(hex)

The bypass register is, as defined, a 1-bit register ac-

cessed by codes 100 through 111, inclusive. Since the

design includes the ID code register, the bypass register

is not placed in the serial path upon power-up or Test-

Logic-Reset.

VPX 3225D and “7231”

. in case of VPX 3224D. The

(hex)

version code starts from “1”

and changes with every

(hex)

revision. The version number relates to changes of the

chip interface only.

2.16.4.7. Performance

The master mode is an 8-bit test register which is used

to force the VPX into special test modes. This is reset

upon power-on-reset. This register supports shift and

update only. It is not recommended to access this regis-

ter. The loading of that register can drive the IC into an

undefined state.

(Section 12.3.1.b.vii of IEEE 1149.1-1990)

See section “Specification” for further information.

Version

Part Number

7F

Manufacturer ID

0 0 0 1 0 1 0 0 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 1 1 0 1 1 0 0 1

31

28 27

12 11

8

7

1

0

2

7

2

3

0

d

9

Fig. 2–41: Device identification register

40

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

TAP State Transitions

TDO could be used as programmable output pin or LLC2

clock signal (see Pin Description).

$F

1

0

Test-Logic-Reset

0

$C

$7

$4

1

Run / Idle

Select Data Reg

Select Instr. Reg

0

$6

$2

$E

$A

1

Capture DR

Capture IR

0

1

0

1

Shift DR

Shift IR

1

$1

$3

$9

$B

Exit1 DR

Exit1 IR

0

Pause DR

Pause IR

1

$0

$5

$8

Exit2 DR

Exit2 IR

1

$D

State Code

Update DR

Update IR

TDO inactive

TMS=1

TMS=0

TMS=1

TMS=0

TDO active

State transitions are dependend on the value of TMS, synchronized by TCK.

Fig. 2–42: TAP state transitions

Micronas

41

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

––*************************************************************

––

–– This is the BSDL for the 44-Pin Version of the VPXD design.

––

––*************************************************************

Library IEEE;

Use work.STD_1149_1_1990.ALL;

Entity VPXD_44 is

Generic (Physical_Pin_Map:string := ”UNDEFINED”);

Port(

––define ports

TDI,TCK,TMS:

TDO,HREF,VREF,FIELD:

A:

in bit;

out bit;

out bit_vector(7 downto 0);

PVDD,PVSS:

PIXCLK:

linkage bit;

out bit;

OEQ:

in bit;

LLC, VACT:

out bit;

B:

out bit_vector(7 downto 0);

inout bit;

SDA,SCL:

VSS,XTAL2,XTAL1,VDD:

RESQ:

linkage bit;

in bit;

AVDD,AVSS,VRT,ISGND:

CIN,VIN1,VIN2,VIN3:

linkage bit;

in bit

);

Attribute Pin_Map of VPXD_44 : Entity is Physical_Pin_Map;

constant Package_44 : Pin_Map_String :=

––map pins to signals

”TDI

: 1 ” &

: 2 ” &

: 3 ” &

: 4 ” &

: 5 ” &

”TCK

”TDO

”HREF

”VREF

”FIELD : 6 ” &

”A

: (7,8,9,10,14,15,16,17)” &

”PVDD : 11 ” &

”PIXCLK : 12 ” &

”PVSS

”OEQ

”LLC

”VACT

”B

: 13 ” &

: 18 ” &

: 19 ” &

: 20 ” &

: (21,22,23,24,25,26,27,28),” &

”SDA

”SCL

”RESQ

”VSS

”VDD

: 29 ” &

: 30 ” &

: 31 ” &

: 32 ” &

: 33 ” &

”XTAL2 : 34 ” &

”XTAL1 : 35 ” &

”AVDD : 36 ” &

”CIN

: 37 ” &

: 38 ” &

: 39 ” &

: 40 ” &

: 41 ” &

: 42 ” &

”AVSS

”VIN1

”VIN2

”VRT

”VIN3

”ISGND : 43 ” &

”TMS : 44 ” ;

Attribute Tap_Scan_In

of TDI

: signal is true;

––define JTAG Controls

Attribute Tap_Scan_Mode of TMS : signal is true;

Attribute Tap_Scan_Out of TDO : signal is true;

Attribute Tap_Scan_Clock of TCK

: signal is (10.0e6,Both);

––max frequency and levels TCK can be stopped at.

––define instr. length

Attribute Instruction_Length

of VPXD_44: entity is 3;

Attribute Instruction_Opcode

of VPXD_44: entity is

”EXTEST

(000),” &

––External Test

42

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

”SAMPLE

”IDCODE

(001),” &

(010),” &

––Sample/Preload

––ID Code

”MASTERMODE

”HIGHZ

(011),” &

(100),” &

––Master Mode (internal Test)

–– Highz

”CLAMP”

”BYPASS

(110),” &

(100,101,110,111),”;

–– Clamp

––Bypass

Attribute Register_Access

”BOUNDARY

of VPXD_44: entity is

(EXTEST,SAMPLE),” &

(BYPASS, HIGHZ, CLAMP),” &

(IDCODE),” &

––instr. vs register

––control

”BYPASS

”IDCODE[32]

”MASTERMODE[8]

(MASTERMODE) ”;

Attribute INSTRUCTION_Capture of VPXD_44: entity is ”101”;

––captured instr.

Attribute IDCODE_Register

Attribute Boundary_Cells

of VPXD_44: entity is

”0001” &

”0100011010000000” &

”0000” &

”1101100” &

”1”;

––initial rev

––part numb. 7230

––7F Count

––Micronas Code–Parity

––Mandatory LSB

of VPXD_44: entity is ”BC_1,BC_4”;

–-BC_1 for output cell

––BC_4 for input cell

Attribute Boundary_Length

Attribute Boundary_Register

of VPXD_44: entity is 38;

of VPXD_44: entity is

––Boundary scan length

––Boundary scan defin.

––

num

” 37

” 36

” 35

” 34

” 33

” 32

” 31

” 30

” 29

” 28

” 27

” 26

” 25

” 24

” 23

” 22

” 21

” 20

” 19

” 18

” 17

” 16

” 15

” 14

” 13

” 12

” 11

” 10

cell port

function safe

ccel

disval rslt

(BC_4, VIN3, input,

(BC_4, VIN2, input,

(BC_4, VIN1, input,

(BC_4, CIN,

(BC_1, *,

X

),” &

input,

internal, X

),” & ––low power mode

),” &

),” & ––open collector

),” &

),” & ––open collector

),” &

),” & ––control

),” &

),” & ––control

),” &

(BC_4, RESQ, input,

X

(BC_4, SCL,

(BC_1, SCL,

(BC_4, SDA,

(BC_1, SDA,

(BC_1, B(0),

(BC_1, B(1),

(BC_1, B(2),

(BC_1, B(3),

(BC_1, B(4),

(BC_1, B(5),

(BC_1, B(6),

(BC_1, B(7),

(BC_1, *,

(BC_1, VACT, output3, X,

(BC_1, LLC,

(BC_1, *,

(BC_4, OEQ,

(BC_1, A(0),

(BC_1, A(1),

(BC_1, A(2),

(BC_1, A(3),

(BC_1, *,

input,

output3, X,

input,

30,

1,

Z

X

output3, X,

control, X

28,

19,

1,

Z

16,

1,

Z

output3, X,

control, X

input,

X

output3, X,

control, X

8,

1,

Z

),” & ––control

”

9

8

7

6

5

4

3

2

1

0

(BC_1, PIXCLK,output3, X,

10,

1,

Z

),” &

),” & ––control

),” &

),” & ––control

),” &

),”;

(BC_1, *,

control, X

output3, X,

control, X,

(BC_1, A(4),

(BC_1, A(5),

(BC_1, A(6),

(BC_1, A(7),

(BC_1, *,

8,

,

3,

16,

1,

Z

(BC_1, FIELD, output3, X,

(BC_1, VREF, output3, X,

(BC_1, HREF, output3, X,

End VPXD_44;

Micronas

43

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2

2.17. Enable/Disable of Output Signals

I C Control:

In order to enable the output pins of the VPX to achieve

thehighimpedance/tristatemode, variouscontrolshave

been implemented. The following paragraphs give an

overview of the different tristate modes of the output sig-

nals. It is valid for all output pins, except the XTAL2

(which is the oscillator output) and the VRT pin (which is

an analog reference voltage).

The tristate condition of groups of signals can also be

controlled by setting the I C-Register 0xF2. If the circuit

2

is neither in EXTEST mode nor RESET state, then the

2

I C-Register 0xF2 defines whether the output is in tris-

2

tate condition or not (see “I C-Registers VPX Back-

end”).

Output Enable Input OE:

BS (Boundary Scan) Mode:

The output enable signal OE only effects the video out-

put ports. If the previous three conditions do not cause

the output drivers to go into high impedance mode, then

the OE signal defines the driving conditions of the video

data ports.

The tristate control by the test access port TAP for

boundary scan has the highest priority. Even if the TAP-

controller is in the EXTEST or CLAMP mode, the tristate

behavior is only defined by the state of the different

boundary scan registers for enable control. If the TAP

controller is in HIGHZ mode, then all output pins are in

tristate mode independently of the state of the different

boundary scan registers for enable control.

2

The OE pin function can be disabled via I C register

0xF2 [oeq_dis]. The OE signal will either directly con-

nect the output drivers or it will be latched internally with

2

the LLC signal depending on I C register 0xF2 [latoeq].

Additionally, a delay of 1 LLC clock cycle can be enabled

with I C register 0xF2 [oeqdel].

RESET State:

2

IftheTAP-controllerisnotintheEXTESTmode, thenthe

RESET-state defines the state of all digital outputs. The

only exception is made for the data output of the bound-

ary scan interface TDO. If the circuit is in reset condition

(RES = 0), then all output interfaces are in tristate mode.

Table 2–17: Output driver configuration

2

EXTEST

RESET

I C

OE#

Driver Stages

active

–

Output driver stages are defined by the state of the different

boundary scan enable registers.

inactive

active

–

Output drivers are in high impedance mode.

inactive

= 0

= 1

–

Output drivers are in high impedance mode. PIXCLK is working.

= 0

Output drivers HREF, VREF, FIELD, VACT, LLC, are working.

Outputs A[7:0] and B[7:0] are working

inactive

= 1

Output drivers HREF, VREF, FIELD, VACT, LLC, are working.

Output drivers of A[7:0] and B[7:0] are in high impedance mode.

Remark: EXTEST mode is an instruction conforming to the standard for Boundary Scan Test IEEE 1149.1 – 1990

44

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

3. Specification

3.1. Outline Dimensions

± 0.1

10 x 1.27 = 12.7

±0.1

1.27

1.2 x 45°

1.1 x 45 °

6

1

40

7

39

1.6

6

2

8.6

5

17

29

1.9

4.05

18

28

± 0.125

± 0.1

16.5

17.525

0.1

±0.15

4.75

SPGS7003-2/3E

Fig. 3–1:

44-Pin Plastic Leaded Chip Carrier Package

(PLCC44)

Weight approximately 2.5 g

Dimensions in mm

3.2. Pin Connections and Short Descriptions

NC = not connected; leave vacant

X = obligatory

Pin No.

PLCC44

Pin Name

Pin Type

Connection

(if not used)

Short Description

1

2

3

TDI

IN

NC

Boundary-Scan-Test Data Input

Boundary-Scan-Test Clock Input

TCK

IN

TDO

LLC2

DACT

OUT

Boundary-Scan-Test Data Output

LLC / 2 = 13.5MHz Output

Active VBI Data Qualifier Output

4

HREF

VREF

FIELD

A7

OUT

NC

X

Horizontal Reference Output

Vertical Reference Output

Odd/Even Field Identifier Output

Port A – Video Data Output

Supply Voltage Pad Circuits

Pixel Clock Output

5

OUT

6

OUT

7

OUT

8

A6

OUT

9

A5

OUT

10

11

12

13

14

A4

OUT

PVDD

PIXCLK

PVSS

A3

SUPPLY

OUT

NC

X

SUPPLY

OUT

Ground, Pad Circuits

NC

Port A – Video Data Output

Micronas

45

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

Pin Connections and Short Descriptions, continued

Pin No.

PLCC44

Pin Name

Type

Connection

(if not used)

Short Description

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

A2

OUT

NC

VSS

NC

X

Port A – Video Data Output

Output Ports Enable Input

PIXCLK * 2 = 27 MHz Output

Active Video Qualifier Output

Port B – Video Data Output

A1

OUT

A0

OUT

OE

IN

LLC

VACT

B7

OUT

B6

OUT

B5

OUT

B4

OUT

B3

OUT

B2

OUT

B1

OUT

B0

OUT

2

SDA

SCL

RES

VSS

VDD

XTAL2

XTAL1

AVDD

CIN

AVSS

VIN1

VIN2

VRT

VIN3

ISGND

TMS

IN/OUT

IN

I C Bus Data

2

I C Bus Clock

Reset Input

SUPPLY

OSC OUT

OSC IN

SUPPLY

AIN

X

Ground, Digital Circuitry

Supply Voltage, Digital Circuitry

Analog Crystal Output

X

Analog Crystal Input

X

Supply Voltage, Analog Circuitry

Analog Chroma Input

NC

X

SUPPLY

AIN

Ground, Analog Circuitry

Analog Video 1 Input

NC

X

AIN

Analog Video 2 Input

Reference

AIN

Reference Voltage Top, Video ADC

Analog Video 3 Input

NC

X

SUPPLY

IN

Signal Ground, Analog Video Inputs

Boundary-Scan-Test Mode Select

NC

46

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

3.3. Pin Descriptions

Pins 21 to 28 – Video, Port B[7:0] (Fig. 3–6)

Video output port to deliver chroma data. In 8-bit modes,

Port B can be activated as programmable output (see

section 2.6.3.).

Pins 44, 1 – JTAG Input Pins, TMS, TDI (Fig. 3–4)

Test Mode Select and Test Data Input signals of the

JTAG Test Access Port (TAP). Both signals are inputs

with a TTL compatible input specification. To comply

with JTAG specification they use pull-ups at their input

stage. The input stage of the TMS and TDI uses a TTL

Schmitt Trigger.

2

Pin 29 – I C Bus Data, SDA (Fig. 3–5)

2

This pin connects to the I C bus data line.

2

Pin 30 – I C Bus Clock, SCL (Fig. 3–5)

2

This pin connects to the I C bus clock line.

Pin 2 – JTAG Input Pin, TCK (Fig. 3–3)

Clock signal of the Test-Access Port. It is used to syn-

chronize all JTAG functions. When JTAG operations are

not being performed, this pin should be driven to VSS.

The input stage of the TCK uses a TTL Schmitt Trigger.

Pin 31 – Reset Input, RES (Fig. 3–3)

A low level on this pin resets the VPX 3225D.

Pin 32 – Ground (Digital Circuitry), VSS

Pin 3 – JTAG Output Pin, TDO, LLC2, DACT (Fig. 3–6)

Data output for JTAG Test Access Port (TAP). Moreover,

if Test Access Port (TAP) is in Test-Logic-Reset State,

this pin can be used as output pin of the LLC2 clock sig-

nal (I C Reg. 0xF2 bit[4] = 1) or it can be used as output

pin for the active VBI-Data signal DACT (see section

2.13.).

Pin 33 – Supply Voltage (Digital Circuitry), VDD

Pins 34, 35 – Crystal Input and Output, XTAL1, XTAL2

(Fig. 3–8)

Thesepinsareconnectedtoa20.25MHzcrystaloscilla-

tor which is digitally tuned by integrated shunt capaci-

tances. An external clock can be fed into XTAL1. In this

case, clock frequency adjustment must be switched off.

2

Pins 4 to 6 – Reference Signals, HREF, VREF, FIELD

(Fig. 3–6)

Pin 36 – Supply Voltage (Analog Circuitry), AVDD

Thesesignalsareinternallygeneratedsyncsignals. The

state of FIELD during the positive edge of RES selects

the power up mode (see section 2.15.1.).

Pin 37 – Chroma Input, CIN (Fig. 3–12, Fig. 3–11)

This pin is connected to the S-VHS chroma signal. A re-

sistive divider is used to bias the input signal to the

middle of the converter input range. CIN can only be

connected to the chroma (Video 2) A/D converter. The

signal must be AC-coupled.

Pins 7 to 10, 14 to 17 – Video, Port A[7:0] (Fig. 3–6)

Video output port to deliver luma and/or chroma data.

Pin 11 – Supply Voltage (Pad Circuitry), PVDD

Pin 38 – Ground (Analog Front-end), AVSS

Pins 12, 19 – Pixel Clock, PIXCLK, LLC (Fig. 3–6)

PIXCLK and LLC are the reference clock signals for the

video data transmission ports A[7:0] and B[7:0].

Pins 39, 40, 42 – Video Input 1–3, VIN1–3 (Fig. 3–10)

These are the analog video inputs. A CVBS, S-VHS

luma signal is converted using the luma (Video 1) A/D

converter. The VIN1 input can also be switched to the

chroma (Video 2) ADC. The input signal must be AC-

coupled.

Pin 13 – Ground (Pad Circuitry), PVSS

Pin 18 – Output Enable Input Signal, OE (Fig. 3–3)

The output enable input signal has TTL Schmitt Trigger

input characteristic. It controls the tri-state condition of

both video ports. The state during the positive edge of

Pin 41 – Reference Voltage Top, VRT (Fig. 3–9)

Via this pin, the reference voltage for the A/D converters

is decoupled. The pin is connected with 10 mF/47 nF to

the Signal Ground Pin.

2

RES selects the I C device address (see section

2.14.3.).

Pins 20 – Video Qualifier Output, VACT (Fig. 3–6)

This pin delivers a signal which qualifies active video

samples.

Pin 43 – Ground (Analog Signal Input), ISGND

This is the high-quality ground reference for the video

input signals.

Micronas

47

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

3.4. Pin Configuration

TDI

TCK

TDO (LLC2, DACT)

HREF

VREF

FIELD

TMS

ISGND

VIN3

VRT

VIN2

6

5

4

3

2

1 44 43 42 41 40

A7

A6

A5

A4

7

VIN1

AVSS

CIN

AVDD

XTAL1

XTAL2

VDD

VSS

RES

SCL

SDA

39

38

37

36

35

34

33

32

31

30

29

8

9

VPX 3225D

VPX 3224D

10

11

12

13

14

15

16

17

PVDD

PIXCLK

PVSS

A3

Top View

A2

A1

A0

18 19 20 21 22 23 24 25 26 27 28

OE

LLC

VACT

B7

B0

B1

B2

B3

B6

B4

B5

Fig. 3–2: 44-pin PLCC package.

VDD

3.5. Pin Circuits

VDD

VSS

2

VSS

Fig. 3–5: I C Interface SDA, SCL

Fig. 3–3: TCK, OE, RES

The characteristics of the Schmitt Triggers are depend

on the supply of VDD/VSS.

PVDD

P

PVDD

VDD

OUT

N

PVSS

VSS

Fig. 3–6: A[7:0], B[7:0], HREF, VREF, LLC,

PIXCLK, VACT, TDO

Fig. 3–4: TMS, TDI

48

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

VDD

AVDD

VIN1

VIN2

VIN3

N

To ADC1

AVSS

N

VSS

RES

N

clamping

Fig. 3–10: Video Inputs ADC1

PVDD

P

FIELD

N

PVSS

Fig. 3–7: Reference Signal FIELD and wake-up

selection LOWPOW on positve edge of RES

AVDD

VIN1

CIN

N

To ADC2

AVDD

XTAL2

XTAL1

P

N

f

ECLK

0.5M

AVSS

bias

Fig. 3–11: Video Inputs ADC2

AVSS

Fig. 3–8: Crystal Oscillator

AVDD

VRT

–

P

BIAS

VIN1,

VIN2,

+

VRT

off

VIN3,

ADC Reference

AVSS

CIN

Fig. 3–12: Unselected Video Inputs

Fig. 3–9: Reference Voltage VRT

Micronas

49

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

4. Electrical Characteristics

4.1. Absolute Maximum Ratings

Symbol

Parameter

Min.

Max.

Unit

Name

T

Ambient Temperature

0

65

°C

V

A

T

Storage Temperature

–40

0

125

6

S

J

Junction Temperature

V

P

Supply Voltage, all Supply Inputs

–0.3

SUB

Power Dissipation due to package

characteristics

VDD,

PVDD,

AVDD

1170

mW

TOT MAX

1)

Input Voltage of FIELD, TMS, TDI

Input Voltage

PVSS – 0.5

VSS – 0.5

PVDD + 0.5

V

TCK

6

Input Voltage

SDA,

SCL

Signal Swing

A[7:0],

B[7:0],

PIXCLK,

HREF,

VREF,

FIELD,

VACT,

LLC,

PVSS – 0.5

PVDD + 0.5

V

TDO

Maximum D | VDD – AVDD |

0.5

0.1

V

Maximum D | VSS – PVSS |

Maximum D | VSS – AVSS |

Maximum D | PVSS – AVSS |

1)

External voltage exceeding PVDD+0.5 V should not be applied to these pins even when they are tri-stated.

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in the

“Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute maxi-

mum ratings conditions for extended periods may affect device reliability.

50

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

4.2. Recommended Operating Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

Name

T

Ambient Operating Temperature

Analog Supply Voltage

Digital Supply Voltage

Pad Supply Voltage

–

0

–

65

°C

V

A

V

AVDD

VDD

4.75

3.15

5.0

5.25

SUPA

SUPD

SUPP

XTAL

V

1)

PVDD

XTAL1/2

3.6

V

f

Clock Frequency

20.250

MHz

1)

could also be connected to the 5 V supply net; but for best performance, it is recommended to connect it to 3.3 V

supply (see Fig. 7–1).

4.2.1. Recommended Analog Video Input Conditions

Symbol

Parameter

Min.

Typ.

Max.

Unit

Name

V

VIN

Analog Input Voltage

VIN1,

VIN2,

VIN3,

CIN

0

–

3.5

V

C

CP

Input Coupling Capacitor

Video Inputs

VIN1,

VIN2,

VIN3

680

nF

C

R

Input Coupling Capacitor

Chroma Input

CIN

1

nF

CP

Recommended Drive Impedance

VIN1,

VIN2,

VIN3,

CIN

75

100

W

PD

Micronas

51

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2

4.2.2. Recommended I C Conditions

(Timing diagram see Fig. 5–3 on page 61)

Symbol

Parameter

Min.

Typ.

Max.

Unit

Name

2

V

I C-BUS Input Low Voltage

SCL,

SDA

0.3

VDD

kHz

ns

IMIL

IMIH

SCL

I2C1

I2C2

I2C3

I2C4

I2C5

2

I C-BUS Input High Voltage

0.6

2

f

t

I C-BUS Frequency

SCL

100

2

I C START Condition Setup Time

SCL,

SDA

1200

5000

55

2

I C STOP Condition Setup Time

ns

2

I C-Clock Low Pulse Time

SCL

ns

2

I C-Clock High Pulse Time

ns

2

I C-Data Setup Time Before

SCL,

SDA

ns

Rising Edge of Clock

2

t

I C-Data Hold Time after Falling

55

ns

I2C6

Edge of Clock

4.2.3. Recommended Digital Inputs Levels of RES, OE, TCK, TMS, TDI

Symbol

Parameter

Min.

Typ.

Max.

Unit

Name

V

IL

Input Voltage LOW

RES,

OE,

–0.5

0

0.8

V

TCK,

TMS,

TDI

V

Input Voltage HIGH

RES,

OE,

TCK

2.0

5

6

V

IH

TDI,

TMS

PVDD

PVDD +

0.3

IH

52

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

4.2.4. Recommended Crystal Characteristics

Symbol

Parameter

Min.

Typ.

Max.

65

Unit

°C

T

A

Operating Ambient Temperature

Parallel Resonance Frequency

0

–

f

P

20.250000

–

MHz

with Load Capacitance C = 13 pF

fundamental

L

Df /f

Accuracy of Adjustment

Frequency Temperature Drift

Series Resistance

–

±20

±30

25

7

ppm

W

P P

Df /f

P P

–

R

C

0

C

1

–

Shunt Capacitance

3

pF

Motional Capacitance

20

30

fF

Load Capacitance Recommendation

1)

C

Lext

External Load Capacitance from

pins to Ground (PLCC44)

–

4.7

–

pF

(pin names: Xtal1 Xtal2)

2)

DCO Characteristics

C

Effective Load Capacitance @ min.

DCO-Position, Code 0,

package: PLCC44

3

4.3

5.5

pF

ICLoadmin

C

Effective Load Capacitance Range,

DCO Codes from 0..255

8.7

12.7

16.7

ICLoadrng

1)

Remarks on defining the External Load Capacitance:

External capacitors at each crystal pin to ground are required. They are necessary to tune the effective load

capacitance of the PCBs to the required load capacitance (C ) of the crystal. The higher the capacitors, the

L

lower the clock frequency results. The nominal free running frequency should match f = 20.25 MHz. Due to

p

different layouts of customer PCBs, the matching capacitor size should be determined in the application. The

suggested value is a figure based on experience with various PCB layouts.

Tuning condition: Code DVCO Register = –720

2)

Remarks on Pulling Range of DCO:

The pulling range of the DCO is a function of the used crystal and effective load capacitance of the IC (C

ICLoad

+ C

). The resulting frequency (f ) with an effective load capacitance of C

= C

+ C

is

LoadBoard

L

Leff

ICLoad

LoadBoard

1 + 0.5 * [ C / (C + C ) ]

1

0

L

f = f * –––––––––––––––––––––––

L

P

1 + 0.5 * [ C / (C + C ) ]

1

0

Leff

3)

Remarks on DCO Codes:

The DCO hardware register has 8 bits; the FP control register uses a range of –2048...2047.

Micronas

53

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

4.3. Characteristics

at T = 0 to 65 °C, V

= 4.75 to 5.25 V, V

= 3.15 to 3.5 V, f = 20.25 MHz for min./max. values

SUPP

A

SUPD/A

at T = 60 °C, V

= 5 V, V

= 3.3 V, f = 20.25 MHz for typical values

SUPP

C

SUPD/A

4.3.1. Current Consumption

Symbol

Parameter

Pin Name

AVDD

Min.

25

Typ.

40

Max.

53

Unit

mA

I

Current Consumption

VSUPA

VSUPD

VSUPP

VDD

80

100

135

PVDD

application dependent

–

45@3.3V

75@5V

P

Total Power Dissipation,

normal operation condition

AVDD, VDD, PVDD

0.95

0.1

W

TOT

Total Power Dissipation, low power mode

TOT

4.3.2. Characteristics, Reset

Symbol

Parameter

Min.

50

Typ.

Max.

Unit

Test Conditions

xtal osc. is working

t

RES Low Pulse to initiate an internal reset

Internal Reset Hold Time

ns

RES MIN

RES INT

3.2

µs

Default Wake-up Selection (see timing diagram in section 5.1. on page 60)

t

RES Low Pulse due to the time needed to

discharge pin FIELD by the internal pull-

down transistor for default selection

(see schematic of fig. 3–7)

1

ms

xtal osc. is working

RES MIN

C

(FIELD) < 50 pF

LOAD

I

< 10 mA

leak

t

I

Setup Time of pin FIELD and OE

to posedge of RES

20

42

ns

mA

kW

s-WU

h-WU

PD

Hold Time of pin FIELD and OE

to posedge of RES

Pull-down current during RES = 0 at pin

FIELD

75

10

68

V

FIELD

= 5V

R

Recommended Pull-up resistor to enforce a

logical 1 to pin FIELD

PU

4.3.3. XTAL Input Characteristics

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Conditions

V

I

Clock Input Voltage, XTAL1

1.3

V

PP

capacitive coupling of

XTAL1,

XTAL 2 remains open

t

Oscillator Startup Time at VDD

Slew-rate of 1 V / 1 µs

(see section 5.1. on page 60)

0.4

1.0

ms

%

Startup1

Reset Hold Time after

the Oscillator is active

(see section 5.1. on page 60)

5.0

Startup2

k

Duty Cycle

50

XTAL

54

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

4.3.4. Characteristics, Analog Front-End and ADCs

Symbol

Parameter

Pin Name

Min.

Typ.

Max.

Unit

Test Conditions

V

VRT

Reference Voltage Top

VRT

2.5

2.61

2.72

V

10 mF//10 nF, 1 GW Probe

Luma – Path

R

C

Input Resistance

VIN1,

VIN2,

VIN3

1

MW

Code clamp – DAC = 0

VIN

Input Capacitance

5

pF

V

Full Scale Input Voltage

AGC step width

1.86

0.5

1.93

0.6

2.0

V

PP

V

PP

min. AGC Gain

0.7

max. AGC Gain

AGC

DNL

0.145

0.163

0.181

±0.5

dB

LSB

V

6-bit resolution = 63 Steps

f

sig

= 1 MHz,

– 2 dBr of max. AGC Gain

AGC Differential Non-Linearity

Input Clamping Level, CVBS

AGC

VINCL

V

1.0

1

Binary Level = 68 LSB

min. AGC Gain

Q

Clamping DAC Resolution

–16

0.7

15

steps

mA

6 Bit – I–DAC, bipolar

CL

V

VIN

= 1.5 V

I

Input Clamping Current per step

1.3

±0.5

CL–LSB

DNL

Clamping DAC Differential

Non-Linearity

LSB

ICL

Chroma – Path

R

Input Resistance

SVHS Chroma

CIN,

VIN1

1.4

2.0

5

2.6

kW

CIN

C

Input Capacitance

CIN,

pF

VIN

VIN1

V

Full Scale Input Voltage, Chroma

CIN,

VIN1

1.08

–

1.14

1.5

1.2

–

V

CIN

PP

Input Bias Level,

SVHS Chroma

CINDC

Binary Code for Open

Chroma Input

128

Dynamic Characteristics for all Video-Paths (Luma + Chroma)

BW

Bandwidth

VIN1,

VIN2,

VIN3,

CIN

10

42

14

MHz

dB

–2 dBr input signal level

1 MHz, –2 dBr signal level

XTALK

THD

Crosstalk, any two video inputs

Total Harmonic Distortion

–56

–48

–45

dB

1 MHz, 5 harmonics,

–2 dBr signal level

SINAD

Signal to Noise and

Distortion Ratio

46

dB

1 MHz, all outputs,

–2 dBr signal level

INL

DNL

DG

DP

Integral Non-Linearity,

Differential Non-Linearity

Differential Gain

±1.3

±0.5

±2.4

±0.85

±3

LSB

%

Code Density,

DC-ramp

–12 dBr, 4.4 MHz signal on

DC-Ramp

Differential Phase

1.5

deg

Micronas

55

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

4.3.5. Characteristics, Control Bus Interface

(Timing diagram see Fig. 5–3 on page 61)

Symbol

Parameter

Name

Min.

–

Typ.

Max.

Unit

Test Conditions

V

Output Low Voltage

SDA,

SCL

–

0.4

0.6

V

I = 3 mA

l

I = 6 mA

l

IMOL

IMOL1

IMOL2

F

2

t

f

I C-Data Output Hold Time after

SDA

15

100

–

ns

Falling Edge of Clock SCL

2

I C-Data Output Setup Time be-

f

= 1 MHz, VDD = 5 V

SCL

fore Rising Edge of Clock SCL

Signal Fall Time

SDA,

SCL

–

300

C = 400 pF,

L

R

= 4,7 k

PU

1)

Clock Frequency

SCL

0

100

1000

kHz

low power mode

normal operating condition

SCL

1)

The maximum clock frequency of the I2C interface is limited to 100 kHz while the IC is working in the low power mode.

4.3.6. Characteristics, JTAG Interface (Test Access Port TAP)

(Timing diagram see Fig. 5–5 on page 63)

Symbol

Parameter

Min.

100

50

Typ.

Max.

Unit

ns

V

Test Conditions

F

JTAG Cycle Time

TCK High Time

TCK Low Time

CYCL-TAP

H-TAP

50

L-TAP

V

Minimum supply voltage to initiate an

internal reset of the JTAG-TAP generated

by a voltage supply supervision circuit

3.5

VDD pin

RES-TAP

Test Access Port (TAP), see timing diagram (Fig. 5–5 on page 63)

t

TMS, TDI Setup Time

TMS, TDI Hold Time

12

ns

S-TAP

H-TAP

D-TAP

TCK to TDO Propagation Delay

for Valid Data

50

t

TDO Turn-on Delay

TDO Turn-off Delay

45

ns

ON-TAP

OFF-TAP

Boundary-Scan Test, Characteristics of all IO pins which are connected to the boundary scan register chain

t

Input Signals Setup Time at CAPTURE-DR

Input Signals Hold Time at CAPTURE-DR

10

ns

S-PINS

H-PINS

D-PINS

TCK to Output Signals,

Delay for Valid Data

50

t

Turn-on Delay

Turn-off Delay

20

ns

ON-PINS

OFF-PINS

56

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

4.3.7. Characteristics, Digital Inputs/Outputs

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Conditions

Digital Input Pins TMS, TDI, TCK, RES, OE, SCL, SDA

C

Input Capacitance

5

8

pF

IN

I

Input Leakage Current

Input Pins TCK, RES, OE, SCL, SDA

–1

+1

mA

V = V

V ≤V

I

SS

DD

I

Input Leakage Current

Input Pins with Pull-ups: TDI and TMS

–25

–55

+1

mA

V = V

I

SS

DD

V ≤V

I

Pull-down Current at Pin FIELD

during RES = 0 for Default Selection

see section 4.3.2.

PD

Digital Output pins A[7:0], B[7:0], HREF, VREF, FIELD, VACT, LLC, PIXCLK, TDO

C

High-Impedance Output Capacitance

5

8

pF

V

O

V

Output Voltage LOW

(all digital output pins except SDA, SCL)

0.6

OL

Output Voltage LOW

(only SDA, SCL)

0.4

0.6

V

I = 3 mA

l

I = 6 mA

l

OL

Output Voltage HIGH

2.4

–

PVDD

V

OH

(all digital output pins except SDA, SCL)

I

O

Output Leakage Current

while IC remains in low

power mode

–1

+1

V = V

V ≤V

I

mA

I

SS

DD

A special VDD, VSS supply is used only to support the digital output pins. This means, inherently, that in case of tri-state conditions,

external sources should not drive these signals above the voltage PVDD which supplies the output pins.

4.3.8. Clock Signals PIXCLK, LLC, and LLC2

The following timing specifications refer to the timing diagrams of section 5.7.1. on page 64.

Symbol

Parameter

Min.

Typ.

37

Max.

Unit

ns

%

Test Conditions

t

LLC Cycle Time

LLC

F

LLC

LLC Duty Cycle F / (F

F

H

)

50

H

L +

t

LLC2 Cycle Time

74

ns

%

LLC2

F

LLC2 Duty Cycle F / (F

F

H

)

50

LLC2

H

L +

t

PIXCLK Cycle Time

74

ns

%

PIXCLK

F

PIXCLK Duty Cycle F / (F

F

H

)

50

PIXCLK

HCLK1

DCLK1

HCLK2

DCLK2

H

L +

t

Output Signal Hold Time for LLC2

Propagation Delay for LLC2

0

ns

10

18

Output Signal Hold Time for PIXCLK

Propagation Delay for PIXCLK

10

Micronas

57

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

4.3.9. Digital Video Interface

Symbol

Parameter

Min.

Typ.

Max.

Unit

Test Conditions

Data and Control Pins (LLC to A[7:0], B[7:0], HREF, VREF, FIELD, VACT:

The following timing specifications refer to the timing diagrams of section 5.7. on page 64.

2

t

Output Hold Time

Propagation Delay

20

ns

I C Reg. h’AA –bit[6]=1

OH

PD

35

23

New LLC output timing (available starting version D4)

2

t

Output Hold Time

Propagation Delay

8

ns

I C Reg. h’AA –bit[6]=0

OH

PD

Output Enable by OE (For more information, see section 5.4. on page 62)

t

Output Enable OE of A[7:0], B[7:0]

Output Disable OE of A[7:0], B[7:0]

Output Enable OE of A[7:0], B[7:0]

Output Disable OE of A[7:0], B[7:0]

15

5

ns

ON

OFF

ON1

OFF1

5

OE input timing

t

input data set-up time

input data hold time

11

3

ns

SU

HD

t

4.3.10. Characteristics, TTL Output Driver

Output Pins A[7:0], B[7:0], PIXCLK, LLC, VACT, HREF, VREF, FIELD, TDO/LLC2

Symbol

Parameter

Min.

2

Typ.

5

Max.

10

Unit

ns

Test Conditions

t

I

Rise Time

C = 30 pF, strength = 4

l

RA

FA

Fall Time

2

5

10

ns

C = 30 pF, strength = 4

l

(0)

Output High Current (strength = 0)

Output Low Current (strength = 0)

Output High Current (strength = 7)

Output Low Current (strength = 7)

–1.37

1.75

–11

14

–2.25

3.5

–18

28

–2.87

4.5

mA

V

OH

V

OH

V

OH

V

OH

= 0.6 V

= 2.4 V

= 0.6 V

= 2.4 V

OH

(0)

OL

(7)

–25

36

OH

(7)

OL

58

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

strength = 7

strength w 6

strength w 5

strength w 4

strength w 3

strength w 2

strength w 1

strength w 0

4.3.10.1. TTL Output Driver Description

The driving capability/strength is controlled by the state

2

of the two I C registers F8

and F9

.

hex

A special PVDD, PVSS supply is used only to support

the digital output pins. This means, inherently, that in

case of tri-state conditions, external sources should not

drive these signals above the voltage PVDD which sup-

plies the output pins.

All timing specifications are based on the following as-

sumptions:

– the load capacitance of the fast pins (output driver ty-

pe A) is C = 30 pF,

A

– the load capacitance of the remaining pins (output

driver type B) is C = 50 pF,

B

– no static currents are assumed,

– the driving capability of the pads is STR = 4, which

means that 5 of 8 output drivers are enabled.

The typical case specification relates to:

– the ambient temperature is T = 25 °C, which relates

A

to a junction temperature of T = 70 °C;

J

– the power supply of the pad circuits is PVDD = 3.3 V,

and the power supply of the digital parts is VDD =

5.0 V.

Fig. 4–1: Block diagram of the output stages

The best case specification relates to:

– a junction temperature of T = 0 °C,

J

Note: The drivers of the output pads are implemented

as a parallel connection of 8 tri-state buffers of the

same size. The buffers are enabled depending on the

desired driver strength. This opportunity offers the ad-

vantage of adapting the driver strength to on-chip and

off-chip constraints, e.g. to minimize the noise result-

ing from steep signal transitions.

– the power supply of the pad circuits is PVDD = 3.6 V,

and the power supply of the digital parts is VDD =

5.25 V.

The worst case specification relates to:

– a junction temperature of T = 125 °C,

J

– the power supply of the pad circuits is PVDD = 3.0 V,

and the power supply of the digital parts is VDD =

4.75 V.

Rise times are specified as a transition between 0.6 V to

2.4 V. Fall times are defined as a transition between

2.4 V to 0.6 V.

Micronas

59

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

5. Timing Diagrams

5.1. Power-Up Sequence

Theresetshouldnotreachhighlevelbeforetheoscillatorhasstarted. Thisrequiresaresetdelayof>1ms(seeFig.5–1).

95%

Supplies

Crystal

Oscillator

V

IOH

RES

t

STARTUP2

STARTUP1

Fig. 5–1: Power-up sequence

5.2. Default Wake-up Selection

t

RES MIN

V

IOH

V

IOL

V

IOH

V

IOL

The state of FIELD and OE pins are sampled at the high

(inactive) going edge of RES in order to select between

two power-on parameters. OE determines the I C ad-

RES

2

dress.

TheFIELDpinisinternallypulleddown. Anexternalpull-

up resistor defines a different power on configuration.

FIELD defines the global wake-up mode of the VPX.

With FIELD pulled down, the VPX goes into low power

mode.

FIELD

OE

t

s-WU h-WU

Fig. 5–2: Default wake-up selection

60

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

5.3. Control Bus Timing Diagram

(Data: MSB first)

F

IM

T

I2C4

T

I2C3

SCL

T

I2C1

T

I2C5

T

I2C6

T

I2C2

SDA as input

T

IMOL2

T

IMOL1

SDA as output

2

Fig. 5–3: I C bus timing diagram

Micronas

61

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

5.4. Output Enable by Pin OE

OE

t

ON

OFF

Signals

A[7:0], B[7:0]

Synchronizing the OE signal with clock LLC:

2

controlled by I C register ’OENA’ h’f2 bit[5] oeqdel = 1

OE

t

SU

t

OFF1

ON1

latoeq = 0

Signals

A[7:0], B[7:0]

t

OFF1

ON1

latoeq = 1

Signals

A[7:0], B[7:0]

Fig. 5–4: Drive Control by OE input

62

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

5.5. Timing of the Test Access Port TAP

F

CYCL

F

L–TAP

F

H-TAP

TCK

t

H-TAP

S-TAP

TDI, TMS

t

D-TAP

t

OFF-TAP

t

ON-TAP

TDO

Fig. 5–5: Timing of Test Access Port TAP

5.6. Timing of all Pins connected to the Boundary-Scan-Register-Chain

TCK

t

H-PINS

S-PINS

Inputs

t

D-PINS

t

OFF-PINS

t

ON-PINS

Outputs

Fig. 5–6: Timing with respect to input and output signals

Micronas

63

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

5.7. Timing Diagram of the Digital Video Interface

t

LLC

2.4 V

1.5 V

0.6 V

Clock Output LLC

t

PD

t

OH

2.4 V

1.5 V

0.6 V

A[7:0], B[7:0]

HREF, VREF, FIELD, VACT

Fig. 5–7: Video output interface (detailed timing)

5.7.1. Characteristics, Clock Signals

t

LLC

2.4 V

1.5 V

0.6 V

LLC

t

RA

t

FA

t

DCLK1

t

HCLK1

2.4 V

1.5 V

0.6 V

LLC2

t

DCLK2

t

HCLK2

t

HCLK2

2.4 V

1.5 V

0.6 V

PIXCLK

Fig. 5–8: Clocks: LLC, LLC2, PIXCLK (detailed timing)

64

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

6. Control and Status Registers

The control register modes are

– w

– r

write-only register

read-only register

The following tables give definitions for the VPX control

and status registers. The number of bits indicated for

each register in the table is the number of bits imple-

mented in the hardware, i.e. a 9-bit register must always

be accessed using two data bytes, but the 7 MSB will be

“0” on write operations and don’t care on read opera-

tions. Write registers that can be read back are indicated

in the mode column.

– w/r write/read register

– d

– v

register is double latched

register is latched with vsync

Default values are initialized at reset. The mnemonics

used in the Micronas VPX demo software are given in

the last column.

6.1. Overview

2

I C-Registers

Address

Hex

Number

of Bits

Mode

Function

Group

Name

h’00

8

r

Manufacture ID

Chip Ident.

JEDEC

h’01

h’02

8

16-bit part number

PARTNUM

h’03

h’35

h’36

h’37

h’38

h’AA

h’B3

h’B4

h’B5

h’B6

h’B7

8

r

JEDEC2

Chip Ident.

FP Interface

Output

JEDEC2

FPSTA

FPRD

8

r

FP status

16

8

w

w/r

w

r

FP read

FP write

FPWR

FPDAT

llc

FP data

Low power mode, LLC mode

soft error counter

sync status

8

Byte Slicer

Sync Slicer

Bit Slicer

softerrcnt

sync_stat

sync_cnt

coeff_rd

level_rd

mask

8

r

8

r

hsync counter

read filter coefficient

read data slicer level

8

r

8

r

Bit Slicer

h’B8

h’B9

h’BA

8

w

clock run-in and framing code don’t care mask high

clock run-in and framing code don’t care mask mid

clock run-in and framing code don’t care mask low

Byte Slicer

h’BB

h’BC

h’BD

8

w

clock run-in and framing code reference high

clock run-in and framing code reference mid

clock run-in and framing code reference low

Byte Slicer

reference

h’C0

8

w

soft slicer level

Bit Slicer

soft_slicer

ttx_freq

h’C1

h’C2

8

w

ttx bitslicer frequency LSB

ttx bitslicer frequency MSB

h’C5

h’C6

h’C7

h’C8

h’C9

h’CE

h’CF

h’F2

h’F8

h’F9

8

w

filter coefficient

Bit Slicer

Sync Slicer

Byte Slicer

Output

coeff

data slicer level

data_slicer

accu

accumulator mode

sync slicer level

sync_slicer

standard

tolerance

byte_cnt

oena

standard

bit error tolerance

byte count

Output Enable

Pad Driver Strength – TTL Output Pads Type A

Pad Driver Strength – TTL Output Pads Type B

Output

driver_a

driver_b

Output

Micronas

65

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

FP-RAM

Address

Hex

Number

of Bits

Mode

Function

Group

Name

h’12

h’13

h’15

h’20

h’21

h’22

h’23

h’30

h’31

h’32

12

r/w

r

general purpose control

standard recognition status

vertical field counter

Standard select

Status

gp_ctrl

asr

Status

r

Status

vcnt

sdt

w

r

Stand. Sel.

Color Proc.

Status

Input select

insel

sfif

start point of active video

luma/chroma delay adjust

ldly

ACC reference level to adjust C , C levels on picture bus

accref

bampl

accb

r

b

measured burst amplitude

w

ACC multiplier value for SECAM Db chroma comp. to adjust

C on pict. bus

b

Color Proc.

h’33

12

w

ACC multiplier value for SECAM Dr chroma comp. to adjust

C on pict. bus

r

Color Proc.

accr

h’39

12

w

r

amplitude killer level

Color Proc.

Status

kilvl

h’3A

amplitude killer hysteresis

measured sync amplitude value

number of lines per field, P/S: 312, N: 262

NTSC tint angle, $512 = $π/4

software version number

crystal oscillator line-locked mode,

crystal oscillator center frequency adjust

crystal oscillator center frequency adjustment value

Delay of VACT relative to HREF during window 1

Delay of VACT relative to HREF during window 2

Vertical Begin

kilhy

h’74

sampl

h’CB

h’DC

h’F0

r

Status

nlpf

w

r

Color Proc.

Status

tint

version

xlck

h’F7

w/r

w

r

DVCO

h’F8

DVCO

dvco

h’F9

DVCO

adjust

h’10F

h’11F

h’120

h’121

h’122

h’123

h’124

h’125

h’126

h’127

h’128

h’12A

h’12B

h’12C

h’12D

h’12E

h’12F

h’130

h’131

r

ReadTab1

vact_dly1

vact_dly2

vbegin1

vlinesin1

vlinesout1

hbeg1

r

ReadTab2

w

WinLoadTab1

WinLoadTab2

Vertical Lines In / Temporal Decimation / Field Select

Vertical Lines Out

Horizontal Begin

Horizontal Length

hlen1

Number of Pixels

npix1

Selection for peaking / coring

Brightness

peaking1

brightness1

contrast1

vbegin2

vlinesin2

vlinesout2

hbeg2

Contrast / Noise shaping / Clamping

Vertical Begin

Vertical Lines In

Vertical Lines Out

Horizontal Begin

Horizontal Length

hlen2

Number of Pixels

npix2

Selection for peaking / coring

Brightness

peaking2

brightness2

66

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

FP-RAM

Address

Hex

Number

of Bits

Mode

Function

Group

Name

h’132

h’134

h’135

h’136

h’137

h’138

h’139

h’140

h’141

h’150

h’151

h’152

h’153

h’154

h’157

12

w

w r

r

Contrast

WinLoadTab2

VBI-window

contrast2

start_even

end_even

start_odd

end_odd

vbicontrol

slsize

Start line even field

End line even field

Start line odd field

End line odd field

Control VBI-Window

Slicer Data Size

Register for control and latching

ControlWord

InfoWord

format_sel

pval_start

pval_stop

refsig

Internal status register, do not overwrite

Format Selection / Shuffler / PIXCLK-mode

Start position of the programmable ‘video active’

End position of the programmable ‘video active’

Length and polarity of HREF, VREF, FIELD

Output Multiplexer / Multi-purpose output

Number of frames to output within 3000 frames

w

Formatter

HVREF

Output Mux.

Temp. Decim.

outmux

tdecframes

Micronas

67

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2

6.1.1. Description of I C Control and Status Registers

2

Table 6–1: I C-Registers VPX Front-End

2

I C-Registers VPX Front-End

Address

Hex

Number

of bits

Mode

Function

Default

Name

FP Interface

h’35

8

r

FP status

bit [0]

FPSTA

write request

bit [1]

bit [2]

read request

busy

h’36

h’37

h’38

16

w

FP read

bit [8:0]

bit [11:9]

FPRD

FPWR

FPDAT

9-bit FP read address

reserved, set to zero

w

FP write

bit [8:0]

bit [11:9]

9-bit FP write address

reserved, set to zero

w/r

FP data

bit [11:0]

FP data register, reading/writing to this

register will autoincrement the FP read/

write address. Only 16 bit of data are

2

transferred per I C telegram.

2

Table 6–2: I C-Registers VPX Back-End

2

I C-Registers VPX Back-End

Address

Hex

Number

of bits

Mode

Function

Default

Name

Chip Identification

h’00

8

r

Manufacture ID in accordance with

JEDEC Solid State Products Engineering Council, Washington DC

JEDEC

Micronas Code EC

hex

16 bit part number (01: LSBs, 02: MSBs)

PARTNUM

partlow

parthigh

h’01

h’02

8

r

VPX 3225D 7230

;

VPX 3224D 7231

hex

h’03

8

r

JEDEC2

ifield

bit [0] :

IFIELD

reserved (must be treated don’t care)

bit [7:1] :

68

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

2

I C-Registers VPX Back-End

Address

Hex

Number

of bits

Mode

Function

Default

Name

Output

h’F8

8

w

Pad Driver Strength – TTL Output Pads Typ A

DRIVER_A

stra1

bit [2:0] :

bit [5:3] :

bit [7:6] :

Driver strength of Port A[7:0]

Driver strength of PIXCLK, LLC, and VACT

stra2

additional PIXCLK driver strength

strength = bit [5:3] | {bit [7:6], 0}

stra3

h’F9

h’F2

8

w

Pad Driver Strength – TTL Output Pads Typ B

DRIVER_B

strb1

bit [2:0] :

Driver strength of Port B[7:0]

bit [5:3] :

Driver strength of HREF, VREF, FIELD, and LLC2

reserved (must be set to zero)

strb2

bit [7:6] :

w

Output Enable

OENA

aen

direct

bit [0] :

bit [1] :

bit [2] :

bit [3] :

bit[4]

1

0

Enable Video Port A

Disable / High Impedance Mode

direct

1

0

Enable Video Port B

Disable / High Impedance Mode

ben

1

0

Enable Pixclk Output

Disable / High Impedance Mode

clken

zen

1

0

Enable HREF, VREF, FIELD, VACT, LLC, LLC2

Disable / High Impedance Mode

1

0

Enable LLC2 to TDO pin

(if JTAG interface is in Test-Logic-Reset State)

Disable LLC2

llc2en

direct

bit [5] :

bit [6] :

bit [7] :

1

0

no delay of OEQ input signal

1 LLC cycle delay of OEQ input signal (if bit [6] = 1)

oeqdel

latoeq

1

0

latch OEQ input signal with rising edge of LLC

don’t latch OEQ input signal

direct

w

1

disable OEQ pin function

oeq_dis

LLC

h’AA

8

Low power mode, LLC mode

bit [1:0] :

Low power mode

00 active mode, outputs enabled

01 outputs tri-stated; clock divided by 2, I C full speed

lowpow

2

10 outputs tri-stated; clock divided by 4, I C full speed

2

11

outputs tri-stated; clock divided by 8, I C < 100 kbit/s

2

bit [2] :

bit [3] :

I C reset

iresen

llc2

1

0

connect LLC2 to TDO pin

connect bit[4] to TDO pin

bit [4] :

bit [5] :

bit [6] :

if bit[3] then bit[4] defines LLC2 polarity

else bit[4] is connected to TDO pin

llc2_pol

slowpow

oldllc

switch-off slicer

(if slowpow = 1 then all slicer registers are reset).

1

0

use old llc timing with long hold time

use new llc timing with shorter hold time

(version D4 only)

bit [7] : reserved (must be set to zero)

Micronas

69

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

2

Table 6–3: I C-Registers VPX Slicer

2

I C-Registers VPX Slicer

Address

Hex

Number

of bits

Mode

Function

Default

Name

Sync Slicer

h’C8

h’B4

8

w

sync slicer

sync_slicer

sync_level

bit [6:0] : binary sync slicer level is compared with binary data

64

0

(0 ≤ data ≤ 127)

bit [7] :

0

1

vertical sync window enable

vertical sync window disable

vsw

r

sync status

bit [5:0] : reserved (must be read don’t care)

bit [6] :

sync_stat

vwin

0

1

0

1

vert. window reset at line 624/524 (PAL/NTSC)

vert. retrace set at line 628/528 (PAL/NTSC)

field 2

bit [7] :

reset at line 313/263 (PAL/NTSC)

set at line 624/524 (PAL/NTSC)

field

field 1

h’B5

h’C0

8

hsync counter

sync_cnt

bit [7:0] : number of detected horizontal sync pulses per frame / 4

sync is detected within horizontal window of HPLL

counter is latched with vertical sync

the register can be read at any time

Bit Slicer

w

soft slicer

soft_slicer

soft_level

bit [6:0] : binary soft slicer level is compared with ABS[data]

16

(–128 ≤ data ≤ +127)

reserved (must be set to zero)

bit [7] :

h’C1

h’C2

8

w

ttx bitslicer frequency LSB

ttx bitslicer frequency MSB

bit [10:0] : Freq = 2 * bitfreq / 20.25MHz

ttx_freql

ttx_freqh

ttx_freq

11

702

= 702 for WST PAL

= 579 for WST NTSC or NABTS

= 506 for VPS or WSS

= 102 for CAPTION

= 627 for Antiope

= 183 for Time Code

phase inc = Freq

phase inc = Freq*(1+1/8) before framing code

phase inc = Freq*(1+1/16) after framing code

bit [11] :

0

1

0

ttx_phinc

bit [15:12] :reserved (must be set to zero)

h’C5

h’C6

8

w

filter coefficient

bit [5:0] : high pass filter coefficient in 2’s complement

100000 = not allowed

filter

coeff

7

100001 = –31

000000 =

011111 = +31

0

bit [7:6] : reserved (must be set to zero)

data slicer

data_slicer

data_level

bit [7:0] : binary data slicer level is compared with ABS[data]

64

(–128 ≤ data ≤ +127)

70

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

2

I C-Registers VPX Slicer

Address

Hex

Number

of bits

Mode

Function

Default

Name

h’C7

8

w

accumulator mode

accu

reset

bit [0] :

bit [1] :

bit [2] :

0

1

0

1

0

1

no action

reset DC and AC and FLT accu

DC accu enable

DC accu disable

AC and FLT accu enable

AC and FLT accu disable

0

1

(one shot)

dcen

acen

(only for VPS and CAPTION and WSS line)

soft error correction enable

soft error correction disable

ac adaption disable

ac adaption enable

flt adaption disable

bit [3] :

bit [4] :

bit [5] :

0

1

0

1

0

1

0

1

soften

acaden

fltaden

flt adaption enable

bit [7:6] : reserved (must be set to zero)

h’B6

h’B7

8

r

read filter coefficient

coeff_rd

level_rd

read data slicer level

Byte Slicer

h’B3

h’C9

8

r

soft error counter

bit [7:0] : counts number of soft error corrected bytes

counter stops at 255

soft_cnt

reset after read

w

standard

ttx

bit [0] :

bit [1] :

bit [2] :

bit [3] :

bit [4] :

bit [5] :

bit [6] :

bit [7] :

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

TTX disable

TTX enable

PAL mode

NTSC mode

full field disable

full field enable

VPS line 16 disable

VPS line 16 enable

WSS line 23 disable

WSS line 23 enable

CAPTION line 21 field 1 disable

CAPTION line 21 field 1 enable

CAPTION line 21 field 2 disable

CAPTION line 21 field 2 enable

horizontal quit signal enable

horizontal quit signal disable

1

0

1

0

ntsc

full

vps

wss

caption1

caption2

disquit

h’BD

h’BC

h’BB

8

w

clock run-in and framing code reference low

clock run-in and framing code reference mid

clock run-in and framing code reference high

bit [23:0] : clock run-in and framing code reference

(LSB corresponds to first transmitted bit)

h’55

h’27

reference

h’BA

h’B9

h’B8

8

w

clock run-in and framing code don’t care mask low

clock run-in and framing code don’t care mask mid

clock run-in and framing code don’t care mask high

bit [23:0] : clock run-in and framing code don’t care mask

(LSB corresponds to first transmitted bit)

h’00

mask

h’CE

h’CF

8

w

bit error tolerance

tolerance

bit [1:0] : maximum number of bit errors in low mask

bit [3:2] : maximum number of bit errors in mid mask

bit [5:4] : maximum number of bit errors in high mask

bit [7:6] : reserved (must be set to zero)

1

output mode

out_mode

byte_cnt

fill64

bit [5:0] : number of data bytes per text line including framing code

43

1

bit [6] :

0

1

0

1

64 byte mode disable

64 byte mode enable

data output only for text lines

data output for every video line

bit [7] :

0

dump

Micronas

71

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

6.1.2. Description of FP Control and Status Registers

Table 6–4: FP-RAM VPX Front-End

FP-RAM VPX Front-End

Standard Selection

Address

Hex

Number

of Bits

Mode

Function

Default

Name

h’20

12

w

Standard select:

bit [2:0] standard

0

sdt

0

1

2

3

4

5

6

7

PAL B,G,H,I

NTSC M

SECAM

NTSC44

PAL M

PAL N

PAL 60

NTSC COMB (60 Hz)

MOD standard modifier

PAL modified to simple PAL

(50 Hz)

(60 Hz)

(50 Hz)

(60 Hz)

(50 Hz)

(60 Hz)

4.433618

3.579545

4.286

4.433618

3.575611

3.582056

4.433618

3.579545

pal

ntsc

secam

ntsc44

palm

paln

pal60

ntscc

sdtmod

bit [3]

0/1

NTSC modified to compensated NTSC

SECAM modified to monochrome 625

NTSCC modified to monochrome 525

bit [5:4]

bit [6]

reserved; must be set to zero

0/1 S-VHS mode off/on

svhs

Option bits allow to suppress parts of the initialization:

sdtopt

bit [7]

bit [8]

bit [9]

bit [10]

no hpll setup

no vertical setup

no acc setup

reserved, set to zero

bit [11]

status bit, write 0. After the FP has switched to a new

standard, this bit is set to 1 to indicate operation

complete.

h’21

12

w

Input select: Writing to this register will also initialize the standard.

insel

vis

bit [1:0]

luma selector

00

01

10

11

VIN3

VIN2

VIN1

reserved

bit [2]

chroma selector

0/1

IF compensation

1

cis

ifc

VIN1/CIN

bit [4:3]

00

01

10

11

off

6 dB/Okt

12 dB/Okt

10 dB/MHz only for SECAM

bit [6:5]

chroma bandwidth selector

01

cbw

00

01

10

11

0/1

narrow

normal

broad

wide

bit [7]

bit [8]

adaptive/fixed SECAM notch filter

enable luma lowpass filter

fntch

lowp

bit [10:9]

hpll speed

hpllmd

00

01

10

11

no change

terrestrial

vcr

mixed

bit [11]

status bit, write 0; This bit is set to 1 to indicate

operation complete.

h’22

h’23

12

w

picture start position, This register sets the start point of active vid-

eo. This can be used e.g. for panning. The setting is updated when

’sdt’ register is updated

0

sfif

luma/chroma delay adjust, The setting is updated when ’sdt’ register

is updated

ldly

bit [5:0]

bit [11:6]

reserved, set to zero

luma delay in clocks, allowed range is +1 ... –7

72

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

FP-RAM VPX Front-End

Address

Hex

Number

of Bits

Mode

Function

Default

Name

Color Processing

h’30

h’32

h’33

12

w

ACC reference level to adjust C , C levels on picture bus.

P/N: 2070

S: 0

accref

accb

accr

r

b

A value of 0 disables the ACC, chroma gain can be adjusted via

ACCb / ACCr register. The setting is updated when ’sdt’ register is

updated.

ACC multiplier value for SECAM Db chroma component to adjust

S: 1155

S: 1496

C level on picture bus. The setting is updated when ’sdt’ register is

b

updated.

b [10:0] eeemmmmmmmm

–e

m * 2

ACC multiplier value for SECAM Dr chroma component to adjust C

level on picture bus. The setting is updated when ’sdt’ register is

r

updated.

–e

b [10:0] eeemmmmmmmm

amplitude killer level (0: killer disabled)

amplitude killer hysteresis

m * 2

h’39

h’3A

h’DC

12

w

25

5

kilvl

kilhy

tint

NTSC tint angle, $512 = $π/4

0

DVCO

h’F8

h’F9

12

w

r

crystal oscillator center frequency adjust, –2048 ... 2047

–720

dvco

crystal oscillator center frequency adjustment value for line-locked

mode, true adjust value is DVCO – ADJUST.

adjust

For factory crystal alignment, using standard video signal:

set DVCO = 0, set lock mode, read crystal offset from ADJUST

register and use negative value for initial center frequency adjust-

ment via DVCO.

h’F7

h’12

12

w/r

crystal oscillator line-locked mode, lock command/status

0

xlck

write:

100

0

enable lock

disable lock

read:

4095/0

locked/unlocked

FP Status Register

general purpose control bits

gp_ctrl

vfrc

bit [2:0]

bit [3]

bit [8:4]

bit [9]

reserved, do not change

vertical standard force

reserved, do not change

disable flywheel interlace

reserved, do not change

0

1

dflw

bit [11:10]

to enable vertical free run mode set vfrc=1 and dflw=0

automatic standard recognition status

h’13

12

r

asr

bit [0]

bit [1]

bit [2]

bit [3]

bit [4]

bit [5]

bit [6]

bit [7]

bit [8]

bit [9]

bit [11:10]

1

vertical lock

horizontally locked

no signal detected

color amplitude killer active

disable amplitude killer

color ident killer active

disable ident killer

interlace detected

no vertical sync detection

spurious vertical sync detection

reserved

h’CB

h’15

h’74

h’31

h’F0

12

r

number of lines per field, P/S: 312, N: 262

vertical field counter, incremented per field

measured sync amplitude value, nominal: 768

measured burst amplitude

nlpf

w/r

vcnt

r

sampl

bampl

software version number

bit [7:0]

bit [11:8]

internal software revision number

software release

x

Micronas

73

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

FP-RAM VPX Front-End

Address

Hex

Number

of Bits

Mode

Function

Default

Name

Macrovision Detection (version D4 only)

h’170

12

r

Status of macrovision detection

mcv_status

bit [0]:

bit [1]:

AGC pulse detected

pseudo sync detected

h’171

h’172

12

w

first line of macrovision detection window

last line of macrovision detection window

6

mcv_start

mcv_stop

15

74

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

Table 6–5: FP-RAM VPX Back-End

FP-RAM VPX Back-End

Address

Hex

Number

of Bits

Mode

Function

Default

Name

Read Table for Window #1

h’10f

12

r

Position of VACT

bit [11:1]: Delay of VACT relative to the trailing edge of HREF

vact_delay1

Load Table for Window #1 (WinLoadTab1)

h’120

w

Vertical Begin

12

bit [8:0]: Vertical Begin (first active video line within a field)

min. line number for 625/50 standards: 7

vbeg1

min. line number for 525/60 standards: 10

max. line number: determined by current TV line standard

bit [11:9]: reserved (must be set to zero)

Vertical Lines In

h’121

12

w

0

bit [8:0]: Number of input lines

vlinei1

tdec1

determines the range between the first and the last active

video line within a field; vbeg + vlinei should not exceed the

max. number of lines determined by the current line

standard (exceeding values will be corrected automatically)

bit [9]:

enable temporal decimation (0: off, 1: on)

with temporal decimation enabled, only the number of frames

selected in register h’157 (tdecframes) will be output within

an interval of 3000 frames

bit [11:10]: field disable flags

11 Window disabled

10 Window enabled in ODD fields only

01 Window enabled in EVEN fields only

00 Window enabled in both fields

h’122

12

w

Vertical Lines Out

0

bit [8:0]: Number of output lines

vlineout cannot be greater than vlinein (no interpolation);

vlineo1

for vlineout < vlinein vertical compression via line dropping

is applied

bit [11:9]: reserved (must be set to zero)

h’123

h’124

h’125

12

w

Horizontal Begin

0

bit [10:0]: Horizontal start of window after scaling (relative to npix)

hbeg > 0 enables cropping on the left side of the window

hbeg1

hlen1

npix1

bit [11]:

reserved (must be set to zero)

Horizontal Length

704

bit [10:0]: Horizontal length of window after scaling (relative to npix)

hbeg + hlen cannot exceed npix

bit [11]:

reserved (must be set to zero)

Number of Pixels

bit [10:0]: Number of active pixels for the full active line (after scaling)

npix must be an even value within the range 32...864

bit [11]:

reserved (must be set to zero)

Micronas

75

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

FP-RAM VPX Back-End

Address

Hex

Number

of Bits

Mode

Function

Default

Name

h’126

12

w

Selection for peaking/coring

bit [1:0]: coring

0

peaking1

subtracts LSBs of the higher frequency part of the video

signal

00: subtract 0 LSBs

01: subtract 1/2 LSB

10: subtract 1 LSB

11: subtract 2 LSBs

bit [4:2]: peaking

an implemented peaking filter supports sharpness control

with up to eight steps:

000: no peaking

001: low peaking

111: high peaking

bit [5]:

bit [6]:

bit [7]:

bit [8]:

Bypass Lowpass

Bypass Skewfilter

Bypass Skewfilter VACT

Swapping of Chroma values

0

1

Cb-Pixels first

Cr-Pixels first

bit [11:9]: reserved (must be set to zero)

Brightness

h’127

12

w

0

bit [7:0]: Brightness Level

offset value added to the video samples

brightness can be selected in 256 steps within the range

–127...128 (binary offset format):

0: –127

brightness1

255: 128

bit [11:8]: reserved (must be set to zero)

Contrast

h’128

12

w

32

contrast1

contr1

bit [5:0]: Contrast Level

linear scale factor for luminance (default = 1.0)

[5] integer part

[4:0] fractional part

bit [7:6]: Noise Shaping

noise1

clamp1

Control for 10-bit to 8-bit conversion (default: rounding)

00: 9-bit to 8-bit via 1-bit rounding

01: 9-bit to 8-bit via truncation

10: 9-bit to 8-bit via 1-bit accumulation

11: 10-bit to 8-bit via 2-bit accumulation

bit [8]:

Contrast Brightness: Clamping Level

0

1

clamping level = 32,

clamping level = 16

(should normally be set to 1)

bit [9]:

Bypass Brightness Adder

bribyp1

bit [10]:

bit [11]:

Bypass Contrast Multiplier

conbyp1

reserved (must be set to zero)

76

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

FP-RAM VPX Back-End

Address

Hex

Number

of Bits

Mode

Function

Default

Name

Read Table for Window #2

h’11f

12

r

Position of VACT

bit [11:1]: Delay of VACT relative to the trailing edge of HREF

vact_delay2

Load Table for Window #2 (WinLoadTab2)

h’12A

w

Vertical Begin

17

bit [8:0]: Vertical Begin (first active video line within a field)

min. line number for 625/50 standards: 7

vbeg2

min. line number for 525/60 standards: 10

max. line number: determined by current TV line standard

bit [11:9]: reserved (must be set to zero)

Vertical Lines In

h’12B

12

w

500

bit [8:0]: Number of input lines

vlinei2

tdec2

determines the range between the first and the last active

video line within a field; vbeg + vlinei should not exceed the

max. number of lines determined by the current line

standard (exceeding values will be corrected automatically)

bit [9]:

enable temporal decimation (0: off, 1: on)

with temporal decimation enabled, only the number of

frames selected in register h’157 (tdecframes) will be output

within an interval of 3000 frames

bit [11:10]: field disable flags

11: Window disabled

10: Window enabled in ODD fields only

01: Window enabled in EVEN fields only

00: Window enabled in both fields

h’12C

12

w

Vertical Lines Out

240

bit [8:0]: Number of output lines

vlineout cannot be greater than vlinein (no interpolation);

vlineo2

for vlineout < vlinein vertical compression via line dropping

is applied

bit [11:9]: reserved (must be set to zero)

h’12D

h’12E

h’12F

12

w

Horizontal Begin

0

bit [10:0]: Horizontal start of window after scaling (relative to npix)

hbeg > 0 enables cropping on the left side of the window

hbeg2

hlen2

npix2

bit [11]:

reserved (must be set to zero)

Horizontal Length

640

bit [10:0]: Horizontal length of window after scaling (relative to npix)

hbeg + hlen can not exceed npix

bit [11]:

reserved (must be set to zero)

Number of Pixels

bit [10:0]: Number of active pixels for the full active line (after scaling)

npix must be an even value within the range 32...864

bit [11]:

reserved (must be set to zero)

Micronas

77

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

FP-RAM VPX Back-End

Address

Hex

Number

of Bits

Mode

Function

Default

Name

h’130

12

w

Selection for peaking/coring

bit [1:0]: coring

0

peaking2

subtracts LSBs of the higher frequency part of the video

signal

00: subtract 0 LSBs

01: subtract 1/2 LSB

10: subtract 1 LSB

11: subtract 2 LSBs

bit [4:2]: peaking

an implemented peaking filter supports sharpness control

with up to eight steps:

000: no peaking

001: low peaking

111: high peaking

bit [5]:

bit [6]:

bit [7]:

bit [8]:

Bypass Lowpass

Bypass Skewfilter

Bypass Skewfilter VACT

Swapping of Chroma values

0

1

Cb-Pixels first

Cr-Pixels first

bit [11:9]: reserved (must be set to zero)

Brightness

h’131

12

w

0

bit [7:0]: Brightness Level

offset value added to the video samples

brightness can be selected in 256 steps within the range

–127...128 (binary offset format):

0: –127

brightness2

255: 128

bit [11:8]: reserved (must be set to zero)

Contrast

h’132

12

w

32

contrast2

contr1

bit [5:0]: Contrast Level

linear scale factor for luminance (default = 1.0)

[5] integer part

[4:0] fractional part

bit [7:6]: Noise Shaping

noise1

clamp1

Control for 10-bit to 8-bit conversion (default: rounding)

00: 9-bit to 8-bit via 1-bit rounding

01: 9-bit to 8-bit via truncation

10: 9-bit to 8-bit via 1-bit accumulation

11: 10-bit to 8-bit via 2-bit accumulation

bit [8]:

Contrast Brightness: Clamping Level

0

1

clamping level = 32,

clamping level = 16

(should normally be set to 1)

bit [9]:

Bypass Brightness Adder

bribyp1

bit [10]:

bit [11]:

Bypass Contrast Multiplier

conbyp1

reserved (must be set to zero)

78

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

FP-RAM VPX Back-End

Address

Hex

Number

of Bits

Mode

Function

Default

Name

Load Table for VBI-Window

h’134

h’135

12

w

Start line even field

determines the first line of the VBI-window within even fields

(note that lines are counted relative to the whole frame!)

272

283

start_even

end_even

End line even field

determines the last line of the VBI-window within even fields

(note that lines are counted relative to the whole frame!)

h’136

h’137

h’138

12

w

Start line odd field

determines the first line of the VBI-window within odd fields

10

21

0

start_odd

end_odd

End line odd field

determines the last line of the VBI-window within odd fields

Control VBI-Window

vbicontrol

vbien

bit [0]:

bit [1]:

VBI-window enable

the selected VBI-window is activated only if this flag is set

0: disable

1: enable

VBI mode

vbimode

vbiident

two modes for the output of VBI-data are supported

0: raw data

1140 samples of the video input are given directly

to the output

1: sliced data

sliced teletext data (in a package of 64 bytes)

bit [2]:

vertical identification

the valid VBI-lines defined by the VBI-window can either be

marked as active or as blanked lines

0: active lines during VBI-window (VACT enabled)

1: blanked lines during VBI-window (VACT suppressed)

bit [11]:

update the settings for the VBI-window

(settings will only be updated if this latch flag is set!)

vbilatch

slsize

h’139

12

w

Slicer Data Size (0 corresponds to default value 64)

0

Micronas

79

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

FP-RAM VPX Back-End

Control Word

Address

Hex

Number

of Bits

Mode

Function

Default

Name

h’140

12

w r

w

Register for control and latching

Control

Word

bit [1:0]: Sync timing mode

00 Open mode

0

settm

horizontal and vertical sync are tracking the input

signal

10 Scan mode

horizontal and vertical sync are free running

w

bit [2]:

Mode for VACT reference signal

vactmode

0

1

length of VACT corresponds to the size of the current

window

programmable length of VACT (for the whole field!)

w

bit [4:3]: reserved (must be set to zero)

0

1

bit [5]:

bit [6]:

Latch Window #1

latwin1

latwin2

1

latch (reset automatically)

w

Latch Window #2

1

latch (reset automatically)

bit [9]:

reserved (must be set to zero)

0

1

bit [10]:

Latch value for temporal decimation

The number of frames for the temporal decimation is

updated only if this flag is set

lattdec

lattm

1

latch (reset automatically)

w

bit [11]:

Latch Timing Modes

Selection of the timing mode is updated only if this flag is set

1

latch (reset automatically)

Info Word

h’141

12

r

Internal status register, do not overwrite

This register can be used to query the current internal state due to the

settings in the control word.

InfoWord

actvact

bit [2]:

Mode for VACT reference signal

0

1

current window size

programmable size

bit [4:3]: reserved

bit [11:8]: reserved

80

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

FP-RAM VPX Back-End

Formatter

Address

Hex

Number

of Bits

Mode

Function

Default

Name

h’150

12

w

Format Selection

format_sel

format

bit [1:0]: Format Selector

0

00: YUV 4:2:2, ITU-R601

01: YUV 4:2:2, ITU-R656

10: YUV 4:2:2, BStream

bit [2]:

bit [3]:

Shuffler

0

shuf

0

1

Port A = Y, Port B = UV

Port A = UV, Port B = Y

Format of VBI-data (in ITU-R656 mode only!)

Two possibilities are supported to disable the protected

values 0 and 255:

range

0

1

limitation

7-bit resolution + odd parity LSB

Note that this selection is applied for lines within the VBI-

window only!

bit [4]:

bit [5]:

Transmission of VBI-data (in ITU-R656 mode only)

1

0

ancillary

halfclk

0

1

transmit as normal video data

transmit as ancillary data (with ANC-header)

PIXCLK selection

Setting this bit activates the half-clock mode, in which

PIXCLK is divided by 2 in order to spread the video data

stream

0

1

full PIXCLK (normal operation)

PIXCLK divided by 2

bit [6]:

Disable splitting of text data bytes

0

splitdis

During normal operation, sliced teletext bytes are splitted

into 2 nibbles and multiplexed to the luminance and

chrominance part. Setting this bit will disable this splitting.

Sliced teletext data will be output directly on the luminance

path. Note that the limitation of luminance data has to be

disabled with bit [8]. The values 0 and 255 will no longer be

protected in the luminance path!

bit [7]:

bit [8]:

reserved (must be set to zero)

0

Disable limitation of luminance data (see bit [6])

dislim

0

1

enabled

disabled

bit [9]:

Suppress ITU–R656 headers for blank lines

Change of ITU–R656 header flags

0

hsup

bit [10]:

flagdel

0

1

change header flags in SAV

change header flags in EAV

bit [11]:

reserved (must be set to zero)

0

Micronas

81

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

FP-RAM VPX Back-End

HVREF

Address

Hex

Number

of Bits

Mode

Function

Default

Name

h’151

12

w

Start position of the programmable ‘video active’

The start position has to be an even value and is given relative to the

trailing edge of HREF. Programmable VACT is activated with bit [2] of

the control word (h’140)!

40

pval_

start

bit [10:0]: start of VACT reference signal

h’152

h’153

12

w

End position of the programmable ‘video active’

The end position has to be an even value and is given relative to the

trailing edge of HREF.

720

pval_stop

bit [10:0]: end of VACT reference signal

HREF and VREF control

determines length and polarity of the timing reference signals

refsig

oepol

bit [0]:

bit [1]:

bit [2]:

Odd/Even polarity

0

1

odd high

even high

HREF Polarity

hpol

0

1

active high

active low

VREF Polarity

vpol

0

1

active high

active low

bit [5:3]: VREF pulse width, binary value + 2

000: pulse width = 2

vlen

111: pulse width = 9

bit [6]:

1 disables field as output

disfield

setting this bit will force the ‘field’ pin to the high impedance

state

Output Multiplexer

h’154

12

w

Output Multiplexer

0

outmux

bmp

bit [7:0]: Multi-purpose bits on Port B

determines the state of Port B when used as programmable

output

bit [8]:

bit [9]:

activate multi-purpose bits on Port B

note that double clock mode has to be selected for this

option!

bmpon

double

Port Mode

0

1

parallel_out, ‘single clock’, Port A & B = FO[15:0];

‘double clock’

Port A = FO[15:8] / FO[7:0],

Port B = programmable output/not used;

bit [10]:

bit [11]:

switch ‘VBI active’ qualifier

vbiact

0

1

connect ‘VBI active’ to VACT pin

connect ‘VBI active’ to TDO pin

reserved (must be set to zero)

Temporal Decimation

h’157

12

w

Number of frames to output within 3000 frames

This value will be activated only if the corresponding latch flag is set

(control word h’140, bit [10] ).

3000

tdecframes

82

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

7. Application Notes

7.2. Impact to Signal to Noise Ratio

Fig. 7–1 shows the impact of the variation of the power

supply with respect to the SNR of the ADCs. The noise

due to the digital output interface leads to an impact of

theanalogperformanceoftheanalogADCs. Application

engineersshouldminimizeloadcapacitancesanddriver

strength of the output signals.

7.1. Differences between VPX 3220A and VPX 322xD

The following items indicate the differences between the

VPX 322xD and the VPX 3220A:

Internal

45

44

43

42

41

40

39

2

– The control registers (I C and FP-RAM) contain signif-

icant changes.

– VPX 322xD incorporates a text slicer. Furthermore,

raw ADC data is supported (sampling frequency of

20.25 MHz/8 bit, output data rate 13.5 MHz/16 bit).

– VPX 322xD does not support RGB and compressed

video data output formats. The VPX 322xD supports

ITU-R601 and ITU-R656.

38

2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0

PVDD [V]

– The VPX 322xD does not provide an asynchronous

output mode, PIXCLK functions as an output only. The

VPX 322xD supports half-clock data rate (6.75 MHz).

Fig. 7–1: Dependency between SNR and

Power Supply

– The VPX 322xD does not provide a video data rate of

20.25 MHz at the output interface.

Note: Both ADCs are working and routed to A[7:0], and

B[7:0]. All interfaces are working with maximum driver

strength bandwidth measurement is performed up to 5

MHz.

– The VPX 322xD has an implemented low power

mode.

External

7.3. Control Interface

7.3.1. Symbols

– Power-up Default Selection

Selection

VPX 3220A

VPX 322xD

<

>

aa

dd

Start Condition

Stop Condition

(Sub-)Address Byte

Data Byte

2

I C device

PREF

OE

address

wake-up default

Pads tristate/

active

PIXCLK

FIELD

2

7.3.2. Write Data into I C Register

<86 f2 dd>

write to register OENA

2

– The VPX 322xD does not use the internal I C bus for

2

power-up initialization. Resultingly, the I C interface

2

7.3.3. Read Data from I C Register

will not be locked during that period.

<86 00 <87 dd>

read Manufacture ID

– The VPX 322xD supports an 8-bit programmable out-

put port if the device uses only A[7:0] for video data

output.

7.3.4. Write Data into FP Register

– The VPX 322xD provides a HREF signal with a fixed

low period, whereas the width of the high period will

vary while the video input signal varies.

<86 35 <87 dd>

<86 37 aa aa>

<86 35 <87 dd>

<86 38 dd dd>

poll busy bit[2] until it is cleared

write FP register write address

poll busy bit[2] until it is cleared

write data into FP register

7.3.5. Read Data from FP Register

<86 35 <87 dd>

<86 36 aa aa>

<86 35 <87 dd>

poll busy bit[2] until it is cleared

write FP register read address

poll busy bit[2] until it is cleared

<86 38 <87 dd dd> read data from FP register

Micronas

83

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

7.3.6. Sample Control Code

A Windows API function set is provided for controlling

the VPX. This API is independent of the actual used ver-

sion of the VPX. It is recommended to control the VPX

via this API, which allows flexible switching between dif-

ferent VPX family members. The API is available on re-

quest. The following code demonstrates the usage of

the API to initialize the VPX.

#include <vpx.h>

VPXInit();

// VPXAPI support header

// initializes the VPX from an INI file

VPXSetVideoSource(VPX_VIN1, VPX_COMPOSITE);

VPXSetVideoWindow(VPX_VIDEO_WINDOW1, 23, 288, 0, 720, 720, 3000, 0);

VPXSetVideoWindow(VPX_VIDEO_WINDOW2, 0,

0, 0,

0,

0, 0);

VPXSetVideoWindow(VPX_VBI_WINDOW,

VPXSetVideoStandard(VPX_PAL);

320, 336, 7, 23,

VPXSetVBIMode(VPX_VBI_SLICED_DATA, VPX_VBI_ACTIVE);

VPXSetVideoAttribute(VPX_VIDEO_WINDOW1, VPX_CONTRAST,

128);

VPXSetVideoAttribute(VPX_VIDEO_WINDOW1, VPX_BRIGHTNESS, 128);

VPXSetVideoAttribute(VPX_VIDEO_WINDOW1, VPX_SATURATION, 128);

VPXSetVideoAttribute(VPX_VIDEO_WINDOW1, VPX_HUE,

VPXSetVideoAttribute(VPX_VIDEO_WINDOW1, VPX_PEAKING,

VPXSetVideoAttribute(VPX_VIDEO_WINDOW1, VPX_CORING,

128);

7.4. Xtal Supplier

Name

Part No.

Country

Phone

Contact

Notes

Acal Auremia

2351051

Germany

+49 (713) 15810

(905) 623 4101

(619) 433–4510

(408) 257–3399

Crystal Holder

HC49U

Lap Tech

XT1750

Canada

USA

Bob Parkins

Specify 13 pF

Load Cap

Monitor Product

Co.

MM 49x–5297

5009–359@20.25

Mtron

USA

George Panos

84

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

7.5. Typical Application

Micronas

85

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

86

Micronas

PRELIMINARY DATA SHEET

VPX 3225D, VPX 3224D

Micronas

87

VPX 3225D, VPX 3224D

PRELIMINARY DATA SHEET

8. Data Sheet History

1. Preliminary data sheet: “VPX 3225D, VPX 3224D

Video Pixel Decoders”, Edition March 5, 1997,

6251-432-1PD. First release of the preliminary data

sheet.

2. Preliminary data sheet: “VPX 3225D, VPX 3224D

Video Pixel Decoders”, Edition Nov. 9, 1998,

6251-432-2PD. Second release of the preliminary data

sheet. Major changes:

– additional feature: macrovision detection

– format of ITU-R656 ancillary data modified

– new timing for LLC and OE pins

– section 3.1.: package outline dimensions changed

All information and data contained in this data sheet are without any

commitment, are not to be considered as an offer for conclusion of a

contract, nor shall they be construed as to create any liability. Any new

issueofthisdatasheetinvalidatespreviousissues.Productavailability

and delivery are exclusively subject to our respective order confirma-

tion form; the same applies to orders based on development samples

delivered. By this publication, Micronas GmbH does not assume re-

sponsibility for patent infringements or other rights of third parties

which may result from its use.

Further, Micronas GmbH reserves the right to revise this publication

and to make changes to its content, at any time, without obligation to

notify any person or entity of such revisions or changes.

No part of this publication may be reproduced, photocopied, stored on

a retrieval system, or transmitted without the express written consent

of Micronas GmbH.

Micronas GmbH

Hans-Bunte-Strasse 19

D-79108 Freiburg (Germany)

P.O. Box 840

D-79008 Freiburg (Germany)

Tel. +49-761-517-0

Fax +49-761-517-2174

E-mail: docservice@micronas.com

Internet: www.micronas.com

Printed in Germany

Order No. 6251-432-2PD

88

Micronas

VPX 3225D, VPX 3224D

Preliminary Data Sheet Supplement

New Package for VPX 3225D, VPX 3224D

Subject:

Data Sheet Concerned:

VPX 3225D, VPX 3224D

6251-432-2PD, Edition Nov. 9, 1998

Supplement:

Edition:

No. 6 / 6251-432-6PDS

April 8, 1999

New Package for the VPX 3225D–C3, VPX 3224D–C3

1. The VPX 3225D–C3, VPX 3224D–C3 is also available in the PMQFP44 package.

2. The pinning of the PMQFP44 package has been changed, i.e. mirrored vertically.

3. Production of the PLCC44 package will continue.

Attachment: Package Information VPX 3225D, VPX 3224D

MICRONAS INTERMETALL

page 1 of 4

VPX 3225D, VPX 3224D

PACKAGE INFORMATION

1. Specifications

1.1. Outline Dimensions

10 x 0.8 = 8

0.8

0.17

33

23

34

22

12

1.3

44

1

11

2.0

1.75

13.2

10

0.1

2.15

D0024/2E

Fig. 1–1:

44-Pin Plastic Metric Quad Flat Pack

(PMQFP44)

Weight approx. 0.4 g

Dimensions in mm

1.2. Pin Connections and Short Descriptions

NC = not connected; leave vacant

LV = if not used, leave vacant

X = obligatory

Pin No. Pin Name

Pin Type

Connection

Short Description

(if not used)

1

VIN1

AVSS

CIN

AIN

NC

X

Analog Video 1 Input

Ground, Analog Circuitry

Analog Chroma Input

2

SUPPLY

AIN

3

NC

X

4

AVDD

XTAL1

XTAL2

VDD

VSS

RESQ

SCL

SDA

B0

SUPPLY

OSC IN

OSC OUT

SUPPLY

IN

Supply Voltage, Analog Circuitry

Analog Crystal Input

5

X

6

X

Analog Crystal Output

Supply Voltage, Digital Circuitry

Ground, Digital Circuitry

Reset Input

7

X

8

X

9

X

10

11

12

13

14

IN/OUT

OUT

NC

I²C Bus Clock

I²C Bus Data

Port B - Video Data Output

B1

OUT

B2

OUT

page 2 of 4

MICRONAS INTERMETALL

PACKAGE INFORMATION

VPX 3225D, VPX 3224D

Pin No. Pin Name

Pin Type

Connection

(if not used)

Short Description

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

B3

OUT

IN

NC

VSS

NC

X

Port B - Video Data Output

Active Video Qualifier Output

PIXCLK * 2 = 27 MHz Output

Output Ports Enable Input

Port A - Video Data Output

Ground, Pad Circuits

B4

B5

B6

B7

VACT

LLC

OEQ

A0

OUT

SUPPLY

OUT

SUPPLY

A1

A2

A3

PVSS

PIXCLK

PVDD

NC

X

Pixel Clock Output

Supply Voltage Pad Circuits

MICRONAS INTERMETALL

page 3 of 4

VPX 3225D, VPX 3224D

PACKAGE INFORMATION

1.3. Pin Configuration

PIXCLK

PVDD

A4

PVSS

A3

A5

A2

A6

A1

A7

A0

33 32 31 30 29 28 27 26 25 24 23

FIELD 34

VREF 35

22 OEQ

21 LLC

20 VACT

19 B7

18 B6

17 B5

16 B4

15 B3

14 B2

13 B1

12 B0

HREF 36

TDO (DACT, LLC2) 37

TCK 38

VPX 3225D

VPX 3224D

TDI 39

TMS 40

ISGND 41

VIN3 42

VRT 43

VIN2 44

1

2

3

4

5

6

7

8

9

10 11

VIN1

SDA

AVSS

SCL

RESQ

VSS

VDD

CIN

AVDD

XTAL1

XTAL2

Fig. 1–2: 44-pin PMQFP package

1.4. Electrical Characteristics

1.4.1. Absolute Maximum Ratings

Symbol

T_A

Parameter

Pin Name

Min.

0

Max.

55

Unit

°C

Ambient Temperature

Storage Temperature

Junction Temperature

T_S

−40

0

125

°C

T_J

°C

Stresses beyond those listed in the “Absolute Maximum Ratings” may cause permanent damage to the device. This

is a stress rating only. Functional operation of the device at these or any other conditions beyond those indicated in

the “Recommended Operating Conditions/Characteristics” of this specification is not implied. Exposure to absolute

maximum ratings conditions for extended periods may affect device reliability.

page 4 of 4

MICRONAS INTERMETALL


型号：	VPX3224D
厂家：	ETC
描述：	Video Pixel Decoders 视频像素解码器解码器商用集成电路
文件：	总92页 (文件大小：661K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

VPX3224D [ETC]

相关型号：

VPX3224D-B2

VPX3224D-C3

VPX3224E

VPX3224E

VPX3224EPQ

VPX3225D

VPX3225D-B2

VPX3225D-C3

VPX3225E

VPX3225E

VPX3225EQG

VPX3226E