W132-10B [ETC]

Ten Distributed-Output Clock Driver ; 十大分布式输出时钟驱动器\n


型号：	W132-10B
厂家：	ETC
描述：	Ten Distributed-Output Clock Driver 十大分布式输出时钟驱动器\n 时钟驱动器
文件：	总13页 (文件大小：154K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

W134M/W134S

Direct Rambus™ Clock Generator

Features

Overview

• Differential clock source for Direct Rambus™ memory

subsystem for up to 800-MHz data transfer rate

• Providesynchronizationflexibility: theRambus^®Chan-

nel can optionally be synchronous to an external sys-

tem or processor clock

The Cypress W134M/W134S provides the differential clock

signals for a Direct Rambus memory subsystem. It includes

signals to synchronize the Direct Rambus Channel clock to an

external system clock but can also be used in systems that do

not require synchronization of the Rambus clock.

• Power managed output allows Rambus Channel clock

to be turned off to minimize power consumption for

mobile applications

Key Specifications

Supply Voltage: ..................................... V_DD= 3.3V±0.165V

Operating Temperature: .................................. 0°C to +70°C

Input Threshold: ..................................................1.5V typical

Maximum Input Voltage:.........................................V_DD+0.5V

Maximum Input Frequency:..................................... 100 MHz

Output Duty Cycle: .................................. 40/60% worst case

Output Type:........................... Rambus signaling level (RSL)

• WorkswithCypressCY2210, W133, W158,W159, W161,

and W167 to support Intel^®architecture platforms

• Low-power CMOS design packaged in a 24-pin, 150-mil

SSOP package

Block Diagram

Pin Configuration

REFCLK

VDDIR

REFCLK

VDD

PLL

MULT0:1

VDD

GND

CLK

GND

PCLKM

SYNCLKN

GND

CLKB

GND

VDD

MULT0

MULT1

GND

CLK

Output

Phase

Alignment

PCLKM

Logic

CLKB

VDD

SYNCLKN

VDDIPD

STOPB

PWRDNB

Test

Logic

S0:1

STOPB

Cypress Semiconductor Corporation

Document #: 38-07426 Rev. *A

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised December 14, 2002

W134M/W134S

Pin Definitions

No.

Type

Pin Name

Pin Description

REFCLK

Reference Clock Input: Reference clock input, normally supplied by a system

frequency synthesizer (Cypress W133).

PCLKM

Phase Detector Input: The phase difference between this signal and SYNCLKN

is used to synchronize the Rambus Channel Clock with the system clock. Both

PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory con-

troller. If Gear Ratio Logic is not used, this pin would be connected to Ground.

SYNCLKN

Phase Detector Input: The phase difference between this signal and PCLKM is

used to synchronize the Rambus Channel Clock with the system clock. Both

PCLKM and SYNCLKN are provided by the Gear Ratio Logic in the memory con-

troller. If Gear Ratio Logic is not used, this pin would be connected to Ground.

STOPB

Clock Output Enable: When this input is driven to active LOW, it disables the

differential Rambus Channel clocks.

PWRDNB

Active LOW Power-Down: When this input is driven to active LOW, it disables the

differential Rambus Channel clocks and places the W134M/W134S in power-down

mode.

MULT 0:1

15, 14

PLL Multiplier Select: These inputs select the PLL prescaler and feedback divid-

ers to determine the multiply ratio for the PLL for the input REFCLK.

W134S

W134M

PLL/REFCLK

MULT0

MULT1

4.5

5.333

CLK, CLKB

S0, S1

20, 18

24, 23

Complementary Output Clock: Differential Rambus Channel clock outputs.

Mode Control Input: These inputs control the operating mode of the

W134M/W134S.

MODE

Normal

Output Enable Test

Bypass

Test

No Connect

VDDIR

VDDIPD

RefV

Reference for REFCLK: Voltage reference for input reference clock.

Reference for Phase Detector: Voltage reference for phase detector inputs and

StopB.

VDD

GND

3, 9, 16, 22

Power Connection: Power supply for core logic and output buffers. Connected to

3.3V supply.

4, 5, 8, 13,

17, 21

Ground Connection: Connect all ground pins to the common system ground

plane.

Document #: 38-07426 Rev. *A

Page 2 of 13

W134M/W134S

W133

W158

W159

W161

W167

Refclk

Phase

PLL

Busclk

Align

CY2210

RAC

RMC

Pclk

DLL

Synclk

Gear

Ratio

Logic

Figure 1. DDLL System Architecture

face of the RAC. The DDLL together with the Gear Ratio Logic

enables users to exchange data directly from the Pclk domain

to the Synclk domain without incurring additional latency for

synchronization. In general, Pclk and Synclk can be of differ-

ent frequencies, so the Gear Ratio Logic must select the ap-

propriate M and N dividers such that the frequencies of Pclk/M

and Synclk/N are equal. In one interesting example,

Pclk = 133 MHz, Synclk = 100 MHz, and M = 4 while N = 3,

giving Pclk/M = Synclk/N = 33 MHz. This example of the clock

waveforms with the Gear Ratio Logic is shown in Figure 2.

DDLL System Architecture and Gear Ratio Log-

Figure 1 shows the Distributed Delay Lock Loop (DDLL) sys-

tem architecture, including the main system clock source, the

Direct Rambus clock generator (DRCG), and the core logic

that contains the Rambus Access Cell (RAC), the Rambus

Memory Controller (RMC), and the Gear Ratio Logic. (This

diagram abstractly represents the differential clocks as a sin-

gle Busclk wire.)

The output clocks from the Gear Ratio Logic, Pclk/M, and

Synclk/N, are output from the core logic and routed to the

DRCG Phase Detector inputs. The routing of Pclk/M and Syn-

clk/N must be matched in the core logic as well as on the

board.

The purpose of the DDLL is to frequency-lock and phase-align

the core logic and Rambus clocks (Pclk and Synclk) at the

RMC/RAC boundary in order to allow data transfers without

incurring additional latency. In the DDLL architecture, a PLL is

used to generate the desired Busclk frequency, while a distrib-

uted loop forms a DLL to align the phase of Pclk and Synclk at

the RMC/RAC boundary.

After comparing the phase of Pclk/M vs. Synclk/N, the DRCG

Phase Detector drives a phase aligner that adjusts the phase

of the DRCG output clock, Busclk. Since everything else in the

distributed loop is fixed delay, adjusting Busclk adjusts the

phase of Synclk and thus the phase of Synclk/N. In this man-

ner the distributed loop adjusts the phase of Synclk/N to match

that of Pclk/M, nulling the phase error at the input of the DRCG

Phase Detector. When the clocks are aligned, data can be

exchanged directly from the Pclk domain to the Synclk do-

main.

The main clock source drives the system clock (Pclk) to the

core logic, and also drives the reference clock (Refclk) to the

DRCG. For typical Intel architecture platforms, Refclk will be

half the CPU front side bus frequency. A PLL inside the DRCG

multiplies Refclk to generate the desired frequency for Busclk,

and Busclk is driven through a terminated transmission line

(Rambus Channel). At the mid-point of the channel, the RAC

senses Busclk using its own DLL for clock alignment, followed

by a fixed divide-by-4 that generates Synclk.

Table 1 shows the combinations of Pclk and Busclk frequen-

cies of greatest interest, organized by Gear Ratio.

Pclk is the clock used in the memory controller (RMC) in the

core logic, and Synclk is the clock used at the core logic inter-

Pclk

Synclk

Pclk/M =

Synclk/N

Figure 2. Gear Ratio Timing Diagram

Document #: 38-07426 Rev. *A

Page 3 of 13

W134M/W134S

Table 1. Supported Pclk and Busclk Frequencies, by Gear Ratio

Gear Ratio and Busclk

Pclk

2.0

1.5

1.33

1.0

67 MHz

267 MHz

400 MHz

100 MHz

133 MHz

150 MHz

200 MHz

300 MHz

400 MHz

267 MHz

400 MHz

356 MHz

400 MHz

StopB

S0/S1

W134M/W134S

W133

W158

W159

W161

W167

Refclk

Phase

PLL

Busclk

Align

CY2210

RAC

RMC

Pclk

DLL

Synclk

Gear

Ratio

Logic

Figure 3. DDLL Including Details of DRCG

Figure 3 shows more details of the DDLL system architecture,

including the DRCG output enable and bypass modes.

directly, by bypassing the Phase Aligner. If PclkM and SynclkN

are not used, those inputs must be grounded.

Phase Detector Signals

Selection Logic

The DRCG Phase Detector receives two inputs from the core

logic, PclkM (Pclk/M) and SynclkN (Synclk/N). The M and N

dividers in the core logic are chosen so that the frequencies of

PclkM and SynclkN are identical. The Phase Detector detects

the phase difference between the two input clocks, and drives

the DRCG Phase Aligner to null the input phase error through

the distributed loop. When the loop is locked, the input phase

error between PclkM and SynclkN is within the specification

t_ERR,PDgiven in Table 14 after the lock time given in the State

Transition Section.

Table 2 shows the logic for selecting the PLL prescaler and

feedback dividers to determine the multiply ratio for the PLL

from the input Refclk. Divider A sets the feedback and divider

B sets the prescaler, so the PLL output clock frequency is set

by: PLLclk=Refclk*A/B.

Table 2. PLL Divider Selection

W134M

W134S

Mult0

Mult1

The Phase Detector aligns the rising edge of PclkM to the

rising edge of SynclkN. The duty cycle of the phase detector

input clocks will be within the specification DC_IN,PDgiven in

Table 13. Because the duty cycles of the two phase detector

input clocks will not necessarily be identical, the falling edges

of PclkM and SynclkN may not be aligned when the rising edg-

es are aligned.

Table 3 shows the logic for enabling the clock outputs, using

the StopB input signal. When StopB is HIGH, the DRCG is in

its normal mode, and Clk and ClkB are complementary outputs

following the Phase Aligner output (PAclk). When StopB is

LOW, the DRCG is in the Clk Stop mode, the output clock

drivers are disabled (set to Hi-Z), and the Clk and ClkB settle

to the DC voltage V_X,STOPas given in Table 14. The level of

V_X,STOPis set by an external resistor network.

The voltage levels of the PclkM and SynclkN signals are de-

termined by the controller. The pin VDDIPD is used as the

voltage reference for the phase detector inputs and should be

connected to the output voltage supply of the controller. In

some applications, the DRCG PLL output clock will be used

Document #: 38-07426 Rev. *A

Page 4 of 13

W134M/W134S

Table 3. Clock Stop Mode Selection

Table 5. Power-down Mode Selection

Mode

Normal

Clk Stop

StopB

Clk

ClkB

Mode

Normal

PwrDnB

Clk

ClkB

PAclkB

GND

PAclk

PAclkB

V_X,STOP

PAclk

GND

V_X,STOP

Power-down

Table 4 shows the logic for selecting the Bypass and Test

modes. The select bits, S0 and S1, control the selection of

these modes. The Bypass mode brings out the full-speed PLL

output clock, bypassing the Phase Aligner. The Test mode

brings the Refclk input all the way to the output, bypassing

both the PLL and the Phase Aligner. In the Output Test mode

(OE), both the Clk and ClkB outputs are put into a high-imped-

ance state (Hi-Z). This can be used for component testing and

for board-level testing.

Table of Frequencies and Gear Ratios

Table 6 shows several supported Pclk and Busclk frequencies,

the corresponding A and B dividers required in the DRCG PLL,

and the corresponding M and N dividers in the gear ratio logic.

The column Ratio gives the Gear Ratio as defined Pclk/Synclk

(same as M and N). The column F@PD gives the divided down

frequency (in MHz) at the Phase Detector, where

F@PD = Pclk/M = Synclk/N.

Table 4. Bypass and Test Mode Selection

Bypclk

State Transitions

The clock source has three fundamental operating states. Fig-

ure 4 shows the state diagram with each transition labelled A

through H. Note that the clock source output may NOT be

glitch-free during state transitions.

Mode

(int.)

Gnd

Clk

PAclk

Hi-Z

ClkB

PAclkB

Hi-Z

Normal

Output Test (OE)

Bypass

Upon powering up the device, the device can enter any state,

depending on the settings of the control signals, PwrDnB and

StopB.

PLLclk PLLclk PLLclkB

Refclk Refclk RefclkB

Test

In Power-down mode, the clock source is powered down with

the control signal, PwrDnB, equal to 0. The control signals S0

and S1 must be stable before power is applied to the device,

and can only be changed in Power-down mode (PwrDnB = 0).

The reference inputs, V_DDRand V_DDPD, may remain on or may

be grounded during the Power-down mode.

Table 5 shows the logic for selecting the Power-down mode,

using the PwrDnB input signal. PwrDnB is active LOW (en-

abled when 0). When PwrDnB is disabled, the DRCG is in its

normal mode. When PwrDnB is enabled, the DRCG is put into

a powered-off state, and the Clk and ClkB outputs are three-

stated.

Table 6. Examples of Frequencies, Dividers, and Gear Ratios

Pclk

Refclk

Busclk

267

Synclk

Ratio

1.0

F@PD

100

133

300

1.33

1.0

12.5

400

100

267

2.0

400

100

1.33

16.7

Turn-On

Test

Normal

Turn-On

Power-Down

Clk Stop

Figure 4. Clock Source State Diagram

Document #: 38-07426 Rev. *A

Page 5 of 13

W134M/W134S

The control signals Mult0 and Mult1 can be used in two ways.

If they are changed during Power-down mode, then the Pow-

er-down transition timings determine the settling time of the

DRCG. However, the Mult0 and Mult1 control signals can also

be changed during Normal mode. When the Mult control sig-

nals are “hot swapped” in this manner, the Mult transition tim-

ings determine the settling time of the DRCG.

Table 7. Control Signals for Clock Source States

Clock

Source

Output

State

PwrDnB

StopB

Buffer

Ground

Disabled

Enabled

Power-down

Clock Stop

Normal

OFF

In Clock Stop mode, the clock source is on, but the output is

disabled (StopB asserted). The V_DDPDreference input may

remain on or may be grounded during the Clk Stop mode. The

V_DDRreference input must remain on during the Clock Stop

mode.

Figure 5 shows the timing diagrams for the various transitions

between states, and Table 8 specifies the latencies of each

state transition. Note that these transition latencies assume

the following:

In Normal mode, the clock source is on, and the output is en-

abled.

• Refclk input has settled and meets specification shown in

Table 13.

Table 7 lists the control signals for each state.

• Mult0, Mult1, S0 and S1 control signals are stable.

Timing Diagrams

Figure 5. State Transition Timing Diagrams

Power-Down Exit and Entry

PwrDnB

t_POWERDN

t_POWERUP

Clk/ClkB

Output Enable Control

t_ON

t_STOP

StopB

CLKON

t_CLKOFF

CLKSETL

Clk/ClkB

Clock output settled within

50 ps of the phase before

disabled

Clock enabled

and glitch free

Output clock

not specified

glitches may

occur

Figure 6. Multiply Transition Timing

Mult0 and/or Mult1

t_MULT

Clk/ClkB

Document #: 38-07426 Rev. *A

Page 6 of 13

W134M/W134S

Table 8. State Transition Latency Specifications

Transition Latency

Transition

From

Symbol

Max.

Description

Power-down

Normal

t_POWERUP

3 ms

Time from PwrDnB to Clk/ClkB output settled

(excluding t_DISTLOCK).

Power-down

V_DDON

Clk Stop

Test

t_POWERUP

Time from PwrDnB until the internal PLL and

clock has turned ON and settled.

Time from PwrDnB to Clk/ClkB output settled

(excluding t_DISTLOCK).

Normal

Clk Stop

Time from V_DDis applied and settled until

Clk/ClkB output settled (excluding t_DISTLOCK).

V_DDON

Time from V_DDis applied and settled until

internal PLL and clock has turned ON and

settled.

V_DDON

Normal

Test

t_POWERUP

3 ms

1 ms

10 ns

Time from V_DDis applied and settled until

internal PLL and clock has turned ON and

settled.

Normal

t_MULT

Time from when Mult0 or Mult1 changed until

Clk/ClkB output resettled (excluding

t_DISTLOCK).

Clk Stop

Normal

t_CLKON

Time from StopB until Clk/ClkB provides

glitch-free clock edges.

t_CLKSETL

20 cycles Time from StopB to Clk/ClkB output settled to

within 50 ps of the phase before CLK/CLKB

was disabled.

Normal

Test

Clk Stop

Normal

t_CLKOFF

t_CTL

5 ns

Time from StopB Φ to Clk/ClkB output

disabled.

3 ms

Time from when S0 or S1 is changed until

CLK/CLKB output has resettled (excluding

t_DISTLOCK).

Normal

Test

t_CTL

3 ms

1 ms

Time from when S0 or S1 is changed until

CLK/CLKB output has resettled (excluding

t_DISTLOCK).

B,D

Normal or Clk Stop Power-down

t_POWERDN

Time from PwrDnB Φ to the device in Power-

down.

Figure 5 shows that the Clk Stop to Normal transition goes

through three phases. During t_CLKON, the clock output is not

specified and can have glitches. For t_CLKON< t < t_CLKSETL, the

clock output is enabled and must be glitch-free. For

t > t_CLKSETL, the clock output phase must be settled to within

50 ps of the phase before the clock output was disabled. At

this time, the clock output must also meet the voltage and tim-

ing specifications of Table 14. The outputs are in a high-imped-

ance state during the Clk Stop mode.

Document #: 38-07426 Rev. *A

Page 7 of 13

W134M/W134S

Table 9. Distributed Loop Lock Time Specification

Symbol

Min.

Max.

Units

Description

t_DISTLOCK

Time from when Clk/ClkB output is settled to when the phase error between

SynclkN and PclkM falls within the t_ERR,PDspec in Table 14.

Table 10. Supply and Reference Current Specification

Parameter

I_POWERDOWN

I_CLKSTOP

Description

Min.

Max.

250

Unit

µA

“Supply” current in Power-down state (PwrDnB=0)

“Supply” current in Clk Stop state (StopB=0)

“Supply” current in Normal state (StopB=1,PwrDnB=1)

µA

I_NORMAL

100

I_REF,PWDN

Current at VDDIR or VDDIPD reference pin in Power-down

state (PwrDnB=0)

I_REF,NORM

Current at VDDIR or VDDIPD reference pin in Normal or Clk

Stop state (PwrDnB=1)

Table 11 represents stress ratings only, and functional operation at the maximums is not guaranteed.

Table 11. Absolute Maximum Ratings

Parameter

V_{DD, ABS}

V_{I, ABS}

Description

Min.

–0.5

Max.

Unit

Max. voltage on V_DDwith respect to ground

Max. voltage on any pin with respect ground

4.0

V_DD+0.5

Table 12 gives the nominal values of the external components and their maximum acceptable tolerance, assuming Z_CH=28Ω.

Table 12. External Component Values

Parameter

Description

Min.

Max.

±5%

Unit

Ω

R_S

R_P

C_F

Serial Resistor

Parallel Resistor

4–15^[1]

±5%

Ω

Edge Rate Filter Capacitor

AC Ground Capacitor

±10%

0.1 µF

C_MID

470 pF

±20%

Note:

1. Do not populate C_F. Leave pads for future use.

Document #: 38-07426 Rev. *A

Page 8 of 13

W134M/W134S

Table 13. Operating Conditions^[2]

Parameter

Description

Min.

3.135

Max.

3.465

Unit

V_DD

Supply Voltage

°C

T_A

Ambient Operating Temperature

t_CYCLE,IN

t_J,IN

Refclk Input Cycle Time

Input Cycle-to-Cycle Jitter^[3]

250

DC_IN

FM_IN

Input Duty Cycle over 10,000 Cycles

Input Frequency of Modulation

%t_CYCLE

kHz

[4]

PM_IN

Modulation Index for Triangular Modulation

Modulation Index for Non-Triangular Modulation

Phase Detector Input Cycle Time at PclkM & SynclkN

Initial Phase error at Phase Detector Inputs

Phase Detector Input Duty Cycle over 10,000 Cycles

0.6

0.5^[6]

100

0.5

t_CYCLE,PD

t_ERR,INIT

DC_IN,PD

t_I,SR

–0.5

t_CYCLE,PD

V/ns

Input Slew Rate (measured at 20%-80% of input voltage) for PclkM,

SynclkN, and Refclk

C_IN,PD

Input Capacitance at PclkM, SynclkN, and Refclk^[5]

Input Capacitance matching at PclkM and SynclkN^[5]

∆C_IN,PD

C_IN,CMOS

0.5

Input Capacitance at CMOS pins (excluding PclkM, SynclkN, and

Refclk)^[5]

V_IL

Input (CMOS) Signal Low Voltage

Input (CMOS) Signal High Voltage

Refclk input Low Voltage

0.7

0.3

VDD

V_DDIR

V_DDIPD

V_IH

V_IL,R

V_IH,R

V_IL,PD

V_IH,PD

V_DDIR

0.3

Refclk input High Voltage

0.7

Input Signal Low Voltage for PD Inputs and StopB

Input Signal High Voltage for PD Inputs and StopB

Input Supply Reference for Refclk

Input Supply Reference for PD Inputs

0.3

0.7

1.235

3.465

2.625

V_DDIPD

Notes:

2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.

3. Refclk jitter measured at V_DDIR(nom)/2.

4. If input modulation is used: input modulation is allowed but not required.

5. Capacitance measured at Freq=1 MHz, DC bias = 0.9V and V_AC< 100 mV.

6. The amount of allowed spreading for any non-triangular modulation is determined by the induced downstream tracking skew, which cannot exceed the skew

generated by the specified 0.6% triangular modulation. Typically, the amount of allowed non-triangular modulation is about 0.5%.

Document #: 38-07426 Rev. *A

Page 9 of 13

W134M/W134S

Table 14. Device Characteristics

Parameter

Description

Min.

Max.

3.75

Unit

t_CYCLE

t_J

Clock Cycle Time

Cycle-to-Cycle Jitter at Clk/ClkB^[7]

2.5

Total Jitter over 2, 3, or 4 Clock Cycles^[7]

266-MHz Cycle-to-Cycle Jitter^[8]

266-MHz Total Jitter over 2, 3, or 4 Clock Cycles^[8]

100

160

t_STEP

Phase Aligner Phase Step Size (at Clk/ClkB)

t_ERR,PD

Phase Detector Phase Error for Distributed Loop Measured at PclkM-

SynclkN (rising edges) (does not include clock jitter)

–100

100

t_ERR,SSC

V_X,STOP

V_X

PLL Output Phase Error when Tracking SSC

Output Voltage during Clk Stop (StopB=0)

Differential Output Crossing-Point Voltage

Output Voltage Swing (p-p single-ended)^[9]

Output High Voltage

–100

1.1

1.3

0.4

100

2.0

1.8

0.6

2.0

V_COS

V_OH

V_OL

Output Low voltage

1.0

r_OUT

Output Dynamic Resistance (at pins)^[10]

Output Current during Hi-Z (S0 = 0, S1 = 1)

Output Current during Clk Stop (StopB = 0)

Output Duty Cycle over 10,000 Cycles

Output Cycle-to-Cycle Duty Cycle Error

Output Rise and Fall Times (measured at 20%–80% of output voltage)

Ω

I_OZ

µA

I_OZ,STOP

t_DC,ERR

t_R,t_F

500

µA

%t_CYCLE

250

500

100

t_CR,CF

Difference between Output Rise and Fall Times on the Same Pin of a

Single Device (20%–80%)

Notes:

7. Output Jitter spec measured at t_CYCLE= 2.5 ns.

8. Output Jitter Spec measured at t_CYCLE= 3.75 ns.

V_COS= V_OH–V_OL.

10. r_OUT= ∆V_O/ ∆ I_O. This is defined at the output pins.

Ordering Information

Package

Ordering Code

W134M/W134S

Name

Package Type

24-pin SSOP (150 mils)

Document #: 38-07426 Rev. *A

Page 10 of 13

W134M/W134S

Layout Example

+3.3V Supply

10 µF

C4^{0.005 µF}

VDDIR

VDDIPD

Internal Power Supply Plane

FB = Dale ILB1206 - 300 (300Ω @ 100 MHz)

= VIA to GND plane layer

All Bypass cap = 0.1 Ceramic XR7

Document #: 38-07426 Rev. *A

Page 11 of 13

W134M/W134S

Package Diagram

24-Pin Small Shrink Outline Package (SSOP, 150 mils)

Direct Rambus is a trademark and Rambus is a registered trademark of Rambus Inc.

Intel is a registered trademark of Intel Corporation.

All product and company names mentioned in this document may be the trademarks of their respective holders.

Document #: 38-07426 Rev. *A

Page 12 of 13

of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize

its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress

Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.

W134M/W134S

Document Title: W134M/W134S Direct Rambus™ Clock Generator

Document Number: 38-07426

Issue

Date

Orig. of

Change

REV.

ECN NO.

115531

Description of Change

05/10/02

12/14/02

DSG

RBI

Change from Spec number: 38-00822 to 38-07246

122927

Add power up requirements to operating information.

Document #: 38-07426 Rev. *A

Page 13 of 13

W132-10B [ETC]

相关型号：

W132-10BX

W132-10BXT

W132XGD

W132XGT

W132XIT

W132XNC

W132XPGT

W132XYT

W132_04

W133

W1334EC

W1334GC