W224BH [ETC]
CPU SYSTEM CLOCK GENERATOR|SSOP|56PIN|PLASTIC ; CPU的系统时钟发生器| SSOP | 56PIN |塑料\n
| 型号： | W224BH |
| 厂家： | 
ETC |
| 描述： | CPU SYSTEM CLOCK GENERATOR|SSOP|56PIN|PLASTIC
|
| 文件： | 总17页 (文件大小：334K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
1W224B
W224B
133-MHz Spread Spectrum FTG for Mobile Pentium III Platforms
APIC, 48-MHz, 3V66, PCI Outputs
Cycle-to-Cycle Jitter: ...................................................500 ps
Features
• Maximized EMI suppression using Cypress’s Spread
Spectrum technology (–0.5% and –1.0%)
CPU Output Skew: ......................................................150 ps
3V66 Output Skew:......................................................175 ps
APIC, SDRAM Output Skew:.......................................250 ps
PCI Output Skew:........................................................500 ps
VDDQ3 (REF, PCI, 3V66, 48 MHz, SDRAM: .........3.3V±5%
VDDQ2 (CPU, APIC):.............................................2.5V ±5%
• Single chip system FTG for Mobile Intel® Platforms
• Three CPU outputs
• Seven copies of PCI clock (one Free Running)
• Seven SDRAM clock (one DCLK for Memory Hub)
• Two copies of 48-MHz clock (non-spread spectrum) op-
timized for USB reference input and video DOT clock
• Three 3V66 Hublink/AGP outputs
• One VCH clock (48-MHz non-SSC or 66.67-MHz SSC)
• Two APIC outputs
Table 1. Pin Selectable Functions
TEST#
FS1
x
FS0
0
CPU
SDRAM
0
0
1
1
1
1
Three-state Three-state
• One buffered reference output
• Supports frequencies up to 133 MHz
• Supports 5% and 10% overclocking
• SMBus interface for programming
• Power management control inputs
Key Specifications
x
1
Test
Test
0
0
66 MHz
100 MHz
133 MHz
133 MHz
100 MHz
100 MHz
133 MHz
100 MHz
0
1
1
0
CPU, SDRAM Outputs Cycle-to-Cycle Jitter:.............. 250 ps
1
1
Block Diagram
Pin Configuration
VDD_REF
X1
X2
XTAL
OSC
REF
R EF
VDD_REF
X1
1
2
3
4
5
6
7
8
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
G ND_A PIC
APIC0
APIC1
VDD_APIC
C PU 0
V DD_CPU
C PU _F1
PLL Ref Freq
Divider
Network
PLL 1
VDD_CPU
CPU0
Stop
Clock
Control
X2
FS0:1
G N D_R EF
G ND_3V66
3V66_0
CPU_F1:2
CPU_STP#
VDD_SDRAM
SDRAM0:5
DCLK
3V66_1
C PU _F2
3V66_AG P
VDD_3V66
PC I_STP#
PCI_F
PCI1
G ND_P CI
PCI2
PCI3
VDD_P CI
G N D _C PU
G ND_S DRAM
SDRAM 0
SDRAM 1
V DD_SDRAM
SDRAM 2
SDRAM 3
G ND_S DRAM
SDRAM 4
SDRAM 5
D C LK
V DD_SDRAM
V CH_CLK
VDD_VCH
C PU _STP#
TEST#
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
VDD_APIC
APIC0:1
PWR_DWN#
PCI_STP#
VDD_PCI
PCI_F
PCI4
PCI5
PCI6
Stop
Clock
Control
PCI1:6
G ND_P CI
VD D _C O R E
G N D _C O R E
GND_48M Hz
USB
DO T
VDD_48M Hz
FS0
VDD_3V66
3V66_0:1
34
33
32
31
30
29
3V66_AGP
P W R_DW N#
SCLK
SDATA
FS1
25
26
27
28
VDD_48MHz
USB (48MHz)
PLL2
DOT (48MHz)
VCH_CLK
SDATA
SCLK
SMBus
Logic
Intel is a registered trademark of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
June 12, 2001
W224B
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
CPU0,
CPU_F1:2
52, 50, 49
O
O
O
O
O
CPU Clock Outputs: Frequency is set by the FS0:1 inputs or through serial input
interface. The CPU0 output is gated by the CLK_STOP# input.
PCI1:6, PCI_F
13, 15, 16, 18,
19, 20, 12
33MHz PCI Outputs: Except for the PCI_F output, these outputs are gated by
the PCI_STOP# input.
APIC0:1
55, 54
APIC Output: 2.5V fixed 33.33-MHz clock. This output is synchronous to the
CPU clock.
SDRAM0:5,
DCLK
46, 45, 43, 42,
40, 39, 38
SDRAM Output Clocks: 3.3V outputs running at either 100 MHz or 133 MHz
depending on the setting of FS0:1 inputs. DCLK is a free-running clock.
3V66_0:1,
3V66_AGP
7, 8, 9
66-MHz Clock Outputs: 3.3V fixed 66-MHz clock.
USB
25
26
1
O
O
O
O
USB Clock Output: 3.3V fixed 48-MHz, non-spread spectrum USB clock output.
Dot Clock Output: 3.3V fixed 48-MHz, non-spread spectrum signal.
Reference Clock: 3.3V 14.318-MHz clock output.
DOT
REF
VCH_CLK
36
Video Control Hub Clock Output: 3.3V selectable 48-MHz non-spread spec-
trum or 66.67-MHz spread spectrum clock output.
PWR_DWN#
CPU_STP#
PCI_STP#
TEST#
32
34
I
I
I
I
I
Power Down Control: 3.3V LVTTL-compatible input that places the device in
power-down mode when held LOW.
CPU Output Control: 3.3V LVTTL-compatible input that stops only the CPU0
clock. Output remains in the LOW state.
11
PCI Output Control: 3.3V LVTTL-compatible input that stops PCI1:6 clocks.
Output remains in the LOW state.
33
Test Mode Control: 3.3V LVTTL-compatible input to place the device into test
mode.
FS0:1
28, 29
Frequency Selection Input: 3.3V LVTTL-compatible input used to select the
CPU and SDRAM frequencies. See Frequency Table.
SCLK
SDATA
X1
31
30
3
I
I/O
I
SMBus Clock Input: Clock pin for SMBus circuitry.
SMBus Data Input: Data pin for SMBus circuitry.
CrystalConnectionor ExternalReferenceFrequencyInput:Thispinhas dual
functions. It can be used as an external 14.318-MHz crystal connection or as an
external reference frequency input.
X2
4
O
P
Crystal Connection: Connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
VDD_REF,
VDD_3V66
VDD _PCI,
2, 10, 17, 27, 35,
37, 44
3.3V Power Connection: Power supply for core logic, PLL circuitry, SDRAM
outputs buffers, PCI output buffers, reference output buffers and 48-MHz output
buffers. Connect to 3.3V.
VDD_48MHz,
VDD_VCH,
VDD_SDRAM,
VDD_SDRAM
VDD_APIC,
VDD_CPU
51, 53
P
2.5V Power Connection: Power supply for APIC and CPU output buffers. Con-
nect to 2.5V.
GND_REF,
GND_3V66,
5, 6, 14, 21, 24,
41, 47, 48, 56
G
Ground Connection: Connect all ground pins to the common system ground
plane.
GND_PCI,
GND_PCI,
GND_48MHz,
GND_SDRAM.
GND_SDRAM.
GND_CPU,
GND_APIC
2
W224B
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
VDD_CORE
22
P
3.3V Analog Power Connection: Power supply for core logic, PLL circuitry. Con-
nect to 3.3V.
GND_CORE
23
G
Analog Ground Connection: Ground for core logic, PLL circuitry.
Overview
CPU/SDRAM Frequency Selection
CPU output frequency is selected through pins 28 and 29. For
CPU/SDRAM frequency programming information, refer to
Table 2 Alternatively, frequency selections are available
through the serial data interface.
The W224 is a highly integrated frequency timing generator,
supplying all the required clock sources for an Intel® architec-
ture platform using graphics integrated core logic.
.
Table 2. Frequency Select Truth Table
TEST#
FS1
X
FS0
0
CPU
Hi-Z
SDRAM
Hi-Z
3V66
Hi-Z
PCI
48MHz
Hi-Z
REF
Hi-Z
APIC
Hi-Z
Notes
1
0
0
1
1
1
1
Hi-Z
X
1
TCLK/2
66 MHz
TCLK/2
TCLK/3
TCLK/6
33 MHz
33 MHz
33 MHz
33 MHz
TCLK/2
TCLK
TCLK/6
2, 3
0
0
100 MHz 66 MHz
48 MHz 14.318 MHz 33 MHz
48 MHz 14.318 MHz 33 MHz
48 MHz 14.318 MHz 33 MHz
48 MHz 14.318 MHz 33 MHz
4, 5, 6
4, 5, 6
4, 5, 6
4, 5, 6
0
1
100 MHz 100 MHz 66 MHz
133 MHz 133 MHz 66 MHz
133 MHz 100 MHz 66 MHz
1
0
1
1
Notes:
1. Provided for board-level “bed of nails” testing.
2. TCLK is a test clock overdriven on the XTAL_IN input during test mode.
3. Required for DC output impedance verification.
4. “Normal” mode of operation.
5. Range of reference frequency allowed is min. = 14.316 MHz, nominal = 14.31818 MHz, max. = 14.32 MHz.
6. Frequency accuracy of 48 MHz must be +167 PPM to match USB default.
3
W224B
Offsets Among Clock Signal Groups
spectively. It should be noted that when CPU clock is operating
at 100 MHz, CPU clock output is 180 degrees out of phase with
SDRAM clock outputs.
Figure 1 and Figure 2 represent the phase relationship among
the different groups of clock outputs from W224 when it is pro-
viding a 66-MHz CPU clock and a 100-MHz CPU clock, re-
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 66-MHz
SDRAM 100-M Hz
3V66 66-MHz
PCI 33-MHz
APIC33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 1. Group Offset Waveforms (66 MHz CPU/100 MHz SDRAM Clock)
Table 3. 66 MHz Group Timing Relationships and Tolerances
CPU to
SDRAM to
3V66
SDRAM CPU to 3V66
3V66 to PCI
1.5–3.5 ns
500 ps
PCI to APIC
0.0 ns
USB & DOT
Async
Offset
–2.5 ns
500 ps
7.5 ns
0.0 ns
Tolerance
500 ps
500 ps
1.0 ns
N/A
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 100-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 2. Group Offset Waveforms (100 MHz CPU/100 MHz SDRAM Clock)
4
W224B
Table 4. 100 MHz Group Timing Relationships and Tolerances
CPU to
SDRAM
CPU to
3V66
SDRAM to
3V66
3V66 to PCI PCI to APIC
USB & DOT
Offset
5.0 ns
5.0ns
0.0 ns
1.5–3.5 ns
500 ps
0.0 ns
1.0 ns
Async
N/A
Tolerance
500 ps
500 ps
500 ps
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 133-MHz
SDRAM 100-MHz
3V66 66-MHz
PCI 33-MHz
APIC33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 3. Group Offset Waveforms (133-MHz CPU/100-MHz SDRAM Clock)
Table 5. 133 MHz/SDRAM 100 MHz Group Timing Relationships and Tolerances
CPU to
SDRAM to
3V66
SDRAM CPU to 3V66
3V66 to PCI
1.5–3.5 ns
500 ps
PCI to APIC
0.0 ns
USB & DOT
Async
Offset
0.0 ns
500 ps
0.0 ns
0.0 ns
Tolerance
500 ps
500 ps
1.0 ns
N/A
Power-Down Control
0 ns
10 ns
20 ns
30 ns
40 ns
Cycle Repeats
CPU 133-MHz
SDRAM 133-MHz
3V66 66-MHz
PCI 33-MHz
APIC33-MHz
REF 14.318-MHz
USB 48-MHz
DOT 48-MHz
Figure 4. Group Offset Waveforms (133-MHz CPU/133-MHz SDRAM Clock)
5
W224B
Table 6. 133 MHz/SDRAM Test Mode Group Timing Relationships and Tolerance
CPU to
SDRAM to
3V66
SDRAM CPU to 3V66
3V66 to PCI
1.5–3.5 ns
500 ps
PCI to APIC
0.0 ns
USB& DOT
Offset
3.75 ns
500 ps
0.0 ns
3.75 ns
500 ps
Async
N/A
Tolerance
500 ps
1.0 ns
W224 provides one PWR_DWN# signal to place the device in low-power mode. In low-power mode, the PLLs are turned off and
all clock outputs are driven LOW.
0ns
25ns
50ns
75ns
Center
1
2
VCO Internal
CPU 100MHz
3V66 66MHz
PCI 33MHz
APIC 33MHz
PwrDwn
SDRAM 100MHz
REF 14.318MHz
USB 48MHz
Figure 5. W224 PWR_DWN# Timing Diagram[7, 8, 9, 10]
Table 7. W224 Maximum Allowed Current
Max. 2.5V supply consumption
Max. discrete cap loads,
VDDQ2 = 2.625V
Max. 3.3V supply consumption
Max. discrete cap loads
VDDQ3 = 3.465V
W224
Condition
All static inputs = VDDQ3 or VSS
All static inputs = VDDQ3 or VSS
Powerdown Mode
(PWR_DWN# = 0)
< 1 mA
60 mA
75 mA
90 mA
< 1 mA
160 mA
160 mA
160 mA
Full Active 66 MHz
FS1:0 = 00 (PWR_DWN# =1)
Full Active 100 MHz
FS1:0 = 01 (PWR_DWN# =1)
Full Active 133 MHz
FS1:0 = 11 (PWR_DWN# =1)
Notes:
7. Once the PWR_DWN# signal is sampled LOW for two consecutive rising edges of CPU, clocks of interest will be held LOW on the next HIGH-to-LOW transition.
8. PWR_DWN# is an asynchronous input and metastable conditions could exist. This signal is synchronized inside W224.
9. The shaded sections on the SDRAM, REF, and USB clocks indicate “Don’t Care” states.
10. Diagrams shown with respect to 100 MHz. Similar operation when CPU is 66 MHz.
6
W224B
Where P is the percentage of deviation and F is the frequency
in MHz where the reduction is measured.
Spread Spectrum Frequency Timing
Generation
The output clock is modulated with a waveform depicted in
Figure 7. This waveform, as discussed in “Spread Spectrum
Clock Generation for the Reduction of Radiated Emissions” by
Bush, Fessler, and Hardin, produces the maximum reduction
in the amplitude of radiated electromagnetic emissions. The
deviation selected for this chip is –0.5% or –1.0% of the select-
ed frequency. Figure 7 details the Cypress spreading pattern.
Cypress does offer options with more spread and greater EMI
reduction. Contact your local Sales representative for details
on these devices.
The device generates a clock that is frequency modulated in
order to increase the bandwidth that it occupies. By increasing
the bandwidth of the fundamental and its harmonics, the am-
plitudes of the radiated electromagnetic emissions are re-
duced. This effect is depicted in Figure 6.
As shown in Figure 6, a harmonic of a modulated clock has a
much lower amplitude than that of an unmodulated signal. The
reduction in amplitude is dependent on the harmonic number
and the frequency deviation or spread. The equation for the
reduction is:
Spread Spectrum clocking is activated or deactivated by se-
lecting the appropriate value for bit 3 in data byte 0 of the SM-
Bus data stream. Refer to page 9 for more details.
dB = 6.5 + 9*log10(P) + 9*log10(F)
EMI Reduction
Spread
Non-
Spread
Spectrum
Spectrum
Enabled
Figure 6. Clock Harmonic with and without SSCG Modulation Frequency Domain Representation
MAX.
MIN.
Figure 7. Typical Modulation Profile
7
W224B
1 bit
7 bits
1
1
8 bits
1
Start bit
Slave Address
R/W
Ack
Command Code
Ack
Byte Count = N
Ack
1 bit
Data Byte 1
8 bits
Ack
Data Byte 2
8 bits
Ack
1
...
Data Byte N
8 bits
Ack
1
Stop
1
1
Figure 8. An Example of a Block Write[11]
Serial Data Interface
the number 20 (14h), followed by the 20 bytes of data. The byte
count may not be 0. A block write command is allowed to trans-
fer a maximum of 32 data bytes. The slave receiver address
for W224 is 11010010. Figure 8 shows an example of a block
write.
The W224 features a two-pin, serial data interface that can be
used to configure internal register settings that control partic-
ular device functions.
Data Protocol
The command code and the byte count bytes are required as
the first two bytes of any transfer. W224 expects a command
code of 0000 0000. The byte count byte is the number of ad-
ditional bytes required for the transfer, not counting the com-
mand code and byte count bytes. Additionally, the byte count
byte is required to be a minimum of 1 byte and a maximum of
32 bytes to satisfy the above requirement. Table 8 shows an
example of a possible byte count value.
The clock driver serial protocol accepts only block writes from
the controller. The bytes must be accessed in sequential order
from lowest to highest byte with the ability to stop after any
complete byte has been transferred. Indexed bytes are not al-
lowed.
A block write begins with a slave address and a write condition.
After the command code the core logic issues a byte count
which describes how many more bytes will follow in the mes-
sage. If the host had 20 bytes to send, the first byte would be
A transfer is considered valid after the acknowledge bit corre-
sponding to the byte count is read by the controller.
Table 8. Example of Possible Byte Count Value
Byte Count Byte
Notes
MSB
0000
0000
0000
0000
0000
0000
0000
0000
0010
LSB
0000
0001
0010
0011
0100
0101
0110
0111
0000
Not allowed. Must have at least one byte.
Data for functional and frequency select register (currently byte 0 in spec)
Writes first two bytes of data (byte 0 then byte 1)
Writes first three bytes (byte 0, 1, 2 in order)
Writes first four bytes (byte 0, 1, 2, 3 in order)
Writes first five bytes (byte 0, 1, 2, 3, 4 in order)
Writes first six bytes (byte 0, 1, 2, 3, 4, 5 in order)
Writes first seven bytes (byte 0, 1, 2, 3, 4, 5, 6 in order)
Max. byte count supported = 32
Note:
11. The acknowledgment bit is returned by the slave/receiver (W224).
8
W224B
W224 Serial Configuration Map
1. The serial bits will be read by the clock driver in the following
order:
2. All unused register bits (reserved and N/A) should be writ-
ten to a “0” level.
Byte 0 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte 1 - Bits 7, 6, 5, 4, 3, 2, 1, 0
Byte N - Bits 7, 6, 5, 4, 3, 2, 1, 0
3. All register bits labeled “Initialize to 0" must be written to
zero during initialization. Failure to do so may result in high-
er than normal operating current.
Byte 0: Control Register (1 = Enable, 0 = Disable)[12]
Bit
Pin#
36
49
50
52
-
Name
Pin Description
(Disabled/Enabled)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
VCH
CPU_F2
CPU_F1
CPU0
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
Spread Spectrum (1 = On/0 = Off) (Active/Inactive)
26
25
--
DOT
(Disabled/Enabled)
(Disabled/Enabled)
(Active/Inactive)
USB
Reserved Drive to ‘0’
Byte 1: Control Register (1 = Enable, 0 = Disable)[12]
Bit
Pin#
--
Name
Reserved Drive to ‘0’
Reserved Drive to ‘0’
SDRAM5
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
(Active/Inactive)
--
(Active/Inactive)
39
40
42
43
45
46
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
SDRAM4
SDRAM3
SDRAM2
SDRAM1
SDRAM0
Byte 2: Control Register (1 = Enable, 0 = Disable)[12]
Bit
Pin#
9
Name
Pin Description
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
3V66_AGP
3V66_1
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
((Active/Inactive)
8
7
3V66_0
--
Reserved Drive to ‘0’
Reserved Drive to ‘0’
Reserved Drive to ‘0’
Reserved Drive to ‘0’
Reserved Drive to ‘0’
--
--
--
--
Note:
12. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be configured at power-on and are not expected to be
configured during the normal modes of operation.
9
W224B
Byte 3: Control Register (1 = Enable, 0 = Disable)
Bit
Pin#
-
Name
Reserved Drive to ’0’
Pin Description
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
20
19
18
16
15
13
--
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Disabled/Enabled)
(Active/Inactive)
SDRAM 133 MHz Mode Enable
Default is Disabled = ‘0’, Enabled = ‘1’
Byte 4: Control Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Pin Description
Bit 7
36
VCH_CLK SSC Mode Enable
Default is Disabled = ‘0’
(Disabled/Enabled)
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
-
Byte 5: Control Register (1 = Enable, 0 = Disable)
Bit
Pin#
Name
Reserved Drive to’0’
Pin Description
(Active/Inactive)
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
-
-
-
-
-
-
SpreadSpectrumandOverclockingMode (Active/Inactive)
Select. See Table 9
(Active/Inactive)
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to ’0’
Reserved Drive to’0’
Reserved Drive to’0’
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
(Active/Inactive)
-
Byte 5 has been provided as an optional register to enable a
greater degree of spread spectrum and overclocking perfor-
mance for all PLL1 outputs. (CPU, SDRAM, DCLK, APIC, PCI,
3V66 and VCH_CLK)
programming both bits 5 and 6 to ‘1.’ The part will enter this
mode irrespective of pin 33, TEST#.
It is not necessary to access Byte 5 if these additional features
are not implemented. All outputs will default to 0% overclock-
ing upon power up, with either 0% or –0.5% spread spectrum.
(Spread spectrum ON/OFF remains under Byte 0, bit 3 con-
trol). Note that 10% overclocking can only be enabled with
Spread Spectrum turned OFF.
By enabling Byte 5, (bits 5 and 6) spread spectrum can be
increased to –1.0% and /or overclocking of either 5% or 10%
can be enabled. Although the default values are ‘0’ for all bits,
the part can be placed into either Three-State or Test Mode by
10
W224B
Table 9. Spread Spectrum and Overclocking Mode Select[13]
Byte 0
Bit 3
Byte 5
SS%
Overclock%
Description and Comments
Bit 5
0
Bit 6
0
–0.5%
0%
0%
5%[13]
5%[13]
0%
10%[13]
5%[13]
No overclocking
No overclocking
Spread
Spectrum
ON
0
1
–1.0%
1
0
–0.5%
1
1
–1.0%
0
0
-
-
-
Spread
Spectrum
OFF
0
1
1
0
1
1
Three-state or Test Mode Mode determined by FS0 (see Table 1)
Note:
13. Overclocking not tested; characterized at room temperature only. Base Frequency determined through hardware select pins, FS0 & FS1.
11
W224B
DC Electrical Characteristics
Absolute Maximum DC Power Supply
Parameter
Description
Min.
–0.5
–0.5
–0.5
–65
Max.
4.6
Unit
V
VDD3
VDDQ2
VDDQ3
TS
3.3V Core Supply Voltage
2.5V I/O Supply Voltage
3.6
V
3.3V Supply Voltage
Storage Temperature
4.6
V
150
°C
Absolute Maximum DC I/O
Parameter
Description
Min.
–0.5
–0.5
2000
Max.
Unit
V
Vih3
3.3V Input High Voltage
4.6
Vil3
3.3V Input Low Voltage
Input ESD Protection
V
ESD prot.
V
DC Operating Requirements
Parameter
Description
Condition
3.3V ±5%
3.3V ±5%
2.5V ±5%
Min.
Max.
Unit
V
VDD3
3.3V Core Supply Voltage
3.3V I/O Supply Voltage
2.5V I/O Supply Voltage
3.135
3.135
2.375
3.465
3.465
2.625
VDDQ3
V
VDDQ2
V
VDD3 = 3.3V±5%
Vih3
3.3V Input High Voltage
3.3V Input Low Voltage
Input Leakage Current[14]
VDD3
2.0
VSS – 0.3
–5
VDD + 0.3
0.8
V
V
Vil3
Iil
0<Vin<VDD3
+5
µA
VDDQ2 = 2.5V±5%
Voh2
2.5V Output High Voltage
2.5V Output Low Voltage
Ioh = (–1 mA)
Iol = (1 mA)
2.0
2.4
2.4
V
V
Vol2
0.4
0.4
VDDQ3 = 3.3V±5%
Voh3
3.3V Output High Voltage
3.3V Output Low Voltage
Ioh = (–1 mA)
Iol = (1 mA)
V
V
Vol3
VDDQ3 = 3.3V±5%
Vpoh3
PCI Bus Output High Voltage
PCI Bus Output Low Voltage
Ioh = (–1 mA)
Iol = (1 mA)
V
V
Vpol3
0.55
Cin
Input Pin Capacitance
Xtal Pin Capacitance
Output Pin Capacitance
Pin Inductance
5
22.5
6
pF
pF
pF
nH
°C
Cxtal
Cout
Lpin
13.5
0
0
7
Ta
Ambient Temperature
No Airflow
70
Note:
14. Input Leakage Current does not include inputs with pull-up or pull-down resistors.
12
W224B
AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V ±5%, VDDQ2= 2.5V ±5%
fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[15]
AC Electrical Characteristics
66.6-MHz Host
100-MHz Host
133-MHz Host
Parameter
TPeriod
THIGH
Description
Host/CPUCLK Period
Min.
15.0
5.2
Max.
15.5
N/A
N/A
1.6
Min.
10.0
3.0
Max.
10.5
N/A
N/A
1.6
Min.
7.5
Max.
8.0
Unit Notes
ns
ns
ns
ns
ns
15
16
17
18
18
Host/CPUCLK High Time
Host/CPUCLK Low Time
Host/CPUCLK Rise Time
Host/CPUCLK Fall Time
1.87
1.67
0.4
N/A
N/A
1.6
TLOW
5.0
2.8
TRISE
0.4
0.4
TFALL
0.4
1.6
0.4
1.6
0.4
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
SDRAM CLK Period (100-MHz)
SDRAM CLK High Time (100-MHz)
SDRAM CLK Low Time (100-MHz)
SDRAM CLK Rise Time (100-MHz)
SDRAM CLK Fall Time (100-MHz)
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
10.0
3.0
2.8
0.4
0.4
10.5
N/A
N/A
1.6
ns
ns
ns
ns
ns
15
16
17
18
18
1.6
1.6
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
APIC 33-MHz CLK Period
APIC 33-MHz CLK High Time
APIC 33-MHz CLK Low Time
APIC CLK Rise Time
30.0
12.0
12.0
0.4
N/A
N/A
N/A
1.6
30.0
12.0
12.0
0.4
N/A
N/A
N/A
1.6
30.0
12.0
12.0
0.4
N/A
N/A
N/A
1.6
ns
ns
ns
ns
ns
15
16
17
18
18
APIC CLK Fall Time
0.4
1.6
0.4
1.6
0.4
1.6
TPeriod
THIGH
TLOW
TRISE
TFALL
3V66 CLK Period
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
15.0
5.25
5.05
0.5
16.0
N/A
N/A
2.0
ns
ns
ns
ns
ns
15
16
17
18
18
3V66 CLK High Time
3V66 CLK Low Time
3V66 CLK Rise Time
3V66 CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
TPeriod
THIGH
TLOW
TRISE
TFALL
PCI CLK Period
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
30.0
12.0
12.0
0.5
N/A
N/A
N/A
2.0
15
16
17
18
18
PCI CLK High Time
PCI CLK Low Time
PCI CLK Rise Time
PCI CLK Fall Time
0.5
2.0
0.5
2.0
0.5
2.0
tpZL, tpZH
tpLZ, tpZH
Output Enable Delay (All outputs)
Output Disable Delay (All outputs)
All Clock Stabilization from Power-Up
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
1.0
1.0
10.0
10.0
3
ns
ns
tstable
ms 19
Notes:
15. Period, jitter, offset, and skew measured on rising edge at 1.25 for 2.5V clocks and at 1.5V for 3.3V clocks.
16. THIGH is measured at 2.0V for 2.5V outputs, 2.4V for 3.3V outputs.
17. TLOW is measured at 0.4V for all outputs.
18. TRISE and TFALL are measured as a transition through the threshold region Vol = 0.4V and Voh = 2.0V (1 mA) JEDEC specification for 2.5V outputs and VOL
= 0.4V and VOH = 2.4V for 3.3V outputs.
19. The time specified is measured from when VDDQ3 achieves its nominal operating level (typical condition VDDQ3 = 3.3V) until the frequency output is stable
and operating within specification.
13
W224B
Group Skew and Jitter Limits
Skew, Jitter
Output Group
CPU
Pin-Pin Skew Max.
Cycle-Cycle Jitter
250 ps
Duty Cycle
45/55
Nom Vdd
2.5V
Measure Point
1.25V
1.5V
150 ps
250 ps
250 ps
N/A
SDRAM
APIC
250 ps
45/55
3.3V
500 ps
45/55
2.5V
1.25V
1.5V
48MHz
3V66
500 ps
45/55
3.3V
175 ps
500 ps
N/A
500 ps
45/55
3.3V
1.5V
PCI
500 ps
45/55
3.3V
1.5V
REF
1000 ps
250 ps
45/55
3.3V
1.5V
VCH_CLK
N/A
45/55
3.3V
1.5V
Test Point
Output
Buffer
Test Load
Clock Output Wave
TPERIOD
Duty Cycle
THIGH
2.0
1.25
2.5V Clocking
Interface
0.4
TLOW
TRISE
TFALL
TPERIOD
Duty Cycle
THIGH
2.4
1.5
0.4
3.3V Clocking
Interface
TLOW
TRISE
TFALL
Figure 9. Output Buffer
Ordering Information
Package
Name
Ordering Code
Package Type
W224B
H
X
56-pin SSOP (7.5 mm)
56-pin TSSOP (6.1 mm)
Document #: 38-00926-**
14
W224B
Layout Example
+2.5V Supply
FB
+3.3V Supply
FB
VDDQ2
VDDQ3
10
µF
0.005
µ
F C2
10
µF
0.005
µF
C1
C3
C4
G
G
G
G
G
V
1
56
G
G
2
55
54
53
G
V
G
3
4
G
5
52
G
V
G
G
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
G
G
V
G
G
G
V
G
G
G
G
G
V
G
G
V
G
G
G
G
V
G
V
G
VDDQ3
10
Ω
PLL2
G
G
C5
C6
G
G
FB = Dale ILB1206 - 300 (300
Ceramic Caps: C1, C3 & C5 = 10–22
G = VIA to GND plane layer
V =VIA to respective supply plane layer
Ω
@ 100 MHz)
µF
C2 & C4 = 0.005
µF C6 = 0.1 µF
Note: Each supply plane or strip should have a ferrite bead and capacitors
15
W224B
Package Diagram
56-Pin Thin Shrink Small Outline Package (TSSOP, 6.1 mm)
4
B
1.00
0.00
0.05
1.00 DIA. DEEP
C
3
2
1
1
2
3
H/2
E/2
1.00
C
E
H
8
L
0.20
0.20
H
C
A-B
A-B
D
D
N
N
7
D
4
SEE
DETAIL "A"
e/2
X = A AND B
X
X = A AND B
A
4
X
TOP VIEW
END VIEW
BOTTOM VIEW
EVEN LEAD SIDES
TOPVIEW
ODD LEAD SIDES
TOPVIEW
bbb
M
C
A-B
D
b
9
SEE DETAIL 'B'
b
A2
0.05
C
b1
A
C
WITH PLATING
C
H
3
aaa
8
e
A1
SEATING
PLANE
c
c1
D
5
SIDE VIEW
BASE METAL
SECTION "C-C"
SCALE: 120/1
(SEE NOTE 10)
0.25
PARTING
LINE
H
SEATING PLANE
L
6
C
C
)
(
OC
DETAIL "B"
(SCALE: 30/1)
DAMBAR PROTRUSION
PACKAGE OUTLINE,
6.10mm BODY, TSSOP
DETAIL 'A'
(SCALE: 30/1)
THIS TABLE FOR 0.50mm PITCH
NOTES:
1. DIE THICKNESS ALLOWABLE IS 0.2790.0127 H
2. DIMENSIONING & TOLERANCES PER ASME. Y14.5M-1994.
S
COMMON
DIMENSIONS
NOM.
NOTE
VARI-
ATIONS
ED
EE
EF*
5
7
Y
M
N
B
D
N
O
O
T
E
L
MIN.
12.40
13.90
16.90
NOM.
12.50
14.00
17.00
MAX.
12.60
14.10
17.10
MIN.
MAX.
1.10
0.15
1.05
3. DATUM PLANE H LOCATED AT MOLD PARTING LINE AND CONCIDENT
WITH LEAD, WHERE LEAD EXITS PLASTIC BODY AT BOTTOM OF PARTING LINE.
48
56
64
A
A1
A2
0.05
0.80
4. DATUMS A-B AND D TO BE DETERMINED WHERE CENTERLINE
BETWEEN LEADS EXITS PLASTIC BODY AT DATUM PLANE H.
1.00
0.10
-
0.20
0.08
-
aaa
b
b1
bbb
c
*DESIGNED BUT NOT TOOLED
0.17
0.17
0.27
0.23
9
5.
"D" & "E" ARE REFERENCE DATUMS AND DO NOT INCLUDE MOLD FLASH OR
PROTRUSIONS, AND ARE MEASURED AT THE BOTTOM PARTING LINE. MOLD
FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.15mm ON D AND 0.25mm
ON E PER SIDE.
0.09
0.09
0.20
0.16
0.127
SEE VARIATIONS
c1
D
6. DIMENSION IS THE LENGTH OF TERMINAL
FOR SOLDERING TO A SUBSTRATE.
7. TERMINAL POSITIONS ARE SHOWN FOR REFERENCE ONLY.
5
5
6.00
6.10
0.50 BSC
8.10 BSC
0.60
6.20
E
e
H
8. FORMED LEADS SHALL BE PLANAR WITH RESPECT TO
ONE ANOTHER WITHIN 0.076mm AT SEATING PLANE.
9. THE LEAD WIDTH DIMENSION DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE
0.08mm TOTAL IN EXCESS OF THE LEAD WIDTH DIMENSION
AT MAXIMUM MATERIAL CONDITION. DAMBAR CANNOT BE
LOCATED ON THE LOWER RADIUS OR THE FOOT. MINIMUM
SPACE BETWEEN PROTRUSIONS AND AN ADJACENT LEAD TO
BE 0.10MM FOR 0.65MM PITCH, 0.08MM FOR 0.50MM PITCH AND
0.07MM FOR 0.40MM PITCH PACKAGES.
0.50
0.75
8
6
7
L
N
SEE VARIATIONS
C
OC
0
ALL DIMENSIONS IN MILLIMETERS
SEE DETAIL 'B' AND SECTION "C-C".
SECTION "C-C" TO BE DETERMINED AT 0.10
TO 0.25 MM FROM THE LEAD TIP.
10.
11. CONTROLLING DIMENSION: MILLIMETERS.
12. THIS PART IS COMPLIANT WITH JEDEC SPECIFICATION
MO-153, VARIATIONS DB, DC, DE, ED, EE, AND FE.
16
W224B
Package Diagram
56-Pin Shrink Small Outline Package (SSOP, 7.5 mm)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.725
Body Height: 0.102
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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