W250-03 [ETC]
Clocks and Buffers ; 时钟和缓冲器\n型号: | W250-03 |
厂家: | ETC |
描述: | Clocks and Buffers
|
文件: | 总12页 (文件大小:123K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
3
PRELIMINARY
W250-03
FTG for VIA Apollo Pro-266
Table 1. Pin Selectable Frequency (continued)
Features
Input Address
CPU,
(MHz)
PCI
(MHz)
Spread
Spectrum
• Maximized EMI Suppression using Cypress’s Spread
Spectrum Technology
• System frequency synthesizer for VIA Apollo Pro-266
• Supports Intel® Pentium® II and Pentium® III class pro-
cessor
• Three copies of CPU output
• Nine copies of PCI output
FS4 FS3 FS2 FS1 FS0
AGP
80.0
75.0
72.5
70.0
68.0
65.0
62.0
66.6
66.6
78.7
66.6
66.8
66.8
76.7
66.8
66.8
66.8
73.3
66.8
70.0
60.0
56.7
78.0
66.6
66.6
75.0
66.6
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
160.0
150.0
145.0
140.0
136.0
130.0
124.0
66.6
40.0
37.5
36.3
35.0
34.0
32.5
31.0
33.3
33.3
39.3
33.3
33.4
33.4
38.3
33.4
33.4
33.4
36.7
33.4
35.0
30.0
28.3
39.0
33.3
33.3
37.5
33.3
OFF
OFF
OFF
OFF
OFF
• One 48-MHz output for USB
OFF
• One 24-MHz or 48-MHz output for SIO
• Two buffered reference outputs
• Three copies of APIC output
• Supports frequencies up to 200 MHz
• SMBus interface for programming
• Power management control inputs
• Available in 48-pin SSOP
OFF
OFF
100.0
118.0
133.3
66.8
OFF
OFF
OFF
+0.25%
+0.25%
OFF
100.2
115.0
133.6
66.8
Key Specifications
CPU Cycle-to-Cycle Jitter:................................................ 250 ps
CPU to CPU Output Skew:............................................... 175 ps
PCI Cycle to Cycle Jitter:.................................................. 500 ps
PCI to PCI Output Skew:.................................................. 500 ps
+0.25%
+0.5%
+0.5%
OFF
100.2
110.0
133.6
105.0
90.0
+0.5%
OFF
Table 1. Pin Selectable Frequency
Input Address
OFF
CPU,
PCI
Spread
FS4 FS3 FS2 FS1 FS0
(MHz)
AGP
66.6
63.3
60.0
56.7
83.0
(MHz)
Spectrum
85.0
OFF
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
0
0
1
0
1
0
200.0
190.0
180.0
170.0
166.0
33.3
31.7
30.0
28.3
41.5
OFF
OFF
OFF
OFF
OFF
78.0
OFF
66.6
-0.5%
-0.5%
OFF
100.0
75.0
133.3
-0.5%
Pin Configuration[1]
Block Diagram
VDD_REF
REF0
VDD_REF
GND_REF
X1
48
REF0
1
REF1/FS4
X1
X2
XTAL
OSC
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
REF1/FS4*
VDD_APIC
APIC0
2
3
VDD_APIC
PLL Ref Freq
X2
4
APIC0:2
VDD_AGP
VDD_48 MHz
FS3*/48 MHz
FS2*/24_48 MHz
GND_48 MHz
PCI_F
5
APIC1
DIV
DIV
6
GND_APIC
APIC2
7
AGP0:2
8
VDD_CPU
GND_CPU
CPU1
CPU_STOP#
VDD_CPU
9
PCI1
PCI2
GND_PCI
PCI3
PCI4
VDD_PCI
PCI5
PCI6
PCI7
GND_PCI
PCI8
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
PWR_DWN#
FS0:1
CPU2
VDD_CPU
GND_CPU
CPU3
Stop
Clock
CPU1:3
PLL 1
Control
VDD_PCI
PCI_F
CPU_STOP#*
PCI_STOP#*
PWR_DWN#*
VDD_CORE
GND_CORE
SDATA
SCLK
AGP2
AGP1
GND_AGP
÷2,3,4
PCI1:8
Stop
Clock
PCI_STOP#
*FS1
*FS0
AGP0
VDD_AGP
Control
SDATA
SCLK
SMBus
Logic
VDD_48 MHz
48MHz/FS3
Note:
1. Signals marked with ‘*’ have internal pull-up resistors.
PLL2
÷2
24_48MHz/FS2
Intel and Pentium are registered trademarks of Intel Corporation.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Document #: 38-07254 Rev. *A
Revised December 14, 2002
PRELIMINARY
W250-03
Pin Definitions
Pin
Type
Pin Name
Pin No.
Pin Description
CPU1:3
39, 38, 35
O
CPU Clock Output: Frequency is set by the FS0:4 input or through serial input interface.
The CPU1:3 output are gated by the CLK_STOP# input.
CPU_STOP#*
PCI1:8
34
I
CPU Output Control: 3.3V LVTTL compatible input that stop CPU1:3 clocks.
10, 11, 13,
14, 16, 17,
18, 20
O
PCI Clock Outputs 1 through 8: Frequency is set by FS0:4 inputs or through serial input
interface, see Table 1 and Table 5 for details. Output voltage swing is controlled by voltage
applied to VDD_PCI.
PCI_STOP#*
PCI_F
33
9
O
O
PCI_STOP# Input: 3.3V LVTTL compatible input that stops PCI1:8.
Free-Running PCI Clock Output: Output voltage swing is controlled by the voltage
applied to VDD_PCI. See Table 1. and Table 5. for detailed frequency information.
PWR_DWN#*
APIC0:2
32
45, 44, 42
6
I
PWR_DWN# Input: LVTTL-compatible input that places the device in power-down mode
when held LOW.
O
APIC Clock Output: APIC clock outputs. The output voltage swing is controlled by
VDD_APIC.
48MHz/FS3*
I/O 48-MHz Output/Frequency Select 3: 48 MHz is provided in normal operation. In stan-
dard PC systems, this output can be used as the reference for the Universal Serial Bus
host controller. This pin also serves as a power-on strap option to determine device
operating frequency as described in Table 1.
24_48MHz/
FS2*
7
I/O 24_48-MHz Output/Frequency Select 2: In standard PC systems, this output can be
used as the clock input for a Super I/O chip. The output frequency is controlled by Con-
figuration Byte 3 bit[6]. The default output frequency is 24 MHz. This pin also serves as
a power-on strap option to determine device operating frequency as described in Table 1.
REF1/FS4*
47
I/O Reference Clock Output 1/Frequency Select 4: 3.3V 14.318-MHz output clock. This
pin also serves as a power-on strap option to determine device operating frequency as
described in Table 1. Upon power-up, FS4 input will be latched which will set clock fre-
quencies as described in Table 1.
REF0
SCLK
SDATA
X1
48
28
29
3
O
I
Reference Clock Output 0: 3.3V 14.318 MHz output clock.
Clock pin for serial interface circuitry.
I/O Data pin for serial interface circuitry.
I
Crystal Connection or External Reference Frequency Input: This pin has dual func-
tions. It can be used as an external 14.318-MHz crystal connection or as an external
reference frequency input.
X2
4
I
I
Crystal Connection: An input connection for an external 14.318-MHz crystal. If using an
external reference, this pin must be left unconnected.
FS0,FS1
22, 21
FS0, FS1 Inputs: Latched frequency select inputs. These latched input serve as a power-
on strap option to determine device operating frequency as described in Table 1.
AGP0:2
23, 26, 27
O
P
AGP Outputs: Output frequency is set by FS0:4 inputs or through serial interface.
VDD_REF,
VDD_48MHz,
VDD_PCI,
1, 5,15, 24,
31
Power Connection: Power supply for core logic, PLL circuitry, PCI outputs, reference
outputs, 48-MHz output, and 24_48-MHz output, connect to 3.3V supply.
VDD_AGP,
VDD_CORE
VDD_CPU,
VDD_APIC
41, 46, 37
P
Power Connection: Power supply for APIC and CPU1 output buffers, connect to 2.5V.
Ground Connections: Connect all ground pins to the common system ground plane.
GND_REF,
2, 8, 12, 19,
G
GND_48MHz, 25, 30, 36,
GND_PCI,
GND_AGP,
GND_CORE,
GND_CPU,
GND_APIC
40, 43
Document #: 38-07254 Rev. *A
Page 2 of 12
PRELIMINARY
W250-03
changes are normally made upon system initialization, if any
are required. The interface can also be used during system
operation for power management functions. Table 2 summa-
rizes the control functions of the serial data interface.
Serial Data Interface
The serial data interface can be used to configure internal reg-
ister settings that control particular device functions. Upon
power-up, the W250-03 initializes with default register set-
tings, therefore the use of this serial data interface is optional.
The serial interface is write-only (to the clock chip) and is the
dedicated function of device pins SDATA and SCLOCK. In
motherboard applications, SDATA and SCLOCK are typically
driven by two logic outputs of the chipset. Clock device register
Operation
Data is written to the W250-03 in eleven bytes of eight bits
each. Bytes are written in the order shown in Table 3.
Table 2. Serial Data Interface Control Functions Summary
Control Function
Description
Common Application
Clock Output Disable
Any individual clock output(s) can be disabled. Dis- Unused outputs are disabled to reduce EMI
abled outputs are actively held LOW.
and system power. Examples are clock out-
puts to unused PCI slots.
CPU Clock Frequency
Selection
Provides CPU/PCI frequency selections through
software. Frequency is changed in a smooth and
controlled fashion.
For alternate microprocessors and power
management options. Smooth frequency
transition allows CPU frequency change un-
der normal system operation.
Spread Spectrum
Enabling
Enables or disables spread spectrum clocking.
Puts clock output into a high impedance state.
For EMI reduction.
Output Three-state
(Reserved)
Production PCB testing.
Reserved function for future device revision or pro- No user application. Register bit must be writ-
duction device testing.
ten as 0.
Table 3. Byte Writing Sequence
Byte Sequence
Byte Name
Bit Sequence
Byte Description
1
Slave Address 11010010
Commands the W250-03 to accept the bits in Data Bytes 0–6 for internal
register configuration. Since other devices may exist on the same com-
mon serial data bus, it is necessary to have a specific slave address for
each potential receiver. The slave receiver address for the W250-03 is
11010010. Register setting will not be made if the Slave Address is not
correct (or is for an alternate slave receiver).
2
3
Command
Code
Don’t Care
Don’t Care
Unused by the W250-03, therefore bit values are ignored (“don’t care”).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Command Code Byte is part of the standard serial
communication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
Byte Count
Unused by the W250-03, therefore bit values are ignored (“don’t care”).
This byte must be included in the data write sequence to maintain proper
byte allocation. The Byte Count Byte is part of the standard serial com-
munication protocol and may be used when writing to another ad-
dressed slave receiver on the serial data bus.
4
5
Data Byte 0
Data Byte 1
Data Byte 2
Data Byte 3
Data Byte 4
Data Byte 5
Data Byte 6
Data Byte 7
Refer to Table 4 The data bits in Data Bytes 0–7 set internal W250-03 registers that
control device operation. The data bits are only accepted when the Ad-
dress Byte bit sequence is 11010010, as noted above. For description
of bit control functions, refer to Table 4, Data Byte Serial Configuration
Map.
6
7
8
9
10
11
Document #: 38-07254 Rev. *A
Page 3 of 12
PRELIMINARY
W250-03
Writing Data Bytes
7. Table 4 gives the bit formats for registers located in Data
Bytes 0–7.
Each bit in Data Bytes 0–7 controls a particular device function
except for the “reserved” bits which must be written as a logic
0. Bits are written MSB (most significant bit) first, which is bit
Table 5 details additional frequency selections that are avail-
able through the serial data interface.
Table 4. Data Bytes 0–7 Serial Configuration Map
Affected Pin
Bit Control
Bit(s) Pin No.
Data Byte 0
Pin Name
Control Function
0
1
Default
7
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
SEL_2
--
--
0
0
0
0
0
1
0
0
6
See Table 5
See Table 5
See Table 5
5
SEL_1
4
SEL_0
3
Hardware/Software Frequency Select
Hardware
See Table 5
See Table 5
Software
2
SEL_4
SEL_3
1
0
Normal
Three-stated
Data Byte 1
7
6
5
4
--
--
--
--
--
--
(Reserved)
--
--
--
--
0
0
0
0
1
1
1
1
(Reserved)
--
(Reserved)
--
--
--
(Reserved)
--
--
3
2
1
0
35
38
39
42
CPU3
CPU2
CPU1
APIC2
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Active
Active
Active
Active
Data Byte 2
7
6
5
4
3
2
1
0
20
PCI8
PCI7
PCI6
PCI5
PCI4
PCI3
PCI2
PCI1
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Clock Output Disable
Low
Low
Low
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
Active
Active
Active
1
1
1
1
1
1
1
1
18
17
16
14
13
11
10
Data Byte 3
7
6
--
--
--
(Reserved)
--
--
0
0
SEL_48MHz SEL 48MHz as the output frequency for
24_48MHz
24 MHz
48 MHz
5
4
3
6
7
9
48MHz
Clock Output Disable
Low
Low
Low
Low
Low
Active
Active
Active
Active
Active
1
1
1
1
1
24_48MHz Clock Output Disable
PCI_F
AGP2
AGP1
Clock Output Disable
Clock Output Disable
Clock Output Disable
2
1
27
26
Document #: 38-07254 Rev. *A
Page 4 of 12
PRELIMINARY
W250-03
Table 4. Data Bytes 0–7 Serial Configuration Map (continued)
Affected Pin
Bit Control
Bit(s) Pin No.
23
Pin Name
Control Function
Clock Output Disable
0
1
Default
0
AGP0
Low
Active
1
Data Byte 4
7
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Data Byte 5
7
6
--
--
--
--
(Reserved)
--
--
--
--
0
0
1
1
0
0
1
1
(Reserved)
5
4
3
2
1
0
44
45
--
APIC1
APIC0
--
Clock Output Disable
Clock Output Disable
(Reserved)
Low
Low
--
Active
Active
--
--
--
(Reserved)
--
--
47
48
REF1
REF0
Clock Output Disable
Clock Output Disable
Low
Low
Active
Active
Data Byte 6
7
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
0
0
0
6
5
4
3
2
1
0
Data Byte 7
7
6
5
4
3
2
1
0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
(Reserved)
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
0
0
0
0
0
0
0
0
Document #: 38-07254 Rev. *A
Page 5 of 12
PRELIMINARY
W250-03
Table 5. Additional Frequency Selections through Serial Data Interface Data Bytes
Input Conditions
Output Frequency
Data Byte 0, Bit 3 = 1
Bit 2
Bit 1
Bit 6
Bit 5
Bit 4
SEL_4
SEL_3
SEL_2
SEL_1
SEL_0
CPU
200.0
190.0
180.0
170.0
166.0
160.0
150.0
145.0
140.0
136.0
130.0
124.0
66.6
AGP
66.6
63.3
60.0
56.7
83.0
80.0
75.0
72.5
70.0
68.0
65.0
62.0
66.6
66.6
78.7
66.6
66.8
66.8
76.7
66.8
66.8
66.8
73.3
66.8
70.0
60.0
56.7
78.0
66.6
66.6
75.0
66.6
PCI
33.3
31.7
30.0
28.3
41.5
40.0
37.5
36.3
35.0
34.0
32.5
31.0
33.3
33.3
39.3
33.3
33.4
33.4
38.3
33.4
33.4
33.4
36.7
33.4
35.0
30.0
28.3
39.0
33.3
33.3
37.5
33.3
Spread Spectrum
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
OFF
100.0
118.0
133.3
66.8
OFF
OFF
OFF
±0.25%
±0.25%
OFF
100.2
115.0
133.6
66.8
±0.25%
±0.5%
±0.5%
OFF
100.2
110.0
133.6
105.0
90.0
±0.5%
OFF
OFF
85.0
OFF
78.0
OFF
66.6
–0.5%
–0.5%
OFF
100.0
75.0
133.3
–0.5%
Document #: 38-07254 Rev. *A
Page 6 of 12
PRELIMINARY
W250-03
Absolute Maximum Ratings [2]
Stresses greater than those listed in this table may cause per-
manent damage to the device. These represent a stress rating
above those specified in the operating sections of this specifi-
cation is not implied. Maximum conditions for extended peri-
ods may affect reliability.
only. Operation of the device at these or any other conditions
.
Parameter
VDD, VIN
Description
Voltage on any pin with respect to GND
Storage Temperature
Rating
–0.5 to +7.0
–65 to +150
–55 to +125
0 to +70
Unit
V
TSTG
TB
°C
°C
°C
kV
Ambient Temperature under Bias
Operating Temperature
TA
ESDPROT
Input ESD Protection
2 (min.)
DC Electrical Characteristics: TA = 0°C to +70°C, 3.3V, VDD = 3.3V±5%, 2.5V, VDD = 2.5V±5%
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Supply Current
IDD
3.3V Supply Current
2.5V Supply Current
CPU1:3 = 133 MHz [3]
TBD
TBD
mA
mA
IDD
Logic Inputs
VIL
VIH
IIL
Input Low Voltage
Input High Voltage
Input Low Current[4]
Input High Current[4]
GND – 0.3
0.8
VDD + 0.3
–25
V
V
2.0
µA
µA
IIH
10
Clock Outputs
VOL
VOH
VOH
Output Low Voltage
IOL = 1 mA
50
mV
V
Output High Voltage
IOH = –1 mA
IOH = –1 mA
3.1
2.2
Output High Voltage CPU1:3,
APIC0:2
V
IOL
Output Low Current CPU1:3
VOL = 1.25V
VOL = 1.5V
VOL = 1.5V
VOL = 1.25V
VOL = 1.5V
VOL = 1.5V
VOL = 1.5V
VOH = 1.25V
VOH = 1.5V
VOL = 1.5V
VOH = 1.25V
VOH = 1.5V
VOH = 1.5V
27
20.5
40
40
25
25
25
25
31
40
40
27
25
57
53
85
85
37
37
37
55
55
85
87
44
37
97
139
140
140
76
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
PCI_F, PCI1:8
AGP0:2
APIC 0:2
REF0:1
48 MHz
76
24 MHz
76
IOH
Output High Current CPU1:3
97
PCI_F, PCI1:8
139
140
155
94
AGP0:2
APIC0:2
48 MHz
24 MHz
76
Notes:
2. Multiple Supplies: The voltage on any input or I/O pin cannot exceed the power pin during power-up. Power supply sequencing is NOT required.
3. All clock outputs loaded with 6" 60Ω transmission lines with 22-pF capacitors.
4. Inputs have internal pull-up resistors.
Document #: 38-07254 Rev. *A
Page 7 of 12
PRELIMINARY
W250-03
DC Electrical Characteristics: TA = 0°C to +70°C, 3.3V, VDD = 3.3V±5%, 2.5V, VDD = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input Threshold Voltage[5]
VDDQ3 = 3.3V
1.65
18
V
CLOAD
Load Capacitance, Imposed on
External Crystal[6]
pF
CIN,X1
X1 Input Capacitance[7]
Pin X2 unconnected
Except X1 and X2
28
pF
Pin Capacitance/Inductance
CIN
Input Pin Capacitance
5
6
7
pF
pF
nH
COUT
LIN
Output Pin Capacitance
Input Pin Inductance
AC Electrical Characteristics
TA = 0°C to +70°C, 3.3V, VDD= 3.3V±5%, 2.5V, VDD= 2.5V± 5% fXTL = 14.31818 MHz
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output; Spread Spectrum is disabled.
CPU Clock Outputs (Lump Capacitance Test Load = 20 pF)
CPU = 66.6 MHz
CPU = 100 MHz
CPU = 133 MHz
Test Condition/
Comments
Parameter
Description
Period
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Unit
tP
Measured on rising edge
at 1.25
15
15.5
10
3.0
2.8
1
10.5 7.5
1.87
8.0
ns
ns
tH
tL
tR
tF
tD
tJC
High Time
Low Time
Duration of clock cycle
above 2.0V
5.2
Duration of clock cycle be- 5.0
low 0.4V
1.67
ns
Output Rise
Edge Rate
Measured from 0.4V to
2.0V
1
4
4
4
4
1
1
4
4
V/ns
V/ns
%
OutputFallEdge Measured from 2.0V to
1
1
Rate
0.4V
Duty Cycle
Measured on rising and
falling edge at 1.25V
45
55
250
45
55
250
45
55
250
Jitter,
Cycle-to-Cycle
Measured on rising edge
at 1.25V. Maximum differ-
ence of cycle time be-
ps
tween two adjacent cycles.
tSK
fST
Output Skew
Measured on rising edge
at 1.25V
175
3
175
3
175
3
ps
Frequency
Assumes full supply volt-
age reached within 1 ms
from power-up. Short cy-
cles exist prior to frequen-
cy stabilization.
ms
Stabilization
from Power-up
(cold start)
Zo
AC Output
Impedance
Average value during
switching transition. Used
for determining series ter-
mination value.
20
20
20
Ω
Notes:
5. X1 input threshold voltage (typical) is 3.3V/2.
6. The W250-03 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is
18 pF; this includes typical stray capacitance of short PCB traces to crystal.
7. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
Document #: 38-07254 Rev. *A
Page 8 of 12
PRELIMINARY
W250-03
PCI Clock Outputs, PCI0:5 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Period
Test Condition/Comments
Measured on rising edge at 1.5V
Min.
30
12
12
1
Typ.
Max.
Unit
ns
tP
tH
tL
High Time
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
ns
Low Time
ns
tR
tF
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
V/ns
V/ns
%
Measured from 2.4V to 0.4V
1
tD
tJC
Measured on rising and falling edge at 1.5V
45
55
500
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
ps
difference of cycle time between two adjacent cycles.
tSK
tO
Output Skew
Measured on rising edge at 1.5V
500
4
ps
ns
CPU to PCI Clock Skew Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
1.5
fST
Frequency Stabilization
from Power-up (cold
start)
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
3
ms
Zo
AC Output Impedance
Average value during switching transition. Used for
determining series termination value.
30
Ω
AGP Clock Outputs (Lump Capacitance test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Min.
Typ.
Max. Unit
tP
tH
tL
Period
15
5.25
5.05
1
ns
ns
ns
High Time
Low Time
tR
tF
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
4
4
V/ns
V/ns
%
Measured from 2.4V to 0.4V
1
tD
tJC
Measured on rising and falling edge at 1.5V
45
55
500
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent
cycles.
ps
tSK
fST
Output Skew
Measured on rising edge at 1.5V
250
3
ps
FrequencyStabilizationfrom Assumes full supply voltage reached within 1
Power-up (cold start)
ms
ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value duringswitching transition. Used
for determining series termination value.
30
Ω
APIC Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated from PCI divided by 2
Measured from 0.4V to 2.4V
Min.
Typ.
Max. Unit
f
PCI/2
MHz
tR
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
55
3
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within
ms
Power-up (cold start)
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value duringswitching transition. Used
for determining series termination value.
20
Ω
Document #: 38-07254 Rev. *A
Page 9 of 12
PRELIMINARY
W250-03
REF Clock Outputs (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.4V
Min.
Typ.
Max. Unit
f
14.318
MHz
tR
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
55
3
fST
FrequencyStabilizationfrom Assumes full supply voltage reached within
ms
Power-up (cold start)
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Zo
AC Output Impedance
Average value duringswitching transition. Used
for determining series termination value.
40
Ω
48-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Deviation from 48 MHz
PLL Ratio
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(48.008 – 48)/48
Min.
Typ.
48.008
+167
Max. Unit
MHz
f
fD
ppm
m/n
tR
(14.31818 MHz x 57/17 = 48.008 MHz)
Measured from 0.4V to 2.4V
57/17
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
55
3
fST
Frequency Stabilization
Assumes full supply voltage reached within 1 ms
ms
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
quency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
Ω
24-MHz Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
Frequency, Actual
Deviation from 24 MHz
PLL Ratio
Test Condition/Comments
Determined by PLL divider ratio (see m/n below)
(24.004 – 24)/24
Min.
Typ.
24.004
+167
Max. Unit
MHz
f
fD
ppm
m/n
tR
(14.31818 MHz x 57/34 = 24.004 MHz)
Measured from 0.4V to 2.4V
57/34
Output Rise Edge Rate
Output Fall Edge Rate
Duty Cycle
0.5
0.5
45
2
2
V/ns
V/ns
%
tF
Measured from 2.4V to 0.4V
tD
Measured on rising and falling edge at 1.5V
55
3
fST
Frequency Stabilization
Assumes full supply voltage reached within 1 ms
ms
from Power-up (cold start) from power-up. Short cycles exist prior to fre-
quency stabilization.
Zo
AC Output Impedance
Average value during switching transition. Used
for determining series termination value.
40
Ω
Ordering Information
Package
Name
Ordering Code
Package Type
W250-03
H
48-pin SSOP (300 mils)
Document #: 38-07254 Rev. *A
Page 10 of 12
PRELIMINARY
W250-03
Package Diagram
48-Pin Small Shrink Outline Package (SSOP, 300 mils)
Summary of nominal dimensions in inches:
Body Width: 0.296
Lead Pitch: 0.025
Body Length: 0.625
Body Height: 0.102
Document #: 38-07254 Rev. *A
Page 11 of 12
PRELIMINARY
W250-03
Document Title: W250-03 FTG for VIA Apollo Pro-266
Document Number: 38-07254
Issue
Orig. of
Change
REV.
**
ECN NO.
110519
Date
Description of Change
01/07/02
12/14/02
SZV
RBI
Change from Spec number: 38-01080 to 38-07254
*A
122856
Power up requirements added to Operating Conditions Information
Document #: 38-07254 Rev. *A
Page 12 of 12
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
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