W25M512JVEIQ TR [ETC]
IC FLASH 512M SPI 104MHZ 8WSON;
| 型号： | W25M512JVEIQ TR |
| 厂家： | 
ETC |
| 描述： | IC FLASH 512M SPI 104MHZ 8WSON |
| 文件： | 总91页 (文件大小：1530K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
W25M512JV
Featuring
3V 512M-BIT (2 x 256M-BIT)
SERIAL MCP FLASH MEMORY
With Multi I/O SPI & Concurrent Operations
Publication Release Date: September 06, 2017
- Revision D
W25M512JV
Table of Contents
1.
2.
3.
GENERAL DESCRIPTIONS.............................................................................................................6
FEATURES.......................................................................................................................................6
PACKAGE TYPES AND PIN CONFIGURATIONS ..........................................................................7
3.1
3.2
3.3
3.4
3.5
3.6
Pad Configuration WSON 8x6-mm ......................................................................................7
Pad Description WSON 8x6-mm..........................................................................................7
Pin Configuration SOIC 300-mil ...........................................................................................8
Pin Description SOIC 300-mil...............................................................................................8
Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array).................................................9
Ball Description TFBGA 8x6-mm .........................................................................................9
4.
DEVICE CONFIGURATION & PIN DESCRIPTIONS.....................................................................10
4.1
4.2
4.3
4.4
4.5
Serial MCP (SpiStack® ) Device Configuration ...................................................................10
Chip Select (/CS)................................................................................................................10
Serial Input & Output (DI, DO and IO0, IO1, IO2, IO3) ......................................................10
Serial Clock (CLK)..............................................................................................................10
Reset (/RESET)..................................................................................................................10
5.
6.
SINGLE DIE (W25Q256JV) BLOCK DIAGRAM.............................................................................11
FUNCTIONAL DESCRIPTIONS.....................................................................................................12
6.1
Device Operations..............................................................................................................12
6.1.1 Stacked Die Operations........................................................................................................12
6.1.2 Standard SPI Instructions .....................................................................................................12
6.1.3 Dual & Quad SPI Instructions ...............................................................................................13
6.1.4 3-Byte / 4-Byte Address Modes ............................................................................................13
6.1.5 Software Reset & Hardware /RESET pin..............................................................................13
Write Protection..................................................................................................................14
6.2
7.
STATUS AND CONFIGURATION REGISTERS............................................................................15
7.1
Status Registers .................................................................................................................15
7.1.1 Program/Erase/Write In Progress (BUSY) – Status Only ..................................................15
7.1.2 Write Enable Latch (WEL) – Status Only...........................................................................15
7.1.3 Block Protect Bits (BP3, BP2, BP1, BP0) – Volatile/Non-Volatile Writable........................16
7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable........................................16
7.1.5 Complement Protect (CMP) – Volatile/Non-Volatile Writable ............................................16
7.1.6 Status Register Lock (SRL) – Volatile/Non-Volatile OTP Writable.....................................16
7.1.7 Erase/Program Suspend Status (SUS) – Status Only .......................................................17
7.1.8 Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable...........17
7.1.9 Current Address Mode (ADS) – Status Only .....................................................................17
7.1.10 Power-Up Address Mode (ADP) – Non-Volatile Writable ................................................17
7.1.11 Write Protect Selection (WPS) – Volatile/Non-Volatile Writable ......................................17
7.1.12 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable ..........................18
7.1.13 Reserved Bits – Non Functional ......................................................................................18
7.1.14 Single Die W25Q256JV Status Register Memory Protection (WPS = 0, CMP = 0) ............19
7.1.15 Single Die W25Q256JV Status Register Memory Protection (WPS = 0, CMP = 1) ............20
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W25M512JV
7.1.16 Single Die W25Q256JV Individual Block Memory Protection (WPS=1)..............................21
7.2
Extended Address Register – Volatile Writable Only......................................................22
8.
INSTRUCTIONS.............................................................................................................................23
8.1
Device ID and Instruction Set Tables.................................................................................23
8.1.1 Manufacturer and Device Identification.................................................................................23
8.1.2 Instruction Set Table 1 (Standard Single SPI, 3-Byte Address Mode ADS=0)(1)...................24
8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions, 3-Byte Address Mode ADS=0)...........25
8.1.4 Instruction Set Table 3 (Standard Single SPI, 4-Byte Address Mode ADS=1)(1)...................26
8.1.5 Instruction Set Table 4 (Dual/Quad SPI Instructions, 4-Byte Address Mode ADS=1)...........27
Instruction Descriptions ......................................................................................................29
8.2.1 Software Die Select (C2h) ....................................................................................................29
8.2.2 Write Enable (06h)................................................................................................................30
8.2.3 Write Enable for Volatile Status Register (50h).....................................................................30
8.2.4 Write Disable (04h)...............................................................................................................31
8.2.5 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)...............31
8.2.6 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h) ...............32
8.2.7 Read Extended Address Register (C8h)...............................................................................34
8.2.8 Write Extended Address Register (C5h)...............................................................................35
8.2.9 Enter 4-Byte Address Mode (B7h)........................................................................................36
8.2.10 Exit 4-Byte Address Mode (E9h).........................................................................................36
8.2.11 Read Data (03h) .................................................................................................................37
8.2.12 Read Data with 4-Byte Address (13h).................................................................................38
8.2.13 Fast Read (0Bh) .................................................................................................................39
8.2.14 Fast Read with 4-Byte Address (0Ch).................................................................................40
8.2.16 Fast Read Dual Output (3Bh) .............................................................................................41
8.2.17 Fast Read Dual Output with 4-Byte Address (3Ch) ............................................................42
8.2.18 Fast Read Quad Output (6Bh)............................................................................................43
8.2.19 Fast Read Quad Output with 4-Byte Address (6Ch)...........................................................44
8.2.20 Fast Read Dual I/O (BBh)...................................................................................................45
8.2.21 Fast Read Dual I/O with 4-Byte Address (BCh)..................................................................46
8.2.22 Fast Read Quad I/O (EBh)..................................................................................................47
8.2.23 Fast Read Quad I/O with 4-Byte Address (ECh).................................................................48
8.2.25 Set Burst with Wrap (77h)...................................................................................................49
8.2.26 Page Program (02h) ...........................................................................................................50
8.2.27 Page Program with 4-Byte Address (12h)...........................................................................51
8.2.28 Quad Input Page Program (32h).........................................................................................52
8.2.29 Quad Input Page Program with 4-Byte Address (34h)........................................................53
8.2.30 Sector Erase (20h)..............................................................................................................54
8.2.31 Sector Erase with 4-Byte Address (21h).............................................................................55
8.2.32 32KB Block Erase (52h)......................................................................................................56
8.2.33 64KB Block Erase (D8h).....................................................................................................57
8.2.34 64KB Block Erase with 4-Byte Address (DCh)....................................................................58
8.2.35 Single Die Chip Erase (C7h / 60h)......................................................................................59
8.2.36 Erase / Program Suspend (75h) .........................................................................................60
8.2.37 Erase / Program Resume (7Ah)..........................................................................................61
8.2
Publication Release Date: September 06, 2017
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W25M512JV
8.2.38 Read Device ID (ABh).........................................................................................................62
8.2.39 Read Manufacturer / Device ID (90h) .................................................................................63
8.2.40 Read Manufacturer / Device ID Dual I/O (92h) ...................................................................64
8.2.41 Read Manufacturer / Device ID Quad I/O (94h)..................................................................65
8.2.42 Read Unique ID Number (4Bh)...........................................................................................66
8.2.43 Read JEDEC ID (9Fh) ........................................................................................................67
8.2.44 Read SFDP Register (5Ah).................................................................................................68
8.2.45 Erase Security Registers (44h)...........................................................................................69
8.2.46 Program Security Registers (42h).......................................................................................70
8.2.47 Read Security Registers (48h)............................................................................................71
8.2.48 Individual Block/Sector Lock (36h)......................................................................................72
8.2.49 Individual Block/Sector Unlock (39h) ..................................................................................73
8.2.50 Read Block/Sector Lock (3Dh)............................................................................................74
8.2.51 Global Block/Sector Lock (7Eh)..........................................................................................75
8.2.52 Global Block/Sector Unlock (98h).......................................................................................75
8.2.53 Enable Reset (66h) and Reset Device (99h) ......................................................................76
ELECTRICAL CHARACTERISTICS...............................................................................................77
(1)
9.
9.1
9.2
9.3
9.4
9.5
9.6
9.7
9.8
Absolute Maximum Ratings
..........................................................................................77
Operating Ranges ..............................................................................................................77
Power-up Power-down Timing and Requirements.............................................................78
DC Electrical Characteristics(1) ...........................................................................................79
AC Measurement Conditions .............................................................................................80
AC Electrical Characteristics(4,5) .........................................................................................81
Serial Output Timing...........................................................................................................83
Serial Input Timing..............................................................................................................83
10.
PACKAGE SPECIFICATIONS .......................................................................................................84
10.1 8-Pad WSON 8x6-mm (Package Code E) .........................................................................84
10.2 16-Pin SOIC 300-mil (Package Code F) ............................................................................85
10.3 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 Ball Array)...........................................86
10.4 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 Ball Array)..............................................87
ORDERING INFORMATION ..........................................................................................................88
11.1 Valid Part Numbers and Top Side Marking........................................................................89
REVISION HISTORY......................................................................................................................90
11.
12.
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W25M512JV
Table of Figures
Figure 1a. W25M512JV Pad Assignments, 8-pad WSON 8x6-mm (Package Code E)...............................7
Figure 1b. W25M512JV Pin Assignments, 16-pin SOIC 300-mil (Package Code F) ...................................8
Figure 1c. W25M512JV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code B & C) ......................9
Figure 2a. W25M512JV Device Configuration............................................................................................10
Figure 2b. Single Die W25Q256JV Serial Flash Memory Block Diagram ..................................................11
Figure 2c. W25M512JV Serial Flash Memory Operation Diagram.............................................................12
Figure 3a. Status Register-1 .......................................................................................................................15
Figure 3b. Status Register-2 .......................................................................................................................17
Figure 3c. Status Register-3 .......................................................................................................................18
Figure 3d. Individual Block/Sector Locks (Single Die W25Q256JV) ..........................................................21
Figure 3e. Extended Address Register (Single Die W25Q256JV)..............................................................22
Figure 4. Software Die Select Instruction....................................................................................................29
Figure 5. Write Enable Instruction...............................................................................................................30
Figure 6. Write Enable for Volatile Status Register Instruction...................................................................30
Figure 7. Write Disable Instruction..............................................................................................................31
Figure 8. Read Status Register Instruction.................................................................................................31
Figure 9a. Write Status Register-1/2/3 Instruction......................................................................................32
Figure 9b. Write Status Register-1/2 Instruction.........................................................................................33
Figure 10. Read Extended Address Register Instruction............................................................................34
Figure 11. Write Extended Address Register Instruction............................................................................35
Figure 12. Enter 4-Byte Address Mode instruction .....................................................................................36
Figure 13. Exit 4-Byte Address Mode instruction........................................................................................36
Figure 14. Read Data Instruction ................................................................................................................37
Figure 15. Read Data with 4-Byte Address Instruction...............................................................................38
Figure 16. Fast Read Instruction.................................................................................................................39
Figure 17. Fast Read with 4-Byte Address Instruction ...............................................................................40
Figure 19. Fast Read Dual Output Instruction ............................................................................................41
Figure 20. Fast Read Dual Output with 4-Byte Address Instruction ...........................................................42
Figure 21. Fast Read Quad Output Instruction...........................................................................................43
Figure 22. Fast Read Quad Output with 4-Byte Address Instruction..........................................................44
Figure 23. Fast Read Dual I/O Instruction ..................................................................................................45
Figure 24. Fast Read Dual I/O w/ 4-Byte Address Instruction....................................................................46
Figure 26. Fast Read Quad I/O Instruction.................................................................................................47
Figure 27. Fast Read Quad I/O w/ 4-Byte Address Instruction...................................................................48
Figure 29. Set Burst with Wrap Instruction .................................................................................................49
Figure 30. Page Program Instruction ..........................................................................................................50
Figure 31. Page Program with 4-Byte Address Instruction.........................................................................51
Figure 32. Quad Input Page Program Instruction .......................................................................................52
Figure 33. Quad Input Page Program with 4-Byte Address Instruction......................................................53
Figure 34. Sector Erase Instruction ............................................................................................................54
Figure 35. Sector Erase with 4-Byte Address Instruction ...........................................................................55
Figure 36. 32KB Block Erase Instruction ....................................................................................................56
Publication Release Date: September 06, 2017
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- Revision D
W25M512JV
Figure 37. 64KB Block Erase Instruction ....................................................................................................57
Figure 38. 64KB Block Erase with 4-Byte Address Instruction...................................................................58
Figure 39. Single Die Chip Erase Instruction..............................................................................................59
Figure 40. Erase/Program Suspend Instruction..........................................................................................60
Figure 41. Erase/Program Resume Instruction...........................................................................................61
Figure 42. Read Device ID Instruction........................................................................................................62
Figure 43. Read Manufacturer / Device ID Instruction................................................................................63
Figure 44. Read Manufacturer / Device ID Dual I/O Instruction .................................................................64
Figure 45. Read Manufacturer / Device ID Quad I/O Instruction................................................................65
Figure 46. Read Unique ID Number Instruction..........................................................................................66
Figure 47. Read JEDEC ID Instruction .......................................................................................................67
Figure 48. Read SFDP Register Instruction................................................................................................68
Figure 49. Erase Security Registers Instruction..........................................................................................69
Figure 50. Program Security Registers Instruction .....................................................................................70
Figure 51. Read Security Registers Instruction ..........................................................................................71
Figure 52. Individual Block/Sector Lock Instruction....................................................................................72
Figure 53. Individual Block Unlock Instruction ............................................................................................73
Figure 54. Read Block Lock Instruction ......................................................................................................74
Figure 55. Global Block Lock Instruction ....................................................................................................75
Figure 56. Global Block Unlock Instruction.................................................................................................75
Figure 57. Enable Reset and Reset Instruction Sequence.........................................................................76
Figure 58a. Power-up Timing and Voltage Levels......................................................................................78
Figure 58b. Power-up, Power-Down Requirement.....................................................................................78
Figure 59. AC Measurement I/O Waveform................................................................................................80
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W25M512JV
1. GENERAL DESCRIPTIONS
The W25M512JV (2 x 256M-bit) Serial MCP (Multi Chip Package) Flash memory is based on the popular
W25Q SpiFlas h® series by stacking two individual W25Q256JV die into a standard 8-pin package. It offers
the highest memory density for the low pin-count package, as well as Concurrent Operations in Serial Flash
memory for the first time. The W25M SpiStack® series is ideal for small form factor system designs, and
applications that demand high Program/Erase data throughput.
The SpiStack® product series introduces a new “Software Die Select (C2h)” instruction, and a factory
assigned “Die ID#” for each stacked die. Each W25Q256JV die can be accessed independently even
though the interface is shared. The SpiStack® feature only allows a single die to be Active and have control
of the SPI interface at any given time to avoid bus contention.
The W25M512JV maintains all the SpiFlas h® features and functions, with the support for standard SPI
(Serial Peripheral Interface), Dual I/O SPI, and Quad I/O SPI read operations through the shared SPI
interface: Serial Clock, Chip Select, Serial Data I/O0 (DI), I/O1 (DO), I/O2, and I/O3.
Each W25Q256JV memory array is organized into 131,072 programmable pages of 256-Byte each. Up to
256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups
of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The small 4KB
sectors allow for greater flexibility in applications that require data and parameter storage.
2. FEATURES
New Family of SpiFlas h® Memories
– W25M512JV: 2 x 256M-bit (2 x 32M-Byte)
– Standard SPI: CLK, /CS, DI, DO
– Dual SPI: CLK, /CS, IO0, IO1
Low Power, Wide Temperature Range
– Single 2.7 to 3.6V power supply
– 4mA active current, <20µA standby current
– -40°C to +85°C operating range
– Quad SPI: CLK, /CS, IO0, IO1, IO2, IO3
– 3 or 4-Byte Addressing Mode
Flexible Architecture with 4KB sectors
– Uniform Sector/Block Erase (4K/32K/64K-Byte)
– Program 1 to 256 byte per programmable page
– Program/Erase Suspend & Resume
– Software Die Select (C2h)
– Software & Hardware Reset(1)
High Performance Serial Flash
– 104MHz Standard/Dual/Quad SPI clocks
– 208/416MHz equivalent Dual/Quad SPI
– 50MB/s continuous data transfer rate
– Min. 100K Program-Erase cycles per
sector
Advanced Security Features
– Power Supply Lock-Down and OTP protection
– Top/Bottom, Complement array protection
– Individual Block/Sector array protection
– 64-bit Unique ID for individual die
– Discoverable Parameters (SFDP) Register
– 3 x 256-Byte Security Registers with OTP locks
– Volatile & Non-volatile Status Register Bits
– More than 20-year data retention
Flexible “Concurrent Operations”
– Independent single die access
– Allows “Read while Program/Erase”
– Allows “Multi Die Program/Erase”
– Improves Program/Erase throughput
– Reduces Suspend/Resume activities
Space Efficient Packaging
– 8-pad WSON 8x6-mm
– 16-pin SOIC 300-mil (with /RESET pin)
– 24-ball TFBGA 8x6-mm (with /RESET pin)
– Contact Winbond for other options
Note: 1. Hardware /RESET pin is only available on 16-pin SOIC 300-mil and TFBGA packages.
Publication Release Date: September 06, 2017
- Revision D
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W25M512JV
3. PACKAGE TYPES AND PIN CONFIGURATIONS
W25M512JV is offered in an 8-pad WSON 8x6-mm (package code E), a 16-pin SOIC 300-mil (package
code F) and two 24-ball 8x6-mm TFBGA (package code B & C) packages as shown in Figure 1a-c
respectively. Package diagrams and dimensions are illustrated at the end of this datasheet.
3.1 Pad Configuration WSON 8x6-mm
Top View
/CS
DO (IO1)
IO2
1
2
3
4
8
7
6
5
VCC
IO3
CLK
GND
DI (IO0)
Figure 1a. W25M512JV Pad Assignments, 8-pad WSON 8x6-mm (Package Code E)
3.2 Pad Description WSON 8x6-mm
PAD NO.
PAD NAME
/CS
I/O
I
FUNCTION
1
2
3
4
5
6
7
8
Chip Select Input
DO (IO1)
IO2
I/O
I/O
Data Output (Data Input Output 1)(1)
Data Input Output 2(2)
Ground
GND
DI (IO0)
CLK
I/O
I
Data Input (Data Input Output 0)(1)
Serial Clock Input
IO3
I/O
Data Input Output 3(2)
Power Supply
VCC
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions.
2. IO0 – IO3 are used for Quad SPI instructions.
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W25M512JV
3.3 Pin Configuration SOIC 300-mil
Top View
IO3
VCC
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
CLK
DI (IO0)
NC
/RESET
NC
NC
NC
NC
NC
NC
/CS
GND
IO2
DO (IO1)
Figure 1b. W25M512JV Pin Assignments, 16-pin SOIC 300-mil (Package Code F)
3.4 Pin Description SOIC 300-mil
PIN NO.
PIN NAME
IO3
I/O
FUNCTION
1
2
I/O
Data Input Output 3(2)
Power Supply
Reset Input(3)
No Connect
VCC
3
/RESET
N/C
I
4
5
N/C
No Connect
6
N/C
No Connect
7
/CS
I
Chip Select Input
8
DO (IO1)
IO2
I/O
I/O
Data Output (Data Input Output 1)(1)
Data Input Output 2(2)
Ground
9
10
11
12
13
14
15
16
GND
N/C
No Connect
N/C
No Connect
N/C
No Connect
N/C
No Connect
DI (IO0)
CLK
I/O
I
Data Input (Data Input Output 0)(1)
Serial Clock Input
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions.
2. IO0 – IO3 are used for Quad SPI instructions.
3. The /RESET pin is a dedicated hardware reset pin regardless of device settings or operation states. If the hardware reset function
is not used, this pin can be left floating or connected to VCC in the system.
Publication Release Date: September 06, 2017
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W25M512JV
3.5 Ball Configuration TFBGA 8x6-mm (5x5 or 6x4 Ball Array)
Figure 1c. W25M512JV Ball Assignments, 24-ball TFBGA 8x6-mm (Package Code B & C)
3.6 Ball Description TFBGA 8x6-mm
BALL NO.
PIN NAME
/RESET
CLK
I/O
FUNCTION
A4
B2
I
I
Reset Input(3)
Serial Clock Input
Ground
B3
GND
B4
VCC
Power Supply
Chip Select Input
Data Input Output 2(2)
C2
/CS
I
C4
IO2
I/O
I/O
I/O
I/O
D2
DO (IO1)
DI (IO0)
IO3
Data Output (Data Input Output 1)(1)
Data Input (Data Input Output 0)(1)
Data Input Output 3(2)
D3
D4
Multiple
NC
No Connect
Notes:
1. IO0 and IO1 are used for Standard and Dual SPI instructions.
2. IO0 – IO3 are used for Quad SPI instructions.
3. The /RESET pin is a dedicated hardware reset pin regardless of device settings or operation states. If the hardware reset function
is not used, this pin can be left floating or connected to VCC in the system.
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W25M512JV
4. DEVICE CONFIGURATION & PIN DESCRIPTIONS
4.1 Serial MCP (SpiStack® ) Device Configuration
W25Q256JV
W25Q256JV
IO0
IO1
IO2
IO3
/CS
CLK
/RESET*
Die #0
W25M512JV (SpiStack® )
* /RESET pin is available
on SOIC-16 & TFBGA packages
Figure 2a. W25M512JV Device Configuration
All signal pins are shared by the stacked dies within the package. Each die is assigned a “Die ID#” in the
factory. Only a single die is active at any given time, and have the control of the SPI bus to communicate
with the external SPI controller. However, all the dies will accept two instructions regardless their Active or
Idle status: 1) “Software Die Select (C2h)” instruction; it is used to set any single die to be active according
to the 8-bit Die ID following the instruction. 2) “Software Reset (66h + 99h)” instruction; it is used to reset
all the stacked dies to their power-up state.
4.2 Chip Select (/CS)
The SPI Chip Select (/CS) pin enables and disables device operation. When /CS is high the device is
deselected and the Serial Data Output (DO, or IO0, IO1, IO2, IO3) pins are at high impedance. When
deselected, the devices power consumption will be at standby levels unless an internal erase, program or
write status register cycle is in progress. When /CS is brought low the device will be selected, power
consumption will increase to active levels and instructions can be written to and data read from the device.
After power-up, /CS must transition from high to low before a new instruction will be accepted. The /CS
input must track the VCC supply level at power-up and power-down (see “Write Protection” and Figure
58b). If needed, a pull-up resistor on the /CS pin can be used to accomplish this.
4.3 Serial Input & Output (DI, DO and IO0, IO1, IO2, IO3)
The W25M512JV supports Standard SPI, Dual SPI and Quad SPI operation in each individual stacked die.
All 8-bit instructions are shifted into the device through DI (IO0) pin, address and data are shifted in and out
of the device through either DI & DO pins for Standard SPI instructions, IO0 & IO1 pins for Dual SPI
instructions, or IO0-IO3 pins for Quad SPI instructions.
4.4 Serial Clock (CLK)
The SPI Serial Clock Input (CLK) pin provides the timing for serial input and output operations.
4.5 Reset (/RESET)
A dedicated hardware /RESET pin is available on SOIC-16 and TFBGA packages. When it’s driven low for
a minimum period of ~1µS, all stacked dies will terminate any external or internal operations and return to
their power-on state.
Publication Release Date: September 06, 2017
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W25M512JV
5. SINGLE DIE (W25Q256JV) BLOCK DIAGRAM
SFDPRegister
Security Register 1 - 3
BlockSegmentation
Status
Register
High Voltage
Generators
CLK
/CS
Page Address
Latch / Counter
Beginning
Page Address
Ending
Page Address
SPI
Command &
Control Logic
DI(IO0)
DO(IO1)
IO2
ColumnDecode
And 256-Byte Page Buffer
Data
IO3
Byte Address
Latch / Counter
Figure 2b. Single Die W25Q256JV Serial Flash Memory Block Diagram
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W25M512JV
6. FUNCTIONAL DESCRIPTIONS
6.1 Device Operations
Power Up
Device Initialization
& Status Register Refresh
(Non-Volatile Cells)
“0”
“1”
“0”
“1”
ADP=?
ADP=?
3-Byte
Address
4-Byte
Address
3-Byte
Address
4-Byte
Address
B7h
B7h
E9h
SPI
Dual SPI
Quad SPI
SPI
Dual SPI
Quad SPI
SPI
Dual SPI
Quad SPI
SPI
Dual SPI
Quad SPI
E9h
Die #0
(default active after power up)
Die #1
Software
Die Select (C2h)
ID = #0
ID = #1
Note: ADP bit in the Status Register is only used to determine 3-Byte or 4-Byte address modes during
power up. Changing ADP bit value will not switch the address modes during normal operation.
Figure 2c. W25M512JV Serial Flash Memory Operation Diagram
6.1.1 Stacked Die Operations
Once the device is power on, Die #0 will be active and have control of the SPI bus. “Software Die Select
(C2h)” instruction followed by the 8-bit Die ID can be used to select the active die. The active die is available
to accept any instruction issued by the controller and perform specific operations. The inactive/idle die does
not accept any other instructions except the “Software Die Select (C2h)” and “Software Reset (66h + 99h)”.
However, the inactive/idle die can still perform internal Program/Erase operation which was initiated when
the die was active. Therefore, “Read (on Active die) while Program/Erase (on Idle die)” and “Multi-die
Program/Erase (both Active & Idle dies)” concurrent operations are feasible in the SpiStack® series.
“Software Die Select (C2h)” instruction will only change the active/idle status of the stacked dies, and it will
not interrupt any on-going Program/Erase operations.
6.1.2 Standard SPI Instructions
The W25M512JV is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),
Chip Select (/CS), Serial Data Input (DI) and Serial Data Output (DO). Standard SPI instructions use the DI
input pin to serially write instructions, addresses or data to the device on the rising edge of CLK. The DO
output pin is used to read data or status from the device on the falling edge of CLK.
SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and
Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in standby and data is not
being transferred to the Serial Flash. For Mode 0, the CLK signal is normally low on the falling and rising
edges of /CS. For Mode 3, the CLK signal is normally high on the falling and rising edges of /CS.
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W25M512JV
6.1.3 Dual & Quad SPI Instructions
The W25M512JV supports Dual SPI operation when using instructions such as “Fast Read Dual Output
(3Bh)” and “Fast Read Dual I/O (BBh)”. These instructions allow data to be transferred to or from the device
at two to three times the rate of ordinary Serial Flash devices. When using Dual SPI instructions, the DI and
DO pins become bidirectional I/O pins: IO0 and IO1. The W25M512JV also supports Quad SPI operation
when using instructions such as “Fast Read Quad Output (6Bh)”, and “Fast Read Quad I/O (EBh)”. These
instructions allow data to be transferred to or from the device four to six times the rate of ordinary Serial
Flash. When using Quad SPI instructions, the DI and DO pins become bidirectional IO0 and IO1, with the
additional I/O pins: IO2, IO3.
6.1.4 3-Byte / 4-Byte Address Modes
The W25M512JV provides two Address Modes that can be used to specify any byte of data in the memory
array. The 3-Byte Address Mode is backward compatible to older generations of serial flash memory that
only support up to 128M-bit data. To address the 256M-bit or more data in 3-Byte Address Mode, Extended
Address Register must be used in addition to the 3-Byte addresses.
4-Byte Address Mode is designed to support Serial Flash Memory devices from 256M-bit to 32G-bit. The
Extended Address Register is not necessary when the 4-Byte Address Mode is enabled.
Upon power up, the W25M512JV can operate in either 3-Byte Address Mode or 4-Byte Address Mode,
depending on the Non-Volatile Status Register Bit ADP (S17) setting. If ADP=0, the device will operate in
3-Byte Address Mode; if ADP=1, the device will operate in 4-Byte Address Mode. The factory default value
for ADP is 0. ADP bit cannot be used to switch the address mode during normal operation.
To switch between 3-Byte or 4-Byte Address Modes, “Enter 4-Byte Mode (B7h)” or “Exit 4-Byte Mode (E9h)”
instructions must be used. The current address mode is indicated by the Status Register Bit ADS (S16).
W25M512JV also supports a set of basic SPI instructions which requires dedicated 4-Byte address
regardless the device Address Mode setting. Please refer to Instruction Set Tables for details.
6.1.5 Software Reset & Hardware /RESET pin
The W25M512JV can be reset to the initial power-on state by a software Reset sequence. This sequence
must include two consecutive instructions: Enable Reset (66h) & Reset (99h). If the instruction sequence
is successfully accepted, the device will take approximately 30µS (tRST) to reset. No instruction will be
accepted during the reset period. For the SOIC-16 and TFBGA packages, W25M512JV provides a
dedicated hardware /RESET pin. Drive the /RESET pin low for a minimum period of ~1µS (tRESET*) will
interrupt any on-going external/internal operations and reset the device to its initial power-on state.
Hardware /RESET pin has higher priority than other SPI input signals (/CS, CLK, IOs).
Notes:
1. While a faster /RESET pulse (as short as a few hundred nanoseconds) will often reset the device, a minimum 1µS
pulse is recommended to ensure reliable operation.
2. There is an internal pull-up resistor for the dedicated /RESET pin on the SOIC-16 & TFBGA packages. If the reset
function is not used, this pin can be left floating or connected to the VCC in the system.
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W25M512JV
6.2 Write Protection
Applications that use non-volatile memory must take into consideration the possibility of noise and other
adverse system conditions that may compromise data integrity. To address this concern, each stacked die
within W25M512JV provides several means to protect the data from inadvertent writes independently.
Device resets when VCC is below threshold
Time delay write disable after Power-up
Write enable/disable instructions and automatic write disable after erase or program
Software write protection using Status Registers
Lock Down write protection for Status Register until the next power-up
Additional Individual Block/Sector Locks for array protection
One Time Program (OTP) write protection for Array* and Security Registers using Status Register
* Note: This feature is available upon special order. Please contact Winbond for details.
Upon power-up or at power-down, each stacked die will maintain a reset condition while VCC is below the
threshold value of VWI, (See Power-up Timing and Voltage Levels and Figure 58a). While reset, all
operations are disabled and no instructions are recognized. During power-up and after the VCC voltage
exceeds VWI, all program and erase related instructions are further disabled for a time delay of tPUW. This
includes the Write Enable, Page Program, Sector Erase, Block Erase, Chip Erase and the Write Status
Register instructions. Note that the chip select pin (/CS) must track the VCC supply level at power-up until
the VCC-min level and tVSL time delay is reached, and it must also track the VCC supply level at power-
down to prevent adverse instruction sequence. If needed, a pull-up resistor on /CS pin can be used to
accomplish this.
After power-up the device is automatically placed in a write-disabled state with the Status Register Write
Enable Latch (WEL) set to a 0. A Write Enable instruction must be issued before a Page Program, Sector
Erase, Block Erase, Chip Erase or Write Status Register instruction will be accepted. After completing a
program, erase or write instruction the Write Enable Latch (WEL) is automatically cleared to a write-disabled
state of 0.
Software controlled write protection is facilitated using the Write Status Register instruction and setting the
Status Register Lock (SRL) and Block Protect (CMP, TB, BP[3:0]) bits. These settings allow a portion or
the entire memory array to be configured as read only. See Status Register section for further information.
Each stacked die also provides another Write Protect method using the Individual Block Locks. Each 64KB
block (except the top and bottom blocks, total of 510 blocks) and each 4KB sector within the top/bottom
blocks (total of 32 sectors) are equipped with an Individual Block Lock bit. When the lock bit is 0, the
corresponding sector or block can be erased or programmed; when the lock bit is set to 1, Erase or Program
instructions issued to the corresponding sector or block will be ignored. When the device is powered on, all
Individual Block Lock bits will be 1, so the entire memory array is protected from Erase/Program. An
“Individual Block Unlock (39h)” instruction must be issued to unlock any specific sector or block.
The WPS bit in Status Register-3 is used to decide which Write Protect scheme should be used. When
WPS=0 (factory default), the device will only utilize CMP, TB, BP[3:0] bits to protect specific areas of the
array; when WPS=1, the device will utilize the Individual Block Locks for write protection.
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W25M512JV
7. STATUS AND CONFIGURATION REGISTERS
Three Status and Configuration Registers are provided for each stacked W25Q256JV die. The Read Status
Register-1/2/3 instructions can be used to provide status on the availability of the flash memory array,
whether the device is write enabled or disabled, the state of write protection, Security Register lock status,
Erase/Program Suspend status, output driver strength, power-up and current Address Mode. The Write
Status Register instruction can be used to configure the device write protection features, Security Register
OTP locks, output driver strength and power-up Address Mode. Write access to the Status Registers is
controlled by the state of the volatile/non-volatile Status Register Lock bit (SRL), and the Write Enable
instruction.
7.1 Status Registers
S7
S6
TB
S5
S4
S3
S2
S1
S0
(R)
BP3
BP2
BP1
BP0
WEL BUSY
Reserved
Top/Bottom Protect Bit
(Volatile/Non-Volatile Writable)
Block Protect Bits
(Volatile/Non-Volatile Writable)
Write Enable Latch
(Status-Only)
Erase/Write In Progress
(Status-Only)
Figure 3a. Status Register-1
7.1.1 Program/Erase/Write In Progress (BUSY) – Status Only
BUSY is a read only bit in the status register (S0) that is set to a 1 state when the device is executing a
Page Program, Quad Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register or
Erase/Program Security Register instruction. During this time the device will ignore further instructions
except for the Read Status Register and Erase/Program Suspend instruction (see tW, tPP, tSE, tBE, and tCE
in AC Characteristics). When the program, erase or write status/security register instruction has completed,
the BUSY bit will be cleared to a 0 state indicating the device is ready for further instructions. Read Status
Register instruction can always be used to poll the BUSY status during internal operations to determine if
the operation has finished.
7.1.2 Write Enable Latch (WEL) – Status Only
Write Enable Latch (WEL) is a read only bit in the status register (S1) that is set to 1 after executing a Write
Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A write disable
state occurs upon power-up or after any of the following instructions: Write Disable, Page Program, Quad
Page Program, Sector Erase, Block Erase, Chip Erase, Write Status Register, Erase Security Register and
Program Security Register.
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W25M512JV
7.1.3 Block Protect Bits (BP3, BP2, BP1, BP0) – Volatile/Non-Volatile Writable
The Block Protect Bits (BP3, BP2, BP1, BP0) are read/write bits in the status register (S5, S4, S3, and S2)
that provide Write Protection control and status to the memory array. Block Protect bits can be set using
the Write Status Register Instruction (see tW in AC characteristics). All, none or a portion of the memory
array can be protected from Program and Erase instructions (see Status Register Memory Protection table).
The factory default setting for the Block Protection Bits is 0, none of the array protected.
7.1.4 Top/Bottom Block Protect (TB) – Volatile/Non-Volatile Writable
The Top/Bottom bit (TB) controls if the Block Protect Bits (BP3, BP2, BP1, BP0) protect from the Top (TB=0)
or the Bottom (TB=1) of the array as shown in the Status Register Memory Protection table. The factory
default setting is TB=0. The TB bit can be set with the Write Status Register Instruction depending on the
state of the SRL and WEL bits.
7.1.5 Complement Protect (CMP) – Volatile/Non-Volatile Writable
The Complement Protect bit (CMP) is a read/write bit in the status register (S14). It is used in conjunction
with TB, BP3, BP2, BP1 and BP0 bits to provide more flexibility for the array protection. Once CMP is set
to 1, previous array protection set by TB, BP3, BP2, BP1 and BP0 will be reversed. For instance, when
CMP=0, a top 64KB block can be protected while the rest of the array is not; when CMP=1, the top 64KB
block will become unprotected while the rest of the array become read-only. Please refer to the Status
Register Memory Protection table for details. The default setting is CMP=0.
7.1.6 Status Register Lock (SRL) – Volatile/Non-Volatile OTP Writable
The Status Register Lock bit (SRL) is a volatile/non-volatile read/write bit in the status register (S8). The
SRL bit controls the method of write protection to the Status Registers: temporary Power Lock-Down or
permanently One Time Program OTP.
SRL
Status Register Lock
Description
Status Registers are unlocked.
0
Non-Lock
Status Registers are locked and cannot be written to
until the next power-down, power-up cycle to reset
SRL=0.
Power Lock-Down
(Temporary/Volatile)
1
One Time Program(1)
(Permanently/Non-Volatile)
A special instruction flow can be used to permanently
OTP lock the Status Registers.
Note:
1. Please contact Winbond for details regarding the special instruction sequence.
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- Revision D
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W25M512JV
S15
S14
S13
LB3
S12
LB2
S11
LB1
S10
(R)
S9
S8
SUS CMP
(R)
SRL
Suspend Status
(Status-Only)
Complement Protect
(Volatile/Non-Volatile Writable)
Security Register Lock Bits
(Volatile/Non-Volatile OTP Writable)
Reserved
Status Register Lock
(Volatile/Non-Volatile Writable)
Figure 3b. Status Register-2
7.1.7 Erase/Program Suspend Status (SUS) – Status Only
The Suspend Status bit is a read only bit in the status register (S15) that is set to 1 after executing an
Erase/Program Suspend (75h) instruction. The SUS status bit is cleared to 0 by Erase/Program Resume
(7Ah) instruction as well as a power-down, power-up cycle.
7.1.8 Security Register Lock Bits (LB3, LB2, LB1) – Volatile/Non-Volatile OTP Writable
The Security Register Lock Bits (LB3, LB2, LB1) are non-volatile One Time Program (OTP) bits in Status
Register (S13, S12, S11) that provide the write protect control and status to the Security Registers. The
default state of LB3-1 is 0, Security Registers are unlocked. LB3-1 can be set to 1 individually using the
Write Status Register instruction. LB3-1 are One Time Programmable (OTP), once it’s set to 1, the
corresponding 256-Byte Security Register will become read-only permanently.
7.1.9 Current Address Mode (ADS) – Status Only
The Current Address Mode bit is a read only bit in the Status Register-3 that indicates which address mode
the device is currently operating in. When ADS=0, the device is in the 3-Byte Address Mode, when ADS=1,
the device is in the 4-Byte Address Mode.
7.1.10 Power-Up Address Mode (ADP) – Non-Volatile Writable
The ADP bit is a non-volatile bit that determines the initial address mode when the device is powered on or
reset. This bit is only used during the power on or device reset initialization period, and it is only writable by
the non-volatile Write Status sequence (06h + 11h). When ADP=0 (factory default), the device will power
up into 3-Byte Address Mode, the Extended Address Register must be used to access memory regions
beyond 128Mb. When ADP=1, the device will power up into 4-Byte Address Mode directly.
7.1.11 Write Protect Selection (WPS) – Volatile/Non-Volatile Writable
The WPS bit is used to select which Write Protect scheme should be used. When WPS=0 (factory default),
the device will use the combination of CMP, TB, BP[3:0] bits to protect a specific area of the memory array.
When WPS=1, the device will utilize the Individual Block Locks to protect any individual sector or blocks.
The default value for all Individual Block Lock bits is 1 upon device power on or after reset.
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W25M512JV
S23
(R)
S22
S21
S20
S19
(R)
S18
S17
S16
DRV 1 DRV0 (R)
WPS ADP
ADS
Reserved
Output Driver Strength
( Volatile/Non- Volatile Writable)
Reserved
Write Protect Selection
( Volatile/Non- Volatile Writable)
Power Up Address Mode
(Non-Volatile Writable)
Current Address Mode
(Status-Only)
Figure 3c. Status Register-3
7.1.12 Output Driver Strength (DRV1, DRV0) – Volatile/Non-Volatile Writable
The DRV1 & DRV0 bits are used to determine the output driver strength for the Read operations.
DRV1, DRV0
Driver Strength
0, 0
0, 1
1, 0
1, 1
100%
75%
50%
25% (default setting)
7.1.13 Reserved Bits – Non Functional
There are a few reserved Status Register bits that may be read out as a “0” or “1”. It is recommended to
ignore the values of those bits. During a “Write Status Register” instruction, the Reserved Bits can be written
as “0” or “1”, but there will not be any effects.
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W25M512JV
7.1.14 Single Die W25Q256JV Status Register Memory Protection (WPS = 0, CMP = 0)
STATUS REGISTER(1)
W25M512JV (256M-BIT / 32M-BYTE) MEMORY PROTECTION(2)
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION
TB
BP3
BP2
BP1
BP0
X
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
X
X
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
X
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
X
X
NONE
511
NONE
NONE
64KB
128KB
256KB
512KB
1MB
NONE
Upper 1/512
Upper 1/256
Upper 1/128
Upper 1/64
Upper 1/32
Upper 1/16
Upper 1/8
Upper 1/4
Upper 1/2
Lower 1/512
Lower 1/256
Lower 1/128
Lower 1/64
Lower 1/32
Lower 1/16
Lower 1/8
Lower 1/4
Lower 1/2
ALL
01FF0000h - 01FFFFFFh
01FE0000h - 01FFFFFFh
01FC0000h - 01FFFFFFh
01F80000h - 01FFFFFFh
01F00000h - 01FFFFFFh
01E00000h - 01FFFFFFh
01C00000h - 01FFFFFFh
01800000h - 01FFFFFFh
01000000h - 01FFFFFFh
00000000h - 0000FFFFh
00000000h - 0001FFFFh
00000000h - 0003FFFFh
00000000h - 0007FFFFh
00000000h - 000FFFFFh
00000000h - 001FFFFFh
00000000h - 003FFFFFh
00000000h - 007FFFFFh
00000000h - 00FFFFFFh
00000000h - 01FFFFFFh
00000000h - 01FFFFFFh
510 thru 511
508 thru 511
504 thru 511
496 thru 511
480 thru 511
448 thru 511
384 thru 511
256 thru 511
0
2MB
4MB
8MB
16MB
64KB
128KB
256KB
512KB
1MB
0 thru 1
0 thru 3
0 thru 7
0 thru 15
0 thru 31
2MB
0 thru 63
4MB
0 thru 127
0 thru 255
0 thru 511
0 thru 511
8MB
16MB
32MB
32MB
ALL
Notes:
1. X = don’t care
2. If any Erase or Program instruction specifies a memory region that contains protected data portion, this instruction will be
ignored.
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W25M512JV
7.1.15 Single Die W25Q256JV Status Register Memory Protection (WPS = 0, CMP = 1)
STATUS REGISTER(1)
W25M512JV (256M-BIT / 32M-BYTE) MEMORY PROTECTION(2)
PROTECTED
BLOCK(S)
PROTECTED
ADDRESSES
PROTECTED
DENSITY
PROTECTED
PORTION
TB
BP3
BP2
BP1
BP0
X
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
X
X
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
1
X
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
0
0
0
1
0
1
0
1
0
1
0
1
0
1
1
0
1
0
1
0
1
0
1
X
X
ALL
00000000h - 01FFFFFFh
00000000h - 01FEFFFFh
00000000h - 01FDFFFFh
00000000h - 01FBFFFFh
00000000h - 01F7FFFFh
00000000h - 01EFFFFFh
00000000h - 01DFFFFFh
00000000h - 01BFFFFFh
00000000h - 017FFFFFh
00000000h - 00FFFFFFh
00010000h - 01FFFFFFh
00020000h - 01FFFFFFh
00040000h - 01FFFFFFh
00080000h - 01FFFFFFh
00100000h - 01FFFFFFh
00200000h - 01FFFFFFh
00400000h - 01FFFFFFh
00800000h - 01FFFFFFh
01000000h - 01FFFFFFh
NONE
ALL
32,704KB
32,640KB
32,512KB
32,256KB
31MB
ALL
0 thru 510
0 thru 509
0 thru 507
0 thru 503
0 thru 495
0 thru 479
0 thru 447
0 thru 383
0 thru 255
1 thru 511
2 thru 511
4 thru 511
8 thru 511
16 thru 511
32 thru 511
64 thru 511
128 thru 511
256 thru 511
NONE
Lower 511/512
Lower 255/256
Lower 127/128
Lower 63/64
Lower 31/32
Lower 15/16
Lower 7/8
30MB
28MB
24MB
Lower 3/4
16MB
Lower 1/2
32,704KB
32,640KB
32,512KB
32,256KB
31MB
Upper 511/512
Upper 255/256
Upper 127/128
Upper 63/64
Upper 31/32
Upper 15/16
Upper 7/8
30MB
28MB
24MB
Upper 3/4
16MB
Upper 1/2
NONE
NONE
NONE
NONE
NONE
NONE
Notes:
1. X = don’t care
2. If any Erase or Program instruction specifies a memory region that contains protected data portion, this instruction will be
ignored.
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W25M512JV
7.1.16 Single Die W25Q256JV Individual Block Memory Protection (WPS=1)
Sector 15 (4KB)
Sector 14 (4KB)
Sector 1 (4KB)
Sector 0 (4KB)
Individual Block Locks:
32 Sectors (Top/Bottom)
510 Blocks
Block 510 (64KB)
Individual Block Lock:
36h + Address
Individual Block Unlock:
39h + Address
Read Block Lock:
3Dh + Address
Global Block Lock:
7Eh
Block 1 (64KB)
Global Block Unlock:
98h
Sector 15 (4KB)
Sector 14 (4KB)
Sector 1 (4KB)
Sector 0 (4KB)
Figure 3d. Individual Block/Sector Locks (Single Die W25Q256JV)
Notes:
1. Individual Block/Sector protection is only valid when WPS=1.
2. All individual block/sector lock bits are set to 1 by default after power up, all memory array is protected.
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W25M512JV
7.2 Extended Address Register – Volatile Writable Only
In addition to the Status Registers, each W25Q256JV device provides a volatile Extended Address Register
which consists of the 4th byte of memory address. The Extended Address Register is used only when the
device is operating in the 3-Byte Address Mode (ADS=0). The lower 128Mb memory array (00000000h –
00FFFFFFh) is selected when A24=0, all instructions with 3-Byte addresses will be executed within that
region. When A24=1, the upper 128Mb memory array (01000000h – 01FFFFFFh) will be selected.
If the device powers up with ADP bit set to 1, or an “Enter 4-Byte Address Mode (B7h)” instruction is issued,
the device will require 4-Byte address input for all address related instructions, and the Extended Address
Register setting will be ignored. However, any instruction with 4-byte address input will replace the
Extended Address Register Bits (A31-A24) with new settings.
Upon power up or after the execution of a Software/Hardware Reset, the Extended Address Register values
will be cleared to 0.
EA7
A31
EA6
A30
EA5
A29
EA4
A28
EA3
A27
EA2
A26
EA1
A25
EA0
A24
Reserved
for higher densities
512Mb ~ 32Gb
(Volatile Writable Only)
Address Bit #24
A24=0: Select lower 128Mb
A24=1: Select upper 128Mb
(Volatile Writable Only)
Figure 3e. Extended Address Register (Single Die W25Q256JV)
Publication Release Date: September 06, 2017
- Revision D
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W25M512JV
8. INSTRUCTIONS
The Standard/Dual/Quad SPI instruction set of each individual stacked die in W25M512JV consists of 59
basic instructions that are fully controlled through the SPI bus. Instructions are initiated with the falling edge
of Chip Select (/CS). The first byte of data clocked into the DI input provides the instruction code. Data on
the DI input is sampled on the rising edge of clock with most significant bit (MSB) first.
SPI I/O Protocols
3-Byte Address Mode (ADS=0) 4-Byte Address Mode (ADS=1)
Instruction Set Table 1 & 2 Instruction Set Table 3 & 4
Standard/Dual/Quad SPI
Instructions vary in length from a single byte to several bytes and may be followed by address bytes, data
bytes, dummy bytes (don’t care), and in some cases, a combination. In the following instruction tables,
depending on the number I/O pins for either command, address or data Input/Output, instructions are
grouped by the (x-x-x) SPI protocol notation.
SPI I/O Protocols
Command Byte Input
Address Byte Input
Data Byte Input/Output
(1-1-1)
(1-1-2)
(1-1-4)
(1-2-2)
(1-4-4)
X1 (DI) / 8 clocks
X1 (DI) / 8 clocks
X1 (DI) / 8 clocks
X1 (DI) / 8 clocks
X1 (DI) / 8 clocks
X1 (DI) / 8 clocks
X1 (DI) / 8 clocks
X1 (DI) / 8 clocks
X2 (DI, DO) / 4 clocks
X4 (IO 0~3) / 2 clocks
X1 (DI or DO) / 8 clocks
X2 (DI, DO) / 4 clocks
X4 (IO 0~3) / 2 clocks
X2 (DI, DO) / 4 clocks
X4 (IO 0~3) / 2 clocks
Instructions are completed with the rising edge of edge /CS. Clock relative timing diagrams for each
instruction are included in Figures 4 through 57. All read instructions can be completed after any clocked
bit. However, all instructions that Write, Program or Erase must complete on a byte boundary (/CS driven
high after a full 8-bits have been clocked), otherwise the instruction will be ignored. This feature further
protects the device from inadvertent writes.
Additionally, while the memory is being programmed or erased, or when the Status Register is being written,
all instructions except for Read Status Register will be ignored until the program or erase cycle has
completed. “Software Die Select” and “Software Reset” will always be accepted to switch the Active/Idle
status of any stacked die, regardless the operating status of the die.
8.1 Device ID and Instruction Set Tables
8.1.1 Manufacturer and Device Identification
MANUFACTURER ID
(MF7 - MF0)
Winbond Serial Flash
Device ID
EFh
(ID15 - ID0)
9Fh
(ID7 - ID0)
Instruction
ABh, 90h, 92h, 94h
Single Die W25Q256JV
2x stacked
18h
7119h
- 23 -
W25M512JV
8.1.2 Instruction Set Table 1 (Standard Single SPI, 3-Byte Address Mode ADS=0)(1)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
I/O Protocol (1 – 1 – 1)
Die ID#
Software Die Select
C2h
06h
50h
04h
Write Enable
Volatile Status Register Write Enable
Write Disable
Read Device ID
ABh
90h
9Fh
4Bh
Dummy
Dummy
MF7-MF0
Dummy
Dummy
Dummy
ID15-ID8
Dummy
Dummy
00h
ID7-ID0(2)
MF7-MF0
Read Manufacturer/Device ID
Read JEDEC ID
ID7-ID0
UID63-0
ID7-ID0
Dummy
Read Unique ID
Dummy
Read Data
03h
13h
0Bh
0Ch
A23-A16
A31-A24
A23-A16
A31-A24
A15-A8
A23-A16
A15-A8
A7-A0
A15-A8
A7-A0
D7-D0
A7-A0
Dummy
A7-A0
Read Data with 4-Byte Address
Fast Read
D7-D0
D7-D0
Dummy
Fast Read with 4-Byte Address
A23-A16
A15-A8
D7-D0
Page Program
02h
12h
A23-A16
A31-A24
A23-A16
A31-A24
A23-A16
A23-A16
A31-A24
A15-A8
A23-A16
A15-A8
A23-A16
A15-A8
A15-A8
A23-A16
A7-A0
A15-A8
A7-A0
D7-D0
A7-A0
D7-D0(3)
D7-D0
Page Program with 4-Byte Address
4KB Sector Erase
D7-D0(3)
20h
4KB Sector Erase with 4-Byte Address
32KB Block Erase
21h
A15-A8
A7-A0
A7-A0
A7-A0
52h
64KB Block Erase
D8h
A7-A0
64KB Block Erase with 4-Byte Address
Chip Erase
DCh
C7h/60h
A15-A8
Read Status Register-1
Write Status Register-1(4)
Read Status Register-2
Write Status Register-2
Read Status Register-3
Write Status Register-3
Read Extended Address Register
Write Extended Address Register
Read SFDP Register
05h
01h
35h
31h
15h
11h
C8h
C5h
5Ah
44h
42h
48h
7Eh
98h
3Dh
36h
39h
75h
7Ah
B7h
E9h
S7-S0(2)
S7-S0(4)
S15-S8(2)
S15-S8
S23-S16(2)
S23-S16
EA7-EA0(2)
EA7-EA0
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
Dummy
D7-D0
Erase Security Register(5)
Program Security Register(5)
Read Security Register(5)
Global Block Lock
D7-D0
D7-D0(3)
Dummy
D7-D0
Global Block Unlock
Read Block Lock
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
L7-L0
Individual Block Lock
Individual Block Unlock
Erase / Program Suspend
Erase / Program Resume
Enter 4-Byte Address Mode
Exit 4-Byte Address Mode
Enable Reset
Reset Device
66h
99h
Publication Release Date: September 06, 2017
- Revision D
- 24 -
W25M512JV
8.1.3 Instruction Set Table 2 (Dual/Quad SPI Instructions, 3-Byte Address Mode ADS=0)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
I/O Protocol (1 – 1 – 2)(7)
Fast Read Dual Output
3Bh
3Ch
A23-A16
A31-A24
A15-A8
A23-A16
A7-A0
Dummy
A7-A0
D7-D0 /2
Fast Read Dual Output
with 4-Byte Address
A15-A8
Dummy
D7-D0 /2
I/O Protocol (1 – 2 – 2)(6,7)
Mftr./Device ID Dual I/O
Fast Read Dual I/O
92h
A23-A16 /2 A15-A8 /2
00 /2
Dummy /2 MF7-MF0 /2 ID7-ID0 /2 MF7-MF0 /2 ID7-ID0 /2
BBh A23-A16 /2 A15-A8 /2
A7-A0 /2
Dummy /2
A7-A0 /2
D7-D0 /2
Fast Read Dual I/O
with 4-Byte Address
BCh A31-A24 /2 A23-A16 /2 A15-A8 /2
Dummy /2
D7-D0 /2
I/O Protocol (1 – 1 – 4)(9)
Quad Input Page Program(3)
32h
34h
6Bh
6Ch
A23-A16
A31-A24
A23-A16
A31-A24
A15-A8
A23-A16
A15-A8
A7-A0
A15-A8
A7-A0
D7-D0 /4
A7-A0
Quad Page Program
with 4-Byte Address(3)
D7-D0 /4
D7-D0 /4
Dummy
Fast Read Quad Output
Dummy
A7-A0
Fast Read Quad Output
with 4-Byte Address
A23-A16
A15-A8
D7-D0 /4
I/O Protocol (1 – 4 – 4)(8,9)
Mftr./Device ID Quad I/O
Fast Read Quad I/O
94h
A23-A16 /4 A15-A8 /4
00h /4
Dummy /4 Dummy /4 Dummy /4 MF7-MF0 /4 ID7-ID0 /4
EBh A23-A16 /4 A15-A8 /4
A7-A0 /4
Dummy /4 Dummy /4 Dummy /4
A7-A0 /4 Dummy /4 Dummy /4
Dummy /4 Dummy /4 Dummy /4 W7-W0 /4
D7-D0 /4
Fast Read Quad I/O
with 4-Byte Address
ECh A31-A24 /4 A23-A16 /4 A15-A8 /4
77h
Dummy /4
D7-D0 /4
Set Burst with Wrap
- 25 -
W25M512JV
8.1.4 Instruction Set Table 3 (Standard Single SPI, 4-Byte Address Mode ADS=1)(1)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
I/O Protocol (1 – 1 – 1)
Die ID#
Software Die Select
C2h
06h
50h
04h
Write Enable
Volatile Status Register Write Enable
Write Disable
Read Device ID
ABh
90h
9Fh
4Bh
Dummy
Dummy
MF7-MF0
Dummy
Dummy
Dummy
ID15-ID8
Dummy
Dummy
00h
ID7-ID0(2)
MF7-MF0
Read Manufacturer/Device ID
Read JEDEC ID
ID7-ID0
ID7-ID0
Dummy
Read Unique ID
Dummy
Dummy
UID63-0
Read Data
03h
13h
0Bh
0Ch
A31-A24
A31-A24
A31-A24
A31-A24
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0
D7-D0
Read Data with 4-Byte Address
Fast Read
Dummy
Dummy
D7-D0
D7-D0
Fast Read with 4-Byte Address
Page Program
02h
12h
A31-A24
A31-A24
A31-A24
A31-A24
A31-A24
A31-A24
A31-A24
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0
D7-D0
D7-D0(3)
D7-D0(3)
Page Program with 4-Byte Address
4KB Sector Erase
20h
4KB Sector Erase with 4-Byte Address
32KB Block Erase
21h
52h
64KB Block Erase
D8h
64KB Block Erase with 4-Byte Address
Chip Erase
DCh
C7h/60h
Read Status Register-1
Write Status Register-1(4)
Read Status Register-2
Write Status Register-2
Read Status Register-3
Write Status Register-3
Read Extended Address Register
Write Extended Address Register
Read SFDP Register
05h
01h
35h
31h
15h
11h
C8h
C5h
5Ah
44h
42h
48h
7Eh
98h
3Dh
36h
39h
75h
7Ah
B7h
E9h
S7-S0(2)
S7-S0(4)
S15-S8(2)
S15-S8
S23-S16(2)
S23-S16
EA7-EA0(2)
EA7-EA0
A23-A16
A31-A24
A31-A24
A31-A24
A15-A8
A23-A16
A23-A16
A23-A16
A7-A0
A15-A8
A15-A8
A15-A8
Dummy
A7-A0
A7-A0
A7-A0
D7-D0
Erase Security Register(5)
Program Security Register(5)
Read Security Register(5)
Global Block Lock
D7-D0
D7-D0(3)
Dummy
D7-D0
Global Block Unlock
Read Block Lock
A31-A24
A31-A24
A31-A24
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
L7-L0
Individual Block Lock
Individual Block Unlock
Erase / Program Suspend
Erase / Program Resume
Enter 4-Byte Address Mode
Exit 4-Byte Address Mode
Enable Reset
Reset Device
66h
99h
Publication Release Date: September 06, 2017
- Revision D
- 26 -
W25M512JV
8.1.5 Instruction Set Table 4 (Dual/Quad SPI Instructions, 4-Byte Address Mode ADS=1)
Data Input Output
Byte 1
Byte 2
Byte 3
Byte 4
Byte 5
Byte 6
Byte 7
Byte 8
Byte 9
I/O Protocol (1 – 1 – 2)(7)
Fast Read Dual Output
3Bh
3Ch
A31-A24
A31-A24
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
Dummy
Dummy
D7-D0 /2
D7-D0 /2
Fast Read Dual Output
with 4-Byte Address
I/O Protocol (1 – 2 – 2)(6,7)
Mftr./Device ID Dual I/O
Fast Read Dual I/O
92h
A31-A24 /2 A23-A16 /2 A15-A8 /2
00 /2
Dummy /2 MF7-MF0 /2 ID7-ID0 /2 MF7-MF0 /2
BBh A31-A24 /2 A23-A16 /2 A15-A8 /2
BCh A31-A24 /2 A23-A16 /2 A15-A8 /2
A7-A0 /2
Dummy /2
Dummy /2
D7-D0 /2
D7-D0 /2
Fast Read Dual I/O
with 4-Byte Address
A7-A0 /2
I/O Protocol (1 – 1 – 4)(9)
Quad Input Page Program(3)
32h
34h
6Bh
6Ch
A31-A24
A31-A24
A31-A24
A31-A24
A23-A16
A23-A16
A23-A16
A23-A16
A15-A8
A15-A8
A15-A8
A15-A8
A7-A0
A7-A0
A7-A0
A7-A0
D7-D0 /4
D7-D0 /4
Dummy
Dummy
Quad Page Program
with 4-Byte Address(3)
Fast Read Quad Output
D7-D0 /4
D7-D0 /4
Fast Read Quad Output
with 4-Byte Address
I/O Protocol (1 – 4 – 4)(8,9)
Mftr./Device ID Quad I/O
Fast Read Quad I/O
94h
A31-A24 /4 A23-A16 /4 A15-A8 /4
00h /4
Dummy /4 Dummy /4 Dummy /4 MF7-MF0 /4
EBh A31-A24 /4 A23-A16 /4 A15-A8 /4
ECh A31-A24 /4 A23-A16 /4 A15-A8 /4
A7-A0 /4
Dummy /4 Dummy /4 Dummy /4
Dummy /4 Dummy /4 Dummy /4
D7-D0 /4
D7-D0 /4
Fast Read Quad I/O
with 4-Byte Address
A7-A0 /4
Set Burst with Wrap
77h
Dummy /4 Dummy /4 Dummy /4 Dummy /4 W7-W0 /4
- 27 -
W25M512JV
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with bold and italic style D7-D0 indicate data
output from the device. “D7-D0” indicates single I/O pin; “D7-D0 /2” indicates 2 I/O pins; “D7-D0 /4” indicates
4 I/O pins.
2. The Status Register contents and Device ID will repeat continuously until /CS terminates the instruction.
3. At least one byte of data input is required for Page Program, Quad Page Program and Program Security
Registers, up to 256 bytes of data input. If more than 256 bytes of data are sent to the device, the addressing
will wrap to the beginning of the page and overwrite previously sent data.
4. Write Status Register-1 (01h) can also be used to program Status Register-1&2, see section 8.2.6.
5. Security Register Address:
Security Register 1: A23-16 = 00h; A15-8 = 10h; A7-0 = byte address
Security Register 2: A23-16 = 00h; A15-8 = 20h; A7-0 = byte address
Security Register 3: A23-16 = 00h; A15-8 = 30h; A7-0 = byte address
6. Dual SPI address input format:
IO0 = A22, A20, A18, A16, A14, A12, A10, A8, A6, A4, A2, A0
IO1 = A23, A21, A19, A17, A15, A13, A11, A9, A7, A5, A3, A1
7. Dual SPI data input/output format:
IO0 = D6, D4, D2, D0, …..
IO1 = D7, D5, D3, D1, …..
8. Quad SPI address input format:
IO0 = A20, A16, A12, A8, A4, A0
Set Burst with Wrap input format:
IO0 = x, x, x, x, x, x, W4, x
IO1 = x, x, x, x, x, x, W5, x
IO2 = x, x, x, x, x, x, W6, x
IO1 = A21, A17, A13, A9, A5, A1
IO2 = A22, A18, A14, A10, A6, A2
IO3 = A23, A19, A15, A11, A7, A3
IO3 = x, x, x, x, x, x, x,
x
9. Quad SPI data input/output format:
IO0 = D4, D0, …..
IO1 = D5, D1, …..
IO2 = D6, D2, …..
IO3 = D7, D3, …..
Publication Release Date: September 06, 2017
- Revision D
- 28 -
W25M512JV
8.2 Instruction Descriptions
8.2.1 Software Die Select (C2h)
Each stacked die has a pre-assigned “Die ID#” by the factory, in the sequence of 0x00, 0x01, etc. At any
given time, there can only be one Active Die within the W25M package, to communicate with the external
SPI controller. After power-up, Die #0 is always the Active Die. Software Die Select (C2h) instruction is
used to select a specific die to be active, according to the 8-bit Die ID following the C2h instruction as
illustrated in Figure 4.
“Concurrent Operations” can be realized by assigning the current Active Die to perform an Erase/Program
operation which requires some amount of time to finish. While the internal Program/Erase operation is on-
going, the controller can issue a “Software Die Select (C2h)” instruction to select another die to be active.
Depending on the system requirement, a Read, Program or Erase operation can be performed on the newly
selected Active Die. “Read while Program/Erase” or “Multi-Die Program/Erase” can be performed in such
fashion, to improve system Program/Erase throughput and to avoid constant Program/Erase Suspend and
Resume activities in certain applications.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Mode 3
Mode 0
CLK
Instruction (C2h)
Die ID
DI
(IO0)
7
6
5
4
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 4. Software Die Select Instruction
- 29 -
W25M512JV
8.2.2 Write Enable (06h)
The Write Enable instruction (Figure 5) sets the Write Enable Latch (WEL) bit in the Status Register to a 1.
The WEL bit must be set prior to every Page Program, Quad Page Program, Sector Erase, Block Erase,
Chip Erase, Write Status Register and Erase/Program Security Registers instruction. The Write Enable
instruction is entered by driving /CS low, shifting the instruction code “06h” into the Data Input (DI) pin on
the rising edge of CLK, and then driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (06h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 5. Write Enable Instruction
8.2.3 Write Enable for Volatile Status Register (50h)
The non-volatile Status Register bits described in section 7.1 can also be written to as volatile bits. This
gives more flexibility to change the system configuration and memory protection schemes quickly without
waiting for the typical non-volatile bit write cycles or affecting the endurance of the Status Register non-
volatile bits. To write the volatile values into the Status Register bits, the Write Enable for Volatile Status
Register (50h) instruction must be issued prior to a Write Status Register (01h) instruction. Write Enable for
Volatile Status Register instruction (Figure 6) will not set the Write Enable Latch (WEL) bit, it is only valid
for the Write Status Register instruction to change the volatile Status Register bit values.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (50h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 6. Write Enable for Volatile Status Register Instruction
Publication Release Date: September 06, 2017
- Revision D
- 30 -
W25M512JV
8.2.4 Write Disable (04h)
The Write Disable instruction (Figure 7) resets the Write Enable Latch (WEL) bit in the Status Register to a
0. The Write Disable instruction is entered by driving /CS low, shifting the instruction code “04h” into the DI
pin and then driving /CS high. Note that the WEL bit is automatically reset after Power-up and upon
completion of the Write Status Register, Erase/Program Security Registers, Page Program, Quad Page
Program, Sector Erase, Block Erase, Chip Erase and Reset instructions.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (04h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 7. Write Disable Instruction
8.2.5 Read Status Register-1 (05h), Status Register-2 (35h) & Status Register-3 (15h)
The Read Status Register instructions allow the 8-bit Status Registers to be read. The instruction is entered
by driving /CS low and shifting the instruction code “05h” for Status Register-1, “35h” for Status Register-2
or “15h” for Status Register-3 into the DI pin on the rising edge of CLK. The status register bits are then
shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first as shown in Figure
8. Refer to section 7.1 for Status Register descriptions.
The Read Status Register instruction may be used at any time, even while a Program, Erase or Write Status
Register cycle is in progress. This allows the BUSY status bit to be checked to determine when the cycle
is complete and if the device can accept another instruction. The Status Register can be read continuously,
as shown in Figure 8. The instruction is completed by driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Instruction (05h/35h/15h)
High Impedance
DI
(IO0)
Status Register-1/2/3 out
Status Register-1/2/3 out
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
= MSB
*
*
*
Figure 8. Read Status Register Instruction
- 31 -
W25M512JV
8.2.6 Write Status Register-1 (01h), Status Register-2 (31h) & Status Register-3 (11h)
The Write Status Register instruction allows the Status Registers to be written. The writable Status Register
bits include: TB, BP[3:0] in Status Register-1; CMP, LB[3:1], SRL in Status Register-2; DRV1, DRV0, WPS
& ADP in Status Register-3. All other Status Register bit locations are read-only and will not be affected by
the Write Status Register instruction. LB[3:1] are non-volatile OTP bits, once it is set to 1, it cannot be
cleared to 0.
To write non-volatile Status Register bits, a standard Write Enable (06h) instruction must previously have
been executed for the device to accept the Write Status Register instruction (Status Register bit WEL must
equal 1). Once write enabled, the instruction is entered by driving /CS low, sending the instruction code
“01h/31h/11h”, and then writing the status register data byte as illustrated in Figure 9a & 9b.
To write volatile Status Register bits, a Write Enable for Volatile Status Register (50h) instruction must have
been executed prior to the Write Status Register instruction (Status Register bit WEL remains 0). However,
LB[3:1] cannot be changed from “1” to “0” because of the OTP protection for these bits. Upon power off or
the execution of a Software/Hardware Reset, the volatile Status Register bit values will be lost, and the
non-volatile Status Register bit values will be restored.
During non-volatile Status Register write operation (06h followed by 01h/31h/11h), after /CS is driven high,
the self-timed Write Status Register cycle will commence for a time duration of tW (See AC Characteristics).
While the Write Status Register cycle is in progress, the Read Status Register instruction may still be
accessed to check the status of the BUSY bit. The BUSY bit is a 1 during the Write Status Register cycle
and a 0 when the cycle is finished and ready to accept other instructions again. After the Write Status
Register cycle has finished, the Write Enable Latch (WEL) bit in the Status Register will be cleared to 0.
During volatile Status Register write operation (50h followed by 01h/31h/11h), after /CS is driven high, the
Status Register bits will be refreshed to the new values within the time period of tSHSL2 (See AC
Characteristics). BUSY bit will remain 0 during the Status Register bit refresh period.
Refer to section 7.1 for Status Register descriptions. Factory default for all status Register bits are 0.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Register-1/2/3 in
Mode 3
Mode 0
CLK
Instruction
(01h/31h/11h)
DI
(IO0)
7
6
5
4
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 9a. Write Status Register-1/2/3 Instruction
Publication Release Date: September 06, 2017
- Revision D
- 32 -
W25M512JV
The W25M512JV is also backward compatible to Winbond’s previous generations of serial flash memories,
in which the Status Register-1&2 can be written using a single “Write Status Register-1 (01h)” instruction.
To complete the Write Status Register-1&2 instruction, the /CS pin must be driven high after the sixteenth
bit of data that is clocked in as shown in Figure 9c & 9d. If /CS is driven high after the eighth clock, the Write
Status Register-1 (01h) instruction will only program the Status Register-1, the Status Register-2 will not
be affected (Previous generations will clear CMP bit).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
Mode 3
Mode 0
CLK
Instruction (01h)
Status Register 1 in
Status Register 2 in
DI
(IO0)
7
6
5
4
3
2
1
0
15 14 13 12 11 10
9
8
*
*
High Impedance
DO
(IO1)
= MSB
*
Figure 9b. Write Status Register-1/2 Instruction
- 33 -
W25M512JV
8.2.7 Read Extended Address Register (C8h)
When the device is in the 3-Byte Address Mode, the Extended Address Register is used as the 4th address
byte A[31:24] to access memory regions beyond 128Mb. The Read Extended Address Register instruction
is entered by driving /CS low and shifting the instruction code “C8h” into the DI pin on the rising edge of
CLK. The Extended Address Register bits are then shifted out on the DO pin at the falling edge of CLK with
most significant bit (MSB) first as shown in Figure 10.
When the device is in the 4-Byte Address Mode, the Extended Address Register is not used.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Instruction (C8h)
High Impedance
DI
(IO0)
Extended Addr. Reg. Out
Extended Addr. Reg. Out
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
= MSB
*
*
*
Figure 10. Read Extended Address Register Instruction
Publication Release Date: September 06, 2017
- Revision D
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W25M512JV
8.2.8 Write Extended Address Register (C5h)
The Extended Address Register is a volatile register that stores the 4th byte address (A31-A24) when the
device is operating in the 3-Byte Address Mode (ADS=0). To write the Extended Address Register bits, a
Write Enable (06h) instruction must previously have been executed for the device to accept the Write
Extended Address Register instruction (Status Register bit WEL must equal 1). Once write enabled, the
instruction is entered by driving /CS low, sending the instruction code “C5h”, and then writing the Extended
Address Register data byte as illustrated in Figure 11.
Upon power up or the execution of a Software/Hardware Reset, the Extended Address Register bit values
will be cleared to 0.
The Extended Address Register is only effective when the device is in the 3-Byte Address Mode. When the
device operates in the 4-Byte Address Mode (ADS=1), any instruction with address input of A31-A24 will
replace the Extended Address Register values. It is recommended to check and update the Extended
Address Register if necessary when the device is switched from 4-Byte to 3-Byte Address Mode.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Ext. Add. Reg in
Mode 3
Mode 0
CLK
Instruction (C5h)
DI
(IO0)
7
6
5
4
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 11. Write Extended Address Register Instruction
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W25M512JV
8.2.9 Enter 4-Byte Address Mode (B7h)
The Enter 4-Byte Address Mode instruction (Figure 12) will allow 32-bit address (A31-A0) to be used to
access the memory array beyond 128Mb. The Enter 4-Byte Address Mode instruction is entered by driving
/CS low, shifting the instruction code “B7h” into the DI pin and then driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (B7h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 12. Enter 4-Byte Address Mode instruction
8.2.10 Exit 4-Byte Address Mode (E9h)
In order to be backward compatible, the Exit 4-Byte Address Mode instruction (Figure 13) will only allow
24-bit address (A23-A0) to be used to access the memory array up to 128Mb. The Extended Address
Register must be used to access the memory array beyond 128Mb. The Exit 4-Byte Address Mode
instruction is entered by driving /CS low, shifting the instruction code “E9h” into the DI pin and then driving
/CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (E9h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 13. Exit 4-Byte Address Mode instruction
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- Revision D
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W25M512JV
8.2.11 Read Data (03h)
The Read Data instruction allows one or more data bytes to be sequentially read from the memory. The
instruction is initiated by driving the /CS pin low and then shifting the instruction code “03h” followed by a
32/24-bit address (A31/A23-A0) into the DI pin. The code and address bits are latched on the rising edge
of the CLK pin. After the address is received, the data byte of the addressed memory location will be shifted
out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The address is automatically
incremented to the next higher address after each byte of data is shifted out allowing for a continuous
stream of data. This means that the entire memory can be accessed with a single instruction as long as the
clock continues. The instruction is completed by driving /CS high.
The Read Data instruction sequence is shown in Figure 14. If a Read Data instruction is issued while an
Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have any
effects on the current cycle. The Read Data instruction is a legacy SPI read instruction. There’s no dummy
clock between Address Input and Data Output, therefore it can only operate up to 50MHz (see AC Electrical
Characteristics fR).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
CLK
Instruction (03h)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
Data Out 1
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
7
= MSB
*
*
Figure 14. Read Data Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
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W25M512JV
8.2.12 Read Data with 4-Byte Address (13h)
The Read Data with 4-Byte Address instruction is similar to the Read Data (03h) instruction. Instead of 24-
bit address, 32-bit address is needed following the instruction code 13h. No matter the device is operating
in 3-Byte Address Mode or 4-byte Address Mode, the Read Data with 4-Byte Address instruction will always
require 32-bit address to access the entire 256Mb memory.
The Read Data with 4-Byte Address instruction sequence is shown in Figure 15. If this instruction is issued
while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will not have
any effects on the current cycle. The Read Data with 4-Byte Address instruction allows clock rates from
D.C. to a maximum of fR (see AC Electrical Characteristics).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
36 37 38 39 40 41 42 43 44 45 46 47
CLK
Instruction (13h)
32-Bit Address
DI
(IO0)
31 30 29
3
2
1
0
*
Data Out 1
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
7
= MSB
*
*
Figure 15. Read Data with 4-Byte Address Instruction
Publication Release Date: September 06, 2017
- Revision D
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W25M512JV
8.2.13 Fast Read (0Bh)
The Fast Read instruction is similar to the Read Data instruction except that it can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy”
clocks after the 24/32-bit address as shown in Figure 16. The dummy clocks allow the devices internal
circuits additional time for setting up the initial address. During the dummy clocks the data value on the DO
pin is a “don’t care”.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (0Bh)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Clocks
DI
(IO0)
0
Data Out 1
Data Out 2
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
*
*
Figure 16. Fast Read Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
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W25M512JV
8.2.14 Fast Read with 4-Byte Address (0Ch)
The Fast Read with 4-Byte Address instruction is similar to the Fast Read instruction except that it requires
32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address Mode or 4-
byte Address Mode, the Read Data with 4-Byte Address instruction will always require 32-bit address to
access the entire 256Mb memory.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
36 37 38 39
CLK
Instruction (0Ch)
32-Bit Address
DI
(IO0)
31 30 29
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
CLK
Dummy Clocks
DI
(IO0)
0
Data Out 1
Data Out 2
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
*
*
Figure 17. Fast Read with 4-Byte Address Instruction
Publication Release Date: September 06, 2017
- Revision D
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W25M512JV
8.2.16 Fast Read Dual Output (3Bh)
The Fast Read Dual Output (3Bh) instruction is similar to the standard Fast Read (0Bh) instruction except
that data is output on two pins; IO0 and IO1. This allows data to be transferred at twice the rate of standard
SPI devices. The Fast Read Dual Output instruction is ideal for quickly downloading code from Flash to
RAM upon power-up or for applications that cache code-segments to RAM for execution.
Similar to the Fast Read instruction, the Fast Read Dual Output instruction can operate at the highest
possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding eight “dummy”
clocks after the 24/32-bit address as shown in Figure 19. The dummy clocks allow the device's internal
circuits additional time for setting up the initial address. The input data during the dummy clocks is “don’t
care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out clock.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (3Bh)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
IO0 switches from
Dummy Clocks
Input to Output
DI
(IO0)
0
6
4
2
0
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
7
High Impedance
DO
(IO1)
7
5
3
1
7
7
7
Data Out 1
Data Out 2
Data Out 3
Data Out 4
*
*
*
*
Figure 19. Fast Read Dual Output Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 41 -
W25M512JV
8.2.17 Fast Read Dual Output with 4-Byte Address (3Ch)
The Fast Read Dual Output with 4-Byte Address instruction is similar to the Fast Read Dual Output
instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is operating
in 3-Byte Address Mode or 4-byte Address Mode, the Fast Read Dual Output with 4-Byte Address
instruction will always require 32-bit address to access the entire 256Mb memory.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
36 37 38 39
CLK
Instruction (3Ch)
32-Bit Address
DI
(IO0)
31 30 29
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
CLK
IO0 switches from
Dummy Clocks
Input to Output
DI
(IO0)
0
6
4
2
0
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
7
High Impedance
DO
(IO1)
7
5
3
1
7
7
7
Data Out 1
Data Out 2
Data Out 3
Data Out 4
*
*
*
*
Figure 20. Fast Read Dual Output with 4-Byte Address Instruction
Publication Release Date: September 06, 2017
- Revision D
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W25M512JV
8.2.18 Fast Read Quad Output (6Bh)
The Fast Read Quad Output (6Bh) instruction is similar to the Fast Read Dual Output (3Bh) instruction
except that data is output on four pins, IO0, IO1, IO2, and IO3. The Fast Read Quad Output Instruction allows
data to be transferred at four times the rate of standard SPI devices.
The Fast Read Quad Output instruction can operate at the highest possible frequency of FR (see AC
Electrical Characteristics). This is accomplished by adding eight “dummy” clocks after the 24/32-bit address
as shown in Figure 21. The dummy clocks allow the device's internal circuits additional time for setting up
the initial address. The input data during the dummy clocks is “don’t care”. However, the IO pins should be
high-impedance prior to the falling edge of the first data out clock.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
IO0
Instruction (6Bh)
24-Bit Address
23 22 21
3
2
1
0
*
High Impedance
High Impedance
High Impedance
IO1
IO2
IO3
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47
CLK
IO0 switches from
Dummy Clocks
Input to Output
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO0
IO1
IO2
IO3
High Impedance
High Impedance
High Impedance
Byte 1
Byte 2
Byte 3
Byte 4
Figure 21. Fast Read Quad Output Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 43 -
W25M512JV
8.2.19 Fast Read Quad Output with 4-Byte Address (6Ch)
The Fast Read Quad Output with 4-Byte Address instruction is similar to the Fast Read Quad Output
instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is operating
in 3-Byte Address Mode or 4-byte Address Mode, the Fast Read Quad Output with 4-Byte Address
instruction will always require 32-bit address to access the entire 256Mb memory.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
36 37 38 39
CLK
IO0
Instruction (6Ch)
32-Bit Address
31 30 29
3
2
1
0
*
High Impedance
High Impedance
High Impedance
IO1
IO2
IO3
= MSB
*
/CS
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
IO0 switches from
Dummy Clocks
Input to Output
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO0
IO1
IO2
IO3
High Impedance
High Impedance
High Impedance
Byte 1
Byte 2
Byte 3
Byte 4
Figure 22. Fast Read Quad Output with 4-Byte Address Instruction
Publication Release Date: September 06, 2017
- Revision D
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W25M512JV
8.2.20 Fast Read Dual I/O (BBh)
The Fast Read Dual I/O (BBh) instruction allows for improved random access while maintaining two IO
pins, IO0 and IO1. It is similar to the Fast Read Dual Output (3Bh) instruction but with the capability to input
the Address bits (A23/A31-0) two bits per clock. This reduced instruction overhead may allow for code
execution (XIP) directly from the Dual SPI in some applications.
Similar to the Fast Read Dual Output (3Bh) instruction, the Fast Read Dual I/O instruction can operate at
the highest possible frequency of FR (see AC Electrical Characteristics). This is accomplished by adding
four “dummy” clocks after the 24/32-bit address as shown in Figure 23. The dummy clocks allow the device's
internal circuits additional time for setting up the initial address. The input data during the dummy clocks is
“don’t care”. However, the IO0 pin should be high-impedance prior to the falling edge of the first data out
clock.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Instruction (BBh)
A23-16
A15-8
A7-0
Dummy
DI
(IO0)
22 20 18 16 14 12 10
8
9
6
7
4
2
0
1
DO
(IO1)
23 21 19 17 15 13 11
5
3
*
= MSB
*
/CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
CLK
IOs switch from
Input to Output
DI
(IO0)
6
4
5
2
0
6
4
5
2
0
1
6
4
5
2
0
1
6
4
5
2
0
1
6
7
DO
(IO1)
7
3
1
7
3
7
3
7
3
*
*
*
*
Byte 1
Byte 2
Byte 3
Byte 4
Figure 23. Fast Read Dual I/O Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 45 -
W25M512JV
8.2.21 Fast Read Dual I/O with 4-Byte Address (BCh)
The Fast Read Dual I/O with 4-Byte Address instruction is similar to the Fast Read Dual I/O instruction
except that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte
Address Mode or 4-byte Address Mode, the Fast Read Dual I/O with 4-Byte Address instruction will always
require 32-bit address to access the entire 256Mb memory.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
21 22 23 24 25 26 27
CLK
Instruction (BCh)
32-Bit Address
Dummy
DI
(IO0)
30 28 26
4
2
3
0
1
DO
(IO1)
31 29 27
5
*
= MSB
*
/CS
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
CLK
IOs switch from
Input to Output
DI
(IO0)
6
4
5
2
0
6
4
5
2
0
1
6
4
5
2
0
1
6
4
5
2
0
1
6
7
DO
(IO1)
7
3
1
7
3
7
3
7
3
*
*
*
*
Byte 1
Byte 2
Byte 3
Byte 4
Figure 24. Fast Read Dual I/O w/ 4-Byte Address Instruction
Publication Release Date: September 06, 2017
- Revision D
- 46 -
W25M512JV
8.2.22 Fast Read Quad I/O (EBh)
The Fast Read Quad I/O (EBh) instruction is similar to the Fast Read Dual I/O (BBh) instruction except that
address and data bits are input and output through four pins IO0, IO1, IO2 and IO3 and six Dummy clocks
are required in SPI mode prior to the data output. The Quad I/O dramatically reduces instruction overhead
allowing faster random access for code execution (XIP) directly from the Quad SPI.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
IOs switch from
Input to Output
A23-16
A15-8
A7-0
Dummy
Dummy
Dummy
Instruction (EBh)
20 16 12
21 17 13
8
9
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO0
IO1
IO2
IO3
5
6
7
22 18 14 10
23 19 15 11
Byte 1
Byte 2
Byte 3
Figure 26. Fast Read Quad I/O Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Fast Read Quad I/O instruction can also be used to access a specific portion within a page by issuing
a “Set Burst with Wrap” (77h) instruction prior to EBh. The “Set Burst with Wrap” (77h) instruction can either
enable or disable the “Wrap Around” feature for the following EBh instructions. When “Wrap Around” is
enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte section of a 256-byte
page. The output data starts at the initial address specified in the instruction, once it reaches the ending
boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning boundary
automatically until /CS is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section
within a page. Refer to section 8.2.26 for detail descriptions.
- 47 -
W25M512JV
8.2.23 Fast Read Quad I/O with 4-Byte Address (ECh)
The Fast Read Quad I/O with 4-Byte Address instruction is similar to the Fast Read Quad I/O instruction
except that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte
Address Mode or 4-byte Address Mode, the Fast Read Quad I/O with 4-Byte Address instruction will always
require 32-bit address to access the entire 256Mb memory.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
14 15 16 17 18 19 20 21 22 23 24 25
CLK
IOs switch from
Input to Output
Dummy
Dummy
Dummy
Instruction (ECh)
32-Bit Address
28 24
29 25
30 26
31 27
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
IO0
IO1
IO2
IO3
Byte 1
Byte 2
Byte 3
Figure 27. Fast Read Quad I/O w/ 4-Byte Address Instruction
Fast Read Quad I/O with “8/16/32/64-Byte Wrap Around”
The Fast Read Quad I/O with 4-Byte Address instruction can also be used to access a specific portion
within a page by issuing a “Set Burst with Wrap” (77h) instruction prior to ECh. The “Set Burst with Wrap”
(77h) instruction can either enable or disable the “Wrap Around” feature for the following ECh instructions.
When “Wrap Around” is enabled, the data being accessed can be limited to either an 8, 16, 32 or 64-byte
section of a 256-byte page. The output data starts at the initial address specified in the instruction, once it
reaches the ending boundary of the 8/16/32/64-byte section, the output will wrap around to the beginning
boundary automatically until /CS is pulled high to terminate the instruction.
The Burst with Wrap feature allows applications that use cache to quickly fetch a critical address and then
fill the cache afterwards within a fixed length (8/16/32/64-byte) of data without issuing multiple read
instructions.
The “Set Burst with Wrap” instruction allows three “Wrap Bits”, W6-4 to be set. The W4 bit is used to enable
or disable the “Wrap Around” operation while W6-5 are used to specify the length of the wrap around section
within a page. Refer to section 8.2.26 for detail descriptions.
Publication Release Date: September 06, 2017
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- Revision D
W25M512JV
8.2.25 Set Burst with Wrap (77h)
The Set Burst with Wrap (77h) instruction is used in conjunction with “Fast Read Quad I/O” and “Word Read
Quad I/O” instructions to access a fixed length of 8/16/32/64-byte section within a 256-byte page. Certain
applications can benefit from this feature and improve the overall system code execution performance.
Similar to a Quad I/O instruction, the Set Burst with Wrap instruction is initiated by driving the /CS pin low
and then shifting the instruction code “77h” followed by 24/32 dummy bits and 8 “Wrap Bits”, W7-0. The
instruction sequence is shown in Figure 29. Wrap bit W7 and the lower nibble W3-0 are not used.
W4 = 0
Wrap Around
W4 =1 (DEFAULT)
W6, W5
Wrap Length
Wrap Around
Wrap Length
0
0
Yes
8-byte
No
N/A
0
1
1
1
0
1
Yes
Yes
Yes
16-byte
32-byte
64-byte
No
No
No
N/A
N/A
N/A
Once W6-4 is set by a Set Burst with Wrap instruction, all the following “Fast Read Quad I/O” and “Word
Read Quad I/O” instructions will use the W6-4 setting to access the 8/16/32/64-byte section within any
page. To exit the “Wrap Around” function and return to normal read operation, another Set Burst with Wrap
instruction should be issued to set W4 = 1. The default value of W4 upon power on or after a
software/hardware reset is 1.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
Mode 3
Mode 0
CLK
don't
care
don't
care
don't
care
Wrap Bit
Instruction (77h)
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
w4
w5
w6
X
X
X
X
X
IO0
IO1
IO2
IO3
X
X
X
X
X
X
X
X
X
Figure 29. Set Burst with Wrap Instruction
32-Bit dummy bits are required when the device is operating in 4-Byte Address Mode
- 49 -
W25M512JV
8.2.26 Page Program (02h)
The Page Program instruction allows from one byte to 256 bytes (a page) of data to be programmed at
previously erased (FFh) memory locations. A Write Enable instruction must be executed before the device
will accept the Page Program Instruction (Status Register bit WEL= 1). The instruction is initiated by driving
the /CS pin low then shifting the instruction code “02h” followed by a 24/32-bit address (A23/A31-A0) and
at least one data byte, into the DI pin. The /CS pin must be held low for the entire length of the instruction
while data is being sent to the device. The Page Program instruction sequence is shown in Figure 30.
If an entire 256 byte page is to be programmed, the last address byte (the 8 least significant address bits)
should be set to 0. If the last address byte is not zero, and the number of clocks exceeds the remaining
page length, the addressing will wrap to the beginning of the page. In some cases, less than 256 bytes (a
partial page) can be programmed without having any effect on other bytes within the same page. One
condition to perform a partial page program is that the number of clocks cannot exceed the remaining page
length. If more than 256 bytes are sent to the device the addressing will wrap to the beginning of the page
and overwrite previously sent data.
As with the write and erase instructions, the /CS pin must be driven high after the eighth bit of the last byte
has been latched. If this is not done the Page Program instruction will not be executed. After /CS is driven
high, the self-timed Page Program instruction will commence for a time duration of tpp (See AC
Characteristics). While the Page Program cycle is in progress, the Read Status Register instruction may
still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1 during the Page Program
cycle and becomes a 0 when the cycle is finished and the device is ready to accept other instructions again.
After the Page Program cycle has finished the Write Enable Latch (WEL) bit in the Status Register is cleared
to 0. The Page Program instruction will not be executed if the addressed page is protected by the Block
Protect (CMP, TB, BP3, BP2, BP1, and BP0) bits or the Individual Block/Sector Locks.
Multi-Die “Concurrent” Program can be performed by issuing two separate “Page Program” instructions
respectively to the stacked dies. BUSY bit in each individual die’s Status Register can be polled to determine
if the internal Program operation has finished or not.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
CLK
Instruction (02h)
24-Bit Address
Data Byte 1
DI
(IO0)
23 22 21
3
2
1
0
7
6
5
4
3
2
1
0
*
*
= MSB
*
/CS
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Mode 3
Mode 0
CLK
Data Byte 2
Data Byte 3
Data Byte 256
DI
(IO0)
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
*
*
*
Figure 30. Page Program Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
Publication Release Date: September 06, 2017
- Revision D
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W25M512JV
8.2.27 Page Program with 4-Byte Address (12h)
The Page Program with 4-Byte Address instruction is similar to the Page Program instruction except that it
requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address Mode
or 4-byte Address Mode, the Page Program with 4-Byte Address instruction will always require 32-bit
address to access the entire 256Mb memory.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
36 37 38 39 40 41 42 43 44 45 46 47
CLK
Instruction (12h)
32-Bit Address
Data Byte 1
DI
(IO0)
31 30 29
3
2
1
0
7
6
5
4
3
2
1
0
*
*
= MSB
*
/CS
47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63
Mode 3
Mode 0
CLK
Data Byte 2
Data Byte 3
Data Byte 256
DI
(IO0)
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
*
*
*
Figure 31. Page Program with 4-Byte Address Instruction
- 51 -
W25M512JV
8.2.28 Quad Input Page Program (32h)
The Quad Page Program instruction allows up to 256 bytes of data to be programmed at previously erased
(FFh) memory locations using four pins: IO0, IO1, IO2, and IO3. The Quad Page Program can improve
performance for PROM Programmer and applications that have slow clock speeds <5MHz. Systems with
faster clock speed will not realize much benefit for the Quad Page Program instruction since the inherent
page program time is much greater than the time it take to clock-in the data.
To use Quad Page Program, a Write Enable instruction must be executed before the device will accept the
Quad Page Program instruction (Status Register-1, WEL=1). The instruction is initiated by driving the /CS
pin low then shifting the instruction code “32h” followed by a 24/32-bit address (A23/A31-A0) and at least
one data byte, into the IO pins. The /CS pin must be held low for the entire length of the instruction while
data is being sent to the device. All other functions of Quad Page Program are identical to standard Page
Program. The Quad Page Program instruction sequence is shown in Figure 32.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
IO0
Instruction (32h)
24-Bit Address
23 22 21
3
2
1
0
*
IO1
IO2
IO3
= MSB
*
/CS
31 32 33 34 35 36 37
Mode 3
Mode 0
CLK
Byte
253
Byte
254
Byte
255
Byte
256
Byte 1
Byte 2
Byte 3
0
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
0
1
2
3
4
5
6
0
1
2
3
4
0
1
2
3
4
0
1
2
3
IO0
IO1
IO2
IO3
5
6
5
6
5
6
7
7
7
7
7
7
7
*
*
*
*
*
*
*
Figure 32. Quad Input Page Program Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
Publication Release Date: September 06, 2017
- Revision D
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W25M512JV
8.2.29 Quad Input Page Program with 4-Byte Address (34h)
The Quad Input Page Program with 4-Byte Address instruction is similar to the Quad Input Page Program
instruction except that it requires 32-bit address instead of 24-bit address. No matter the device is operating
in 3-Byte Address Mode or 4-byte Address Mode, the Quad Input Page Program with 4-Byte Address
instruction will always require 32-bit address to access the entire 256Mb memory.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
36 37 38 39
CLK
IO0
Instruction (34h)
32-Bit Address
31 30 29
3
2
1
0
*
IO1
IO2
IO3
= MSB
*
/CS
39 40 41 42 43 44 45
Mode 3
Mode 0
CLK
Byte
253
Byte
254
Byte
255
Byte
256
Byte 1
Byte 2
Byte 3
0
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
5
6
0
1
2
3
4
0
1
2
3
4
5
6
0
1
2
3
4
0
1
2
3
4
0
1
2
3
IO0
IO1
IO2
IO3
5
6
5
6
5
6
7
7
7
7
7
7
7
*
*
*
*
*
*
*
Figure 33. Quad Input Page Program with 4-Byte Address Instruction
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W25M512JV
8.2.30 Sector Erase (20h)
The Sector Erase instruction sets all memory within a specified sector (4K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Sector Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “20h” followed a 24/32-bit sector address (A23/A31-A0). The Sector Erase
instruction sequence is shown in Figure 34.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Sector Erase instruction will not be executed. After /CS is driven high, the self-timed Sector Erase instruction
will commence for a time duration of tSE (See AC Characteristics). While the Sector Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Sector Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Sector Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Sector Erase instruction will not be executed if
the addressed page is protected by the Block Protect (CMP, TB, BP3, BP2, BP1, and BP0) bits or the
Individual Block/Sector Locks.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (20h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 34. Sector Erase Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
Publication Release Date: September 06, 2017
- Revision D
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W25M512JV
8.2.31 Sector Erase with 4-Byte Address (21h)
The Sector Erase with 4-Byte Address instruction is similar to the Sector Erase instruction except that it
requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address Mode
or 4-byte Address Mode, the Sector Erase with 4-Byte Address instruction will always require 32-bit address
to access the entire 256Mb memory.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
37 38 39
Mode 3
Mode 0
CLK
Instruction (21h)
32-Bit Address
DI
(IO0)
31 30
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 35. Sector Erase with 4-Byte Address Instruction
- 55 -
W25M512JV
8.2.32 32KB Block Erase (52h)
The Block Erase instruction sets all memory within a specified block (32K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “52h” followed a 24/32-bit block address (A23/A31-A0). The Block Erase
instruction sequence is shown in Figure 36.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE1 (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if
the addressed page is protected by the Block Protect (CMP, TB, BP3, BP2, BP1, and BP0) bits or the
Individual Block/Sector Locks.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (52h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 36. 32KB Block Erase Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
Publication Release Date: September 06, 2017
- Revision D
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W25M512JV
8.2.33 64KB Block Erase (D8h)
The Block Erase instruction sets all memory within a specified block (64K-bytes) to the erased state of all
1s (FFh). A Write Enable instruction must be executed before the device will accept the Block Erase
Instruction (Status Register bit WEL must equal 1). The instruction is initiated by driving the /CS pin low
and shifting the instruction code “D8h” followed a 24/32-bit block address (A23/A31-A0). The Block Erase
instruction sequence is shown in Figure 37.
The /CS pin must be driven high after the eighth bit of the last byte has been latched. If this is not done the
Block Erase instruction will not be executed. After /CS is driven high, the self-timed Block Erase instruction
will commence for a time duration of tBE (See AC Characteristics). While the Block Erase cycle is in
progress, the Read Status Register instruction may still be accessed for checking the status of the BUSY
bit. The BUSY bit is a 1 during the Block Erase cycle and becomes a 0 when the cycle is finished and the
device is ready to accept other instructions again. After the Block Erase cycle has finished the Write Enable
Latch (WEL) bit in the Status Register is cleared to 0. The Block Erase instruction will not be executed if
the addressed page is protected by the Block Protect (CMP, TB, BP3, BP2, BP1, and BP0) bits or the
Individual Block/Sector Locks.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (D8h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 37. 64KB Block Erase Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 57 -
W25M512JV
8.2.34 64KB Block Erase with 4-Byte Address (DCh)
The 64KB Block Erase with 4-Byte Address instruction is similar to the 64KB Block Erase instruction except
that it requires 32-bit address instead of 24-bit address. No matter the device is operating in 3-Byte Address
Mode or 4-byte Address Mode, the 64KB Block Erase with 4-Byte Address instruction will always require
32-bit address to access the entire 256Mb memory.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
37 38 39
Mode 3
Mode 0
CLK
Instruction (DCh)
32-Bit Address
DI
(IO0)
31 30
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 38. 64KB Block Erase with 4-Byte Address Instruction
Publication Release Date: September 06, 2017
- Revision D
- 58 -
W25M512JV
8.2.35 Single Die Chip Erase (C7h / 60h)
The Single Die Chip Erase instruction sets all memory area of an individual die stacked within W25M512JV
to the erased state of all 1s (FFh). A Write Enable instruction must be executed before the device will accept
the Single Die Chip Erase Instruction (Status Register bit WEL must equal 1). The instruction is initiated by
driving the /CS pin low and shifting the instruction code “C7h” or “60h”. The Single Die Chip Erase instruction
sequence is shown in Figure 39.
The /CS pin must be driven high after the eighth bit has been latched. If this is not done the Chip Erase
instruction will not be executed. After /CS is driven high, the self-timed Single Die Chip Erase instruction
will commence for a time duration of tCE (See AC Characteristics). While the Chip Erase cycle is in progress,
the Read Status Register instruction may still be accessed to check the status of the BUSY bit. The BUSY
bit is a 1 during the Chip Erase cycle and becomes a 0 when finished and the device is ready to accept
other instructions again. After the Chip Erase cycle has finished the Write Enable Latch (WEL) bit in the
Status Register is cleared to 0. The Chip Erase instruction will not be executed if any memory region is
protected by the Block Protect (CMP, TB, BP3, BP2, BP1, and BP0) bits or the Individual Block/Sector
Locks.
Multi-Die “Concurrent” Erase can be performed by issuing two separate “Single Die Chip Erase” instructions
respectively to the stacked dies. BUSY bit in each individual die’s Status Register can be polled to determine
if the internal Erase operation has finished or not.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (C7h/60h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 39. Single Die Chip Erase Instruction
- 59 -
W25M512JV
8.2.36 Erase / Program Suspend (75h)
The Erase/Program Suspend instruction “75h”, allows the system to interrupt a Sector or Block Erase
operation or a Page Program operation and then read from or program/erase data to, any other sectors or
blocks. The Erase/Program Suspend instruction sequence is shown in Figure 40.
The Write Status Register instruction (01h) and Erase instructions (20h, 52h, D8h, C7h, 60h, 44h) are not
allowed during Erase Suspend. Erase Suspend is valid only during the Sector or Block erase operation. If
written during the Chip Erase operation, the Erase Suspend instruction is ignored. The Write Status
Register instruction (01h) and Program instructions (02h, 32h, 42h) are not allowed during Program
Suspend. Program Suspend is valid only during the Page Program or Quad Page Program operation.
The Erase/Program Suspend instruction “75h” will be accepted by the device only if the SUS bit in the
Status Register equals to 0 and the BUSY bit equals to 1 while a Sector or Block Erase or a Page Program
operation is on-going. If the SUS bit equals to 1 or the BUSY bit equals to 0, the Suspend instruction will
be ignored by the device. A maximum of time of “tSUS” (See AC Characteristics) is required to suspend the
erase or program operation. The BUSY bit in the Status Register will be cleared from 1 to 0 within “tSUS
”
and the SUS bit in the Status Register will be set from 0 to 1 immediately after Erase/Program Suspend.
For a previously resumed Erase/Program operation, it is also required that the Suspend instruction “75h” is
not issued earlier than a minimum of time of “tSUS” following the preceding Resume instruction “7Ah”.
Unexpected power off during the Erase/Program suspend state will reset the device and release the
suspend state. SUS bit in the Status Register will also reset to 0. The data within the page, sector or block
that was being suspended may become corrupted. It is recommended for the user to implement system
design techniques against the accidental power interruption and preserve data integrity during
erase/program suspend state.
/CS
tSUS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (75h)
High Impedance
DI
(IO0)
DO
(IO1)
Accept instructions
Figure 40. Erase/Program Suspend Instruction
Publication Release Date: September 06, 2017
- Revision D
- 60 -
W25M512JV
8.2.37 Erase / Program Resume (7Ah)
The Erase/Program Resume instruction “7Ah” must be written to resume the Sector or Block Erase
operation or the Page Program operation after an Erase/Program Suspend. The Resume instruction “7Ah”
will be accepted by the device only if the SUS bit in the Status Register equals to 1 and the BUSY bit equals
to 0. After issued the SUS bit will be cleared from 1 to 0 immediately, the BUSY bit will be set from 0 to 1
within 200ns and the Sector or Block will complete the erase operation or the page will complete the
program operation. If the SUS bit equals to 0 or the BUSY bit equals to 1, the Resume instruction “7Ah” will
be ignored by the device. The Erase/Program Resume instruction sequence is shown in Figure 41.
Resume instruction is ignored if the previous Erase/Program Suspend operation was interrupted by
unexpected power off. It is also required that a subsequent Erase/Program Suspend instruction not to be
issued within a minimum of time of “tSUS” following a previous Resume instruction.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (7Ah)
DI
(IO0)
Resume previously
suspended Program or
Erase
Figure 41. Erase/Program Resume Instruction
- 61 -
W25M512JV
8.2.38 Read Device ID (ABh)
The Read Device ID instruction is used to obtain the Device ID for individual die. The instruction is initiated
by driving the /CS pin low and shifting the instruction code “ABh” followed by 3-dummy bytes. The Device
ID bits are then shifted out on the falling edge of CLK with most significant bit (MSB) first. The Device ID
value for individual die stacked in W25M512JV is listed in the Manufacturer and Device Identification table.
The Device ID can be read continuously. The instruction is completed by driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31 32 33 34 35 36 37 38
Mode 3
Mode 0
CLK
Instruction (ABh)
3 Dummy Bytes
DI
(IO0)
23 22
2
1
0
Device ID
*
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
= MSB
*
*
Figure 42. Read Device ID Instruction
Publication Release Date: September 06, 2017
- Revision D
- 62 -
W25M512JV
8.2.39 Read Manufacturer / Device ID (90h)
The Read Manufacturer/Device ID instruction is an alternative to the Read Device ID instruction that
provides both the JEDEC assigned manufacturer ID and the specific device ID.
The Read Manufacturer/Device ID instruction is very similar to the Read Device ID instruction. The
instruction is initiated by driving the /CS pin low and shifting the instruction code “90h” followed by a 24-bit
address (A23-A0) of 000000h. After which, the Manufacturer ID for Winbond (EFh) and the Device ID are
shifted out on the falling edge of CLK with most significant bit (MSB) first as shown in Figure 43. The Device
ID value for individual die stacked in W25M512JV is listed in the Manufacturer and Device Identification
table. The instruction is completed by driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (90h)
Address (000000h)
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
Mode 3
Mode 0
CLK
DI
(IO0)
0
DO
(IO1)
7
6
5
4
3
2
1
0
Manufacturer ID (EFh)
Device ID
*
Figure 43. Read Manufacturer / Device ID Instruction
- 63 -
W25M512JV
8.2.40 Read Manufacturer / Device ID Dual I/O (92h)
The Read Manufacturer / Device ID Dual I/O instruction is an alternative to the Read Manufacturer / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 2x
speed.
The Read Manufacturer / Device ID Dual I/O instruction is similar to the Fast Read Dual I/O instruction. The
instruction is initiated by driving the /CS pin low and shifting the instruction code “92h” followed by a 24/32-
bit address (A23/A31-A0) of 000000h, but with the capability to input the Address bits two bits per clock.
After which, the Manufacturer ID for Winbond (EFh) and the Device ID are shifted out 2 bits per clock on
the falling edge of CLK with most significant bits (MSB) first as shown in Figure 44. The Device ID value for
individual die stacked in W25M512JV is listed in the Manufacturer and Device Identification table. If the 24-
bit address is initially set to 000001h the Device ID will be read first and then followed by the Manufacturer
ID. The Manufacturer and Device IDs can be read continuously, alternating from one to the other. The
instruction is completed by driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
A23-16
A15-8
A7-0 (00h)
Dummy
Instruction (92h)
High Impedance
DI
(IO0)
6
4
2
0
1
6
4
2
0
1
6
4
2
0
1
DO
7
5
3
7
5
3
7
5
3
(IO1)
= MSB
*
*
*
*
/CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
Mode 3
Mode 0
CLK
IOs switch from
Input to Output
DI
(IO0)
6
4
5
2
0
6
4
5
2
3
0
1
6
4
5
2
3
0
1
6
4
5
2
3
0
1
DO
(IO1)
7
3
1
7
7
7
MFR ID
(repeat)
Device ID
(repeat)
*
MFR ID
*
Device ID
*
*
Figure 44. Read Manufacturer / Device ID Dual I/O Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
Publication Release Date: September 06, 2017
- Revision D
- 64 -
W25M512JV
8.2.41 Read Manufacturer / Device ID Quad I/O (94h)
The Read Manufacturer / Device ID Quad I/O instruction is an alternative to the Read Manufacturer / Device
ID instruction that provides both the JEDEC assigned manufacturer ID and the specific device ID at 4x
speed.
The Read Manufacturer / Device ID Quad I/O instruction is similar to the Fast Read Quad I/O instruction.
The instruction is initiated by driving the /CS pin low and shifting the instruction code “94h” followed by a
four clock dummy cycles and then a 24/32-bit address (A23/A31-A0) of 000000h, but with the capability to
input the Address bits four bits per clock. After which, the Manufacturer ID for Winbond (EFh) and the
Device ID are shifted out four bits per clock on the falling edge of CLK with most significant bit (MSB) first
as shown in Figure 45. The Device ID value for individual die stacked in W25M512JV is listed in the
Manufacturer and Device Identification table. If the 24-bit address is initially set to 000001h the Device ID
will be read first and then followed by the Manufacturer ID. The Manufacturer and Device IDs can be read
continuously, alternating from one to the other. The instruction is completed by driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
A7-0
(00h)
IOs switch from
Input to Output
A23-16
A15-8
Dummy
Dummy
Dummy
Instruction (94h)
4
5
6
7
0
1
2
3
4
0
1
2
3
4
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO0
IO1
IO2
IO3
High Impedance
High Impedance
High Impedance
5
6
7
5
6
7
MFR ID Device ID
/CS
23 24 25 26 27 28 29 30
Mode 3
Mode 0
CLK
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
IO0
IO1
IO2
IO3
MFR ID Device ID MFR ID Device ID
(repeat) (repeat) (repeat) (repeat)
Figure 45. Read Manufacturer / Device ID Quad I/O Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 65 -
W25M512JV
8.2.42 Read Unique ID Number (4Bh)
The Read Unique ID Number instruction accesses a factory-set read-only 64-bit number that is unique to
each individual die stacked in the W25M512JV package. The ID number can be used in conjunction with
user software methods to help prevent copying or cloning of a system. The Read Unique ID instruction is
initiated by driving the /CS pin low and shifting the instruction code “4Bh” followed by a four bytes of dummy
clocks. After which, the 64-bit ID is shifted out on the falling edge of CLK as shown in Figure 46.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK
Instruction (4Bh)
Dummy Byte 1
Dummy Byte 2
DI
(IO0)
High Impedance
DO
(IO1)
/CS
23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42
Mode 3
Mode 0
CLK
Dummy Byte 3
Dummy Byte 4
DI
(IO0)
High Impedance
DO
(IO1)
63 62 61
2
1
0
= MSB
64-bit Unique Serial Number
*
*
Figure 46. Read Unique ID Number Instruction
5 Dummy Bytes are required when the device is operating in 4-Byte Address Mode
Publication Release Date: September 06, 2017
- Revision D
- 66 -
W25M512JV
8.2.43 Read JEDEC ID (9Fh)
For compatibility reasons, the W25M512JV provides several instructions to electronically determine the
identity of the device. The Read JEDEC ID instruction is compatible with the JEDEC standard for SPI
compatible serial memories that was adopted in 2003. The instruction is initiated by driving the /CS pin low
and shifting the instruction code “9Fh”. The JEDEC assigned Manufacturer ID byte for Winbond (EFh) and
two Device ID bytes, Memory Type (ID15-ID8) and Capacity (ID7-ID0) are then shifted out on the falling
edge of CLK with most significant bit (MSB) first as shown in Figure 47. For memory type and capacity
values refer to Manufacturer and Device Identification table.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
CLK
Instruction (9Fh)
High Impedance
DI
(IO0)
Manufacturer ID (EFh)
DO
(IO1)
= MSB
*
/CS
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Mode 3
Mode 0
CLK
DI
(IO0)
Memory Type ID15-8
Capacity ID7-0
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
*
*
Figure 47. Read JEDEC ID Instruction
- 67 -
W25M512JV
8.2.44 Read SFDP Register (5Ah)
The W25M512JV features a 256-Byte Serial Flash Discoverable Parameter (SFDP) register that contains
information about device configurations, available instructions and other features. The SFDP parameters
are stored in one or more Parameter Identification (PID) tables. Currently only one PID table is specified,
but more may be added in the future. The Read SFDP Register instruction is compatible with the SFDP
standard initially established in 2010 for PC and other applications, as well as the JEDEC standard
JESD216 that is published in 2011. Most Winbond SpiFlash Memories shipped after June 2011 (date code
1124 and beyond) support the SFDP feature as specified in the applicable datasheet.
The Read SFDP instruction is initiated by driving the /CS pin low and shifting the instruction code “5Ah”
followed by a 24-bit address (A23-A0)(1) into the DI pin. Eight “dummy” clocks are also required before the
SFDP register contents are shifted out on the falling edge of the 40th CLK with most significant bit (MSB)
first as shown in Figure 48. For SFDP register values and descriptions, please refer to the Winbond
Application Note for SFDP Definition Table.
Note: 1. A23-A8 = 0; A7-A0 are used to define the starting byte address for the 256-Byte SFDP Register.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (5Ah)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Byte
DI
(IO0)
0
7
6
5
4
3
2
1
0
Data Out 1
Data Out 2
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
= MSB
*
*
*
Figure 48. Read SFDP Register Instruction
Only 24-Bit Address is required when the device is operating in either 3-Byte or 4-Byte Address Mode
Publication Release Date: September 06, 2017
- Revision D
- 68 -
W25M512JV
8.2.45 Erase Security Registers (44h)
The W25M512JV offers three 256-byte Security Registers which can be erased and programmed
individually. These registers may be used by the system manufacturers to store security and other important
information separately from the main memory array.
The Erase Security Register instruction is similar to the Sector Erase instruction. A Write Enable instruction
must be executed before the device will accept the Erase Security Register Instruction (Status Register bit
WEL must equal 1). The instruction is initiated by driving the /CS pin low and shifting the instruction code
“44h” followed by a 24/32-bit address (A23/A31-A0) to erase one of the three security registers.
ADDRESS
A23/A31-16
A15-12
A11-8
A7-0
Security Register #1
Security Register #2
Security Register #3
00h/0000h
00h/0000h
00h/0000h
0 0 0 1
0 0 1 0
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
Don’t Care
Don’t Care
Don’t Care
The Erase Security Register instruction sequence is shown in Figure 49. The /CS pin must be driven high
after the eighth bit of the last byte has been latched. If this is not done the instruction will not be executed.
After /CS is driven high, the self-timed Erase Security Register operation will commence for a time duration
of tSE (See AC Characteristics). While the Erase Security Register cycle is in progress, the Read Status
Register instruction may still be accessed for checking the status of the BUSY bit. The BUSY bit is a 1
during the erase cycle and becomes a 0 when the cycle is finished and the device is ready to accept other
instructions again. After the Erase Security Register cycle has finished the Write Enable Latch (WEL) bit in
the Status Register is cleared to 0. The Security Register Lock Bits (LB3-1) in the Status Register-2 can be
used to OTP protect the security registers. Once a lock bit is set to 1, the corresponding security register
will be permanently locked, Erase Security Register instruction to that register will be ignored (Refer to
section 7.1.8 for detail descriptions).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (44h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 49. Erase Security Registers Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 69 -
W25M512JV
8.2.46 Program Security Registers (42h)
The Program Security Register instruction is similar to the Page Program instruction. It allows from one
byte to 256 bytes of security register data to be programmed at previously erased (FFh) memory locations.
A Write Enable instruction must be executed before the device will accept the Program Security Register
Instruction (Status Register bit WEL= 1). The instruction is initiated by driving the /CS pin low then shifting
the instruction code “42h” followed by a 24/32-bit address (A23/A31-A0) and at least one data byte, into the
DI pin. The /CS pin must be held low for the entire length of the instruction while data is being sent to the
device.
ADDRESS
A23/A31-16
A15-12
A11-8
A7-0
Security Register #1
Security Register #2
Security Register #3
00h/0000h
00h/0000h
00h/0000h
0 0 0 1
0 0 1 0
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
Byte Address
Byte Address
Byte Address
The Program Security Register instruction sequence is shown in Figure 50. The Security Register Lock Bits
(LB3-1) in the Status Register-2 can be used to OTP protect the security registers. Once a lock bit is set to
1, the corresponding security register will be permanently locked, Program Security Register instruction to
that register will be ignored (See 7.1.8, 8.2.27 for detail descriptions).
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
CLK
Instruction (42h)
24-Bit Address
Data Byte 1
DI
(IO0)
23 22 21
3
2
1
0
7
6
5
4
3
2
1
0
*
*
= MSB
*
/CS
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Mode 3
Mode 0
CLK
Data Byte 2
Data Byte 3
Data Byte 256
DI
(IO0)
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
*
*
*
Figure 50. Program Security Registers Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
Publication Release Date: September 06, 2017
- Revision D
- 70 -
W25M512JV
8.2.47 Read Security Registers (48h)
The Read Security Register instruction is similar to the Fast Read instruction and allows one or more data
bytes to be sequentially read from one of the four security registers. The instruction is initiated by driving
the /CS pin low and then shifting the instruction code “48h” followed by a 24/32-bit address (A23/A31-A0)
and eight “dummy” clocks into the DI pin. The code and address bits are latched on the rising edge of the
CLK pin. After the address is received, the data byte of the addressed memory location will be shifted out
on the DO pin at the falling edge of CLK with most significant bit (MSB) first. The byte address is
automatically incremented to the next byte address after each byte of data is shifted out. Once the byte
address reaches the last byte of the register (byte address FFh), it will reset to address 00h, the first byte
of the register, and continue to increment. The instruction is completed by driving /CS high. The Read
Security Register instruction sequence is shown in Figure 51. If a Read Security Register instruction is
issued while an Erase, Program or Write cycle is in process (BUSY=1) the instruction is ignored and will
not have any effects on the current cycle. The Read Security Register instruction allows clock rates from
D.C. to a maximum of FR (see AC Electrical Characteristics).
ADDRESS
A23/A31-16
A15-12
A11-8
A7-0
Security Register #1
Security Register #2
Security Register #3
00h/0000h
00h/0000h
00h/0000h
0 0 0 1
0 0 1 0
0 0 1 1
0 0 0 0
0 0 0 0
0 0 0 0
Byte Address
Byte Address
Byte Address
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31
CLK
Instruction (48h)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
/CS
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
CLK
Dummy Byte
DI
(IO0)
0
7
6
5
4
3
2
1
0
Data Out 1
Data Out 2
High Impedance
DO
(IO1)
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
*
*
Figure 51. Read Security Registers Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 71 -
W25M512JV
8.2.48 Individual Block/Sector Lock (36h)
The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse
Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must
be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, TB, BP[3:0] bits
in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after
device power up or after a Reset are 1, so the entire memory array is being protected.
To lock a specific block or sector as illustrated in Figure 52, an Individual Block/Sector Lock instruction must
be issued by driving /CS low, shifting the instruction code “36h” into the Data Input (DI) pin on the rising
edge of CLK, followed by a 24/32-bit address and then driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (36h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 52. Individual Block/Sector Lock Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
Publication Release Date: September 06, 2017
- Revision D
- 72 -
W25M512JV
8.2.49 Individual Block/Sector Unlock (39h)
The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse
Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must
be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, TB, BP[3:0] bits
in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after
device power up or after a Reset are 1, so the entire memory array is being protected.
To unlock a specific block or sector as illustrated in Figure 53, an Individual Block/Sector Unlock instruction
must be issued by driving /CS low, shifting the instruction code “39h” into the Data Input (DI) pin on the
rising edge of CLK, followed by a 24/32-bit address and then driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
29 30 31
Mode 3
Mode 0
CLK
Instruction (39h)
24-Bit Address
DI
(IO0)
23 22
2
1
0
*
High Impedance
DO
(IO1)
= MSB
*
Figure 53. Individual Block Unlock Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
- 73 -
W25M512JV
8.2.50 Read Block/Sector Lock (3Dh)
The Individual Block/Sector Lock provides an alternative way to protect the memory array from adverse
Erase/Program. In order to use the Individual Block/Sector Locks, the WPS bit in Status Register-3 must
be set to 1. If WPS=0, the write protection will be determined by the combination of CMP, TB, BP[3:0] bits
in the Status Registers. The Individual Block/Sector Lock bits are volatile bits. The default values after
device power up or after a Reset are 1, so the entire memory array is being protected.
To read out the lock bit value of a specific block or sector as illustrated in Figure 54, a Read Block/Sector
Lock instruction must be issued by driving /CS low, shifting the instruction code “3Dh” into the Data Input
(DI) pin on the rising edge of CLK, followed by a 24/32-bit address. The Block/Sector Lock bit value will be
shifted out on the DO pin at the falling edge of CLK with most significant bit (MSB) first. If the least significant
bit (LSB) is 1, the corresponding block/sector is locked; if LSB=0, the corresponding block/sector is
unlocked, Erase/Program operation can be performed.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
28 29 30 31 32 33 34 35 36 37 38 39
Mode 3
Mode 0
CLK
Instruction (3Dh)
24-Bit Address
DI
(IO0)
23 22 21
3
2
1
0
*
Lock Value Out
High Impedance
DO
(IO1)
X
X
X
X
X
X
X
0
= MSB
*
*
Figure 54. Read Block Lock Instruction
32-Bit Address is required when the device is operating in 4-Byte Address Mode
Publication Release Date: September 06, 2017
- Revision D
- 74 -
W25M512JV
8.2.51 Global Block/Sector Lock (7Eh)
All Block/Sector Lock bits can be set to 1 by the Global Block/Sector Lock instruction. The instruction must
be issued by driving /CS low, shifting the instruction code “7Eh” into the Data Input (DI) pin on the rising
edge of CLK, and then driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (7Eh)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 55. Global Block Lock Instruction
8.2.52 Global Block/Sector Unlock (98h)
All Block/Sector Lock bits can be set to 0 by the Global Block/Sector Unlock instruction. The instruction
must be issued by driving /CS low, shifting the instruction code “98h” into the Data Input (DI) pin on the
rising edge of CLK, and then driving /CS high.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (98h)
High Impedance
DI
(IO0)
DO
(IO1)
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (98h)
High Impedance
DI
(IO0)
DO
(IO1)
Figure 56. Global Block Unlock Instruction
- 75 -
W25M512JV
8.2.53 Enable Reset (66h) and Reset Device (99h)
Because of the small package and the limitation on the number of pins, the W25M512JV provide a software
Reset instruction instead of a dedicated RESET pin. Once the Reset instruction is accepted, any on-going
internal operations will be terminated and the device will return to its default power-on state and lose all the
current volatile settings, such as Active Die status (Die #0 will be active as default after the reset), Volatile
Status Register bits, Write Enable Latch (WEL) status, Program/Erase Suspend status, Read parameter
setting (P7-P0), and Wrap Bit setting (W6-W4).
“Enable Reset (66h)” and “Reset (99h)” instructions must be issued in sequence to avoid accidental reset.
Any other instructions other than “Reset (99h)” after the “Enable Reset (66h)” instruction will disable the
“Reset Enable” state. A new sequence of “Enable Reset (66h)” and “Reset (99h)” is needed to reset the
device. Once the Reset instruction is accepted by the device, the device will take approximately tRST=30us
to reset. During this period, no instruction will be accepted.
Data corruption may happen if there is an on-going or suspended internal Erase or Program operation when
Reset instruction sequence is accepted by the device. It is recommended to check the BUSY bit and the
SUS bit in Status Register before issuing the Reset instruction sequence.
Each individual die stacked in the W25M512JV, regardless its Active or Idle status, will accept the Software
Reset sequence and perform the internal reset respectively.
/CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
0
1
2
3
4
5
6
7
Mode 3
Mode 0
CLK
Instruction (66h)
High Impedance
Instruction (99h)
DI
(IO0)
DO
(IO1)
Figure 57. Enable Reset and Reset Instruction Sequence
Publication Release Date: September 06, 2017
- Revision D
- 76 -
W25M512JV
9. ELECTRICAL CHARACTERISTICS
(1)
9.1 Absolute Maximum Ratings
PARAMETERS
Supply Voltage
SYMBOL
VCC
CONDITIONS
RANGE
UNIT
V
–0.6 to +4.6
Voltage Applied to Any Pin
Transient Voltage on any Pin
VIO
Relative to Ground
–0.6 to VCC+0.4
V
<20nS Transient
Relative to Ground
VIOT
–2.0 to VCC+2.0
V
Storage Temperature
TSTG
TLEAD
VESD
–65 to +150
See Note (2)
°C
°C
V
Lead Temperature
Electrostatic Discharge Voltage
Human Body Model(3)
–2000 to +2000
Notes:
1. This device has been designed and tested for the specified operation ranges. Proper operation outside
of these levels is not guaranteed. Exposure to absolute maximum ratings may affect device reliability.
Exposure beyond absolute maximum ratings may cause permanent damage.
2. Compliant with JEDEC Standard J-STD-20C for small body Sn-Pb or Pb-free (Green) assembly and the
European directive on restrictions on hazardous substances (RoHS) 2002/95/EU.
3. JEDEC Std JESD22-A114A (C1=100pF, R1=1500 ohms, R2=500 ohms).
9.2 Operating Ranges
SPEC
PARAMETER
SYMBOL CONDITIONS
UNIT
MIN
MAX
Supply Voltage
VCC
TA
FR = 104MHz,
Industrial
fR = 50MHz
2.7
3.6
V
Ambient Temperature,
Operating
–40
+85
°C
- 77 -
W25M512JV
9.3 Power-up Power-down Timing and Requirements
SPEC
PARAMETER
SYMBOL
UNIT
MAX
MIN
20
5
VCC (min) to /CS Low
tVSL(1)
tPUW(1)
VWI(1)
µs
Time Delay Before Write Instruction
Write Inhibit Threshold Voltage
ms
1.0
2.0
V
Note:
1. These parameters are characterized only.
VCC
VCC (max)
Program, Erase and Write Instructions are ignored
/CS must track VCC
VCC (min)
VWI
Read Instructions
Allowed
Device is fully
Accessible
tVSL
Reset
State
tPUW
Time
Figure 58a. Power-up Timing and Voltage Levels
/CS must track VCC
during VCC Ramp Up/Down
VCC
/CS
Time
Figure 58b. Power-up, Power-Down Requirement
Publication Release Date: September 06, 2017
- Revision D
- 78 -
W25M512JV
9.4 DC Electrical Characteristics(1)
SPEC
TYP
PARAMETER
SYMBOL CONDITIONS
UNIT
MAX
MIN
Input Capacitance
Output Capacitance
Input Leakage
CIN
Cout
ILI
VIN = 0V
6
8
pF
pF
µA
µA
VOUT = 0V
±4
±4
I/O Leakage
ILO
/CS = VCC,
VIN = GND or VCC
Standby Current
ICC1
ICC3
ICC3
20
120
20
µA
mA
mA
Current Read Data /
Dual /Quad 50MHz
C = 0.1 VCC / 0.9 VCC
DO = Open
(2)
Current Read Data /
Dual /Quad 80MHz
C = 0.1 VCC / 0.9 VCC
DO = Open
25
(2)
Current Read Data /
Dual Output Read/Quad
Output Read 104MHz
C = 0.1 VCC / 0.9 VCC
DO = Open
ICC3
30
mA
(2)
Current Write Status
Register
ICC4
ICC5
ICC6
/CS = VCC
/CS = VCC
/CS = VCC
/CS = VCC
20
20
20
20
25
25
25
mA
mA
mA
Current Page Program
Current Sector/Block
Erase
Current Chip Erase
Input Low Voltage
Input High Voltage
Output Low Voltage
Output High Voltage
ICC7
VIL
25
mA
V
–0.5
VCC x 0.3
VCC + 0.4
0.2
VIH
VCC x 0.7
V
VOL
VOH
IOL = 100 µA
V
IOH = –100 µA
VCC – 0.2
V
Notes:
1. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.0V.
2. Checker Board Pattern.
3. Depending on the specific concurrent operations, such as “Read while Program/Erase”, “Multi-die Program/Erase”.
- 79 -
W25M512JV
9.5 AC Measurement Conditions
SPEC
PARAMETER
SYMBOL
UNIT
MAX
MIN
Load Capacitance
CL
TR, TF
VIN
30
5
pF
ns
V
Input Rise and Fall Times
Input Pulse Voltages
0.1 VCC to 0.9 VCC
0.3 VCC to 0.7 VCC
0.5 VCC to 0.5 VCC
Input Timing Reference Voltages
Output Timing Reference Voltages
IN
V
OUT
V
Note:
1. Output Hi-Z is defined as the point where data out is no longer driven.
Input and Output
Timing Reference Levels
Input Levels
0.9 VCC
0.5 VCC
0.1 VCC
Figure 59. AC Measurement I/O Waveform
Publication Release Date: September 06, 2017
- Revision D
- 80 -
W25M512JV
9.6 AC Electrical Characteristics(4,5)
SPEC
DESCRIPTION
SYMBOL
ALT
UNIT
MIN
TYP
MAX
FR
fR
fC1
D.C.
104
MHz
MHz
Clock frequency for all other instructions
Clock frequency for Read Data instruction (03h)
D.C.
4
50
Clock High, Low Time
for all instructions except for Read Data (03h)
tCLH,
ns
ns
(1)
tCLL
Clock High, Low Time
for Read Data (03h) instruction
tCRLH,
tCRLL
8
(1)
(2)
Clock Rise Time peak to peak
Clock Fall Time peak to peak
0.1
0.1
V/ns
V/ns
tCLCH
(2)
tCHCL
/CS Active Setup Time relative to CLK
/CS Not Active Hold Time relative to CLK
Data In Setup Time
tSLCH
tCHSL
tDVCH
tCHDX
tCHSH
tSHCH
tSHSL1
tSHSL2
tCSS
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
tDSU
tDH
2
Data In Hold Time
3
/CS Active Hold Time relative to CLK
/CS Not Active Setup Time relative to CLK
/CS Deselect Time (During Read)
/CS Deselect Time (During Erase or Program or Write)
Output Disable Time
3
3
tCSH
tCSH
tDIS
10
50
(2)
7
7
tSHQZ
Clock Low to Output Valid
Output Hold Time
tCLQV
tCLQX
tV
ns
ns
tHO
1.5
Continued – next page
- 81 -
W25M512JV
AC Electrical Characteristics (cont’d)
SPEC
DESCRIPTION
SYMBOL
ALT
UNIT
MIN
TYP
MAX
3
(2)
/CS High to Standby Mode without ID Read
/CS High to Standby Mode with ID Read
µs
µs
tRES1
(2)
1.8
tRES2
(2)
/CS High to next Instruction after Suspend
/CS High to next Instruction after Reset
/RESET pin Low period to reset the device
Write Status Register Time
20
30
µs
µs
tSUS
(2)
tRST
1(3)
µs
(2)
tRESET
tW
10
0.7
50
15
3
ms
ms
ms
ms
ms
Page Program Time
tPP
Sector Erase Time (4KB)
tSE
400
1,600
2,000
Block Erase Time (32KB)
tBE1
tBE2
120
150
Block Erase Time (64KB)
Single Die Erase Time (256Mb)
Concurrent Dual-Die Erase Time (2 x 256Mb)
tCE
80
400
s
Notes:
1. Clock high + Clock low must be less than or equal to 1/fC.
2. Value guaranteed by design and/or characterization, not 100% tested in production.
3. It is possible to reset the device with shorter tRESET (as short as a few hundred ns), a 1us minimum is recommended to
ensure reliable operation.
4. Tested on sample basis and specified through design and characterization data. TA = 25° C, VCC = 3.0V.
5. 4-bytes address alignment for Quad Read, start address from [A1,A0]=(0,0).
Publication Release Date: September 06, 2017
- 82 -
- Revision D
W25M512JV
9.7 Serial Output Timing
/CS
tCLH
CLK
tCLQV
tCLQX
tCLQV
tCLL
tSHQZ
tCLQX
IO
output
MSB OUT
LSB OUT
9.8 Serial Input Timing
/CS
tSHSL
tSHCH
tCHSL
tSLCH
tCHSH
CLK
tDVCH
tCHDX
tCLCH
tCHCL
IO
input
MSB IN
LSB IN
- 83 -
W25M512JV
10. PACKAGE SPECIFICATIONS
10.1 8-Pad WSON 8x6-mm (Package Code E)
MILLIMETERS
SYMBOL
INCHES
Min
0.70
0.00
0.35
---
Nom
0.75
Max
0.80
0.05
0.48
---
Min
0.028
0.000
0.014
---
Nom
0.030
Max
0.031
0.002
0.019
---
A
A1
b
0.02
0.001
0.40
0.016
C
0.20 Ref.
8.00
0.008 Ref.
0.315
D
7.90
3.35
5.90
4.25
8.10
3.45
6.10
4.35
0.311
0.132
0.232
0.167
0.319
0.136
0.240
0.171
D2
E
3.40
0.134
6.00
0.236
E2
e
4.30
0.169
1.27 BSC
0.50
0.050 BSC
0.020
L
0.45
0.00
0.55
0.05
0.018
0.000
0.022
0.002
y
---
---
Publication Release Date: September 06, 2017
- Revision D
- 84 -
W25M512JV
10.2 16-Pin SOIC 300-mil (Package Code F)
Millimeters
Symbol
Inches
Nom
0.098
---
Min
2.36
0.10
---
Nom
2.49
---
Max
2.64
0.30
---
Min
0.093
0.004
---
Max
0.104
0.012
---
A
A1
A2
b
2.31
0.41
0.23
10.31
10.31
7.49
1.27 BSC
0.81
---
0.091
0.016
0.009
0.406
0.406
0.295
0.050 BSC
0.032
---
0.33
0.18
10.08
10.01
7.39
0.51
0.28
10.49
10.64
7.59
0.013
0.007
0.397
0.394
0.291
0.020
0.011
0.413
0.419
0.299
C
D
E
E1
e
L
0.38
---
1.27
0.076
8°
0.015
---
0.050
0.003
8°
y
θ
0°
---
0°
---
- 85 -
W25M512JV
10.3 24-Ball TFBGA 8x6-mm (Package Code B, 5x5-1 Ball Array)
Note:
Ball land: 0.45mm. Ball Opening: 0.35mm
PCB ball land suggested <= 0.35mm
Millimeters
Nom
Inches
Nom
Symbol
Min
---
Max
1.20
0.35
---
Min
---
Max
0.047
0.014
---
A
A1
A2
b
---
---
0.25
---
0.30
0.010
---
0.012
0.85
0.033
0.35
7.90
0.40
0.45
8.10
0.014
0.311
0.016
0.018
0.319
D
8.00
0.315
D1
E
4.00 BSC
6.00
0.157 BSC
0.236
5.90
6.10
0.232
0.240
E1
SE
SD
e
4.00 BSC
1.00 TYP
1.00 TYP
1.00 BSC
0.157 BSC
0.039 TYP
0.039 TYP
0.039 BSC
Publication Release Date: September 06, 2017
- Revision D
- 86 -
W25M512JV
10.4 24-Ball TFBGA 8x6-mm (Package Code C, 6x4 Ball Array)
Note:
Ball land: 0.45mm. Ball Opening: 0.35mm
PCB ball land suggested <= 0.35mm
Millimeters
Nom
Inches
Nom
Symbol
Min
---
Max
1.20
0.35
0.45
8.05
Min
---
Max
0.047
0.014
0.018
0.317
A
A1
b
---
---
0.25
0.35
7.95
0.30
0.010
0.014
0.313
0.012
0.40
0.016
D
8.00
0.315
D1
E
5.00 BSC
6.00
0.197 BSC
0.236
5.95
6.05
0.234
0.238
E1
e
3.00 BSC
1.00 BSC
0.118 BSC
0.039 BSC
- 87 -
W25M512JV
11.ORDERING INFORMATION
(1)
W 25M 512J V x I
W
= Winbond
25M
= Serial MCP SpiFlash Memory with SpiStack
512J
= 2 x 256M-bit
V
=
2.7V to 3.6V
F
B
=
=
16-pin SOIC 300-mil
24-ball TFBGA 8x6-mm (5x5 ball array)
E
C
=
=
8-pad WSON 8x6mm
24-ball TFBGA 8x6-mm (6x4 ball array)
I
=
Industrial (-40°C to +85°C)
(2,3)
Q
= Green Package (Lead-free, RoHS Compliant, Halogen-free (TBBA), Antimony-Oxide-free Sb2O3)
Notes:
1. The “W” prefix is not included on the part marking.
2. Standard bulk shipments are in Tube (shape E). Please specify alternate packing method, such as Tape and
Reel (shape T) or Tray (shape S), when placing orders.
3. For shipments with special order options, please specify when placing orders.
Publication Release Date: September 06, 2017
- 88 -
- Revision D
W25M512JV
11.1 Valid Part Numbers and Top Side Marking
The following table provides the valid part numbers for the W25M512JV SpiFlash Memory. Please contact
Winbond for specific availability by density and package type. Winbond SpiFlash memories use a 12-digit
Product Number for ordering. However, due to limited space, the Top Side Marking on all packages uses
an abbreviated 11-digit number.
PACKAGE TYPE
DENSITY
PRODUCT NUMBER
TOP SIDE MARKING
F
2 x 256M-bit
W25M512JVFIQ
25M512JVFIQ
SOIC-16 300mil
E
2 x 256M-bit
2 x 256M-bit
W25M512JVEIQ
W25M512JVBIQ
25M512JVEIQ
25M512JVBIQ
WSON-8 8x6mm
B
TFBGA-24 8x6mm
(5x5-1 Ball Array)
C
TFBGA-24 8x6mm
(6x4 Ball Array)
2 x 256M-bit
W25M512JVCIQ
25M512JVCIQ
- 89 -
W25M512JV
12. REVISION HISTORY
VERSION
DATE
PAGE
DESCRIPTION
New Create Preliminary
A
B
C
08/16/2014
01/04/2017
01/06/2017
Removed Preliminary
Updated ICC3 & tCLQV
79, 81
Removed ICC2 and tDP
Added tRES 1/2
79, 82
82
D
09/05/2017
Trademarks
Winbond, SpiFlash and SpiStack are trademarks of Winbond Electronics Corporation.
All other marks are the property of their respective owner.
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems
or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship
instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for
other applications intended to support or sustain life. Furthermore, Winbond products are not intended for
applications wherein failure of Winbond products could result or lead to a situation wherein personal injury,
death or severe property or environmental damage could occur. Winbond customers using or selling these
products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any
damages resulting from such improper use or sales.
Information in this document is provided solely in connection with Winbond products. Winbond
reserves the right to make changes, corrections, modifications or improvements to this document
and the products and services described herein at any time, without notice.
Publication Release Date: September 06, 2017
- 90 -
- Revision D
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