WED3DG648V-D1 [ETC]
SDRAM Modules - 144 Pin SO-DIMM. Unbuffered ; SDRAM模块 - 144针SO-DIMM 。无缓冲\n
| 型号： | WED3DG648V-D1 |
| 厂家： | 
ETC |
| 描述： | SDRAM Modules - 144 Pin SO-DIMM. Unbuffered
|
| 文件： | 总6页 (文件大小：157K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WED3DG648V-D1
64MB- 8Mx64 SDRAM, UNBUFFERED
FEATURES
DESCRIPTION
Burst Mode Operation
The WED3DG648V is a 8Mx64 synchronous DRAM module
which consists of eight 4Mx16 SDRAM components in TSOP- 11
package, and one 2K EEPROM in an 8- pin TSSOP package for
Serial Presence Detect which are mounted on a 144 Pin SO-DIMM
multilayer FR4 Substrate.
Auto and Self Refresh capability
LVTTL compatible inputs and outputs
Serial Presence Detect with EEPROM
Fully synchronous: All signals are registered on the positive
edge of the system clock
*
This product is subject to change without notice.
Programmable Burst Lengths: 1, 2, 4, 8 or Full Page
3.3 volt + 0.3v Power Supply
144 Pin SO-DIMM JEDEC
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN NAMES
Pin
1
Front
VSS
DQ0
DQ1
DQ2
DQ3
VDD
DQ4
DQ5
DQ6
DQ7
VSS
DQM0
DQM1
VDD
A0
Pin
2
Back
VSS
DQ32
DQ33
DQ34
DQ35
VDD
DQ36
DQ37
DQ38
DQ39
VSS
Pin
51
53
55
57
59
Front
DQ14
DQ15
VSS
NC
Pin
52
54
56
58
60
Back
DQ46
DQ47
VSS
NC
Pin
95
Back
DQ21
DQ22
DQ23
VDD
Pin
96
Back
DQ53
DQ54
DQ55
VDD
A0 – A11
BA0-1
DQ0-63
CLK0,CLK1
CKE0,CKE1
CS0,CS1
RAS
Address input (Multiplexed)
Select Bank
3
4
97
98
Data Input/Output
Clock input
5
6
8
99
100
102
104
106
108
110
112
114
116
118
120
122
124
126
128
130
132
134
136
138
140
142
144
7
101
103
105
107
109
111
113
115
117
119
121
123
125
127
129
131
133
135
137
139
141
143
Clock Enable input
Chip select Input
Row Address Strobe
Column Address Strobe
Write Enable
DQM
Power Supply (3.3V)
Ground
9
10
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
46
48
50
NC
NC
A6
A7
11
13
15
17
19
21
23
25
27
29
31
33
35
37
39
41
43
45
47
49
A8
BA0
VOLTAGE KEY
VSS
VSS
A9
BA1
CAS
61
63
65
67
69
71
73
75
77
79
81
83
85
87
89
91
93
CLK0
VDD
RAS
WE
CS0
CS1
62
64
66
68
70
72
74
76
78
80
82
84
86
88
90
92
94
CKE0
VDD
CAS
CKE1
*A12
*A13
CLK1
VSS
A10/AP
VDD
A11
WE
VDD
DQM0-7
VDD
DQM2
DQM3
VSS
DQ24
DQ25
DQ26
DQ27
VDD
DQ28
DQ29
DQ30
DQ31
VSS
**SDA
VDD
DQM6
DQM7
VSS
DQM4
DQM5
VDD
VSS
SDA
Serial data I/O
Serial clock
Do not use
No Connect
DQ56
DQ57
DQ58
DQ59
VDD
DQ60
DQ61
DQ62
DQ63
VSS
SCL
A3
DNU
VSS
NC
DNU
A1
A4
A2
A5
NC
NC
NC
VSS
DQ8
DQ9
DQ10
DQ11
VDD
DQ12
DQ13
VSS
NC
DQ40
DQ41
DQ42
DQ43
VDD
VDD
DQ16
DQ17
DQ18
DQ19
VSS
DQ20
VDD
DQ48
DQ49
DQ50
DQ51
VSS
*
These pins are not used in this module.
** These pins should be NC in the system which
does not support SPD.
DQ44
DQ45
**SCL
VDD
DQ52
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15457
1
WED3DG648V-D1
FUNCTIONAL BLOCK DIAGRAM
S1
WE
S0
WE
WE
WE
WE
DQMB0
DQMB4
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 4
I/O 5
I/O 6
I/O 4
I/O 5
I/O 6
I/O 7
I/O 4
I/O 5
I/O 6
I/O 7
D0
D4
D2
D6
I/O 7
DQMB1
DQMB5
I/O 8
I/O 9
I/O 8
I/O 9
I/O 8
I/O 9
I/O 8
I/O 9
I/O 10
I/O 11
I/O 10
I/O 11
I/O 10
I/O 11
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 12
I/O 13
I/O 14
I/O 15
I/O 12
I/O 13
I/O 14
I/O 15
I/O 12
I/O 13
I/O 14
I/O 15
DQMB2
DQMB6
WE
WE
WE
WE
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 0
I/O 1
I/O 2
I/O 3
I/O 4
I/O 5
I/O 6
I/O 7
I/O 4
I/O 4
I/O 5
I/O 6
I/O 7
I/O 4
I/O 5
I/O 6
I/O 7
D1
D5
I/O 5
I/O 6
I/O 7
D3
D7
DQMB3
DQMB7
I/O 8
I/O 9
I/O 8
I/O 9
I/O 8
I/O 9
I/O 8
I/O 9
I/O 10
I/O 11
I/O 10
I/O 11
I/O 10
I/O 11
I/O 10
I/O 11
I/O 12
I/O 13
I/O 14
I/O 15
I/O 12
I/O 13
I/O 14
I/O 15
I/O 12
I/O 13
I/O 14
I/O 15
I/O 12
I/O 13
I/O 14
I/O 15
*CLOCK WIRING
CLOCK
INPUT
SDRAMS
RAS
CAS
CKE0
CKE1
RAS: SDRAM D0-D7
CAS: SDRAM D0-D7
CKE: SDRAM D0-D3
*CLK0
*CLK1
4
4
SDRAMS
SDRAMS
CKE: SDRAM D4-D7
* Wire per clock Loading Table/Wiring Diagrams
BA0-BA1
A0-A11
BA0-BA1: SDRAM D0-D8
A0-A11: SDRAM D0-D8
SERIAL PD
SDA
SCL
VDD
D0-D7
D0-D7
A1
A2
A0
VSS
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
2
Sept. 2002 Rev. 0
ECO #15457
WED3DG648V-D1
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Value
Units
V
Voltage on any pin relative to VSS
Voltage on VDD supply relative to VSS
Storage Temperature
VIN, Vout
VDD, VDDQ
TSTG
-1.0 ~ 4.6
-1.0 ~ 4.6
-55 ~ +150
8
V
°C
W
Power Dissipation
PD
Short Circuit Current
IOS
50
mA
Note:
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
(Voltage Referenced to: VSS = 0V, TA = 0°C to +70°C)
Parameter
Symbol
VDD
VIH
Min
3.0
2.0
-0.3
2.4
—
Typ
3.3
3.0
—
Max
Unit
V
Note
Supply Voltage
3.6
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage Current
VDDQ+0.3
V
1
VIL
0.8
—
V
2
VOH
VOL
ILI
—
V
IOH= -2mA
IOL= -2mA
3
—
0.4
10
V
-10
—
µA
Note:
1. VIH (max)= 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. VIL (min)= -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ VIN ≤ VDDQ
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(TA = 23°C, f = 1MHz, VDD = 3.3V, VREF=1.4V 6200mV)
Parameter
Symbol
CIN1
CIN2
CIN3
CIN4
CIN5
CIN6
CIN7
Cout
Min
Max
25
25
25
21
25
12
25
12
Unit
pF
pF
pF
pF
pF
pF
pF
pF
Input Capacitance (A0-A12)
Input Capacitance (RAS,CAS,WE)
Input Capacitance (CKE0,CKE1)
Input Capacitance (CLK0,CLK1)
Input Capacitance (CS0,CS1)
Input Capacitance (DQM0-DQM7)
Input Capacitance (BA0-BA1)
Data input/output capacitance (DQ0-DQ63)
-
-
-
-
-
-
-
-
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15457
3
WED3DG648V-D1
OPERATING CURRENT CHARACTERISTICS
(VCC = 3.3V, TA = 0°C to +70°C)
1 Bank Version
Parameter
Symbol
ICC1
Conditions
Burst Length = 1
133
460
100Units Note
Operating Current
(One bank active)
400 mA
1
tRC ≥ tRC(min)
IOL = 0mA
Precharge Standby Current
in Power Down Mode
ICC2P
ICC2PS
Icc2N
CKE ≤ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tCC = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 10ns
Input signals are charged one time during 20
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
Input signals are stable
5
5
mA
Precharge Standby Current
in Non-Power Down Mode
60
Icc2NS
mA
mA
30
15
15
Active standby current in
power-down mode
ICC3P
ICC3PS
ICC3N
CKE ≥ VIL(max), tCC = 10ns
CKE & CLK ≤ VIL(max), tcc = ∞
CKE ≥ VIH(min), CS ≥ VIH(min), tcc = 10ns
Input signals are changed one time during 20ns
CKE ≥ VIH(min), CLK ≤ VIL(max), tcc = ∞
input signals are stable
Active standby current in
non power-down mode
110
80
mA
ICC3NS
mA
1
Io = mA
Operating current (Burst mode)
ICC4
Page burst
560
560
440 mA
4 Banks activated
tCCD = 2CLK
Refresh current
Self refresh current
ICC5
ICC6
tRC ≥ tRC(min)
500
mA
mA
2
CKE ≤ 0.2V
10
Notes:
1. Measured with outputs open.
2. Refresh period is 64ms.
3. Unless otherwise noticed, input swing level is CMOS (VIH/VIL = VDDQ/VssQ)
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
4
Sept. 2002 Rev. 0
ECO #15457
WED3DG648V-D1
Ordering Information
WED3DG648V10D1
WED3DG648V7D1
WED3DG648V75D1
Speed
100MHz
133MHz
133MHz
Cas Latency
CL=2
CL=2
CL=3
PACKAGE DIMENSIONS
.170
MAX.
ALL DIMENSIONS ARE IN INCHES
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
Sept. 2002 Rev. 0
ECO #15457
5
WED3DG648V-D1
REV.
A
DATE
11-15-01
6-25-02
REQUESTED BY
PAUL MARIEN
PAUL MARIEN
DETAILS
CREATED
B
-CORRECT PART NUMBER
ON THE ORDERING
INFORMATION TABLE
0
9-6-02
PAUL MARIEN
-CHANGE FROM ADVANCED
TO FINAL
White Electronic Designs Corporation • (508) 366-5151 • www.whiteedc.com
6
Sept. 2002 Rev. 0
ECO #15457
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