WM8734EDS [ETC]
STEREO AUDIO CODEC; 立体声音频编解码器
| 型号： | WM8734EDS |
| 厂家： | 
ETC |
| 描述： | STEREO AUDIO CODEC |
| 文件： | 总42页 (文件大小：413K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WM8734
w
Stereo Audio CODEC
DESCRIPTION
FEATURES
•
Audio Performance
The WM8734 is a low power stereo CODEC ideal for MD,
CD-RW machines and DAT recording applications.
−
−
−
−
90dB SNR (‘A’ weighted @ 48kHz) ADC
100dB SNR (‘A’ weighted @ 48kHz) DAC
Stereo line inputs are provided, along with a mute function
and programmable line level volume control.
2.7 – 3.6V Digital Supply Operation
2.7 – 3.6V Analogue Supply Operation
Stereo 24-bit multi-bit sigma delta ADCs and DACs are
used with oversampling digital interpolation and decimation
filters.
•
•
•
•
ADC and DAC Sampling Frequency: 8kHz – 96kHz
Selectable ADC High Pass Filter
2 or 3-Wire MPU Serial Control Interface
Programmable Audio Data Interface Modes
Digital audio input word lengths from 16-32 bits and
sampling rates from 8kHz to 96kHz are supported.
−
−
−
I2S, Left, Right Justified or DSP
16/20/24/32 bit Word Lengths
Master or Slave Clocking Mode
Stereo audio line level outputs are provided along with anti-
thump mute and power up/down circuitry.
The device is controlled via a 2 or 3 wire serial interface.
The interface provides access to all features including level
controls, mutes, de-emphasis and power management
facilities. The device is available in 20-pin SSOP or 5x5mm
QFN packages.
•
•
Stereo Audio Inputs and Outputs
20-Pin SSOP or 5x5mm QFN Package Options
APPLICATIONS
•
•
CD and Minidisc Recorder
MP3 Player / Recorder
BLOCK DIAGRAM
AVDD
CONTROL INTERFACE
VMID
W
WM8734
AGND
VOL
MUTE
ADC
ADC
DAC
DAC
ROUT
LOUT
RLINEIN
LLINEIN
+12 to -34.5dB,
1.5dB Steps
DIGITAL
FILTERS
VOL
MUTE
+12 to -34.5dB,
1.5dB Steps
CLKIN
DIVIDER
(Div x1, x2)
DIGTAL AUDIO INTERFACE
WOLFSON MICROELECTRONICS LTD
Advanced Information, November 2001, Rev 2.2
Copyright 2001 Wolfson Microelectronics Ltd.
www.wolfsonmicro.com
WM8734
Advanced Information
PIN CONFIGURATION – SSOP
ORDERING INFORMATION - SSOP
DEVICE
TEMP. RANGE
PACKAGE
-10 to +70oC
20-pin SSOP
20
19
18
17
16
15
14
13
12
11
DGND
DBVDD
BCLK
1
2
DCVDD
MCLK
SCLK
SDIN
XWM8734EDS
3
DACDAT
DACLRC
ADCDAT
4
5
CSB
6
MODE
7
LLINEIN
RLINEIN
ADCLRC
LOUT
8
ROUT
AVDD
9
VMID
10
AGND
PIN DESCRIPTION - SSOP
PIN
1
NAME
DGND
TYPE
Ground
Supply
DESCRIPTION
Digital GND
Digital Buffers VDD
2
DBVDD
BCLK
3
Digital Input/Output Digital Audio Bit Clock, Pull Down, (see Note 1)
Digital Input
DAC Digital Audio Data Input
Digital Input/Output DAC Sample Rate Left/Right Clock. Pull Down (see Note 1)
Digital Output
ADC Digital Audio Data Output
Digital Input/Output ADC Sample Rate Left/Right Clock, Pull Down (see Note 1)
4
DACDAT
DACLRC
ADCDAT
ADCLRC
LOUT
5
6
7
8
Analogue Output
Analogue Output
Supply
Left Channel Line Output
9
ROUT
Right Channel Line Output
10
11
12
13
14
15
16
AVDD
Analogue VDD
AGND
Ground
Analogue GND
VMID
Analogue Output
Analogue Input
Analogue Input
Digital Input
Mid-rail reference decoupling point
Right Channel Line Input (AC coupled)
Left Channel Line Input (AC coupled)
Control Interface Selection, Pull Up (see Note 1)
RLINEIN
LLINEIN
MODE
CSB
Digital Input
3-Wire MPU Chip Select / 2-Wire MPU interface address selection, active low,
Pull up (see Note 1)
17
18
19
20
SDIN
SCLK
Digital Input/Output 3-Wire MPU Data Input / 2-Wire MPU Data Input
Digital Input
Digital Input
Supply
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
Master Clock Input (MCLK)
MCLK
DCVDD
Digital Core VDD
Note:
1. Pull Up/Down only present when Control Register Interface ACTIVE = 0 to conserve power.
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WM8734
Advanced Information
PIN CONFIGURATION – QFN
ORDERING INFORMATION - QFN
DEVICE
TEMP. RANGE
PACKAGE
28-pin QFN
XWM8734EFL
-10 to +70oC
(5x5x0.9mm)
21 20 19 18 17 16 15
14
NC
NC 22
13 NC
23
24
25
26
27
28
RLINEIN
LLINEIN
MODE
CSB
12 NC
11 ADCLRC
10 ADCDAT
9
SDIN
SCLK
DACLRC
8
DACDAT
1
2
3
4
5
6
7
PIN DESCRIPTION - QFN
PIN
1
NAME
MCLK
NC
TYPE
DESCRIPTION
Digital Input
Do Not Connect
Supply
Master Clock Input (MCLK)
Test Pin, must be left unconnected
Digital Core VDD
2
3
DCVDD
DGND
DBVDD
NC
4
Ground
Digital GND
5
Supply
Digital Buffers VDD
6
Do Not Connect
Test Pin, must be left unconnected
7
BCLK
DACDAT
DACLRC
ADCDAT
ADCLRC
NC
Digital Input/Output Digital Audio Bit Clock, Pull Down, (see Note 1)
Digital Input
DAC Digital Audio Data Input
Digital Input/Output DAC Sample Rate Left/Right Clock. Pull Down (see Note 1)
Digital Output
ADC Digital Audio Data Output
Digital Input/Output ADC Sample Rate Left/Right Clock, Pull Down (see Note 1)
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Do Not Connect
Do Not Connect
Do Not Connect
Do Not Connect
Analogue Output
Analogue Output
Supply
Test Pin, must be left unconnected
Test Pin, must be left unconnected
Test Pin, must be left unconnected
Test Pin, must be left unconnected
Left Channel Line Output
NC
NC
NC
LOUT
ROUT
AVDD
AGND
VMID
NC
Right Channel Line Output
Analogue VDD
Ground
Analogue GND
Analogue Output
Do Not Connect
Do Not Connect
Analogue Input
Analogue Input
Digital Input
Mid-rail reference decoupling point
Test Pin, must be left unconnected
Test Pin, must be left unconnected
Right Channel Line Input (AC coupled)
Left Channel Line Input (AC coupled)
Control Interface Selection, Pull Up (see Note 1)
NC
RLINEIN
LLINEIN
MODE
CSB
Digital Input
3-Wire MPU Chip Select / 2-Wire MPU interface address selection, active low,
Pull up (see Note 1)
27
28
SDIN
SCLK
Digital Input/Output 3-Wire MPU Data Input / 2-Wire MPU Data Input
Digital Input
3-Wire MPU Clock Input / 2-Wire MPU Clock Input
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WM8734
Advanced Information
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
CONDITION
MIN
-0.3V
MAX
+3.63V
Digital supply voltage
Analogue supply voltage
-0.3V
+3.63V
Voltage range digital inputs
DGND -0.3V
AGND -0.3V
DVDD +0.3V
AVDD +0.3V
40MHz
Voltage range analogue inputs
Master Clock Frequency (see Note 4)
Operating temperature range, TA
Storage temperature prior to soldering
Storage temperature after soldering
Package body temperature (soldering 10 seconds)
Package body temperature (soldering 2 minutes)
-10°C
+70°C
30°C max / 85% RH max
-65°C
+150°C
+240°C
+183°C
Notes:
1. Analogue and digital grounds must always be within 0.3V of each other.
2. The digital supply core voltage (DCVDD) must always be less than or equal to the analogue supply voltage (AVDD) or
digital supply buffer voltage (DBVDD).
3. The digital supply buffer voltage (DBVDD) must always be less than or equal to the analogue supply voltage (AVDD).
4. When CLKIDIV2=1.
RECOMMENDED OPERATING CONDITIONS
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital supply range (Core)
Digital supply range (Buffer)
Analogue supply range
Ground
DCVDD
DBVDD
2.7
2.7
2.7
3.3
3.3
3.3
0
3.6
3.6
3.6
V
V
AVDD
V
DGND, AGND
IAVDD
V
Total analogue supply current
DCVDD, DBVDD,
AVDD = 3.3V
16
mA
Digital supply current
IDCVDD, IDBVDD
DCVDD, DBVDD
AVDD = 3.3V
8
5
mA
uA
Standby Current Consumption
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WM8734
Advanced Information
ELECTRICAL CHARACTERISTICS
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Digital Logic Levels (CMOS Levels)
Input LOW level
VIL
VIH
VOL
0.3 x DBVDD
V
V
V
Input HIGH level
0.7 x DBVDD
0.9 x DBVDD
Output LOW
0.10 x
DBVDD
Output HIGH
VOH
V
Power On Reset Threshold (DCVDD)
DCVDD Threshold On -> Off
Hysteresis
Vth
VIH
VOL
0.9
0.3
0.6
V
V
V
DCVDD Threshold Off -> On
Analogue Reference Levels
Reference voltage
VVMID
RVMID
AVDD/2
50k
V
Potential divider resistance
Line Input to ADC
Ohms
Input Signal Level (0dB)
VINLINE
1.0
AVDD/3.3
90
Vrms
SNR (Note 1,3)
SNR (Note 1,3)
SNR (Note 1,3)
A-weighted, 0dB gain
@ fs = 48kHz
85
85
dB
dB
dB
A-weighted, 0dB gain
@ fs = 96kHz
90
88
A-weighted, 0dB gain
@ fs = 48KHz, AVDD =
2.7V
Dynamic Range (Note 3)
DNR
A-weighted, -60dB full
scale input
90
dB
THD
-1dB input, 0dB gain
1kHz 100mVpp
-84
50
45
-74
dB
dB
dB
Power Supply Rejection Ratio
PSSR
20Hz to 20kHz
100mVpp
ADC channel separation
Programmable Gain Maximum
Programmable Gain Minimum
Programmable Gain Step Size
Mute attenuation
1kHz input
1kHz input
90
+12
-34.5
1.5
dB
dB
Rsource < 50 Ohms
Guaranteed Monotonic
0dB, 1kHz input
0dB gain
dB
dB
80
Input Resistance
RINLINE
CINLINE
20k
10k
30k
15k
10
Ohms
Ohms
pF
12dB gain
Input Capacitance
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WM8734
Advanced Information
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Vrms
dB
Line Output for DAC Playback Only (Load = 47k ohms. 50pF)
0dBfs Full scale output voltage
SNR (Note 1,2,3)
At LINE outputs
1.0 x
AVDD/3.3
100
A-weighted,
@ fs = 48kHz
A-weighted
90
SNR (Note 1,2,3)
98
93
dB
@ fs = 96kHz
A-weighted,
@ fs = 48kHz,
AVDD = 2.7V
SNR (Note 1,2,3)
dB
Dynamic Range (Note 3)
THD
DNR
A-weighted, -60dB full
scale input
85
95
dB
1kHz, 0dBfs
1kHz, -3dBfs
1kHz 100mVpp
-88
-92
50
-80
dB
dB
dB
dB
Power Supply Rejection Ratio
PSSR
20Hz to 20kHz
100mVpp
45
DAC channel separation
100
dB
Notes:
1. Ratio of output level with 1kHz full scale input, to the output level with the input short circuited, measured ‘A’ weighted
over a 20Hz to 20kHz bandwidth using an Audio analyser.
2. Ratio of output level with 1kHz full scale input, to the output level with all zeros into the digital input, measured ‘A’
weighted over a 20Hz to 20kHz bandwidth.
3. All performance measurements done with 20kHz low pass filter, and where noted an A-weight filter. Failure to use
such a filter will result in higher THD+N and lower SNR and Dynamic Range readings than are found in the Electrical
Characteristics. The low pass filter removes out of band noise; although it is not audible it may affect dynamic
specification values.
4. VMID decoupled with 10uF and 0.1uF capacitors (smaller values may result in reduced performance).
TERMINOLOGY
1. Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output
with no signal applied. (No Auto-zero or Automute function is employed in achieving these results).
2. Dynamic range (dB) - DNR is a measure of the difference between the highest and lowest portions of a signal.
Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB
to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB).
3. THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal.
4. Stop band attentuation (dB) – Is the degree to which the frequency spectrum is attenuated (outside audio band).
5. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from
the other. Normally measured by sending a full scale signal down one channel and measuring the other.
6. Pass-Band Ripple – Any variation of the frequency response in the pass-band region.
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WM8734
Advanced Information
MASTER CLOCK TIMING
tMCLKL
MCLK
t MCLKH
t MCLKY
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
System Clock Timing Information
MCLK System clock pulse width high
MCLK System clock pulse width low
MCLK System clock cycle time
MCLK Duty cycle
TXTIH
TXTIL
TXTIY
18
18
ns
ns
ns
54
40:60
60:40
DIGITAL AUDIO INTERFACE – MASTER MODE
BCLK
ADCLRC
WM8734
DSP
ENCODER/
DECODER
DACLRC
CODEC
ADCDAT
DACDAT
Figure 2 Master Mode Connection
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WM8734
Advanced Information
BCLK
(Output)
tDL
ADCLRC/
DACLRC
(Outputs)
tDDA
ADCDAT
DACDAT
tDST
tDHT
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
ADCLRC/DACLRC
propagation delay from
BCLK falling edge
tDL
0
10
ns
ADCDAT propagation delay
from BCLK falling edge
tDDA
tDST
tDHT
0
10
ns
ns
ns
DACDAT setup time to
BCLCK rising edge
10
10
DACDAT hold time from
BCLK rising edge
DIGITAL AUDIO INTERFACE – SLAVE MODE
BCLK
ADCLRC
WM8734
DSP
ENCODER/
DECODER
DACLRC
CODEC
ADCDAT
DACDAT
Figure 4 Slave Mode Connection
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WM8734
Advanced Information
tBCH
tBCL
BCLK
tBCY
DACLRC/
ADCLRC
tLRSU
tDS
tLRH
DACDAT
ADCDAT
tDD
tDH
Figure 5 Digital Audio Data Timing – Slave Mode
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Audio Data Input Timing Information
BCLK cycle time
tBCY
tBCH
tBCL
50
20
20
10
ns
ns
ns
ns
BCLK pulse width high
BCLK pulse width low
DACLRC/ADCLRC set-up
time to BCLK rising edge
tLRSU
DACLRC/ADCLRC hold
time from BCLK rising edge
tLRH
tDS
tDH
tDD
10
10
10
0
ns
ns
ns
ns
DACDAT set-up time to
BCLK rising edge
DACDAT hold time from
BCLK rising edge
ADCDAT propagation delay
from BCLK falling edge
10
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Advanced Information
MPU INTERFACE TIMING
tCSL
tCSH
CSB
tSCY
tCSS
tSCS
tSCH
tSCL
SCLK
SDIN
LSB
tDSU
tDHO
Figure 6 Program Register Input Timing – 3-Wire MPU Serial Control Mode
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising
edge
tSCS
60
ns
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
80
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
CSB pulse width high
CSB rising to SCLK rising
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Advanced Information
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t7
t1
t10
Figure 7 Program Register Input Timing – 2-Wire MPU Serial Control Mode
Test Conditions
AVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 3.3V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
400
kHz
ns
us
ns
ns
ns
ns
ns
ns
ns
SCLK Low Pulsewidth
SCLK High Pulsewidth
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
t1
t2
t3
t4
t5
t6
t7
t8
t10
600
1.3
600
600
100
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
300
300
600
900
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Advanced Information
DEVICE DESCRIPTION
The WM8734 is a high performance audio CODEC designed specifically for audio applications that
require recording and playback features.
The CODEC includes line inputs to the on-board ADC, line outputs from the on-board DAC, a
configurable digital audio interface and a choice of 2 or 3 wire MPU control interface. It is fully
compatible and an ideal partner for a range of industry standard microprocessors, controllers and
DSPs.
The CODEC includes a stereo low noise input. Line inputs have +12dB to -34dB logarithmic volume
level adjustments and mute. All the required input filtering is contained within the device.
The on-board stereo analogue to digital converter (ADC) is of a high quality using a multi-bit high-
order oversampling architecture delivering optimum performance with low power consumption. The
output from the ADC is available on the digital audio interface. The ADC includes an optional digital
high pass filter to remove unwanted dc components from the audio signal.
The on-board digital to analogue converter (DAC) accepts digital audio from the digital audio
interface. Digital filter de-emphasis at 32kHz, 44.1kHz and 48kHz can be applied to the digital data
under software control. The DAC employs a high quality multi-bit high-order oversampling
architecture to again deliver optimum performance with low power consumption.
Special techniques allow the audio to be muted and the device safely placed into standby, sections
of the device powered off and volume levels adjusted without any audible clicks, pops or zipper
noises. Therefore standby and power off modes may be used dynamically under software control,
whenever recording or playback is not required.
The device caters for a number of different sampling rates including industry standard 8kHz, 32kHz,
44.1kHz, 48kHz, 88.2kHz and 96kHz. The digital filters used for both record and playback are
optimised for each sampling rate used.
The digitised output is available in a number of audio data formats I2S, DSP Mode (a burst mode in
which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First,
right justified. The digital audio interface can operate in both master or slave modes.
The software control uses either a 2 or 3-wire MPU interface.
AUDIO SIGNAL PATH
LINE INPUTS
The WM8734 provides Left and Right channel line inputs (RLINEIN and LLINEIN). The inputs are
high impedance and low capacitance, thus ideally suited to receiving line level signals from external
hi-fi or audio equipment.
Both line inputs include independent programmable volume level adjustments and input mute. The
scheme is illustrated in Figure 8. Passive RF and active Anti-Alias filters are also incorporated within
the line inputs. These prevent high frequencies aliasing into the audio band or otherwise degrading
performance.
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Advanced Information
LINEIN
12.5K
To
ADC
VMID
Figure 8 Line Input Schematic
The gain between the line inputs and the ADC is logarithmically adjustable from +12dB to –34.5dB in
1.5dB steps under software control. The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any
voltage greater than full scale will possibly overload the ADC and cause distortion. Note that the full
scale input tracks directly with AVDD. The gain is independently adjustable on both Right and Left
Line Inputs. However, by setting the INBOTH bit whilst programming the volume control, both
channels are simultaneously updated with the same value. Use of INBOTH reduces the required
number of software writes required. The line inputs to the ADC can be muted in the analogue domain
under software control. The software control registers are shown below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000000
4:0
LINVOL[4:0]
10111
( 0dB )
Left Channel Line Input Volume
Control
Left Line In
11111 = +12dB . . 1.5dB steps down
to 00000 = -34.5dB
7
8
LINMUTE
1
0
Left Channel Line Input Mute to ADC
1 = Enable Mute
0 = Disable Mute
LRINBOTH
Left to Right Channel Line Input
Volume and Mute Data Load Control
1 = Enable Simultaneous Load of
LINVOL[4:0] and LINMUTE to
RINVOL[4:0] and RINMUTE
0 = Disable Simultaneous Load
0000001
4:0
7
RINVOL[4:0]
RINMUTE
10111
( 0dB )
Right Channel Line Input Volume
Control
Right Line In
11111 = +12dB . .1.5dB steps down
to 00000 = -34.5dB
1
0
Right Channel Line Input Mute to
ADC
1 = Enable Mute
0 = Disable Mute
8
RLINBOTH
Right to Left Channel Line Input
Volume and Mute Data Load Control
1 = Enable Simultaneous Load of
RINVOL[4:0] and RINMUTE to
LINVOL[4:0] and LINMUTE
0 = Disable Simultaneous Load
Table 1 Line Input Software Control
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Advanced Information
The line inputs are biased internally through the operational amplifier to VMID. Whenever the line
inputs are muted or the device placed into standby mode, the line inputs are kept biased to VMID
using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when
re-activating the inputs.
The external components required to complete the line input application is shown in the Figure 9.
C2
R1
LINEIN
C1
R2
AGND
AGND AGND
Figure 9 Line Input Application Drawing
For interfacing to a typical CD system, it is recommended that the input is scaled to ensure that there
is no clipping of the signal. R1 = 5K, R2 = 5K, C1 = 47pF, C2 = 470nF (10V npo ceramic type).
R1 and R2 form a resistive divider to attenuate the 2 Vrms output from a CD player to a 1 Vrms level,
so avoiding overloading the inputs. R2 also provides a discharge path for C2, thus preventing the
input to C2 charging to an excessive voltage which may otherwise damage any equipment connected
that is not suitably protected against high voltages. C1 forms an RF low pass filter for increasing the
rejection of RF interference picked up on any cables. C2 forms a DC blocking capacitor to remove
the DC path between the WM8734 and the driving audio equipment. C2 together with the input
impedance of the WM8734 form a high pass filter.
ADC
The WM8734 uses a multi-bit oversampled sigma-delta ADC. A single channel of the ADC is
illustrated in the Figure 10.
ANALOG
FROM LINE INPUT
TO ADC DIGITAL FILTERS
INTEGRATOR
MULTI
BITS
Figure 10 Multi-Bit Oversampling Sigma Delta ADC Schematic
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The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high
frequency noise.
The ADC Full Scale input is 1.0V rms at AVDD = 3.3 volts. Any voltage greater than full scale will
possibly overload the ADC and cause distortion. Note that the full scale input tracks directly with
AVDD. The device employs a pair of ADCs. The two channels cannot be selected independently.
The digital data from the ADC is fed for signal processing to the ADC Filters.
ADC FILTERS
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data
from the ADC to the correct sampling frequency to be output on the digital audio interface. Figure 11
illustrates the digital filter path.
TO DIGITAL
AUDIO
INTERFACE
DIGITAL
DIGITAL
DIGITAL
HPF
DECIMATION
FILTER
FROM ADC
DECIMATOR
HPFEN
Figure 11 ADC Digital Filter
The ADC digital filters contain a digital high pass filter, selectable via software control. The high-pass
filter response detailed in Digital Filter Characteristics. When the high-pass filter is enabled the dc
offset is continuously calculated and subtracted from the input signal. By setting HPOR the last
calculated dc offset value is stored when the high-pass filter is disabled and will continue to be
subtracted from the input signal. If the dc offset changed, the stored and subtracted value will not
change unless the high-pass filter is enabled. The software control is shown in Table 2.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
00000101
0
ADCHPD
0
ADC High Pass Filter Enable
(Digital)
Digital Audio
Path Control
1 = Disable High Pass Filter
0 = Enable High Pass Filter
4
HPOR
0
Store dc offset when High Pass
Filter disabled
1 = store offset
0 = clear offset
Table 2 ADC Software Control
There are several types of ADC filters, frequency and phase responses of these are shown in Digital
Filter Characteristics. The filter types are automatically configured depending on the sample rate
chosen. Refer to the sample rate section for more details.
DAC FILTERS
The DAC filters perform true 24 bit signal processing to convert the incoming digital audio data from
the digital audio interface at the specified sample rate to multi-bit oversampled data for processing by
the analogue DAC. Figure 12 illustrates the DAC digital filter path.
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FROM DIGITAL
AUDIO
INTERFACE
DIGITAL
INTERPOLATION
FILTER
TO LINE
OUTPUTS
DIGITAL
DE_EMPHASIS
MUTE
DEEMP
DACMU
Figure 12 DAC Filter Schematic
The DAC digital filter can apply digital de-emphasis under software control, as shown in Table 3. The
DAC can also perform a soft mute where the audio data is digitally brought to a mute level. This
removes any abrupt step changes in the audio that might otherwise result in audible clicks in the
audio outputs.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000101
2:1
DEEMP[1:0]
00
De-emphasis Control
(Digital)
Digital Audio
Path Control
11 = 48KHz
10 = 44.1KHz
01 = 32KHz
00 = Disable
3
DACMU
1
DAC Soft Mute Control
(Digital)
1 = Enable soft mute
0 = Disable soft mute
Table 3 DAC Software Control
DAC
The WM8734 employs a multi-bit sigma delta oversampling digital to analogue converter. The
scheme for the converter is illustrated in Figure 13.
FROM DAC
DIGITAL
FILTERS
TO LINE OUTPUT
Figure 13 Multi-Bit Oversampling Sigma Delta Schematic
The DAC converts the multi-level digital audio data stream from the DAC digital filters into high
quality analogue audio.
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LINE OUTPUTS
The WM8734 provides two low impedance line outputs LLINEOUT and RLINEOUT, suitable for
driving typical line loads of impedance 10K and capacitance 50pF. The line output is used to
selectively sum the outputs from the DAC or/and the Line inputs in bypass mode.
The LLINEOUT and RLINEOUT outputs are only available at a line output level and are not level
adjustable in the analogue domain, having a fixed gain of 0dB. The level is fixed such that at the DAC
full scale level the output level is Vrms at AVDD = 3.3 volts. Note that the DAC full scale level tracks
directly with AVDD. The scheme is shown in Figure 14. The line output includes a low order audio
low pass filter for removing out-of band components from the sigma-delta DAC. Therefore no further
external filtering is required in most applications.
DACSEL
FROM DAC
LINEOUT
VMID
TO HEADPHONE AMP
Figure 14 Line Output Schematic
The line output is muted by either muting the DAC (analogue) or Soft Muting (digital). Refer to the
DAC section for more details. Whenever the DAC is muted or the device placed into standby mode
the DC voltage is maintained at the line outputs to prevent any audible clicks from being present.
The software control for the line outputs is shown in Table 4.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
DAC Select
0000100
4
DACSEL
0
Analogue
Audio Path
Control
1 = Select DAC
0 = Don’t select DAC
Table 4 Output Software Control
The recommended external components are shown in Figure 15.
R2
LINEOUT
C1
R1
AGND
AGND
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Figure 15 Line Outputs Application Drawing
Recommended values are C1 = 470nF (10V npo type), R1 = 47KOhms, R2 = 100 Ohms
C1 forms a DC blocking capacitor to the line outputs. R1 prevents the output voltage from drifting so
protecting equipment connected to the line output. R2 forms a de-coupling resistor preventing
abnormal loads from disturbing the device. Note that poor choice of dielectric material for C1 can
have dramatic effects on the measured signal distortion at the output.
DEVICE OPERATION
DEVICE RESETTING
The WM8734 contains a power on reset circuit that resets the internal state of the device to a known
condition. The power on reset is applied as DCVDD powers on and released only after the voltage
level of DCVDD crosses a minimum turn off threshold. If DCVDD later falls below a minimum turn on
threshold voltage then the power on reset is re-applied. The threshold voltages and associated
hysteresis are shown in the Electrical Characteristics table.
The user also has the ability to reset the device to a known state under software control as shown in
the table below.
REGISTER
ADDRESS
BIT
LABEL
RESET
DEFAULT
DESCRIPTION
0001111
Reset Register
8:0
not reset
Reset Register
Writing 00000000 to register resets
device
Table 5 Software Control of Reset
When using the software reset. In 3-wire mode the reset is applied on the rising edge of CSB and
released on the next rising edge of SCLK. In 2-wire mode the reset is applied for the duration of the
ACK signal (approximately 1 SCLK period, refer to Figure 23).
CLOCKING SCHEMES
In a typical digital audio system there is only one central clock source producing a reference clock to
which all audio data processing is synchronised. This clock is often referred to as the audio system’s
Master Clock. To allow WM8734 to be used in a centrally clocked system, the WM8734 is capable of
deriving the sample rate clock from this Master Clock (Master Mode) or receiving the sample rate
clock from an external source (Slave Mode).
CORE CLOCK
The WM8734 DSP core can be clocked either by MCLK or MCLK divided by 2. This is controlled by
software as shown in Table 6 below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001000
6
CLKIDIV2
0
Core Clock divider select
Sampling
Control
1 = Core Clock is MCLK divided by 2
0 = Core Clock is MCLK
Table 6 Software Control of Core Clock
Having a programmable MCLK divider allows the device to be used in applications where higher
frequency master Clocks are available. For example the device can support 512fs master clocks
whilst fundamentally operating in a 256fs mode.
DIGITAL AUDIO INTERFACES
WM8734 may be operated in either one of the 4 offered audio interface modes. These are:
• Right justified
• Left justified
• I2S
• DSP mode
All four of these modes are MSB first and operate with data 16 to 32 bits, except right justified mode
which does not support 32 bits.
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The digital audio interface takes the data from the internal ADC digital filter and places it on the
ADCDAT output. ADCDAT is the formatted digital audio data stream output from the ADC digital
filters with left and right channels multiplexed together. ADCLRC is an alignment clock that controls
whether Left or Right channel data is present on the ADCDAT lines. ADCDAT and ADCLRC are
synchronous with the BCLK signal with each data bit transition signified by a BCLK high to low
transition. BCLK maybe an input or an output dependent on whether the device is in master or slave
mode. Refer to the MASTER/SLAVE OPERATION section.
The digital audio interface also receives the digital audio data for the internal DAC digital filters on the
DACDAT input. DACDAT is the formatted digital audio data stream output to the DAC digital filters
with left and right channels multiplexed together. DACLRC is an alignment clock that controls
whether Left or Right channel data is present on DATDAT. DACDAT and DACLRC are synchronous
with the BCLK signal with each data bit transition signified by a BCLK transition. DACDAT is always
an input. BCLK and DACLRC are either outputs or inputs depending whether the device is in master
or slave mode. Refer to the MASTER/SLAVE OPERATION section
There are four digital audio interface formats accommodated by the WM8734. These are shown in
the figures below. Refer to the Electrical Characteristic section for timing information.
Left Justified mode is where the MSB is available on the first rising edge of BCLK following a ADCLR
or DACLRC transition.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
DACDAT/
ADCDAT
1
2
3
n
n-2 n-1
1
2
3
n
n-2 n-1
MSB
LSB
MSB
LSB
Figure 16 Left Justified Mode
I2S mode is where the MSB is available on the 2nd rising edge of BCLK following a LRCLK transition.
1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
1 BCLK
1 BCLK
DACDAT/
ADCDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
LSB
LSB
MSB
MSB
Figure 17 I2S Mode
Right Justified mode is where the LSB is available on the rising edge of BCLK preceding a LRCLK
transition, yet MSB is still transmitted first.
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1/fs
LEFT CHANNEL
RIGHT CHANNEL
DACLRC/
ADCLRC
BCLK
DACDAT/
ADCDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
MSB
LSB
Figure 18 Right Justified Mode
DSP mode is where the left channel MSB is available on either the 1st or 2nd rising edge of BCLK
(selectable by LRP) following a LRC transition high. Right channel data immediately follows left
channel data.
1/fs
1 BCLK
DACLRC/
ADCLRC
BCLK
RIGHT CHANNEL
LEFT CHANNEL
DACDAT/
ADCDAT
1
2
3
n
1
2
3
n
n-2 n-1
n-2 n-1
MSB
LSB
Input Word Length (IWL)
Note: Input word length is defined by the IWL register, LRP = 1
Figure 19 DSP Mode
In all modes DACLRC and ADCLRC must always change on the falling edge of BCLK, refer to Figure
16, Figure 17, Figure 18 and Figure 19. Operating the digital audio interface in DSP mode allows
ease of use for supporting the various sample rates and word lengths. The only requirement is that
all data is transferred within the correct number of BCLK cycles to suit the chosen word length.
In order for the digital audio interface to offer similar support in the three other modes (Left Justified,
I2S and Right Justified), the DACLRC, ADCLRC and BCLK frequencies, continuity and mark-space
ratios need more careful consideration.
In Slave mode, DACLRC and ADCLRC inputs are not required to have a 50:50 mark-space ratio.
BCLK input need not be continuous. It is however required that there are sufficient BCLK cycles for
each DACLRC/ADCLRC transition to clock the chosen data word length.
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In Master mode, DACLRC and ADCLRC will be output with a 50:50 mark-space ratio with BCLK
output at 64fs.
The ADC and DAC digital audio interface modes are software configurable as indicated in Table 7.
Note that dynamically changing the software format may result in erroneous operation of the
interfaces and is therefore not recommended. The length of the digital audio data is programmable at
16/20/24 or 32 bits. Refer to the software control table below. The data is signed 2’s complement.
Both ADC and DAC are fixed at the same data length. The ADC and DAC digital filters process data
using 24 bits. If the ADC is programmed to output 16 or 20 bit data then it strips the LSBs from the
24 bit data. If the ADC is programmed to output 32 bits then it packs the LSBs with zeros. If the DAC
is programmed to receive 16 or 20 bit data, the WM8734 packs the LSBs with zeros. If the DAC is
programmed to receive 32 bit data, then it strips the LSBs.
The DAC outputs can be swapped under software control using LRP and LRSWAP as shown in
Table 7. Stereo samples are normally generated as a Left/Right sampled pair. LRSWAP reverses the
order of that a Left sample goes to the right DAC output and a Right sample goes to the left DAC
output. LRP swaps the phasing so that a Right/Left sampled pair is expected and preserves the
correct channel phase difference.
To accommodate system timing requirements the interpretation of BCLK may be inverted, this is
controlled vias the software shown in Table 6. This is especially appropriate for DSP mode.
ADCDAT lines are always outputs. They power up and return from standby low.
DACDAT is always an input. It is expected to be set low by the audio interface controller when the
WM8734 is powered off or in standby.
ADCLRC, DACLRC and BCLK can be either outputs or inputs depending on whether the device is
configured as a master or slave. If the device is a master then the ADCLRC, DACLRC and BCLK
signals are outputs that default low. If the device is a slave then the ADCLRC, DACLRC and BCLK
are inputs.
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REGISTER
ADDRESS
BIT
1:0
LABEL
DEFAULT
10
DESCRIPTION
0000111
FORMAT[1:0]
Audio Data Format Select
Digital Audio
Interface
Format
11 = DSP Mode, frame sync + 2 data
packed words
10 = I2S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
3:2
IWL[1:0]
10
Input Audio Data Bit Length Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRP
0
DACLRC phase control (in left, right
or I2S modes)
1 = Right Channel DAC data when
DACLRC high
0 = Right Channel DAC data when
DACLRC low
(opposite phasing in I2S mode)
or
DSP mode A/B select (in DSP mode
only)
1 = MSB is available on 2nd BCLK
rising edge after ADCLRC/DACLRC
rising edge
0 = MSB is available on 1st BCLK
rising edge after ADCLRC/DACLRC
rising edge
5
6
7
LRSWAP
MS
0
0
0
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
BCLKINV
1 = Invert BCLK
0 = Don’t invert BCLK
Table 7 Digital Audio Interface Control
Note: If right justified 32 bit mode is selected then the WM8734 defaults to 24 bits.
MASTER AND SLAVE MODE OPERATION
The WM8734 can be configured as either a master or slave mode device. As a master mode device
the WM8734 controls sequencing of the data and clocks on the digital audio interface. As a slave
device the WM8734 responds with data to the clocks it receives over the digital audio interface. The
mode is set with the MS bit of the control register as shown in Table 8.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000111
6
MS
0
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Digital Audio Interface
Format
Table 8 Programming Master/Slave Modes
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As a master mode device the WM8734 controls the sequencing of data transfer (ADCDAT,
DACDAT) and output of clocks (BCLK, ADCLRC, DACLRC) over the digital audio interface. It uses
the timing generated from either its on-board crystal or the MCLK input as the reference for the clock
and data transitions. This is illustrated in Figure 20. ADCDAT is always an output from and DACDAT
is always an input to the WM8734 independent of master or slave mode.
BCLK
ADCLRC
DSP
WM8734
CODEC
ENCODER/
DECODER
DACLRC
ADCDAT
DACDAT
Figure 20 Master Mode
As a slave device the WM8734 sequences the data transfer (ADCDAT, DACDAT) over the digital
audio interface in response to the external applied clocks (BCLK, ADCLRC, DACLRC). This is
illustrated in Figure 21.
BCLK
ADCLRC
DSP
WM8734
CODEC
ENCODER/
DECODER
DACLRC
ADCDAT
DACDAT
Figure 21 Slave Mode
Note that the WM8734 relies on controlled phase relationships between audio interface BCLK,
DACLRC and the master MCLK. To avoid any timing hazards, refer to the timing section for detailed
information.
AUDIO DATA SAMPLING RATES
The WM8734 provides for two modes of operation (normal and USB) to generate the required DAC
and ADC sampling rates. Normal and USB modes are programmed under software control according
to the table below.
In Normal mode, the user controls the sample rate by using an appropriate MCLK or crystal
frequency and the sample rate control register setting. The WM8734 can support sample rates from
8ks/s up to 96ks/s.
In USB mode, the user must use a fixed MLCK or crystal frequency of 12MHz to generate sample
rates from 8ks/s to 96ks/s. It is called USB mode since the common USB (Universal Serial Bus)
clock is at 12MHz and the WM8734 can be directly used within such systems. WM8734 can
generate all the normal audio sample rates from this one Master Clock frequency, removing the need
for different master clocks or PLL circuits.
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Uniquely, the WM8734 offers the user the ability to sample the ADC and DAC at different rates under
software control in both Normal and USB modes. The reduces the burden on any controlling DSP.
However, the signal processing in the ADC and DAC over-sampling filters is tightly coupled together
in order to minimise power consumption. To this end, only the combinations of sample rates listed in
the following sections are supported. Note that these rates supported are anticipated to be the likely
combinations used in typical audio systems.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001000
0
USB/
0
Mode Select
NORMAL
BOSR
Sampling
Control
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
Base Over-Sampling Rate
1
0
USB Mode
0 = 250fs
1 = 272fs
Normal Mode
0 = 256fs
1 = 384fs
5:2
SR[3:0]
0000
ADC and DAC sample rate control;
See USB Mode and Normal Mode
Sample Rate sections for operation
Table 9 Sample Rate Control
SAMPLE RATE SETTING
In normal mode MCLK/crystal oscillator is set up according to the desired sample rates of the ADC
and DAC. For ADC or DAC sampling rates of 8, 32, 48 or 96KHz, MCLK frequencies of either
12.288MHz (256fs) or 18.432MHz (384fs) can be used. For ADC or DAC sampling rates of 8, 44.1 or
88.2KHz from MCLK frequencies of either 11.2896MHz (256fs) or 16.9344MHz (384fs) can be used.
The table below should be used to set up the device to work with the various sample rate
combinations. For example if the user wishes to use the WM8734 in normal mode with the ADC and
DAC sample rates at 48KHz and 48KHz respectively then the device should be programmed with
BOSR = 0, SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 12.288MHz MCLK or with BOSR = 1,
SR3 = 0, SR2 = 0, SR1 = 0 and SR0 = 0 with a 18.432MHz MCLK. The ADC and DAC will then
operate with a Digital Filter of type 1, refer to Digital Filter Characteristics section for an explanation
of the different filter types.
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SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
ADC
DAC
KHz
48
KHz
MHz
BOSR
SR3
0
SR2
0
SR1
0
SR0
48
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
12.288
18.432
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
11.2896
16.9344
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
1
1
1
1
1
1
2
1
1
1
1
2
0
0
0
48
8
8
48
8
0
0
0
0
0
0
0
0
1
0
0
1
8
0
0
1
0
0
1
32
32
96
44.1
0
1
1
0
1
1
96
0
1
1
0
1
1
44.1
44.1
1
0
0
1
0
0
8
1
0
0
(Note 1)
44.1
1
0
0
8
(Note 1)
8
1
0
1
1
0
1
8
1
0
1
(Note 1) (Note 1)
88.2 88.2
1
0
1
1
1
1
1
1
1
Table 10 Normal Mode Sample Rate Look-up Table
Notes:
1. 8k not exact, actual = 8.018kHz
2. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8734 digital signal
processing is carried out at. In Normal mode, with BOSR = 0, the base over-sampling rate is at
256fs, with BOSR = 1, the base over-sampling rate is at 384fs. This can be used to determine the
actual audio data rate produced by the ADC and required by the DAC.
Example scenarios are:
1. with a requirement that the ADC data rate is 8KHz and DAC data rate is 48KHz, then choosing
MCLK = 12.288MHz the device is programmed with BOSR = 0 (256fs), SR3 = 0, SR2 = 0, SR1
= 1, SR0 = 0.The ADC output data rate will then be exactly 8KHz (derived from 12.288MHz/256
x1/6) and the DAC expects data at exactly 48KHz (derived from 12.288MHz/256)
2. with a requirement that ADC data rate is 8KHz and DAC data rate is 44.1KHz, then choosing
MCLK = 16.9344MHz the device is programmed with BOSR = 1 (384fs), SR3 = 1, SR2 = 0, SR1
= 0, SR0 = 1. The ADC will no longer output data at exactly 8.000KHz, instead it will be
8.018KHz (derived from 16.9344MHz/384 x 2/11), the DAC still is at exactly 44.1KHz (derived
from 16.9344MHz/384). A slight (sub 0.5%) pitch shift will therefore result in the 8KHz audio
data and (importantly) the user must ensure that the data across the digital interface is correctly
synchronised at the 8.018KHz rate.
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The exact sample rates achieved are defined by the relationships in Table 11 below.
TARGET
ACTUAL SAMPLING RATE
SAMPLING
RATE
BOSR=0
(256fs)
BOSR=1
(384fs)
MCLK=12.288
KHz
MCLK=11.2896
KHz
MCLK=18.432
MCLK=16.9344
KHz
KHz
KHz
8
8
8
8.018
8.018
12.288MHz/256 x 1/6
32
11.2896MHz/256 x 2/11
not available
18.432MHz/384 x 1/6
32
16.9344MHz/384 x 2/11
not available
32
44.1
48
12.288MHz/256 x 2/3
not available
18.432MHz/384x 2/3
not available
44.1
44.1
11.2896MHz/256
not available
16.9344MHz /384
not available
48
48
12.288MHz/256
not available
18.432MHz/384
not available
88.2
96
88.2
88.2
11.2896MHz/384 x 2
not available
16.9344MHz /384 x 2
not available
96
96
12.288MHz/256 x 2
18.432MHz/384 x 2
Table 11 Normal Mode Actual Sample Rates
128/192fs NORMAL MODE
The Normal Mode sample rates are designed for standard 256fs and 384fs MCLK rates. However the
WM8734 is also capable of being clocked from a 128 or 192fs MCLK for application over limited
sampling rates as shown in the table below.
SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
ADC
DAC
KHz
48
KHz
MHz
6.144
9.216
5.6448
8.4672
BOSR
SR3
SR2
SR1
SR0
48
0
1
0
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
44.1
44.1
Table 12 128fs Normal Mode Sample Rate Look-up Table
512/768fs NORMAL MODE
512 fs and 768 fs MCLK rates can be accommodated by using the CLKIDIV2 bit. The core clock to
the DSP will be divided by 2 so an external 512/768 MCLK will become 256/384 fs internally and the
device otherwise operates as in Table 8 but with MCLK at twice the specified rate. See Table 6 for
software control.
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USB MODE SAMPLE RATES
In USB mode the MCLK/crystal oscillator input is 12MHz only.
SAMPLING
RATE
MCLK
FREQUENCY
SAMPLE
RATE
REGISTER SETTINGS
DIGITAL
FILTER
TYPE
ADC
DAC
KHz
48
KHz
MHz
BOSR
SR3
SR2
SR1
SR0
48
12.000
0
0
0
0
0
0
1
1
0
0
1
1
0
1
1
0
1
0
1
0
1
0
1
0
3
2
44.1
44.1
12.000
12.000
12.000
12.000
12.000
12.000
12.000
12.000
12.000
12.000
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
0
1
0
0
1
0
0
0
0
0
0
0
1
1
1
0
0
0
1
1
1
1
1
1
1
(Note 2) (Note 2)
48
8
44.1
(Note 2)
8
(Note 1)
48
8
8
44.1
(Note 2)
(Note 1)
8
8
8
8
(Note 1) (Note 1)
32
96
32
96
88.2
88.2
(Note 3) (Note 3)
Table 13 USB Mode Sample Rate Look-ip Table
Notes:
1. 8k not exact, actual = 8.021kHz
2. 44.1k not exact, actual = 44.118kHz
3. 88.1k not exact, actual = 88.235kHz
4. All other combinations of BOSR and SR[3:0] that are not in the truth table are invalid
The table above can be used to set up the device to work with various sample rate combinations. For
example if the user wishes to use the WM8734 in USB mode with the ADC and DAC sample rates at
48KHz and 48KHz respectively then the device should be programmed with BOSR = 0, SR3 = 0,
SR2 = 0, SR1 = 0 and SR0 = 0. The ADC and DAC will then operate with a Digital Filter of type 0,
refer to Digital Filter Characteristics section for an explanation of the different filter types.
The BOSR bit represents the base over-sampling rate. This is the rate that the WM8734 digital signal
processing is carried out at and the sampling rate will always be a sub-multiple of this. In USB mode,
with BOSR = 0, the base over-sampling rate is defined at 250fs, with BOSR = 1, the base over-
sampling rate is defined at 272fs. This can be used to determine the actual audio sampling rate
produced by the ADC and required by the DAC.
Example scenarios are, :-
1. with a requirement that the ADC data sampling rate is 8KHz and DAC data sampling rate is
48KHz the device is programmed with BOSR = 0 (250fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 =
0.The ADC will then be exactly 8KHz ( derived from 12MHz/250 x 1/6 ) and the DAC expects
data at exactly 48KHz ( derived from 12MHz/250 ).
2. with a requirement that ADC data rate is 8KHz and DAC data rate is 44.1KHz the device is
programmed with BOSR = 0 (272fs), SR3 = 0, SR2 = 0, SR1 = 1, SR0 = 0. The ADC will not
output data at exactly 8KHz, instead it will be 8.021KHz ( derived from 12MHz/272 x 2/11 ) and
the DAC at 44.118KHz ( derived from 12MHz/272 ). A slight (sub 0.5%) pitch shift will therefore
results in the 8KHz and 44.1KHz audio data and (more importantly) the user must ensure that
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Advanced Information
the data across the digital interface is correctly synchronised at the 8.021KHz and 44.117KHz
rates.
The exact sample rates supported for all combinations are defined by the relationships in Table 14
below.
TARGET
ACTUAL SAMPLING RATE
SAMPLING
RATE
BOSR=0
BOSR=1
(272fs)
( 250fs)
KHz
KHz
KHz
8
8
8.021
12MHz/(250 x 48/8)
32
12MHz/(272 x 11/2)
not available
32
44.1
48
12MHz/(250 x 48/32)
not available
44.117
12MHz/272
48
not available
12MHz/250
88.2
96
not available
88.235
12MHz/136
96
not available
12MHz/125
Table 14 USB Mode Actual Sample Rates
ACTIVATING DSP AND DIGITAL AUDIO INTERFACE
To prevent any communication problems from arising across the Digital Audio Interface the Audio
Interface is disabled (tristate with weak 100k pulldown). Once the Audio Interface and the Sampling
Control has been programmed it is activated by setting the ACTIVE bit under Software Control.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0001001
Active Control
0
ACTIVE
0
Activate Interface
1 = Active
0 = Inactive
Table 15 Activating DSP and Digital Audio Interface
It is recommended that between changing any content of Digital Audio Interface or Sampling Control
Register that the active bit is reset then set.
SOFTWARE CONTROL INTERFACE
The software control interface may be operated using either a 3-wire (SPI-compatible) or 2-wire MPU
interface. Selection of interface format is achieved by setting the state of the MODE pin.
In 3-wire mode, SDIN is used for the program data, SCLK is used to clock in the program data and
CSB is used to latch in the program data. In 2-wire mode, SDIN is used for serial data and SCLK is
used for the serial clock. In 2-wire mode, the state of CSB pin allows the user to select one of two
addresses.
Unused register bits should always be set to ‘0’ unless specified otherwise.
SELECTION OF SERIAL CONTROL MODE
The serial control interface may be selected to operate in either 2 or 3-wire modes. This is achieved
by setting the state of the MODE pin.
MODE
INTERFACE
FORMAT
0
1
2 wire
3 wire
Table 16 Control Interface Mode Selection
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3-WIRE (SPI COMPATIBLE) SERIAL CONTROL MODE
The WM8734 can be controlled using a 3-wire serial interface. SDIN is used for the program data,
SCLK is used to clock in the program data and CSB is use to latch in the program data. The 3-wire
interface protocol is shown in Figure 22.
CSB
SCLK
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
SDIN
Figure 22 3-Wire Serial Interface
Notes:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
2-WIRE SERIAL CONTROL MODE
The WM8734 supports a 2-wire MPU serial interface. The device operates as a slave device only.
The WM8734 has one of two slave addresses that are selected by setting the state of pin 10, (CSB).
ACK
ACK
ACK
DATA B15-8
R ADDR
R/W
DATA B7-0
SDIN
SCLK
START
STOP
Figure 23 2-Wire Serial Interface
Notes:
1. B[15:9] are Control Address Bits
2. B[8:0] are Control Data Bits
CSB STATE
Address
(Default = LOW)
0
1
0011010
0011011
Table 17 2-Wire MPU Interface Address Selection
To control the WM8734 on the 2-wire bus the master control device must initiate a data transfer by
establishing a start condition, defined by a high to low transition on SDIN while SCLK remains high.
This indicates that an address and data transfer will follow. All peripherals on the 2-wire bus respond
to the start condition and shift in the next eight bits (7-bit address + R/W bit). The transfer is MSB
first. The 7-bit address consists of a 6-bit base address + a single programmable bit to select one of
two available addresses for this device (see table 24). If the correct address is received and the R/W
bit is ‘0’, indicating a write, then the WM8734 will respond by pulling SDIN low on the next clock pulse
(ACK). The WM8734 is a write only device and will only respond to the R/W bit indicating a write. If
the address is not recognised the device will return to the idle condition and wait for a new start
condition and valid address.
Once the WM8734 has acknowledged a correct address, the controller will send eight data bits (bits
B[15]-B[8]). WM8734 will then acknowledge the sent data by pulling SDIN low for one clock pulse.
The controller will then send the remaining eight data bits (bits B[7]-B[0]) and the WM8734 will then
acknowledge again by pulling SDIN low.
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A stop condition is defined when there is a low to high transition on SDIN while SCLK is high. If a
start or stop condition is detected out of sequence at any point in the data transfer then the device
will jump to the idle condition.
After receiving a complete address and data sequence the WM8734 returns to the idle state and
waits for another start condition. Each write to a register requires the complete sequence of start
condition, device address and R/W bit followed by the 16 register address and data bits.
Note that the 16 bit control word is made up of 7 address bits, B[15:9], and 9 data bits, B[8:0].
These are transmitted as 2 blocks of 8 bits. The first block contains 7 address bits and the data
HSB. The second block contains the 8 data LSBs.
POWER DOWN MODES
The WM8734 contains power conservation modes in which various circuit blocks may be safely
powered down in order to conserve power. This is software programmable as shown in the table
below.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000110
0
2
3
4
7
LINEINPD
1
Line Input Power Down
1 = Enable Power Down
0 = Disable Power Down
ADC Power Down
Power Down
Control
ADCPD
1
1
1
1
1 = Enable Power Down
0 = Disable Power Down
DAC Power Down
DACPD
1 = Enable Power Down
0 = Disable Power Down
Line Output Power Down
1 = Enable Power Down
0 = Disable Power Down
Power Off Device
OUTPD
POWEROFF
1 = Device Power Off
0 = Device Power On
Table 18 Power Conservation Modes Software Control
When writing to the powerdown register bits 1,5 & 6 should be set to ‘1’.
The power down control can be used to either a) permanently disable functions when not required in
certain applications or b) to dynamically power up and down functions depending on the operating
mode, e.g.: during playback or record. Please follow the special instructions below if dynamic
implementations are being used.
LINEINPD: Simultaneously powers down both the Line Inputs. This can be done dynamically without
any audible effects either on the ADC or to the Line Outputs in Bypass mode. This is of use when the
device enters Playback, Pause or Stop modes or the Microphone input has been selected.
ADCPD: Powers down the ADC and ADC Filters. If this is done dynamically then audible pops will
result if any signals were present through the ADC. To overcome this whenever the ADC is to be
powered down, either mute the Microphone Input (MUTEIN) or MUTELINEIN, then change ADCPD.
This is of use when the device enters Playback, Pause or Stop modes regardless of whether
Microphone or Line Inputs are selected.
DACPD: Powers down the DAC and DAC Digital Filters. If this is done dynamically then audible pops
will result unless the following guidelines are followed. In order to prevent pops, the DAC should first
be soft-muted (DACMU), the output should then be de-selected from the line and headphone output
(DACSEL), then the DAC powered down (DACPD). This is of use when the device enters Record,
Pause, Stop or Bypass modes.
The device can be put into a standby mode (STANDBY) by powering down all the audio circuitry
under software control as shown in Table 18. Provision has been made to independently power off
these areas according to Table 19.
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Advanced Information
DESCRIPTION
0
1
1
1
1
STANDBY
Table 19 Standby Mode
In STANDBY mode the Control Interface, a small portion of the digital and areas of the analogue
circuitry remain active. The active analogue includes the analogue VMID reference so that the
analogue line inputs, line outputs and headphone outputs remain biased to VMID. This reduces any
audible effects caused by DC glitches when entering or leaving STANDBY mode.
The device can be powered off by writing to the POWEROFF bit of the Power Down register. In
POWEROFF mode the Control Interface and a small portion of the digital remain active. The
analogue VMID reference is disabled.
DESCRIPTION
1
X
X
X
X
POWEROFF
Table 20 Poweroff Mode
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REGISTER MAP
The complete register map is shown in Table 21. The detailed description can be found in the
relevant text of the device description. There are 8 registers with 9 bits per register. These can be
controlled using either the 2 wire or 3 wire MPU interface.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
0000000
4:0
LINVOL[4:0]
10111
( 0dB )
Left Channel Line Input Volume
Control
Left Line In
11111 = +12dB . . 1.5dB steps down
to 00000 = -34.5dB
7
8
LINMUTE
1
0
Left Channel Line Input Mute to ADC
1 = Enable Mute
0 = Disable Mute
LRINBOTH
Left to Right Channel Line Input
Volume and Mute Data Load Control
1 = Enable Simultaneous Load of
LINVOL[4:0] and LINMUTE to
RINVOL[4:0] and RINMUTE
0 = Disable Simultaneous Load
0000001
4:0
7
RINVOL[4:0]
RINMUTE
10111
( 0dB )
Right Channel Line Input Volume
Control
Right Line In
11111 = +12dB . .1.5dB steps down
to 00000 = -34.5dB
1
0
Right Channel Line Input Mute to
ADC
1 = Enable Mute
0 = Disable Mute
8
RLINBOTH
Right to Left Channel Line Input
Volume and Mute Data Load Control
1 = Enable Simultaneous Load of
RINVOL[4:0] and RINMUTE to
LINVOL[4:0] and LINMUTE
0 = Disable Simultaneous Load
DAC Select
0000100
4
DACSEL
0
Analogue Audio
Path Control
1 =Select DAC
0 = Don’t select DAC
ADC High Pass Filter Enable
1 = Enable High Pass Filter
0 = Disable High Pass Filter
De-emphasis Control
11 = 48KHz
0000101
0
ADCHPD
DEEMP[1:0]
0
Digital Audio
Path Control
2:1
00
10 = 44.1KHz
01 = 32KHz
00 = Disable
3
4
DACMU
HPOR
1
0
DAC Soft Mute Control
1 = Enable soft mute
0 = Disable soft mute
Store dc offset when High Pass Filter
disabled
1 = store offset
0 = clear offset
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DESCRIPTION
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
0000110
0
LINEINPD
1
Line Input Power Down
1 = Enable Power Down
0 = Disable Power Down
ADC Power Down
Power Down
Control
2
ADCPD
1
1 = Enable Power Down
0 = Disable Power Down
DAC Power Down
3
DACPD
1
1 = Enable Power Down
0 = Disable Power Down
Line Output Power Down
1 = Enable Power Down
0 = Disable Power Down
POWEROFF mode
4
OUTPD
1
7
POWEROFF
FORMAT[1:0]
1
1 = Enable POWEROFF
0 = Disable POWEROFF
Audio Data Format Select
0000111
1:0
10
Digital Audio
Interface Format
11 = DSP Mode, frame sync + 2 data
packed words
10 = I2S Format, MSB-First left-1
justified
01 = MSB-First, left justified
00 = MSB-First, right justified
3:2
IWL[1:0]
10
Input Audio Data Bit Length Select
11 = 32 bits
10 = 24 bits
01 = 20 bits
00 = 16 bits
4
LRP
0
DACLRC phase control (in left, right
or I2S modes)
1 = Right Channel DAC data when
DACLRC high
0 = Right Channel DAC data when
DACLRC low
(opposite phasing in I2S mode)
or
DSP mode A/B select (in DSP mode
only)
1 = MSB is available on 2nd BCLK
rising edge after ADCLRC/DACLRC
rising edge
0 = MSB is available on 1st BCLK
rising edge after ADCLRC/DACLRC
rising edge
5
6
7
LRSWAP
MS
0
0
0
DAC Left Right Clock Swap
1 = Right Channel DAC Data Left
0 = Right Channel DAC Data Right
Master Slave Mode Control
1 = Enable Master Mode
0 = Enable Slave Mode
Bit Clock Invert
BCLKINV
1 = Invert BCLK
0 = Don’t invert BCLK
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DESCRIPTION
Mode Select
REGISTER
ADDRESS
BIT
LABEL
USB/
DEFAULT
0001000
0
0
NORMAL
Sampling
Control
1 = USB mode (250/272fs)
0 = Normal mode (256/384fs)
Base Over-Sampling Rate
0 = 256fs
1
BOSR
0
1 = 384fs
5:2
6
SR[3:0]
0000
0
ADC and DAC sample rate control
Core Clock divider select
1 = Core Clock is MCLK divided by 2
0 = Core Clock is MCLK
Activate Interface
CLKIDIV2
0001001
0
ACTIVE
0
Active Control
1 = Active
0 = Inactive
Table 21 Register Map Description
Note:
Unused register bits should be set to ‘0’ except when writing to Register 0000110, when bits 1,5 and
6 should be set to ‘1’.
DIGITAL FILTER CHARACTERISTICS
The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2
and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is
shown in the proceeding pages.
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
0.416fs
+/- 0.05
UNIT
ADC Filter Type 0 (USB Mode, 250fs operation)
Passband
+/- 0.05dB
0
-6dB
0.5fs
Passband Ripple
Stopband
dB
dB
0.584fs
-60
Stopband Attenuation
f > 0.584fs
ADC Filter Type 1 (USB mode, 272fs or Normal mode operation)
Passband
+/- 0.05dB
-6dB
0
0.4535fs
+/- 0.05
0.5fs
Passband Ripple
Stopband
dB
dB
Hz
0.5465fs
-60
Stopband Attenuation
f > 0.5465fs
-3dB
High Pass Filter Corner
Frequency
3.7
-0.5dB
10.4
21.6
-0.1dB
DAC Filter Type 0 (USB mode, 250fs operation)
Passband
+/- 0.03dB
0
0.416fs
+/-0.03
-6dB
0.5fs
0.5fs
Passband Ripple
Stopband
dB
dB
0.584fs
-50
Stopband Attenuation
f > 0.584fs
DAC Filter Type 1 (USB mode, 272fs or Normal mode operation)
Passband
+/- 0.03dB
-6dB
0
0.4535fs
+/- 0.03
Passband Ripple
Stopband
dB
dB
0.5465fs
-50
Stopband Attenuation
f > 0.5465fs
Table 22 Digital Filter Characteristics
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Advanced Information
TERMINOLOGY
1. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band)
2. Pass-band Ripple – any variation of the frequency response in the pass-band region
DAC FILTER RESPONSES
0.04
0
0.03
-20
0.02
0.01
-40
0
-60
-80
-0.01
-0.02
-0.03
-0.04
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
Frequency (Fs)
Figure 24 DAC Digital Filter Frequency Response –Type 1
Figure 25 DAC Digital Filter Ripple –Type 1
0.02
0.01
0
0
-20
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
Frequency (Fs)
Frequency (Fs)
Figure 26 DAC Digital Filter Frequency Response –Type 2
Figure 27 DAC Digital Filter Ripple –Type 2
ADC FILTER RESPONSES
0.02
0.01
0
0
-20
-40
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
Frequency (Fs)
Frequency (Fs)
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Advanced Information
Figure 29 ADC Digital Filter Ripple –Type 1
Figure 28 ADC Digital Filter Frequency Response –Type 1
0.02
0.01
0
0
-20
-0.01
-0.02
-0.03
-0.04
-0.05
-0.06
-40
-60
-80
-100
0
0.5
1
1.5
2
2.5
3
0
0.05
0.1
0.15
0.2
0.25
Frequency (Fs)
Frequency (Fs)
Figure 30 ADC Digital Filter Frequency Response –Type 2
Figure 31 ADC Digital Filter Ripple –Type 2
ADC HIGH PASS FILTER
The WM8734 has a selectable digital high pass filter to remove DC offsets. The filter response is
characterised by the following polynomial.
H(z) =
1 – z-1
1 – 0.9995 z-1
DIGITAL DE-EMPHASIS CHARACTERISTICS
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
2000
4000
6000
8000
10000 12000 14000 16000
0
2000
4000
6000
8000
10000 12000 14000 16000
Frequency (Fs)
Frequency (Fs)
Figure 32 De-Emphasis Frequency Response (32kHz)
Figure 33 De-Emphasis Error (32kHz)
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
5000
10000
Frequency (Fs)
15000
20000
0
5000
10000
Frequency (Fs)
15000
20000
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Advanced Information
Figure 34 De-Emphasis Frequency Response (44.1kHz)
Figure 35 De-Emphasis Error (44.1kHz)
0
0.4
0.3
0.2
0.1
0
-2
-4
-6
-0.1
-0.2
-0.3
-0.4
-8
-10
0
5000
10000
15000
20000
0
5000
10000
15000
20000
Frequency (Fs)
Frequency (Fs)
Figure 36 De-Emphasis Frequency Response (48kHz)
Figure 37 De-Emphasis Error (48kHz)
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RECOMMENDED EXTERNAL COMPONENTS
3.3V
3.3V
+
2
10
11
DBVDD
AVDD
AGND
0.4
µF
10
µ
F
1
DGND
10
µF
0.1µF
3.3V
20
DCVDD
LLINEIN
+
5K
Ω
14
5K
Ω
470nF
47pF
+
5K
Ω
+
13
100
Ω
8
RLINEIN
LOUT
ROUT
5K
Ω
470nF
47pF
470nF
47k
Ω
WM8734
Codec
+
100
Ω
9
5
4
6
470nF
47kΩ
DACLRC
DACDAT
ADCDAT
ADCLRC
BCLK
Audio Serial Data I/F
7
3
3.3V
3-wire Interface
10k
Ω
15
16
2-wire Interface
MODE
CSB
SDIN
SCLK
12
VMID
3-wire or 2-wire
MPU Interface
17
18
+
0.1µF
10µF
MCLK
19
Figure 38 External Components Diagram
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Advanced Information
PACKAGE DIMENSIONS (SSOP)
DS: 20 PIN SSOP (7.2 x 5.3 x 1.75 mm)
DM0015.A
b
e
20
11
E1
E
GAUGE
PLANE
Θ
1
10
D
0.25
c
L
A1
A A2
-C-
0.10 C
SEATING PLANE
Dimensions
(mm)
NOM
-----
Symbols
MIN
-----
MAX
2.0
-----
1.85
0.38
0.25
7.50
A
A1
A2
b
c
D
e
E
E1
L
0.05
1.65
0.22
0.09
6.90
-----
1.75
-----
-----
7.20
0.65 BSC
7.80
7.40
5.00
0.55
0o
8.20
5.60
0.95
8o
5.30
0.75
4o
θ
REF:
JEDEC.95, MO-150
NOTES:
A. ALL LINEAR DIMENSIONS ARE IN MILLIMETERS.
B. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
C. BODY DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSION, NOT TO EXCEED 0.20MM.
D. MEETS JEDEC.95 MO-150, VARIATION = AE. REFER TO THIS SPECIFICATION FOR FURTHER DETAILS.
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Advanced Information
PACKAGE DIMENSIONS (QFN)
FL: 28 PIN QFN PLASTIC PACKAGE 5
X
5
X
0.9 mm BODY, 0.50 mm LEAD PITCH
DM023.C
TOP VIEW
D2
B
D
D2/2
INDEX AREA
(D/2 X E/2)
22
27 28
L
21
1
2
E2/2
A
A
E2
E
15
7
SEE DETAIL B
aaa
C
2 X
2 X
14 13
e
8
b
M
A
B
ccc
C
aaa
C
B
DETAIL B
DATUM
R
ccc
C
C
A
(A3)
0.08
SEATING PLANE
e
A1
TERMINAL TIP
C
1
Symbols
Dimensions (mm)
MIN
0.80
0
NOM
0.90
0.02
0.2 REF
0.23
MAX
1.00
0.05
NOTE
A
A1
A3
b
D
D2
2
1
0.18
3.2
0.30
5.00 BSC
3.3
5.00 BSC
3.3
3.4
3.4
2
2
E
E2
3.2
e
L
0.5 BSC
0.4
0.35
0.45
R
b(min)/2
Tolerances of Form and Position
aaa
ccc
0.15
0.10
REF:
JEDEC.95, MO-220, VARIATION VHHD-1
NOTES:
1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 mm AND 0.30 mm FROM TERMINAL TIP.
2. FALLS WITHIN JEDEC.95, MO-220 WITH THE EXCEPTION OF D2, E2, A3:
D2,E2: LARGER PAD SIZE CHOSEN WHICH IS JUST OUTSIDE JEDEC SPECIFICATION
A3:
NOMINAL VALUE LESS THAN JEDEC
3. ALL DIMENSIONS ARE IN MILLIMETRES
4. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
AI Rev 2.2 November 2001
40
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WM8734
Advanced Information
REVISION HISTORY
Revision Originator Change Date History
2.2
EV
19/11/2001
Front Page: Added mention of QFN package; changed SCLK
to input only in Block Diagram (was previously drawn as I/O)
Page 3: Added QFN pinout diagram, pin description, and
order info
Pages 2/3, pin descriptions: SDIN changed to I/O (was input
only)
Page 41: Added QFN package diagram
Page 42: Added Revision history
AI Rev 2.2 November 2001
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WM8734
Advanced Information
IMPORTANT NOTICE
Wolfson Microelectronics Ltd (WM) reserve the right to make changes to their products or to discontinue any product or
service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing
orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale
supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation
of liability.
WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM’s
standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support
this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by
government requirements.
In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used
by the customer to minimise inherent or procedural hazards.
WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that
any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual
property right of WM covering or relating to any combination, machine, or process in which such products or services might
be or are used. WM’s publication of information regarding any third party’s products or services does not constitute WM’s
approval, license, warranty or endorsement thereof.
Reproduction of information from the WM web site or datasheets is permissable only if reproduction is without alteration
and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this
information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive
business practice, and WM is not responsible nor liable for any such use.
Resale of WM’s products or services with statements different from or beyond the parameters stated by WM for that
product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and
deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics Ltd
20 Bernard Terrace
Edinburgh
EH8 9NX
United Kingdom
Tel :: +44 (0)131 667 9386
Fax :: +44 (0)131 667 5176
Email :: sales@wolfsonmicro.com
AI Rev 2.2 November 2001
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