WT8048N2 [ETC]
DPMS (Display Power Management Signaling) Detector for Green Monitor; DPMS （显示器电源管理信号）检测器的绿色显示器
| 型号： | WT8048N2 |
| 厂家： | 
ETC |
| 描述： | DPMS (Display Power Management Signaling) Detector for Green Monitor |
| 文件： | 总10页 (文件大小：55K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
WT8048
DPMS (Display Power Management
Signaling) Detector for Green Monitor
eltrend
Aug. 31, 1995
DESCRIPTION
The WT8048 is a 8 pin P-DIP package IC, designed for the application of Power Saving
Monitor or Green Monitor.
As per DPMS proposal, the WT8048 provides a detective circuit of monitor power
management for the convenience of designers in designing Power Saving Monitor.
FEATURES
{
Accepting two seperated H&V synchronous signals with positive/ negative polarity.
{
Capable of processing horizontal frequency between 0Hz to 100kHz, and vertical
frequency between 0Hz to 100Hz.
{
Power Saving mode - It can detect the conditions of monitor to decide which will be
selected as following: ON mode / STAND_BY mode / SUSPEND mode / OFF mode.
{
An Override mode is defined to override the DPMS function during the design, test,
burn-in manufacture or diagnostic process if desired.
APPLICATION
{
DPMS mode's detection for Green Monitor
Weltrend Semiconductor, Inc.
2F., No. 24, Ind. E. 9th Rd., Science-Based Ind. Park,
Hsin-Chu, Taiwan, R. O. C.
Tel: 886-35-780241 Fax: 886-35-7704191
WT8048
eltrend
ORDERING INFORMATION
Part No.
WT8048
Package
P-DIP 8L
P-DIP 8L
Description
OSC with 32768Hz Crystal
1. OSC with external resistor
2. With mute function
1. OSC with external resistor
2. Without mute function
1. OSC with 3.58MHz resonator
2. With mute function
1. OSC with 3.58MHz resonator
2. Without mute function
WT8048N1
WT8048N2
*WT8048N3
*WT8048N4
P-DIP 8L
P-DIP 8L
P-DIP 8L
Note: "*" means "not available".
PIN CONFIGURATION
WT8048 / N2 / N4
WT8048N1 / N3
HIN
HIN
VIN
1
2
8
7
6
VDD
OFF
1
8
7
6
VDD
OFF
VIN
OSC
VSS
2
3
4
STD_BY +
SUSPEND
SUSPEND
STD_BY
OSC
VSS
3
4
5
5
MUTE
2
WT8048
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ABSOLUTE MAXIMUM RATING
ITEM
Digital Supply Voltage
SYMBOL
VDD
VALUE
5.5
UNIT
V
Horizontal Sync. Input Voltage
Vertical Sync. Input Voltage
Power dissipation
VHS
VVS
PD
TOPT
VDD(5)+0.3
VDD(5)+0.3
30
VPP
VPP
mW
¢ J
¢ J
Operating Temperature Range
0¡ 7ã0
Storage Temperature Range
TSTG
-40¡ 1ã25
RECOMMENDED OPERATING CONDITIONS
ITEM
Digital Supply Voltage
Supply Current (Stand-by)
Synchronous Input Voltage Low
Synchronous Input Voltage High
SYMBOL
VDD(5)
IP
MIN.
4.5
TYP. MAX. UNIT
5
5.5
1
V
mA
VPP
VPP
VIL
VIH
0.8
5.5
2.4
4
3
WT8048
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ELECTRICAL CHARACTERISTICS
A. WT8048
(VDD=5V, TOPT=24¢ J, FOSC=32768Hz)
ITEM
SYMBOL MIN. TYP. MAX. UNIT
Input Current (HIN, VIN), when VIN=5V
Open Drain Output Low, when IOL = 6mA
Open Drain Sink Current, when VOL = 0.4V
Input Current (OSC), when VIN = 5V
IIN1
VOL
VOL
IIN3
5
0.4
6
£ Ag
VPP
mA
5
£ Ag
B. WT8048N1 / N2
(VDD=5V, TOPT=24¢ J, FOSC= 450KHz)
ITEM
SYMBOL MIN. TYP. MAX. UNIT
Input Current (HIN, VIN), when VIN=5V
Open Drain Output Low, when IOL = 6mA
Open Drain Sink Current, when VOL = 0.4V
Input Current (OSC), when VIN = 5V
IIN1
VOL
VOL
IIN3
5
0.4
6
£ Ag
VPP
mA
mA
15
C. WT8048N3 / N4
(VDD=5V, TOPT=24¢ J, FOSC= 3.58MHz)
ITEM
SYMBOL MIN. TYP. MAX. UNIT
Input Current (HIN, VIN), when VIN=5V
Open Drain Output Low, when IOL = 6mA
Open Drain Sink Current, when VOL = 0.4V
Input Current (OSC), when VIN = 5V
IIN1
VOL
VOL
IIN3
5
0.4
6
£ Ag
VPP
mA
5
£ Ag
4
WT8048
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PIN DESCRIPTION
Pin No.
Structure
of
Terminal
WT8048N1
/N3
WT8048/
N2/N4
Name
HSIN
Function
Input,
TTL compatible
1
2
3
1
2
3
Input terminal of horizontal
synchronous signal
Input terminal of vertical
synchronous signal
A clock generator circuit is built
into the chip. So, if a resonator is
connected to OSC pin and
ground, a clock signal can be
obtained.
Input,
TTL compatible
VSIN
Input
OSC
4
5
6
4
5
VSS
STD_BY
Mute
Suspend
Suspend
+
Ground
Output, open drain
Output, open drain
Indicate in Stand_By mode
Indicate in Mute mode
Indicate in Suspend mode
Indicate in Suspend and stand_By
mode
6
STD_BY
Off
Output, open drain
7
8
7
8
Indicate in Off mode
5 volts power supply
VDD
5
WT8048
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APPLICATION DESCRIPTION
DPMS (Display Power Management Signaling) Dection
As per DPMS proposal WT8048 provides Monitor Power Management Detection Circuit for
the convenience of monitor designers in designing power saving minitors, or the so called
"Green Monitors". Please refer to the table 1 as below for power states defined in the DPMS.
DPMS requires at least 5 seconds delay before transition from ON state to any power saving
state, to avoid unintentionally entering a power saving state during display resoultion changes
and timing mode changes. And it can be done instaneously, for the transition between any
power saving state.
Table 1 Display Power Management Summary
Signals
DPMS
Power
Savings
None
Recovery
Time
State
On
Compliance
Requirement
Mandatory
Horizontal Vertical
Video
Active
Pulse
Pulses
Not
Applicable
Short
Stand-By No Pulses
Pulses
Blanked
Optional
Minimal
Suspend
Off
Pulse
No Pulses Blanked
Mandatory Substantial
Mandatory Maximum
Longer
System
No Pulses No Pulses Blanked
Dependent
* "No Pulse" represents the frequency of Hsin or Vsin less than or equal to 10Hz,
but "Pulses" represents that frequency of Hsin greater than or equal to 15KHz
(WT8048), 10KHz (WT8048N1 / N2 / N3 / N4) and Vsin greater than or equal
to 40Hz.
6
WT8048
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The Way WT8048 implements VESA DPMS
As shown on Table 2, when H_SYNC / V_SYNC signals transition from ON state to any one
of the three power saving state, WT8048 will delay 5.9 seconds to meet the VESA DPMS
requirement: the minimum 5 seconds delay to avoid unintentionally entering a power saving
state during display resolution and timing mode changes. If during this delay time period,
H_SYN and V_SYN signals return to ON state, then all three power management pins will
remain ON state. If power management state of H_SYNC and V_SYNC prolong for more
than 5.9 seconds, then these three power management pins will change to the corresponding
states. While changing from any power saving state back to ON state will take about 0.368
second for H_SYNC / V_SYNC pulse checking. And transition between any power saving
state will be done immediately.
Table 2: The truth table of Power Saving Detector
MODE
ON
STAND_BY
SUSPEND
HSIN
VSIN
STD_B
SUSPEND
OFF
Y
1
0
Pulses
No Pulses
Pulses
Pulses
Pulses
No
1
1
0
1
1
1
0
Pulses
No
Pulses
No
OFF
No Pulses
No Pulses
0
1
0
1
0
1
OVERRIDE
Pulses
Manually Power On
7
WT8048
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Synchronization Signals
The basis of DPMS standard is the condition of the synchronization signals to the display.
Two conditions are defined: pulses and no pulses.
{ PULSES
pulses for the Horizontal Sync. Signal are defined as greater than 10KHz repetition
frequency and pulses for the Vertical Sync. Signal are defiened as greater than 40Hz
repetition frequency.
{ NO PULSES
No pulses is defined as less than 10Hz repetition frequency with less than 25% duty cycle
Please refer to the Fig. 1 for the way WT8048 Implement pulses/ no pulses state, between
10Hz and 15KHz / 10KHz, 10Hz and 40Hz. WT8048 use hystersis technique to stable state in
between.
STATE
P
NP
H_SYNC
FREQUENCY
10 Hz
f
T
f = 15k for WT8048
T
= 10k for WT8048N1/N2/N3/N4
STATE
P
NP
V_SYNC
FREQUENCY
10 Hz
40 Hz
Figure 1: pulses / no pulses state implementation
8
WT8048
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OVERRIDE mode
To initiate Override, both the horizontal and vertical sync signals shall be in the no pulses
condition when the display is manually powered on. This condition should be maintained
during the entire time Override is required. As soon as pulses are detected on either horizontal
or vertical sync signal. The display shall enter DPMS operation.
Three power management pins are open drain structure and active low. If you do not need all
those three power saving states in your design. You can just short two or three pins of the
pins: for example, by shorting pin STD_BY and pin Suspend, you will have only two power
saving stated, that is OFF and Suspend states, so you have three states total, including ON
state.
TYPICAL APPLICATION CIRCUIT
WT8048:
5V
VCC
8
7
HSIN
VSIN
1
2
680
10K
5V
3.3M
680
10K
10K
945
6
5
3
4
10K
10K
1
2
470P
32768Hz
NOTE:
1. Transistor: 2SC945¡ A£ >] 300¡ C
2. VDD: +5V ± 10%
9
WT8048
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WT8048N1 / N2:
5V
VCC
8
7
HSIN
VDD
1
2
10k
10p
Rx
(Pin 5 pull up
Rx for N2 only)
VSIN
68K
or
75k
10k
100p
6
5
3
4
NOTE: Connect pin 3 with single resistor for RC oscillation.
WT8048N3 / N4:
5V
VCC
8
7
HSIN
VSIN
1
2
10k
10p
10k
100p
6
5
3
4
3.58
MHz
NOTE:
1. Connect pin 3 with 3.58MHz resonator have good precision of delay time,
frequency division point.
2. This package is not available for production.
10
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