WT9051_技术文档

WT9051

Data Sheet REV1.0

PIN DESCRIPTION

Pin No. Pin Name

Description

Internal Equivalent Circuit

Wave Form

1

GND1

The main ground pin for the

vertical circuit and the I ²C

bus circuit.

GND1

1

2

VOSC

Connect the capacitor for

oscillation of vertical saw

wave.

VCC

25uA 250uA 10uA

5.7V

2.7V

10KΩ

2KΩ

1KΩ

Please connect near pin,

because series resistance

component distorts

Rising waveform of the

vertical saw waveform. Use

the capacitor of the small

temperature drift.

fv

2

5KΩ

1.25KΩ

GND1

GND2

3

VAGC

Connect the capacitor for

AGC of vertical saw

Amplitude of vertical saw

wave is held constant by the

AGC circuit.

Vcc

DC Voltage=3~4V

5KΩ

1.25KΩ

1KΩ

5KΩ

3

GND2

5KΩ

GND1

Weltrend Semiconductor, Inc.

Page 3

WT9051

Data Sheet REV1.0

4

VSAWO

The vertical linearity S/C

compensation are added to

the vertical saw wave form

Vcc

Refers the following

picture image of

correction

2.5KΩ

5KΩ

4

5KΩ

3Vp-p

2.5KΩ

5KΩ

80KΩ

fv

2.5KΩ

GND1

GND2

5

EWO

Outputs the compensation Vcc

signal of the trapezoid, the

side pin, the side pin corner

Refers the following

picture image of

correction

1KΩ

5KΩ

and the horizontal size.

5

5KΩ

333Ω

5KΩ

GND2

GND1

6

VEI

Input the High voltage of the Vcc

EHT. For, it cancel a transient 370uA

response

25uA

DC voltage=4V

5KΩ

10KΩ

5KΩ

of the deflecting voltage. If

this pin isn’t used, connect

10uF capacitor to GND.

4V

10KΩ

6

GND2 10KΩ

2.5Ω

5KΩ

7

HEI

Input the High voltage of the Vcc

EHT. For, it cancel a transient

response

DC Voltage=4V

5KΩ

of the deflecting voltage. If

this pin isn ’t used, connect

10uFcapacitor to GND.

4.0V 10KΩ

10KΩ

5KΩ

7

23.33KΩ

2.5KΩ

GND1

Weltrend Semiconductor, Inc.

Page 4

WT9051

Data Sheet REV1.0

8

DFMIXO

Outputs the mixed signal of

horizontal and vertical

parabola wave for dynamic

focus signal.

Vcc

2.5KΩ

5KΩ

2.5KΩ

8

10KΩ

2.5KΩ

5KΩ

80KΩ

2.5KΩ

GND2

9

HPHASE-C

AP

Vcc

Connect the capacitor 10 μF

to GND

10KΩ

1KΩ

1.67KΩ

9

14KΩ

2.5KΩ

GND2

10

HDSA

Connect the capacitor for

oscillation of Horizontal

dynamic focus signal.

Vcc

DC Voltage=3~4V

5KΩ

10

5K

Ω

5KΩ

2.5KΩ

GND2

11

BAMPI

The input of the error

amplifier for the high voltage

control.

Vcc

50uA

100uA

DC Voltage

5KΩ

2.5KΩ

5KΩ

11

5KΩ

Weltrend Semiconductor, Inc.

Page 5

WT9051

Data Sheet REV1.0

12

BAMPO

Outputs the voltage to control

the PWM pulse width.

Vcc

DC Voltage

1KΩ

5KΩ

12

1KΩ

5KΩ

GND2

13

PSAW

Connect the capacitor and

the resistance for oscillation

of PWM.

Vcc

5kΩ

1.7V

5KΩ

V12pin

1V

13

400Ω

5KΩ

fH

300KΩ

GND2

14

PWMO

Outputs the PWM pulse

Vcc

25uA 25uA

3.33KΩ

30KΩ

Please connect the drive

transistor, because it doesn't

have an enough driving force.

20KΩ

30KΩ

14

0.7V

0V

5KΩ

fH

30KΩ

5KΩ

GND2

15

16

GND2

VCC

The main ground pin for the

horizontal circuit.

15

GND2

Vcc

Input 12volts for the power

supply.

DC voltage=12V

16

Weltrend Semiconductor, Inc.

Page 6

WT9051

Data Sheet REV1.0

17

HOUT

Outputs the horizontal derive Vcc

pulse

20K 20K

50K

17

7.5KΩ

3KΩ

0.7V

0V

GND2

fH

18

FBP

Input the fly back pulse

Vcc

50uA

5KΩ

100uA

2.5KΩ

5V

10KΩ

18

0V

fH

5KΩ

10KΩ

GND2

19

XRAY

The input pin for the X ray

protection.

Vcc

25uA

5KΩ

The bias voltage of the

outside

5KΩ

19

GND2

20

VREF

Outputs the internal reference Vcc 25uA 25uA

106uA

5KΩ

DC voltage=5V

voltage, and creates

internal

a

5KΩ

Reference current by the

resistance. Please connect

the resistor and

10KΩ

Capacitor near this pin,

because noise component

input to this pin affects

38KΩ

10KΩ

20

Horizontal jitter. A current

12KΩ

control

function

is

not

GND2

provided, such that an

External circuit cannot use

the voltage output from this

pin.

Weltrend Semiconductor, Inc.

Page 7

WT9051

Data Sheet REV1.0

21

HFVO

Outputs the voltage tracking Vcc 25uA 25uA

to the horizontal frequency.

DC voltage tracking to

the horizontal frequency

10KΩ

5KΩ

Please connect the resistor

and capacitor near this pin,

because noise component

input to this pin affects

horizontal jitter

15KΩ 15KΩ

25KΩ

5KΩ

4.8V

21

5KΩ

GND2

22

HFVR

Creates the current for the

horizontal oscillator. Please

connect this resistor near this

pin, because noise

component input to this pin

affects horizontal jitter.

Vcc

25uA

Same voltage that pin21

825Ω

10KΩ 10KΩ

15KΩ 15KΩ

22

5KΩ

GND2

23

HOSC

Please connect the capacitor

(390pF) for horizontal

oscillation.

Vcc

463uA

2.5KΩ

1.25KΩ

23

9.9V

4.9V

fH

1.25KΩ

GND2

24

HAFC

Creates the current for the

horizontal oscillator. Please

connect this resistor near this

pin, because noise

Vcc

2.5KΩ

5KΩ

24KΩ 8KΩ

1.67KΩ

3.5V

component input to this pin

affects horizontal jitter.

Please connect the capacitor

(390pF) for horizontal

24

fH

oscillation. Connect the filter

for the auto frequency control

of horizontal. Following is the

item that the filter affects

jitter. The time constant of the

filter The noise of the Vcc and

GND. Connect resistor and

capacitor near this pin.

5KΩ

GND2

Weltrend Semiconductor, Inc.

Page 8

WT9051

Data Sheet REV1.0

25

HLO

The lock detection output of Vcc

the horizontal oscillator

10uA

5V

20KΩ

10uA

2.5KΩ

DC voltage

2.5KΩ

5KΩ

25

5V

5KΩ

Lock

0V

Unlock

GND2

26

HIN

The separate horizontal sync Vcc 50uA

50uA

5KΩ

signal input is

connection.

a

direct

5KΩ

5KΩ 5KΩ

5.0V

0.0V

10KΩ

85Ω

26

fH

5KΩ

separate sync

GND2

27

VIN

The separate Vertical sync

signal input is

connection.

a

direct Vcc

5V

4.7V

5KΩ

2.5V

0V

27

500Ω

fv

separate sync

5KΩ

GND2 GND1

5KΩ

28

BLKO

Outputs the following 3 items

by I ²C bus. The mixed signal Vcc

of the vertical blanking pulse

and the video clamp pulse.

The vertical blanking pulse

only. The video clamp pulse

2.5KΩ

10KΩ

5KΩ

Refers

figure.

the

following

28

only.

5V

2V

10KΩ

GND2

GND1

GND

Weltrend Semiconductor, Inc.

Page 9

WT9051

Data Sheet REV1.0

29

SDA

Input the serial data, and

outputs the acknowledge of

the I 2 C bus.

Vcc

10uA

10KΩ

20uA

5KΩ

5V

5KΩ

29

0V

100KΩ

GND2

GND1

30

SCL

Input the serial clock of I 2 C

bus. The clock frequency Vcc

corresponds to 400 KHZ

10uA

10KΩ

20uA

5KΩ

5V

0V

5KΩ

30

GND2

GND1

Weltrend Semiconductor, Inc.

Page 10

WT9051

Data Sheet REV1.0

Picture Image of Correction

Vertical Output Stage

Function

Output Control Control

Output Wave form

Image

Sub

Condition

Address

Vertical

Size 4

0B_HEX

00_HEX

Correction

D7~D0

(8bits)

2.0Vp-p

FF_HEX

01_HEX

7F_HEX

3.0Vp-p

Vertical Linearity 4

S Correction

0D_HEX

D6~D0

(7bits)

240mVp-p

3.0Vp-p

240mVp-p

3.0 Vp-p

Vertical Linearity 4

C Correction

0E_HEX

D6~D0

(7bits)

01_HEX

135mVp-p

3.0Vp-p

7F_HEX

135mVp-p

Notice: 1. The output amplitude depends on vertical saw wave amplitude(“output amplitude” shows the

wave form when the vertical saw wave is 3.0 Vp-p)

2. Vertical Linearity S or C corrections are OFF status when DAC value is 00H.

Weltrend Semiconductor, Inc.

Page 11

WT9051

Data Sheet REV1.0

E/W Output Stage

Function

Output Control Control

Inside Wave form

Image

Sub

Condition

Address

Trapezoid

Correction

Control

5

0A_HEX

D6~D0

(7bits)

01_HEX

5VDC

0.56Vp-p

7F_HEX

0.56Vp-p

5VDC

Side

Pin 5

09_HEX

00_HEX

Correction

Control

D6~D0

(7bits)

5VDC

0Vp-p

7F_HEX

1.45Vp-p

5VDC

Side Pin Corner 5

Top Correction

Control

07_HEX

D6~D0

(7bits)

00_HEX

0.34Vp-p

7F_HEX

00_HEX

7F_HEX

5VDC

Side Pin Corner 5

Bottom

Correction

Control

08_HEX

D6~D0

(7bits)

0.34Vp-p

5VDC

Notice1The output amplitude depends on vertical saw wave amplitude(output amplitude shows the

waveform when the vertical is 3.0Vp-p.2. Trapezoid or side pin correction is OFF status when DAC

value is 00H.3Side Pin Corner Top/Bottom is 0FF status when both DAC(SPCT and SPCB)value are

00H.

Weltrend Semiconductor, Inc.

Page 12

WT9051

Data Sheet REV1.0

Horizontal Phase Stage

Function

Output Control Control

Inside Wave form

Image

Sub

Condition

Address

Parallelogram

Correction

Control

--

04_HEX

D6~D0

(7bits)

01_HEX

2.5VDC

0.48Vp-p

7F_HEX

0.48Vp-p

2.5VDC

Side

Pin --

03_HEX

01_HEX

Balance

Correction

Control

D6~D0

(7bits)

0.46Vp-p

7F_HEX

0.46Vp-p

0.31Vp-p

2.5VDC

Side Pin Corner --

Balance Top

Correct Control

05_HEX

D6~D0

(7bits)

00_HEX

7F_HEX

00_HEX

7F_HEX

0.31Vp-p

2.5VDC

Side Pin Corner --

Balance Bottom

Correction

06_HEX

D6~D0

(7bits)

Control

2.5VDC

Notice: 1. The output amplitude depends on vertical saw wave amplitude(output amplitude shows the

waveform when the vertical is 3.0Vp-p.

2. Trapezoid or side pin Balance correction is OFF status when DAC value is 00H.

3. Side Pin Corner Balance Top/Bottom are 0FF status when both DAC(SPCT and SPCB)value are

00H.

Weltrend Semiconductor, Inc.

Page 13

WT9051

Data Sheet REV1.0

FUNCTIONAL DESCRIPTION

I 2 C Bus Interface

1. Serial Bus(I 2 C Bus)Interface

(1) I ²C Bus Overview

The I ²C bus is a dual bi-directional serial bus, developed by Philips. It is configured with

two lines –a serial data line(SDA)and a serial clock line(SCL).

The WT9051 features a built-in I ²C bus interface circuit,20 8-bit rewritable registers, and

one 8-bit read-only register that is used for indicating the internal status of the IC and so

on. These are used in write mode(slave receive)and read mode(slave transmit).

(2) Data Transmission Format

The transmission format features a sub address in write mode only. Data is configured in 8-bit

units, after which an acknowledge bit must be appended. Note that data transmission is performed

by transmitting the most significant bit(MSB)first.

The data to be transmitted immediately after the issue of the start conditions is the slave

address used to select the address of the WT9051.This address is configured using seven

bits, with the remaining one bit being the data direction bit, used to set the direction of the

subsequently transmitted data. Read involves transferring data from the WT9051 to the master

device, while write involves transferring data from the master device to the WT9051.

Set 1 for read, or 0 for write. An example of the data transfer format is shown below.

1.Write Mode(Slave Receive)

The slave address is read into the first byte, the sub address is read into the second byte,

while the data can be read into the third and subsequent bytes. By using the sub address

auto-increment function, data can be read out continuously.

(A)1-byte transfer format

STA

SLV

7bit

W

A

SUB

A

DATA

A

STP

1bit

8bit

1bit

8bit

1bit

(B) Continuous byte transfer format

STA SLV

W

A

SUB

A

DATA1

A

7bit

1bit 1bit

1bit

DATA

8bit

1bit

A

STP

1bit

Weltrend Semiconductor, Inc.

Page 14

WT9051

Data Sheet REV1.0

2.Read Mode(Slave Transmit)

The slave address is transmitted from the first byte and data is transmitted from the second and

subsequent bytes. When no acknowledgement bit is received from the master device, release the SDA

line. Do not return an acknowledge signal before issuing the stop conditions.

STA

SLV

7bit

R

A

DATA

8bit

NA

STP

1bit

*Remarks

・STA :Start condition

・SLV :Slave address

・W/R :Data direction bit

W :Write mode (slave receive)

R :Read mode (salve transmit)

・Data :Data

・Sub :Sub address

・A/NA :Acknowledge bit

A :acknowledge

N :No acknowledge

STP :Stop condition

(3) V Period Transfer Mode

The WT9051 is provided with a switch (05H :D7)for setting whether rewriting DAC of the WT9051

is performed in free-run mode or in sync with the V-Sync signal.

・05H :D7 =“0 ”→ Rewriting is performed in free-run mode.

Data is changed while the screen is being displayed, such that if the VSAW amplitude or position

data is changed, horizontal noise lines will appear on the screen.

・05H :D7 =“1 ”→ Rewriting is performed in sync with the V-Sync signal.

Data is changed in the BLK period, such that horizontal noise lines do not appear on the screen.

This technique can be used only to convert the following four items of vertical data.

1.Vertical size control (0BH : D7 to D0)

2.Vertical position control (0CH : D7 to D0)

3.Vertical S linearity (0DH : D6 to D0)

4.Vertical C linearity (0EH : D6 to D0)

*Note on data rewriting in V period transfer mode

When V period transfer mode is used, automatic increment cannot be used.

Only one item of data can be received for each 1V.The second and subsequent items of data are

discarded until BLK is received again. When automatic increment is used, only one item of data

Weltrend Semiconductor, Inc.

Page 15

WT9051

Data Sheet REV1.0

Address Table

1.Slave Address

Mode

White

Read

D7

1

D6

0

D5

0

D4

0

D3

1

D2

1

D1

0

D0

0

1

2. SUB ADDRESS

2-1 Write Mode

<>: initial condition at power on reset

sub

Address

D7

D6

D5

D4

HORIZONTAL DUTY(HDUTY)

<1> <0> <0>

D3

D2

D1

D0

H OUT

Control(HO) Control(PO)

0:exhibit

1:inhibit

PWN OUT

00_HEXX-ray

Protector(XP)

0:normal

<1:reset>

0:exhibit

1:inhibit

<0>

01 _HEX

Horizontal Size <HSIZE>

<1>

<0>

02 _HEX

Horizontal Position<HPOSI>

<1>

<0>

<1>

<0>

03 _HEXV.BLK

Width<VBW>

<0:short>

1:long

04 _HEXDF.OUT

SELECT

0:SEP.

<1:MIX>

05 _HEXV.Period Transfer

SIDE PIN BALANCE <SPB>

<0>

PARALLELOGRAM <PARA>

<0>

SIDE PIN CORNER BALANCE TOP <SPCBT)

Mode

<0:Off>

1:On

<1>

<0>

06 _HEXUnused

SIDE PIN BALANCE BOTTOM(SPCBB)

<0>

07 _HEXClamp Pulse

Position<CP>

<0:Trailing>

1:Leading

08 _HEXV-BLKACI amp

Select<BCI>

<0:BLK+CLP>

1:Select2

09 _HEXV-BLKA CIamp

Select2<BC2>

<0:BLK>

SIDE OIN CORNER TOP<SPCT>

<0>

SIDE PIN CORNER BOTTOM<SPCB>

<0>

SIDE PIN<SP>

1:CLP

<0>

Weltrend Semiconductor, Inc.

Page 16

WT9051

Data Sheet REV1.0

Sub

D7

D6

D5

D4

D3

D2

D1

D0

Address

0A _HEXFHOSC Max.

Frequency

Trapezoid <TRAP>

<0:100kHz>

1:150kHz <1>

<0>

0B _HEX

0C _HEX

Vertical Size <Vsize>

<1>

<0>

Vertical Position <VPOSI>

<1>

<0>

0D _HEXUnused

Vertical Linearity S<VLS>

<0>

0E _HEXHEHT-fH

Tracking

<1>

<0>

Vertical Linearity C<VLC>

EW-HSIZE <1>

0F _HEXTracking

<0>

Horizontal Moire cancellor <HMC>

<0:Track>

1:Unrack

10 _HEXEW-fH

<0>

Vertical Moire cancellor <VMC>

Tracking

0:Untrack

<1:Track>

<0>

11 _HEXHDF-HSIZE

Tracking

Horizontal Dynamic Focus Amplitude<HDFA>

<0:Untrack>

1:Track

12 _HEXUnused

<1>

<0>

Horizontal Dynamic Focus Phase<HDFP>

<0>

13 _HEXUnused

Vertical Dynamic Focus Amplitude<VDF>

<0>

2-2 Read Mode

Sub Address

00_HEX

D7

Unused

D6

Unused

D5

Unused

D4

Unused

D3

Unused Power On H Lock

Reset Detector

D2

D1

D0

X-ray

Detector

0:Undetct

1:Detect

<0>

0:Power on 0:Lock

1:Power Off 1:Unlock

Weltrend Semiconductor, Inc.

Page 17

WT9051

Data Sheet REV1.0

Details of Each Sub Address

Those value in carets <>indicate the settings at a Power On Reset.

Write Mode

1.Sub address 00_H

Sub

D7

D6

H OUT

D5

D4

D3

D2

D1

D0

Address

X-ray

PWM OUT

00_HEX

Horizontal DUTY <HDUTY>

Protector(X Control(HO) Control(PO)

P)

<0:Exhibit> <0:Exhibit>

1:Inhibit 1:Inhibit

0:Normal

<1:Reset>

<1>

<0>

D7: X-ray protector

When the input of Pin19 is over 5V,X-ray protection circuit is active. So the output of the

horizontal output signal(H-OUT)from Pin17 and the output of the PWM pulse (PWMO) from Pin14

disappear.

D6: H-OUT Control

Bit for controlling the output of the horizontal output signal (H-OUT) from Pin17.

When this bit is set to 0,output is possible. When this bit is set to 1,output is disabled.

D5: PWM OUT Control

Bit for controlling the output of the PWM pulse for high voltage control from Pin14.

When this bit is set to 0,output is possible. When this bit is set to 1,output is disabled.

D4 to D0: Horizontal DUTY (HDUTY)

Bit for controlling the duty of the horizontal output signal, output from Pin17.

The duty can be held to roughly will be large.

Sub

D7

D6

D5

D4

D3

D2

D1

D0

Address

01_HEX

Horizontal Size <HSIZE>

<0> <0>

<1>

<0>

D7 to D0: Horizontal Size (HSIZE)

Bit for controlling the horizontal size.

This data is used to modify the DC voltage of the waveform output from Pin5.

Sub

D7

D6

D5

D4

D3

D2

D1

D0

Address

02 _HEX

Horizontal Position<HPOSI>

<0> <0>

<1>

<0>

D7 to D0: Horizontal Position (HPOSI) Bit for controlling the horizontal position. Based on this data, the

horizontal oscillator signal (Pin17)for the horizontal sync input signal

can be converted.

Weltrend Semiconductor, Inc.

Page 18

WT9051

Data Sheet REV1.0

Sub

D7

D6

D5

D4

D3

D2

D1

D0

Address

03_HEXV.BLK

Side Pin Balance<SPB>

Width<VBW>

<0:Short>

1:long

<1>

<0>

D7: V BLK Width

Bit for selecting the vertical blanking pulse width.

When this bit is set to 0, the width is short pulse width. When this bit is set to 1,the width

is long pulse width.

D6 to D0: Side Pin Balance (SPB)

The amount of compensation for the side pin balance can be set using the seven bits from D6 to

D0.The initial value is 40_HEX.The variable range is from 01_HEXto 7F_HEX. When the value is 00_HEXSide

Pin Balance correction is OFF status.

Sub

Address

D7

D6

D5

D4

Parallelogram <PARA>

<0> <0>

D3

D2

D1

D0

04_HEXDF.OUT

Select

0:sep.

<1>

<0>

<1:Mix>

D7: DF.OUT Select

Bit for selecting the output of the parabola wave for dynamic focus signal from Pin8.

When this bit is set to 0,output the vertical dynamic focus signal from Pin8. When this bit is set to

1,output the mixed signal of the horizontal and vertical dynamic focus from Pin8.

D6 to D0: Parallelogram (PARA)

The amount of compensation for the horizontal square wave is set using the seven bits from D6 to

D0.The initial value is 40_HEXthe variable range is from 01_HEXto 7F_HEX. When the value is 00_HEX

Parallelogram correction is OFF status.

Sub

D7

D6

D5

D4

D3

D2

D1

D0

Address

05_HEX

V Period

Transfer

Mode

Side Pin Corner Balance Top<SPCRT>

<0:Off>

1:On

<1>

<0>

D7: V.Period Transfer Mode Bit for setting whether I 2 C-Bus write data transfer is performed in free-run

mode or in sync with the V-Sync signal. When this bit is set to 0,data transfer is performed in free-run

mode. When this bit is set to 1,data transfer is performed in sync with the V-Sync signal.

D6 to D0: Side Pin Corner Balance Top(SPCBT)The amount of compensation for the side pin corner

balance top can be set using the seven bits from D6 to D0.The initial value is 40_HEX.The variable range

is from 00_HEXto 7F_HEX.When this value and Side Pin Corner Balance Bottom DAC value is 00_HEX,Side

Pin Corner Balance Top correction is OFF status.

Weltrend Semiconductor, Inc.

Page 19

WT9051

Data Sheet REV1.0

Sub

Address

D7

D6

D5

D4

Side Pin Corner Balance Bottom<SPCBB>

<0> <0> <0> <0>

D3

D2

D1

D0

06_HEXUnused

<0>

<1>

<0>

D7: Unused

D6 to D0: Side Pin Corner Balance Bottom (SPCBB)

The amount of compensation for the side pin corner balance bottom can be set using the seven bits

from D6 to D0. The initial value is 40_HEX. The variable range is from 00_HEXto 7F_HEX. When this value is

00_HEXand Side Pin Corner Balance Top DAC value is 00_HEX, Side Pin Corner Balance Bottom correction

is OFF status.

Sub

D7

D6

D5

D4

D3

D2

D1

D0

Address

07_HEXClamp Pulse

Position<CP>

<0:Trailing>

Side Pin Corner Top<SPCT>

1:Leading

<1>

<0>

D7: Clamp Pulse Position

Bit for tuning the clamp pulse signal output.

When this bit is set to 0, the clump pulse is output at the trailing edge of the horizontal sync input signal.

When this bit is set to 1, the clump pulse is output at the leading edge of the horizontal sync input signal.

D6 to D0: Side Pin Corner Top (SPCT)

The amount of compensation for the side pin corner top can be set using the seven bits from D6 to D0.

The initial value is 40_HEX. The variable range is from 00_HEXto 7F_HEX. When this value is 00_HEXand Side

Pin Corner Balance Top DAC value is 00_HEX, Side Pin Corner Top correction is OFF status.

Sub

Address

08_HEXV-BLK&Clamp

Select1 (BC1)

D7

D6

D5

D4

Side Pin Corner Bottom<SPCB>

<0> <0> <0>

D3

D2

D1

D0

<0:BLK+CLP> <1>

<0>

1: Select 2

D7: V-BLK&Clamp Select1

Bit for selecting the output from Pin (BLKO)

When this bit is set to 0,the vertical blanking pulse and the clamp pulse are output.

When this bit is set to 1, this output depends on the bit D7 of the sub address”09”

D6 to D0: Side Pin Corner Bottom (SPCB)

The amount of compensation for the side pin corner bottom can be set using the seven bits from D6 to

D0. The initial value is 40_HEX. The variable range is from 00_HEXto 7F_HEX. When this value is 00_HEXand

Side Pin Corner Top DAC value is 00_HEX, Side Pin Corner bottom correction is OFF status.

Weltrend Semiconductor, Inc.

Page 20

WT9051

Data Sheet REV1.0

Sub

Address

09_HEXV-BLK&CIamp

Select2<BC2>

(0: BLK)

D7

D6

D5

D4

Side Pin<SP>

<0> <0>

D3

D2

D1

D0

<0>

1:CLP

D7: V-BLK&Clamp Select2

Bit for selecting the output from Pin28 (BLKO)

When this bit is set to 0,the vertical blanking pulse is output

When this bit is set to 1, the clamp pulse is output.

D6 to D0: Side Pin (SP)

The amount of compensation for the side pin can be set using the seven bits from D6 to D0. The initial

value is 40_HEX. The variable range is from 00_HEXto 7F_HEX. When this value is 00_HEX, Side Pin correction

is OFF status.

Sub

D7

D6

D5

D4

D3

D2

D1

D0

Address

0A_HEXfH OSC Max

Frequency

Trapezoid <TRAP>

<0> <0>

<0:100kHz>

1:150kHz

<1>

<0>

D7: fH OSC Max. Frequency

Bit for setting the maximum horizontal oscillation frequency.

When this bit is set to 0, the maximum oscillation frequency is 100kHz. When this bit is set to 1, the

maximum oscillation frequency is 150kHz.

D6 to D0: Trapezoid (TRAP)

The amount of trapezoid is set using the seven bits from D6 to D0. The initial value is 40_HEX. The

variable range is from 00_HEXto 7F_HEX. When this value is 00_HEX, Trapezoid correction is OFF status.

Sub

Address

D7

D6

D5

D4

Vertical Size <VSIZE>

<0> <0>

D3

D2

D1

D0

0B_HEX

<1>

<0>

D7 to D0: Vertical Size (VSIZE)

Bit used for controlling the vertical size.

The input data is used to control the amplitude of the vertical sawtooth waveform output from Pin4. The

initial value is 80_HEX. The variable range is from 00_HEXto FF_HEX

.

Sub

Address

D7

D6

D5

Vertical Position <VPOSI>

<0> <0> <0>

D4

D3

D2

D1

D0

0C_HEX

<1>

<0>

D7 to D0: Vertical Position (VPOSI)

Bit for controlling the vertical position.

The Data is used to control the DC voltage of the vertical sawtooth waveform output from Pin4.

Weltrend Semiconductor, Inc.

Page 21

WT9051

Data Sheet REV1.0

Sub

Address

D7

D6

D5

D4

Vertical Linearity S<VLS>

<0> <0> <0>

D3

D2

D1

D0

0D_HEXUnused

<0>

<1>

<0>

D7: Unused

D6 to D0: Vertical Linearity S (VLS)

Bits D6 to D0 are used to set the amount of vertical S compensation.

The compensation signal is mixed with the vertical SAW waveform output from Pin4, then output. The

initial value is 40_HEX. The variable range is from 00_HEXto 7F_HEX. When this value is 00_HEX, Vertical

Linearity S correction is OFF status.

Sub

D7

D6

D5

D4

D3

D2

D1

D0

Address

0E_HEXHEHT-fH

Tracking

Vertical Linearity C<VLC>

0:Untrack

<1:Track> <1>

<0>

D7: HEHT-fH Tracking

Bit for selecting whether HEHT gain is tracking to horizontal frequency or not. This function works on

EW fH Tracking (10H:D7)=1 and this bit =1. If EW fH Tracking (10H:D7)=0, this function does not work.

D6 to D0: Vertical Linearity C (VLC)

Bits D6 to D0 are used to set the amount of vertical C compensation.

The compensation signal is mixed with the vertical SAW waveform output from Pin4, then output. The

initial value is 40_HEX. The variable range is from 00_HEXto 7F_HEX. When this value is 00_HEX, Vertical

Linearity C correction is OFF status.

Sub

D7

D6

D5

D4

D3

D2

D1

D0

Address

0F_HEXEW-HSIZ

E

Horizontal Moire Cancellor <HMC>

Tracking

<0:Track>

1:Untrack <0>

<0>

D7: EW-HSIZE

Bit for selecting whether E/W output is tracking to HSIZE or not.

When this bit is set to 0, E/W output is tracking to HSIZE. When this bit is set to 1, E/W output is not

tracking to HSIZE.

D6 to D0: Horizontal Moire Cancellor (HMR)

Bits D6 to D0 are used to set the compensation amount for H moiré cancel.

When the value is 00_HEX, horizontal Moire Cancellor is OFF status.

Weltrend Semiconductor, Inc.

Page 22

WT9051

Data Sheet REV1.0

Sub

D7

D6

D5

D4

D3

D2

D1

D0

Address

10_HEXEW-fH

Tracking

Vertical Moire Cancellor <VMC>

0:Untrack

<1:Track> <0>

<0>

D7: EW-fH Tracking

Bit for selecting whether E/W output is tracking to horizontal frequency or not.

When this bit is set to 0, E/W output is tracking to horizontal frequency. When this bit is set to 1, E/W

output is not tracking to horizontal frequency.

D6 to D0: Vertical Moire Cancellor (VMC)

Bits D6 to D0 are used to set the compensation amount for V moiré cancel.

When the value is 00_HEX, Vertical Moire Cancellor is OFF status.

Sub

D7

D6

D5

D4

D3

D2

D1

D0

Address

11_HEXHDF-HSIZE

Tracking

Horizontal Dynamic Focus Amplitude<HDFA>

<0:Untrack>

1:Track

<1>

<0>

D7: HDF-HSIZE Tracking

Bit for selecting whether HDF output is tracking to HSIZE or not.

When this bit is set to 0, HDF output is tracking to HSIZE. When this bit is set to 1, HDF output is not

tracking to HSIZE.

D6 to D0: Horizontal Dynamic Focus Amplitude (HDFA)

Bits D6 to D0 are used to set the amplitude of the dynamic focus parabola.

When the value is 00_HEX, Horizontal Dynamic Focus is OFF status.

Sub

Address

D7

D6

D5

D4

Horizontal Dynamic Focus Phase<HDFP>

<0> <0> <0>

D3

D2

D1

D0

12_HEXUnused

<0>

<1>

<0>

D7: Unused

D6 to D0: Horizontal Dynamic Focus Phase (HDFP)

Bits D6 to D0 are used to set the amount of compensation for the dynamic focus phase.

Sub

Address

D7

D6

D5

D4

Vertical Dynamic Focus Amplitudes<VDF>

<0> <0> <0>

D3

D2

D1

D0

13_HEXUnused

<0>

<1>

<0>

D7: Unused

D6 to D0: Vertical Dynamic Focus Amplitude (VDF)

Bits D6 to D0 are used to set the amplitude of the dynamic focus parabola.

When the value is 00_HEX, Vertical Dynamic Focus is OFF status.

Weltrend Semiconductor, Inc.

Page 23

WT9051

Data Sheet REV1.0

Read Mode

Sub

Address

D7

Unused Unused Unused Unused

<0> <0> <0> <0>

D6

D5

D4

D3

D2

D1

D0

00_HEX

Unused Power On

Reset

H. Lock

Detector

X-ray

Detector

0: Undetect

1: Detect

<0> 0: Power on 0: Lock

1: Power off 1: Unlock

D7 to D3: Unused

D2: Power On Reset

Used to detect a power on reset. When a power on reset is applied, this bit is set to 1.

Usually, set this bit to 0.Immediately after power-on, or if the power supply voltage ever drops

below around 6.5V(low →high)or 6.2V(high →low),this bit is set to 1.After this bit has been

set to 1, it should be cleared to 0 after two read cycles, provided the 12V power is applied

normally. If, for example, the 12V power is not applied, no matter how many times read is performed,

this bit will not be cleared to 0 and instead will remain set to 1.

D1: H Lock Detector

Used to detect the Lock status of the horizontal sync signal and the oscillator output. In the

lock status, this bit will be set to 0.In the unlock status, this bit will be set to 1.

D0: X-ray Detector

Used to detect the X-ray protection. When the X-ray protection circuit is active, this bit is

set to 1.Usually, set this bit to 0.

Weltrend Semiconductor, Inc.

Page 24

WT9051

Data Sheet REV1.0

OPERATION DESCRIPTION

Automatic Sync. Processing System Sequence

System Block Diagram

18pin FBP

17pin Hout

H-OSC

DAC

Auto Sync.

H-IN

System

25pin HLO

WT9051

Processing Sequence

H-out: oscillate in horizontal

minimum frequency (when

no input signal)

AutoSync Operation

Start

(Trigger:V-In)

Compare H-In frequency and

H-OSC frequency

No

H-In Freq=H.OSC

Freq.?

Counter 1 bit up

H-Out Freq-Up

YES

Counter OFF. AFC On

AFC Lock in 5

vertical term

Court down using H-OSC

Down to minimum freq.

YES

25 Pin “H”

Auto Sync Operation

finish

H-in freq change OR H-in no input

Weltrend Semiconductor, Inc.

Page 25

WT9051

Data Sheet REV1.0

Notice

1) Automatic Sync. system can ’t start count up operation without vertical sync signal input.

The start trigger of count up operation is vertical sync signal input.

2) WT9051 oscillates in minimum free-run frequency during no signal status. Please input desirable

frequency quasi-pulse from MCU to WT9051during no signal status.

3) Please input no signal term for at least 3m sec in changing frequency at any time (Please show

in the following figure.).In the following figure,f1 and f2 means a horizontal input signal

which corresponds to a mode or quasi-pulse signal from MCU.

f1

f2

H-In

No signal term = at least 3m sec

TIMING CHART

The timing of horizontal stage is set by ratio to horizontal frequency (fH ).For example, if

the delay time is 10 μs and fH is 30kHz,the ratio is 30%.

T_ID: I 2 C bus control this delay time.

The control range is form 16%to 43%.

T_HW: The pulse width of signal to the AFC.

This value is 10%.

T_FBP: This delay time is 30%from the rising edge of the fly back pulse.

Horizontal sync

Signal input

Threshold voltage

T_ID

AFC internal pulse

AFC filter waveform

T_HW

Fly back delay

internal pulse

T_FBP

Fly back pulse

input signal

Threshold voltage

Weltrend Semiconductor, Inc.

Page 26

WT9051

Data Sheet REV1.0

Vertical Blanking Pulse (V-BLK)and Video Clamp Pulse (CLAMP)Generator

The WT9051 has an on-chip circuit that generates vertical blanking pulse and clamp pulse.

The output signal mode must be selected by I 2 C bus. Figure illustrates the output signal. (WT9051)

was selecting with outside the putting device. WT9051 was only mixed signal output. However,

WT9051 can be simply selected with the bus.)

The vertical blanking pulse width must be selected by I 2 C bus. It is 288 μs (typical)or 335

μs (typical).The video clamp pulse width is 0.8 μs (typical). (Provided that 20pin resistor is set to 47K

Ω.

The clamp pulse can choose the leading edge or the trailing edge of the horizontal sync by I2C BUS.

1. mixed signal output

5Vpp

2Vpp

GND

CLAMP width

V-BLK width

2. clamp pulse (CLAMP) output

5Vpp

GND

CLAMP width

3. vertical blanking pulse (V-BLK) output

5Vpp

GND

V-BLK width

Weltrend Semiconductor, Inc.

Page 27

WT9051

Data Sheet REV1.0

MOIRE Canceller

1. Vertical MOIRE canceller

It divides V-IN.

The MOIRE can be canceled when shifting a vertical position by this signal.

The shift value can be controlled by I²C bus.

2.Horizontal MOIRE canceller

It divides FBP.

And, it generates the signal, which reversed a phase every other vertical period.

The MOIRE can be canceled when shifting a horizontal position by this signal.

The shift value can be controlled by I²C bus.

V-IN

(Vertical input)

V MOIRE cancel

signal (A point)

FBP -IN

Divided signal

(B point)

H MOIRE cancel

Signal (C point)

A

V-IN

1/2 Divider

V-POSITION

B

C

FBP-IN

V-POSITION

Weltrend Semiconductor, Inc.

Page 28

WT9051

Data Sheet REV1.0

4.5 PWM for B+ control

The PWM Block consists of the error amplifier, and the flip-flop, the oscillator.

1. Error amplifier

The error amplifier is the transconductance amplifier type. The non-inverting input is

connected to the pin11.The non-inverting input is connected to the reference voltage (=2.5Volts).

The output is connected to pin12 and the comparator, the clamp. The clamp limits the maximum

output voltage to 5.0Volts.

2. Oscillator

The external capacitor is charged by a external resistor. When the flip-flop is reset, it is

discharged. The discharge is done until it becomes limit voltage (=1.0Volts).

3. Flip-Flop

This flip-flop will be set at the rising edge of the H-OUT. When the charging voltage (pin13)

of the condenser becomes equal to the output voltage (pin12)of the error amplifier, the output

of the comparator resets a flip-flop.

4. Inhibit mode

It doesn't output in the following case.

・When the X-ray protection becomes active.

・When lower than the voltage of Power On Reset.

・When setting to off by I²C Bus.

Weltrend Semiconductor, Inc.

Page 29

WT9051

Data Sheet REV1.0

Tracking Specifications

Tracking specifications of each waveform and function are shown in the following.

*) “ ( ) “ stands for ON/OFF switch for tracking function.

Waveform/Function

VSAW Amplitude

Vertical S-Linearity

Vertical C-Linearity

Trapezoid

Tracking items

VSIZE, V-EHT

VSIZE, VPOSI, V-EHT

VSIZE, VPOSI, V-EHT, HSIZE(0FH:D7), fH(10H:D7)

VSIZE, VPOSI, V-EHT

HSIZE(11H:D7)

HSIZE, fH(10H:D7), H-EHT

VSIZE

Side Pin

Side Pin Corner Top

Side Pin Corner Bottom

Vertical Dynamic Focus

Horizontal Dynamic Focus

EW DC

V-EHT Gain

H-EHT Gain

FH(10H:D7)

Details of Tracking Specifications

1.EW output tracking to HSIZE

1

HSIZE-DAC vs EW amplitude

HSIZE-DAC small

EW Amp big

big

samll

EW.Amp

HSIZE-DAC

2

3

On/Off Switch of this function

Sub address 0FH:D7

“0”: Track(Initial)

“1”:Untrack

Note

When HSIZE-DAC is changed form FFH to 00H. EW amplitude becomes bigger 30%

2.HDF output tracking to HSIZE

1

HSIZE-DAC vs. HDF amplitude

HSIZE-DAC small

HDF Amp. big

big

samll

HDF.Amp

HSIZE-DAC

2

3

On/Off Switch of this function

Sub address 11H:D7

“0”: Track(Initial)

“1”:Untrack

Note

When HSIZE-DAC is changed form FFH to 00H. HDF amplitude becomes bigger 70%

Weltrend Semiconductor, Inc.

Page 30

WT9051

Data Sheet REV1.0

3. EW output tracking to horizontal frequency

1

Horizontal frequency vs. EW DC voltage

FH

EW DC

low

high

EW DC

fH

2

3

On/Off Switch of this function

Sub address 10H:D7

“0”: Untrack (Initial)

“1”:track

Note

Formula for EW DC voltage EW DC=((fH/100k-1)x 0.325+1)x 5V

4. H-EHT Gain tracking to horizontal frequency

1

Horizontal frequency vs. Gain(=△EWO/△HEI)

FH

Gain

low

small

high

big

△ EWO/

△HEI

fH

2

On/Off Switch of this function

Sub address 0FH:D7(only on the condition that the data of sub address 10H:D7 is “1”

“1”: Track (Initial) “0”:Untrack

Weltrend Semiconductor, Inc.

Page 31

WT9051

Data Sheet REV1.0

Electrical Characteristics

Absolute Maximum Ratings (Unless otherwise specified, Ta=25^。C)

Parameter

Power Supply

Symbol

V_CC

Condition

Input Voltage of pin16

Rating

14

Unit

V

SDA Input Voltage

SDA Output Sink Current

SCL Input Voltage

VSAW Output Source Current

VSAW Output Sink Current

E/W Output Source Current

VEI Input Voltage

V_SDA

I_SDA

V_SCL

I_VSAWO

I_VSAWI

I_EWO

Input Voltage Range of pin29

Output sink current of pin29

Input Voltage Range of pin30

Output Source Current of pin4

Output Sink Current of pin4

Output Source current of pin5

Input Voltage Range of pin6

Input Voltage Range of pin7

Input Voltage Range of pin11

Input Voltage Range of pin12

Output Sink Current of pin14

Output Source Current of pin8

Output Source Current of pin9

Input Pulse Voltage Range of pin18

Output Sink Current of pin17

Input Pulse Voltage Range of pin26

Input Pulse Voltage Range of pin27

Output Source Current of pin28

Ta=70。C, R_TH=55。C

-0.2~Vcc

10

-0.2~Vcc

4.5

V

mA

V

mA

V

mA

V

mA

V

mA

W

4.5

V_VEI

V_HEI

-0.2~Vcc

10

HEI Input Voltage

BAMPI Input Voltage

V_BAMPI

V_BAPO

I_PWMI

I_VDF1

I_HDF1

V_FBP

I_HOUTI

V_HIN

BAMPO Input Voltage

PWM Output Sink Current

V.DF Output Source Current

H.DF Output Source Current

Fly Back Pulse Input Voltage

Horizontal Output Sink Current

Horizontal Input Voltage

Vertical Input Voltage

4.5

-0.2~Vcc

10

-0.2~Vcc

4.5

V_VIN

I_BLK

BLK&CLP Output Source Current

Permissible package power dissipation P_d

1.0

Operating ambient temperature

Storage temperature

T_a

T_STG

-10~+75 。C

-40~+125 。C

Notice:

If the absolute maximum rating of even one of the above parameters is exceeded even momentarily,

the quality of the product may be degraded. In other words, absolute maximum ratings specify the

values exceeding which the product may be physically damaged. Be sure to use the product with these

ratings never exceeded. In addition, pins not listed in the above table must also be used in a

range of 0 to Vcc .

RECOMMENDED OPERATING RANGE(Vcc=12V, Ta=25^。C, Vcc=12V, unless otherwise noted)

Parameter

Supply Voltage

Symbol Test Condition

MIN TYP MAX Unit

11.5 12.0 12.5 V

V_CC

V_SDAL

Pin16 input voltage

Pin29 input low level

SDA Input Low Level

SDA Input High Level

SCL Input Low Level

SCL Input High Level

Horizontal Operating Frequency F_H

Range

0

5

0

5

-

1.5

5

V

V_SDAHPin29 input high level

2.3

0

2.3

30

V_SCLL

V_SCLH

Pin30 input low level

Pin30 input high level

Pin26 input frequency

1.5

5

150 KHz

Horizontal Input Duty Ratio1

D_HIN1

Pin26 input pulse duty ratio

-

20

-

%

amplitude=5Vp-p input polarity: positive

Pin26 input pulse duty ratio amplitude

=5Vp-p input polarity: Negative

Pin27 Input Frequency

Horizontal Input Duty Ratio2

D_HIN2

60

50

-

Vertical Operating Frequency F_v

Range

Vertical Input Pulse Width

200 Hz

580 us

W_VIN1Pin27 Input Pulse duty ratio amplitude

=5Vp-p Input Polarity: Positive

Weltrend Semiconductor, Inc.

Page 32

WT9051

Data Sheet REV1.0

ELECTRONICAL CHARACTERICS(TA=25^。C, Vcc=12V, unless otherwise noted)

Parameter

Symbol Test Condition

MIN TYP MAX Unit

Supply Current

I_CC

VREF

V_PORH

Supply current of pin16 no signal

Pin20

Input Vcc from 0V to 12V.Judged by

existence of ACK

60

4.5

6.0

69

5.0

6.5

81 mA

Reference Voltage

Power on reset voltage1

(LowÆHigh)

5.5

7.0

V

Power on Reset Voltage2

(HighÆLow)

SDA Input Threshold

Voltage1

SDA Input Threshold

Voltage2

V_PORL

V_SDA1

V_SDA2

Input level from 0V to 5V

5.7

1.7

1.4

6.2

2.0

1.7

6.7

2.3

2.0

V

Input level from 0V to 5V

Input level from 5V to 0V

SCL Input Threshold

Voltage1

SCL Input Threshold

Voltage2

V_SCL1

V_SCL2

Input level from 0V to 5V

Input level from 5V to 0V

1.7

1.4

2.0

1.7

2.3

2.0

V

Horizontal Sync Input Block (measurement at Pin26(HIN)

Parameter

Direct input Threshold Voltage

Symbol Test Condition

V_HTHInput signal: separate sync direct input

MIN

0.4

TYP MAX Unit

0.6 0.8 V

H.IN Delay Block(measurement at Pin24 (HAFC))

Parameter

Symbol Test Condition

MIN TYP MAX Unit

HIN Delay Variable 1

T _HPD1HPOSI=00_HEX, Difference from pin26 to 11.5 15.5 19.4 %

pin24. Ratio with period.fH=30kHz

HIN Delay Variable 2

T _HPD2HPOSI=FF_HEX, Difference from pin26 to 33.6 40.0 46.4 %

pin24. Ratio with period. fH=30kHz

HIN Delay Variable Amount1

HIN Delay Variable 3

T _HPDA1(T_HPD2-T_HPD1)/255 fH=30kHz

T _HPD3HPOSI=00_HEX, Difference from pin26 to 14.3 17.5 20.7 %

pin24. Ratio with period. fH=150kHz

0.083 0.105 0.127 %/step

HIN Delay Variable 4

T _HPD4HPOSI=FF_HEX, Difference from pin26 to 36.3 42.0 47.7 %

pin24. Ratio with period. fH=150kHz

HIN Delay Variable Amount 2

T _HPDA2(T_HPD4-T_HPD3)/255 fH=30kHz

0.079 0.100 0.121 %/step

H-WIDH BLOCK(measurement at pin24(HAFC))

Parameter

Symbol Test Condition

MIN TYP MAX Unit

H-WIDTH Variable1

H-WIDTH Variable2

T _HWD1

T _HWD2

F_H=30kHz

F_H=150kHz

8.5

10.0 11.5 %

AFC BLOCK(measurement at pin24(HAFC))

Parameter

Symbol Test Condition

AFC1 Positive Capture Range at F_H=30kHz 7.47 8.30 9.13

AFC2 Negative Capture Range at F_H=30kHz -9.13 -8.30 -7.47 %

AFC3 Positive Capture Range at F_H=150kHz 7.65 8.50 9.35

AFC4 Negative Capture Range at F_H-9.35 -8.50 -7.65 %

=150kHz

MIN TYP MAX Unit

Horizontal AFC Pull in Range1

Horizontal AFC Pull in Range2

Horizontal AFC Pull in Range3

Horizontal AFC Pull in Range4

%

Weltrend Semiconductor, Inc.

Page 33

WT9051

Data Sheet REV1.0

FBP Delay Block(measurement at pin18(FBPIN) and pin24(HAFC))

Parameter

Symbol Test Condition

MIN TYP MAX Unit

FBP Input Threshold Voltage1

FBP Input Threshold Voltage 2

FBP Delay

V_FBP1Input level from 0V to 5V

V_FBP2Input level from 5V to 0V

2.2

1.9

2.5

2.2

30

2.8 V

2.5 V

T_FBP

Difference from pin18 to pin24.Ratio with 24.3

period

30

%

H-OSC Block(measurement at pin17(HOUT)) these value is excluding spread of

external components

Parameter

Symbol Test Condition

MIN TYP MAX Unit

20.38 22.30 24.22 KHz

22.92 25.09 27.25 KHz

34.4 37.0 39.6 KHz

H.free-run frequency 1

H.free-run frequency 2

H-OSC frequency 1

F_H01

F_H02

F_H01

No input signal pin22 resistor=1.8KΩ

No input signal pin22 resistor=1.6KΩ

No input signal pin22 is 1V. Pin22

resistor=1.8KΩ

H-OSC frequency 2

F_H02

No input signal when pin22 resistor

=1.8KΩ

135

145

155 KHz

H-Duty Block(measurement at pin17(HOUT))

Parameter

H-duty 1

H-duty 2

H-duty 3

H-duty Amount1

H-duty 4

H-duty 5

H-duty 6

H-duty Amount 2

Symbol Test Condition

MIN TYP MAX Unit

34.3 39.0 43.7 %

44.0 50.0 56.0 %

53.2 60.5 67.8 %

0.590 0.694 0.798 %/step

34.3 39.0 43.7 %

44.0 50.0 56.0 %

53.2 60.5 67.8 %

0.590 0.694 0.798 %/step

H_DUTY1HDUTY=00_HEXfH=30kHz

H_DUTY2HDUTY=10_HEXfH=30kHz

H_DUTY3HDUTY=1F_HEXfH=30kHz

H_DUTYA1(H_DUTY3-H_DUTY1)/31 fH=30kHz

H_DUTY4HDUTY=00_HEXfH=150kHz

H_DUTY5HDUTY=10_HEXfH=150kHz

H_DUTY6HDUTY=1F_HEXfH=150kHz

H_DUTYA2(H_DUTY6-H_DUTY4)/31 fH=150kHz

H-Out Block(measurement at collector of transistor attached at pin17)

Parameter

Symbol Test Condition

MIN TYP MAX Unit

H-Out Low Level

V_HOL

0

0.2

0.3 V

Pull up resistor 20KΩ

Difference from GND Level

H-Out High Level

V_HOH

-0.2

0

V

Pull up resistor 20KΩ

Difference from Vcc Level

Weltrend Semiconductor, Inc.

Page 34

WT9051

Data Sheet REV1.0

Vertical Input Block (measurement at pin27(VIN))

Parameter

Vertical Input Threshold Voltage

Symbol Test Condition

V_VINThreshold voltage of pin27

MIN

2.2

TYP MAX Unit

2.5 2.8

V

V Position Block (measurement at pin4(VSAWO))

Parameter

Symbol Test Condition

MIN

TYP MAX Unit

Vertical Position1

Vertical Position2

Vertical Position3

Vertical Position Amount

V_P01

V_P02

V_P03

V_P0A

VPOSI=00_H

VPOSI=7F_H

VPOSI=FF_H

(VP₀₃-VP₀₁)/255

2.962 3.153 3.348 V

3.325 3.500 3.675 V

3.620 3.847 4.076 V

2.32

2.72 3.15 mV/step

V-SAW Block measurement at pin4(VSAWO))

Parameter

Symbol Test Condition

V_SAW1VSIZE=00_H

V_SAW2VSIZE=FF_H

V_SAWV_SAW1-V_SAW2/255

MIN

1.65

2.65

3.27

TYP MAX Unit

Vertical Saw wave Amplitude 1

Vertical Saw wave Amplitude 2

Vertical Saw wave Amplitude

Amount

2.0

3.0

2.35 V_P-P

3.35 V_P-P

3.94 4.61 mV/step

V.free-run frequency

V.free-run Amplitude

F_V0

No input signal

10

3.2

25

3.6

40 Hz

4.0 V

V_SAW0No input signal

<V-BLK/CLAMP Pulse unit>

V-BLK/CLAMP Pulse (measurement at pin28)

Parameter

Vertical Blanking Pulse Width1

Vertical Blanking Pulse Width2

Vertical Blanking Pulse Amplitude V_BLK

Video Clamp Pulse Width

Symbol Test Condition

MIN

225

260

4.5

0.4

4.5

TYP MAX Unit

265 305 us

305 350 us

T_BLK1

T_BLK2

VBW=0, 20pin Resistor=47kΩ

VBW=1, 20pin Resistor=47kΩ

5.0

0.6

5.0

5.5 V_P-P

0.8 us

5.5 V_P-P

T_CLP

V_CLP

20pin Resistor=47kΩ

Video Clamp Pulse Amplitude

Vertical Linearity “s” Correction Block(measurement at pin4(VSAWO), (notice1, 2)

Parameter

Symbol Test Condition

MIN

TYP MAX Unit

Vertical Linearity”S”

Correction Amplitude1

Vertical Linearity”S”

Correction Amplitude2

Vertical Linearity”S”

Correction Amplitude3

Vertical Linearity”S”

Correction Amplitude4

Vertical Linearity”S”

Correction Amplitude5

Vertical Linearity”S”

Correction Amplitude6

Vertical Linearity”S”

Correction Amount

V_S1

V_S2

V_S3

V_S4

V_S5

V_S6

V_S

VLS=01_HEX,VSIZE=FF_HEX

Difference from V_POCat top part

VLS=01_HEX,VSIZE=FF_HEX

Difference from V_POCat bottom part

VLS=40_HEX,VSIZE=FF_HEX

Difference from V_POCat top part

VLS=40_HEX,VSIZE=FF_HEX

Difference from V_POCat bottom part

VLS=7F_HEX,VSIZE=FF_HEX

Difference from V_POCat top part

-370 -240 -110 mV

110

-70

110

240 370 mV

0

70 mV

240 370 mV

VLS=7F_HEX,VSIZE=FF_HEX

Difference from V_POCat bottom part

(V_S5-V_S1)/126

-370 -240 -110 mV

2.39 3.81 5.23 mV/step

Weltrend Semiconductor, Inc.

Page 35

WT9051

Data Sheet REV1.0

Vertical Linearity”C” Correction Block(measurement at pin4(VSAWO), (notice1, 3))

Parameter

Symbol Test Condition

MIN

60

TYP MAX Unit

135 210 mV

Vertical Linearity”C”

Correction Amplitude1

Vertical Linearity”C”

Correction Amplitude1

Vertical Linearity”C”

Correction Amplitude2

Vertical Linearity”C”

Correction Amplitude2

Vertical Linearity”C”

Correction Amplitude3

Vertical Linearity”C”

Correction Amplitude3

Vertical Linearity”C”

Correction Amount

V_C1

V_C2

V_C3

V_C4

V_C5

V_C6

V_C

VLC=01_HEX,VSIZE=FF_HEX

Difference from V_POCat top part

VLC=01_HEX,VSIZE=FF_HEX

Difference from V_POCat bottom part

VLC=40_HEX,VSIZE=FF_HEX

Difference from V_POCat top part

VLC=40_HEX,VSIZE=FF_HEX

Difference from V_POCat bottom part

VLC=7F_HEX,VSIZE=FF_HEX

Difference from V_POCat top part

60

135 210 mV

-100

0

100 mV

-210 -135 -60 mV

VLC=7F_HEX,VSIZE=FF_HEX

Difference from V_POCat bottom part

(V_C5-V_C1)/126

1.55

2.14 2.75 mV/step

H-Size Control Block(measurement at Pin5(EWO), (notice4, 5, 6)

Parameter

Symbol Test Condition

MIN

3.15

3.83

4.5

5.31

3.40

5.11

TYP MAX Unit

3.5 3.85 V

4.25 4.68 V

E/W Output DC Voltage1

E/W Output DC Voltage2

E/W Output DC Voltage3

E/W Output DC Voltage Amount V_EW

E/W Output DC Voltage4

E/W Output DC Voltage5

V_EW1

V_EW2

V_EW3

HSIZE=00_H,fH-track=off

HSIZE=7F_H,fH-track=off

HSIZE=FF_H,fH-track=off

(V_EW3-V_EW1)/255

5.0

5.5 V

5.91 6.51 mV/step

3.86 4.32 V

5.81 6.51 V

V_EW4

V_EW5

HSIZE=FF_H,fH=30k

HSIZE=FF_H,fH=150k

Trapezoid Correction Block(measurement at pin5(EWO), (notice5, 6)

Parameter Symbol Test Condition

MIN

-350

TYP MAX Unit

-280 -210 mV

Trapezoid Correction Amplitude1 V_TRA1

Trapezoid Correction Amplitude2 V_TRA2

Trapezoid Correction Amplitude3 V_TRA3

Trapezoid Correction Amplitude4 V_TRA4

Trapezoid Correction Amplitude5 V_TRA5

Trapezoid Correction Amplitude6 V_TRA6

TRAP=01_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at top part,

fH-track=off

TRAP=01_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at bottom

part, fH-track=off

TRAP=40_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at top part,

fH-track=off

TRAP=40F_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at bottom

part, fH-track=off

TRAP=7F_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at top part,

fH-track=off

TRAP=7F_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at bottom

part, fH-track=off

210

-50

280 350 mV

0

50 mV

-50

210

-350

3.55

280 350 mV

-280 -210 mV

Trapezoid Correction Amplitude V_TRA

Amount

V _TRA5-V_TRA1/126

4.44 5.33 mV/ste

p

Trapezoid Correction Amplitude7 V_TRA7

Trapezoid Correction Amplitude8 V_TRA8

Trapezoid Correction Amplitude9 V_TRA9

V_TRA5, HSIZE=FF_H, fH=30k

V_TRA5, HSIZE=FF_H, fH=150k

V_TRA5, HSIZE=FF_H, fH-track=off

175

256

273

235 295 mV

344 432 mV

364 455 mV

Weltrend Semiconductor, Inc.

Page 36

WT9051

Data Sheet REV1.0

Side Pin Correction Block (measurement at pin5(EWO), (notice4, 6)

Parameter

Symbol Test Condition

MIN TYP MAX Unit

Side Pin Correction Amplitude1

V_SP1

V_SP2

V_SP3

V_SP4

V_SP5

V_SP6

SP=01_H, VSIZE= FF_H,HSIZE= FF_H,

Difference from V_EW3at top part,

fH-track=off

SP=01_H, VSIZE= FF_H,HSIZE= FF_H,

Difference from V_EW3at bottom part,

fH-track=off

SP=40_H, VSIZE= FF_H,HSIZE= FF_H,

Difference from V_EW3at top part,

fH-track=off

SP=40F_H, VSIZE= FF_H,HSIZE= FF_H,430

Difference from V_EW3at bottom part,

fH-track=off

SP=7F_H, VSIZE= FF_H,HSIZE= FF_H,

Difference from V_EW3at top part,

fH-track=off

SP=7F_H, VSIZE= FF_H,HSIZE= FF_H,

Difference from V_EW3at bottom part,

fH-track=off

-120

430

0

120 mV

Side Pin Correction Amplitude2

Side Pin Correction Amplitude3

Side Pin Correction Amplitude4

Side Pin Correction Amplitude5

Side Pin Correction Amplitude6

0

120 mV

725 1020 mV

1025 1450 1875 mV

Side Pin Correction Amplitude

Amount

V_SP

V _SP5-V_SP1/126

9.21 11.51 13.81 mV/ste

p

Side Pin Correction Amplitude7

Side Pin Correction Amplitude8

Side Pin Correction Amplitude9

V_SP7

V_SP5, HSIZE=FF_H, fH=30k

844 1215 1586 mV

1237 1780 2323 mV

1320 1885 2451 mV

V_TSP8V_SP5, HSIZE=FF_H, fH=150k

V_SP9V_SP5, HSIZE=FF_H, fH-track=off

Side Pin Corner “Top” Correct Block (measurement at Pin5(EWO), (notice4, 5, 8)

Parameter

Symbol Test Condition

MIN TYP MAX Unit

SPC-T Correction Amplitude1

V_SPCT1SPCT=00_H, VSIZE= FF_H,HSIZE= FF_H,-480 -340 -200 mV

Difference from V_EW3at top part,

fH-track=off

SPC-T Correction Amplitude2

SPC-T Correction Amplitude3

SPC-T Correction Amplitude4

SPC-T Correction Amplitude5

SPC-T Correction Amplitude6

V_SPCT2SPCT=00_H, VSIZE= FF_H,HSIZE= FF_H,-80

Difference from V_EW3at bottom part,

fH-track=off

0

80 mV

480 mV

80 mV

V_SPCT3SPCT =40_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at top part,

fH-track=off

-80

200

-80

V_SPCT4SPCT =40F_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at bottom

part, fH-track=off

0

V_SPCT5SPCT =7F_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at top part,

fH-track=off

340

0

V_SPCT6SPCT =7F_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at bottom

part, fH-track=off

SPC-T Correction Amplitude

Amount

V_SPCT

V _SPCT5-V_SPCT1/127

3.17 5.40 7.62 mV/ste

p

SPC-T Correction Amplitude7

SPC-T Correction Amplitude8

SPC-T Correction Amplitude9

V_SPCT7V_{SPCT 5}, HSIZE=FF_H, fH=30k

V_SPCT8V_{SPCT 5}, HSIZE=FF_H, fH=150k

V_SPCT9V_{SPCT 5}, HSIZE=00_H, fH-track=off

165

242

256

285

417

442

405 mV

592 mV

628 mV

Weltrend Semiconductor, Inc.

Page 37

WT9051

Data Sheet REV1.0

Side Pin Corner “BOTTOM” Correct Block (measurement at Pin5(EWO), (notice4, 5, 8)

Parameter

Symbol Test Condition

MIN TYP MAX Unit

SPC-B Correction Amplitude1

V_SPCB1SPCB=00_H, VSIZE= FF_H,HSIZE= FF_H,-80

Difference from V_EW3at top part,

fH-track=off

0

80 mV

SPC-B Correction Amplitude2

SPC-B Correction Amplitude3

SPC-B Correction Amplitude4

SPC-B Correction Amplitude5

SPC-B Correction Amplitude6

V_SPCB2SPCB=00_H, VSIZE= FF_H,HSIZE= FF_H,-480 -340 -200 mV

Difference from V_EW3at bottom part,

fH-track=off

V_SPCB3SPCB =40_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at top part,

fH-track=off

V_SPCB4SPCB =40F_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at bottom

part, fH-track=off

V_SPCB5SPCB =7F_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at top part,

fH-track=off

V_SPCB6SPCB =7F_H, VSIZE= FF_H,HSIZE=

FF_H,Difference from V_EW3at bottom

part, fH-track=off

-80

200

0

80 mV

480 mV

0

340

SPC-B Correction Amplitude

Amount

V_SPCBV _SPCB6-V_SPCB2/127

3.17 5.40 7.62 mV/ste

p

SPC-B Correction Amplitude7

SPC-B Correction Amplitude8

SPC-B Correction Amplitude9

V_SPCB7V_{SPCB 6}, HSIZE=FF_H, fH=30k

V_SPCB8V_SPCB6, HSIZE=FF_H, fH=150k

V_SPCB9V_SPCB6, HSIZE=FF_H, fH-track=off

165

242

256

285

417

442

405 mV

592 mV

628 mV

Parallelogram Correction Block (internal measurement, (notice 10,11))

Parameter

Parallelogram Correction

Amplitude1

Symbol Test Condition

V_PARA1PARA=01_H, Top part

MIN TYP MAX Unit

-300 -240 -180 mV

Parallelogram Correction

Amplitude2

Parallelogram Correction

Amplitude3

Parallelogram Correction

Amplitude4

Parallelogram Correction

Amplitude5

V_PARA2PARA=01_H, Bottom part

V_PARA3PARA =40_H, Top part

V_PARA4PARA=40_H, Bottom part

V_PARA5PARA =7F_H, Top part

V_PARA6PARA=7F_H, Bottom part

180 240 300 mV

-45

0

45 mV

180 240 300 mV

-300 -240 -180 mV

3.04 3.81 4.58 mV/step

Parallelogram Correction

Amplitude6

Parallelogram Correction Amount V_PARAT _PARA5-T_PARA1/126

Weltrend Semiconductor, Inc.

Page 38

WT9051

Data Sheet REV1.0

Side Pin Balance Correct Block (internal measurement, (notice9, 11))

Parameter

SPB Correction

Amplitude1

SPB Correction

Amplitude2

SPB Correction

Amplitude3

SPB Correction

Amplitude4

SPB Correction

Amplitude5

Symbol Test Condition

MIN TYP MAX Unit

-600 -460 -320 mV

V_SPB1

V_SPB2

V_SPB3

V_SPB4

V_SPB5

SPB=01_H, Top part

SPB=01_H, Bottom part

SPB =40_H, Top part

SPB=40_H, Bottom part

SPB =7F_H, Top part

-600 -460 -320 mV

-120

0

120 mV

320 460 600 mV

SPB Correction

Amplitude6

SPB Correction Amount V_SPB

V_SPB6

SPB=7F_H, Bottom part

T _PARA5-T_PARA1/126

320 460 600 mV

5.84 7.30 8.76 mV/step

Side Pin Corner Balance Top Correction Block(internal measurement, (notice9,10, 13))

Parameter

Symbol Test Condition

MIN TYP MAX Unit

SPCB-T Correction

Amplitude1

V_SPCBT1SPCBT=00_H, Top part

-410 -310 -210 mV

SPCB-T Correction

Amplitude2

SPCB-T Correction

Amplitude3

SPCB-T Correction

Amplitude4

SPCB-T Correction

Amplitude5

V_SPCBT2SPCBT=00_H, Bottom part

V_SPCBT3SPCBT =40_H, Top part

V_SPCBT4SPCBT=40_H, Bottom part

V_SPCBT5SPCBT =7F_H, Top part

-80

210

0

80 mV

410 mV

0

310

SPCB-T Correction

Amplitude6

V_SPCBT6SPCBT=7F_H, Bottom part

-80

0

80 mV

SPCB-T Correction

Amount

V_SPCBT

V _SPCBT5-V_SPCBT1/127

3.33 4.92 6.51 mV/step

Side Pin Corner Balance Bottom Correction Block(internal measurement, (notice9,10, 12))

Parameter

Symbol Test Condition

MIN TYP MAX Unit

SPCB-B

Amplitude1

SPCB- B

Correction Amplitude2

SPCB- B

Correction Amplitude3

SPCB- B

Correction Amplitude4

SPCB- B

Correction V_SPCBB1SPCBB=00_H, Top part

-80

210

-80

0

310

0

80 mV

410 mV

80 mV

V_SPCBB2SPCBB=00_H, Bottom part

V_SPCBB3SPCBB =40_H, Top part

V_SPCBB4SPCBB=40_H, Bottom part

V_SPCBB5SPCBB =7F_H, Top part

0

Correction Amplitude5

SPCB-B

V_SPCBB6SPCBB=7F_H, Bottom part

-410 -310 -210 mV

Correction Amplitude6

SPCB- B

V_SPCBB

V _SPCBB5-V_SPCBB1/127

3.33 4.92 6.51 mV/step

Correction Amount

Weltrend Semiconductor, Inc.

Page 39

WT9051

Data Sheet REV1.0

H-EHT Block(measurement at pin5(EW))

Parameter

Symbol Test Condition

MIN TYP MAX Unit

7pinOpen Voltage

V_7PIN

3.6

-

4.77

4.0

-

4.4

2.2

-

V

Input Minimum D-Range V_LEHTH

Input Maximum D-Range V_HEHTH

EHT-H Correction Gain1 G_EHTH1

Minimum input voltage

Maximum input voltage

Between EWO to EHTH gain FH- tracking -1.06 -0.88 -0.70 Times

=off

EHT-H Correction Gain2 G_EHTH2

EHT-H Correction Gain3 G_EHTH3

G_EHTH1,fH=30k

-0.28 -0.20 -0.12 Times

G_EHTH1,fH=150k

-1.70 -1.42 -1.14 Times

V-EHT Block (measurement at pin4(VSAWO))

Parameter

Symbol Test Condition

MIN TYP MAX Unit

6pinOpen Voltage

V_6PIN

3.6

-

4.75

4.0

-

4.4

3.81

-

V

Input Minimum D-Range V_LEHTV

Input Maximum D-Range V_HEHTV

EHT-V Correction Gain1 G_EHTV1

EHT-V Correction Gain2 G_EHTV2

Minimum input voltage

Maximum input voltage

Between Vsawo to EHTV gain Vsize=FF

Between Vsawo to EHTV gain Vsize=01

1.47 1.72 1.97 Times

1.65 1.92 2.19 Times

Horizontal Moire Canceller Block(measurement at 17pin(HOUT))

Parameter

Symbol Test Condition

MIN TYP MAX Unit

H Moire Canceller Variable1 T_HMC1HMC=01_H,fH=30kHz

Ratio with period

0

2.8

5.0

ppm

H Moire Canceller Variable2 T_HMC2HMC=7F_H,fH=30kHz

Ratio with period

170

200

230

ppm

H Moire Canceller Variable T_HMC

Amount

T_HMC2-T_HMC1/126

1.32 1.55 1.79 ppm

Vertical Moire Canceller Block (measurement at 4 pin(VSAWO))

Parameter Symbol Test Condition

MIN TYP MAX Unit

V Moire Canceller Variable1 V_VMC1VMC=01_H

V Moire Canceller Variable2 V_VMC2VMC=7F_H

0

0.4

3.06 3.6

24.09 28.35 32.60 uV/step

0.8

mVp-p

4.14 mVp-p

V Moire Canceller Variable V_VMC

Amount

V_VMC2-V_VMC1/126

Horizontal/Vertical Mixed Dynamic Focus Block (measurement at 8pin)

Parameter

Symbol Test Condition

MIN TYP MAX Unit

H-DF Amplitude1

H-DF Amplitude2

H-DF Amplitude Amount

H-DF Amplitude3

H-DF Amplitude4

V-DF Amplitude1

V-DF Amplitude2

V-DF Amplitude Amount

H-DF Phase1

V_HDFMA1HDFA=01_HEX, 04_HEXD7=”1”

V_HDFMA2HDFA=7F_HEX, 04_HEXD7=”1”

V_HDFMAV_HDFMA2-V_HDFMA1/126

V_HDFMA3V_HDFMA2,HSIZE-Track=ON HSIZE=00_HEX

V_HDFMA4V_HDFMA2,HSIZE-Track=ON HSIZE=FF_HEX

V_VDFMA1VDFA=01_HEX, 04_HEXD7=”1”

V_VDFMA2VDFA=01_HEX, 04_HEXD7=”1”

V_VDFMAV_VDFA2-V_VDFM1/126

0.3

1.5

8.7

1.8

0.5

2.0

0.7

2.5

Vp-p

11.9 15.3 mV/step

2.41 3.01 Vp-p

1.05 1.4

1.75 Vp-p

0.7

2.5

0.3

1.5

8.7

0.5

2.0

Vp-p

11.9 15.3 mV/step

V_HDFP1HDFP=00 _HEX

V_HDFP2HDFP=7F _HEX

0.25 0.36 0.47 us

0.70 1.00 1.30 us

H-DF Phase2

H-DF Phase Amount

V_HDFPV_HDFP2-V_HDFP1/127

3.6

5.1

6.6

ns/step

Weltrend Semiconductor, Inc.

Page 40

WT9051

Data Sheet REV1.0

Vertical Dynamic Focus Block (measurement at 9pin)

Parameter

Symbol Test Condition

MIN TYP MAX Unit

V-DF Amplitude1

V-DF Amplitude2

V-DF Amplitude Amount

V_VDFA1VDFA=01_HEX, DFSelect=”0”

V_VDFA2VDFA=7F_HEX, DFSelect=”0”

V_VDFAV_VDFA2-V_VDFA1/126

0.6

3.0

18

1.0

4.0

24

1.4

5.0

30

Vp-p

mV/step

Error AMP Block (measurement at pin12)

Parameter

Symbol Test Condition

MIN TYP MAX Unit

Input Low Voltage

V_EINL

Input V_EINat pin11, short between pin11and 0

pin12

0

V

Input High Voltage

Reference Voltage

Limit level

V_EINHinput V_EINat pin11, short between pin11

and pin12

V_REF

4.5

5.0

5.5

2.75

5.5

No signal at pin11, short between pin11 and 2.25 2.5

pin12

Input 6V at pin11, short between pin11 and 4.5

pin12

V_LIM

5.0

PWM OSC Block (measurement at pin13)

Parameter

Low level

Symbol Test Condition

V_LInput 5V at pin11

MIN TYP MAX Unit

0.8 1.0 1.2

V

PWM OUT Block(measurement at pin14)

Parameter

Symbol Test Condition

MIN TYP MAX Unit

PWM Duty1

PWM Duty2

PWM Duty3

PWM Duty4

PWM Duty5

PWM Duty1

PWM Duty2

PWM Duty3

PWM Duty4

PWM Duty1

PWM Duty2

PWM Duty3

P_D1

P_D2

P_D1

P_D4

P_D5

P_D1

P_D2

P_D3

P_D4

P_D1

P_D2

P_D3

f_H=30kHz, V₁₂=1V

f_H=30kHz, V₁₂=2V

f_H=30kHz, V₁₂=3V

f_H=30kHz, V₁₂=4V

f_H=30kHz, V₁₂=5V

f_H=90kHz, V₁₂=1V

f_H=90kHz, V₁₂=2V

f_H=90kHz, V₁₂=3V

f_H=90kHz, V₁₂=4V

f_H=150kHz, V₁₂=1V

f_H=150kHz, V₁₂=2V

f_H=150kHz, V₁₂=3V

94

88

81

73

65

93

74

53

30

91

60

25

99

93

86

78

70

98

79

58

35

96

65

30

100

98

91

83

75

100

84

63

40

100

70

%

35

<X-RAY Det. Units>

X-RAY Det. Block (measurement at pin19)

Parameter

Threshold Voltage

Symbol Test Condition

V_XRAY

MIN TYP MAX Unit

4.8 5.0 5.2

V

Weltrend Semiconductor, Inc.

Page 41

WT9051

Data Sheet REV1.0

Notice:

1.The period is the time, which excluded retrace width of V-SAW from the vertical period.

2.The Vertical C Correction is off mode.

3.The Vertical S Correction is off mode.

4.The Trapezoid Correction is off mode.

5.The Side Pin Correction is off mode.

6.The Side Pin Corner Top/Bottom Correction is off mode.

7.The Side Pin Corner Top Correction is center.

8.The Side Pin Corner Bottom Correction is center.

9.The Parallelogram Correction is off mode.

10.The Side Pin Balance Correction is off mode.

11.The Side Pin Corner Balance Top/Bottom Correction is off mode.

12.The Side Pin Corner Balance Top Correction is center.

13.The Side Pin Corner Balance Bottom Correction is center.

14.The precision of the D/A converter is as follows.

8bits DAC ： --1LSB ～ +2LSB

7bits DAC ： --1LSB ～ +1.5LSB

ORDERING INFORMATION

Part Number

WT9051

Package

30-pin plastic shrink DIP (400 mil)

Weltrend Semiconductor, Inc.

Page 42


型号：	WT9051
厂家：	ETC
描述：	SYNC SINGAL PROCESSOR TOR MILTI-SYNC DISPLAY SYNC SINGAL处理器TOR MILTI -SYNC显示器显示器
文件：	总42页 (文件大小：1851K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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