XE3005I033 [ETC]
Low-Power Audio CODEC; 低功耗音频编解码器
| 型号： | XE3005I033 |
| 厂家： | 
ETC |
| 描述： | Low-Power Audio CODEC |
| 文件： | 总32页 (文件大小：458K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Data Sheet
XE3005/XE3006
VSSD VSSA VSSA VDD VREF
VREG11
VREG16
Power supply
management
Microphone
Bias
RESET
XE3006
VDDPA
AOUTP
PWM
DAC
Power
AIN
Σ∆
modulator
Decimator
Amp.
amplifier
AOUTN
VSSPA
Sandman
Functions
Serial Audio
Interface
Clock
mgt
SPI
MISO SS SCK MOSI SMAD SMDA BCLK SDI SDO FSYNC MCLK
XE3005 / XE3006
Low-Power Audio CODEC
Features
General Description
•
•
•
Ultra low-power consumption, below 2 mW
Low-voltage operation down to 1.8 V
Sandman™ function to reduce system
power consumption (XE3006)
Single supply voltage
The XE3005 is an ultra low-power CODEC (Analog
to Digital and Digital to Analog Converter) for voice
and audio applications. It includes microphone
supply, preamplifier, 16-bit ADC, 16-bit DAC, serial
audio interface, power management and clock
management for the ADC and the DAC. The
sampling frequency of the ADC and of the DAC
can be adjusted from 4 kHz to 48 kHz.
•
•
•
•
Adjustable sampling frequency: 4 – 48 kHz
Digital format: 16 bit 2s complement
Requires a minimum number of external
components
•
•
Easy interfacing to various DSPs
Direct connection to microphone and
speaker
The XE3006 also includes the Sandman™
function, which signals whether a relevant voice or
audio signal is present for the ADC or DAC.
•
Various programming options
Quick Reference Data
Applications
•
•
•
•
•
supply voltage
1.8 – 3.6 V
0.4 mA
current (@20 kHz sampling)
sampling frequency
4 – 48 kHz
78 dB
•
•
•
•
•
•
Wireless Headsets
Typical dynamic range ADC
Typical dynamic range DAC
Bluetooth™ headset
78 dB
Hands-free telephony
Digital hearing instruments
Consumer and multimedia applications
All battery-operated portable audio
devices
Ordering Information
Part
Package
Ext. part no.
Temperature
range
-20 to 70° C
-20 to 70° C
XE3005
XE3006
TSSOP 20 pins
TSSOP 24 pins
XE3005I033
XE3006I019
Cool Solutions for Wireless Connectivity
XEMICS SA • e-mail: info@xemics.com • web: www.xemics.com
Data Sheet
XE3005/XE3006
Table of contents
1
Device Description................................................................................................................................... 3
1.1 Terminal Descriptions XE3005/6................................................................................................................ 3
Functional Description ............................................................................................................................ 4
2
2.1 Device Functions........................................................................................................................................ 4
2.2 Power-Down Functions............................................................................................................................ 11
3
Serial Communications ......................................................................................................................... 12
3.1 Serial Audio Interface............................................................................................................................... 12
3.2 Register Programming ............................................................................................................................. 13
3.3 Serial Peripheral Interface - SPI............................................................................................................... 14
4
Sandman™ Function (XE3006)............................................................................................................. 16
5
Specifications......................................................................................................................................... 18
5.1 Absolute Maximum Ratings ..................................................................................................................... 18
5.2 Recommended Operating Conditions...................................................................................................... 18
5.3 Electrical Characteristics.......................................................................................................................... 19
6
Application Information......................................................................................................................... 26
6.1 Application Schematics – XE3006 ........................................................................................................... 26
Register Description .............................................................................................................................. 27
7
7.1 Register Functional Summary.................................................................................................................. 27
7.2 Register Definitions .................................................................................................................................. 28
8
Mechanical Information......................................................................................................................... 31
8.1 XE3005 package size (TSSOP20)........................................................................................................... 31
8.2 XE3006 Package size (TSSOP24) .......................................................................................................... 32
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Data Sheet
XE3005/XE3006
1 Device Description
MOSI
SCK 19
1
2
3
4
5
6
7
8
9
20
MCLK
SS
MOSI
SS
1
2
MCLK
SMAD
SMDA
VDD
24
23
22
21
20
19
18
17
16
15
14
13
SDI
SDO
18
17
16
15
14
13
12
11
VDD
SCK
3
NRESET
VREG16
VREF
VSSA
VSSD
VREG11
MISO
SDI
4
BCLK
5
NRESET
VSSA
FSYNC
AOUTP
VDDPA
AOUTN
VSSPA
SDO
6
BCLK
FSYNC
AOUTP
VDDPA
AOUTN
VSSPA
VREG16
VREF
7
8
VSSA
9
10 AIN
VSSD
10
11
12
VREG11
AIN
Figure 1: Pin layout of the XE3006 and XE3005
The XE3006 is available in a TSSOP24 package. The XE3005 is available in a TSSOP20 package. Detailed
information is found in chapter 8, Mechanical Information.
1.1 Terminal Descriptions XE3005/6
Terminals
Type 1
Description
XE3006
XE3005
Name
MCLK
SMAD
SMDA
VDD
1
2
3
4
1
DI
DO
DO
AI
Master Clock. MCLK derives the internal clocks of ADC and DAC
Sandman output ADC
N/A
N/A
3
Sandman output DAC
Digital power supply
Reset signal generated by the CODEC. If required, the reset signal can
be applied externally to initialize all the internal CODEC registers
Analog ground
5
4
NRESET
ZI/O
6
7
N/A
5
VSSA
VREG16
VREF
VSSA
VSSD
VREG11
AIN
AI
AO
AO
AI
Regulator voltage 1.6 V. Can be used to supply the microphone
Reference voltage
8
6
9
7
Analog ground
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Note: (1)
8
AI
Digital ground
9
AO
AI
ADC Regulated microphone output supply voltage 1.1 V
ADC Analog input signal
10
11
12
13
14
15
16
17
18
N/A
19
2
VSSPA
AOUTN
VDDPA
AOUTP
FSYNC
BCLK
SDO
AI
DAC Power Amplifier Ground
AO
AI
DAC Analog Output negative
DAC Power Amplifier Supply
AO
DI/O
DI/O
ZO
DAC Analog Output positive
Serial audio interface Frame Synchronization
Serial audio interface Bit Clock
Serial audio interface Data Output
SDI
DI PD Serial audio interface Data Input
MISO
SCK
ZO
SPI Master In Slave Out
DI PD SPI Serial Clock
DI PU SPI Slave Select
DI PD SPI Master Out Slave In
AO = Analog Output
SS
20
MOSI
AI = Analog Input
DI = Digital Input
DO = Digital Output
DI/O = Digital In or Out
PU = internal Pull Up
ZO = Hi Impedance or Output
PD = internal Pull Down
ZI/O = Hi impedance In or Out
3
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Data Sheet
XE3005/XE3006
2 Functional Description
A CODEC is typically used for voice and audio applications as an interface between a Digital Signal processor
(DSP) or microcontroller and the analogue interfaces like a microphone and loudspeaker.
DAC
ADC
MIC-Amplifier
CODEC
Power Amplifier
Serial Audio Interface
SPI
DSP / Microcontroller
Digital wireless transmission – Bluetooth™
Voice recognition / speech synthesis
Figure 2: typical usage of CODEC
This chapter provides a brief description of the CODEC features relating to the CODEC configuration. The
configuration of the CODEC is defined by programming registers through a serial interface. A detailed description
of the registers defining details of the CODEC setup can be found in chapter 3 and 7. Digital voice and audio
samples are passed through the Serial Audio Interface.
2.1 Device Functions
2.1.1 ADC Signal Channel
The ADC channel is a chain of programmable amplifier, band-pass filter, sigma-delta modulator and a decimation
filter. The amplifier gain is programmable to 5x (default) and 20x. The band-pass filter has cut-off frequencies
proportional to the sampling rate. The sigma-delta modulator operates at a frequency of 64 times the sampling
rate. The analog modulator is followed by a digital decimation filter. The digital output data (16 bits, 2’s
complement format) is made available through the Serial Audio Interface. The format of the Serial Audio interface
can be selected through register J.
With the default register settings the ADC can run at a sampling frequency up to 20 kHz. When used with a
sampling frequency higher than 20 kHz, then register C has to be changed.
The whole ADC chain can be powered-down through register I.
4
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Data Sheet
XE3005/XE3006
2.1.2 MIC Input
The programmable pre-amplifier and the microphone bias sources VREG11 or VREG16 are optimized to operate
with electret microphones. VREG11 provides a 1.1 V reference voltage. The VREG11 can deliver up to 50 µA.
VREG11 is enabled through control register E. VREG16 is a regulated voltage of typically 1.6V and can deliver
up to 1 mA.VREG16 is always enabled.
Vcc
4
5
VDD
0.1µF
NRESET
VSSA
6
7
VREG16
VREF
8
VSSA
9
VSSD
10
11
1kΩ
VREG11
AIN
12
50 pF (gain is 5)
820kΩ
200 pF (gain is 20)
1µF
1µF
GND
Figure 3: typical microphone interface (1.1 V / 50 uA bias through VREG11)
Vcc
4
5
VDD
0.1µF
NRESET
VSSA
6
1kΩ*
7
VREG16
VREF
8
9
VSSA
VSSD
10
11 VREG11
AIN
12
50 pF (gain is 5)
200 pF (gain is 20)
820kΩ
1µF
1µF
*
depends on microphone type
GND
Figure 4: typical microphone interface (1.6 V / 1 mA bias through VREG16)
5
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Data Sheet
XE3005/XE3006
2.1.3 DAC Signal Channel
The DAC is based on a multi bit sigma-delta modulator, which operates at a frequency of 8 times the sampling
rate. The outputs of the modulator are 2’s complement words of 6 bit. A pulse-width modulator (PWM) converts
the 6 bit words into 2 single bit streams at 256 times the sampling frequency. Finally the 2 bit streams are
supplied to the power amplifier. The Power Amplifier is a Class D amplifier, which offers higher efficiency than the
traditional Class AB topologies. It uses a three-state unbalanced PWM. This means that both channels of the PA
(AOUTP and AOUTN) will not switch at the same time, therefore the outputs are not purely differential (see figure
5 and 6)
XE3005/6
VDDPA
P
P
s
N
AOUTP
AOUTN
P
From Serial Audio
Interface
Interpolator
&
Pulse Width
Modulator
Power
N
Amplifier
Modulator
dac_in(15:0)
@ Fsync
pwm_in(5:0)
@ 8xFsync
bit streams
@ 256xFsync
VSSPA
s = 0
s = 1
Figure 5: DAC block diagram
Figure 6 shows the relation of input and output samples of the PWM (The timing diagram is not to scale in the
time-axis).
pwm_in(5:0) = 1
pwm_in(5:0) = -1
pwm_in(5:0) = 0
pwm_in(5:0) = 2
1
0
P
1
0
N
1/(256 x Fsync)
1/(8 x Fsync)
VDDPA
VSSPA
OUTP-OUTN
-VDDPA
1/(256 x Fsync)
2/(256 x Fsync)
Figure 6: examples PWM in and out (not to scale)
The DAC receives 16-bit wide 2’s complement format through the Serial Audio Interface. The protocol can be
selected through register J. The complete DAC and PA amplifier chain can be powered-down through register I.
6
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Data Sheet
XE3005/XE3006
2.1.4 Digital Loop Back
In digital loop back mode, the ADC output is routed directly to the DAC input. This allows in-circuit system level
tests. The digital loop back mode can be selected through register J.
2.1.5 Operating Frequency
A master clock (MCLK) has to be applied to the XE3005/3006. The clock frequency of the signal applied to the
MCLK pin may vary between 1.024 MHz minimum and 33.9 MHz maximum. The maximum internal clock signal
frequency (MCLK/div_factor) should not exceed 12.288 MHz.
The div_factor can be set by the user in register I to 1,2 or 4. The default value for div_factor is ‘1’.
2.1.6 Serial Audio Interface
The Serial Audio Interface is a 4-wire interface for bi-directional communication of audio data. It operates on the
bit serial clock BCLK and the frame synchronization signal FSYNC. The sampling frequency of the CODEC
corresponds to the rate at which the Audio Serial Interface will put out succeeding frames. One frame always
corresponds to one sample. One frame always contains 2 channels.
Synchronizing the Serial Audio Interface to the MCLK is recommended. FSYNC and MCLK must have a fixed
ratio as defined by the following relation:
FSYNC = Sampling frequency = frame rate = MCLK/(256 x div_factor).
The pin BCLK defines the time when the data must be presented to the serial audio interface and shifted into (pin
SDI) or out of (pin SDO) the CODEC. The number of BCLK periods in one FSYNC period is 32. The user can
select to use the first 16 clock cycles (channel 1) or the second 16 clock cycles (channel 2) of BLCK to shift in or
out the data samples.
The table below shows some examples of the relationships between MCLK, BCLK and FSYNC
MCLK
2048 kHz
8192 kHz
5120 kHz
22579.2 kHz
Div_factor
BCLK
256 kHz
256 kHz
640 kHz
1411.2 kHz
FSYNC
8 kHz
1
4
1
2
8 kHz
20 kHz
44.1 kHz
The table below shows the possible functional configurations of the serial audio interface
CODEC
master
slave
supported protocol
LFS (long frame sync)
LFS (long frame sync), SFS (short frame sync)
By default the Serial Audio Interface operates in slave, SFS mode. In slave mode the user needs to generate the
signals BLCK, FSYNC and supply to the CODEC.
In master mode the CODEC generates the BLCK and FSYNC signals. In that case the BLCK operates at 32
times the frequency of FSYNC. The CODEC master mode can be used with the LFS protocol only.
The register J is used for the different setups of the serial audio interface.
7
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Data Sheet
XE3005/XE3006
2.1.7 Serial Peripheral Interface - SPI
The SPI interface is used to control register values. It is a serial communications interface that is independent of
the rest of the CODEC. It allows the device to communicate synchronously with a microprocessor or DSP. The
CODEC interface only implements a slave controller.
A detailed description can be found in chapter 3.3.
2.1.8
Sandman™ ADC Function
The Sandman™ function monitors the signals, which are processed in the ADC signal channel and the DAC
signal channel. The logic output signal SMAD indicates whether the ADC signal channel has processed an audio
signal or only noise, and for how long. The reference signal amplitude can be selected through register O, the
time window parameters are the off time and on time (registers L, M and N).
FSYNC
BCLK
SDO
Serial Audio
Interface
AIN
Σ∆
modulator
Decimator
Amp.
Sandman
Interface
SMAD
Figure 7: Implementation of the Sandman function for the ADC (SMAD)
The logic output SMAD can be used to power-down or reduce clock speed in other devices in the application,
such as a microcontroller, DSP or wireless link. Also, SMAD can be used as phone pick-up indicator. The
Sandman™ function is illustrated in Figure 9 and is valid for both SMAD (related to the ADC signal) and SMDA
(related to the DAC signal).
Initially, SMAD is inactive (low), which means that “noise” is processed by the ADC, i.e. no audio signal amplitude
above the Reference. The Sandman™ Interface compares every output sample of the ADC signal channel to the
Reference value. If the signal is lower than the Reference value, SMAD remains inactive (low).
As soon as the signal passes the reference (time = 1), the on-time counter is started. (for the moment defined by
time=’x’ see Figure 9). However, as the signal returns below the reference (time = 2) before the on-time counter
has reached the on time, the on-time counter is reset and the SMAD signal remains inactive (low).
The next time the signal gets higher than the Reference (time = 3), the on-time counter is started again and when
it reaches the on time, the SMAD signal becomes active (high), indicating that an audio signal is present (time =
4). As long as the signal remains above the Reference, nothing happens and the SMAD signal remains active
(high). When the signal falls below the Reference (time = 5), the off-time counter is started, but as it does not
reach the off time before the signal passes again the Reference (time = 6), SMAD remains active (high). Also
during the period from time = 7 to time = 8, the off time counter does not reach the off time.
When the signal falls below the Reference (time = 9) and remains below the Reference until the off-time counter
has reached the off-time, the SMAD signal is changed into the inactive (low) state (time = 10).
8
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Data Sheet
XE3005/XE3006
2.1.9
Sandman™ DAC Function
The Sandman™ function monitors the signals, which are processed in the ADC signal, channel and the DAC
signal channel. The logic output signal SMDA indicates whether the DAC signal channel processes an audio
signal or only noise, and this for certain duration. The reference signal amplitude can be selected through register
P, the time window parameters are the off time and on time (registers L, M and N).
Reg I, bit 4
Sandman
SMDA
Interface
VDDPA
FSYNC
BCLK
SDI
AOUTP
Serial Audio
Interface
PWM
DAC
Power
amplifier
AOUTN
VSSPA
Figure 8: Implementation of the Sandman function for the DAC (SMDA)
The logic output SMDA can be employed to power-down other devices in the application, such as an external
audio power amplifier. By setting bit 4 in register I, the on-chip DAC signal channel can be powered-down through
SMDA too. The Sandman™ function is illustrated in Figure 9 and is valid for both SMAD (related to the ADC
signal) and SMDA (related to the DAC signal).
AIN/SDO
(AOUT/SDI)
+ reference
- reference
On-time counter
Time step = 1/fs = 1/FSYNC
Off-time counter
on-time
off-time
SMAD
(SMDA)
1
2
3
4
5
6
7
8
9
10 time
Figure 9: Illustration of the Sandman™ function.
The above illustration is valid for either the SMAD output as a result of AIN/SDO or for the SMDA output as a
function of AOUT/SDI.
9
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Data Sheet
XE3005/XE3006
2.1.10 Start-up and Initialization
The CODEC generates its own power on reset signal after a power supply is connected to the VDD pin. The
reset signal is made available for the user at the pin NRESET. The rising edge of the NRESET indicates that the
startup sequence of the CODEC has finished. In most applications the NRESET pin can be left open.
The NRESET signal generated by the CODEC is used to initialize the various blocks in the device and
guarantees a correct start-up of the circuit. The start-up sequence that is automatically carried out upon power-up
of the device is listed below and illustrated in Figure 10.
1) NRESET is low (0V) when the device is not powered and remains low for a short time when VDD (upper
curve in Figure 10) is applied. The low state sustains while VDD, VREG16, VREF are stabilizing.
2) As soon as the MCLK signal is present, a counter is activated that counts 221 periods of the MCLK. After this
moment the NRESET is in the high state (VDD).
VDD = 1.8..3.3V
VREG16 = 1.6V
VREF = 1.2V
time
. . .
MCLK
977 ms (MCLK=2.048KHz)
main reset
NRESET
Figure 10: Startup sequence and NRESET signal after power-on.
The user can use the NRESET pin in 3 different ways and combinations:
1) Leave the NRESET pin not connected. In this case the CODEC will startup as described in figure 10.
2) Use the NRESET pin as an output to indicate, to e.g. a microcontroller, that the CODEC finished its
power up sequence and that the CODEC is ready to operate.
3) Use the NRESET pin to force a re-initialisation of the registers to their default values. In this case the
user has to force the NRESET to 0V for at least 32 periods of the MCLK. The circuit which forces the
NRESET to 0V should be able to sink at least 50 uA.
10
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Data Sheet
XE3005/XE3006
Figure 11 shows the block diagram of the CODEC reset.
reset to analog and
digital circuitry of codec
delay
Power
On
NRESET
counter
Reset
low drive
buffer
MCLK
XE3005/6
Figure 11: Codec reset circuitry
2.2 Power-Down Functions
2.2.1 Software Power-Down
Register I allows for the selective power down of the ADC signal channel or the DAC signal channel through SPI
control. The wake-up time, after powering down the device is typically 200µs. The maximum standby current is
96µA, depending highly upon the Master clock (MCLK), see 5.3.5.2 Low Power Modes.
2.2.2 Hardware Power-Down
The device has no power-down pin. However, by holding down (0 V) the NRESET pin (resetting the device) as
well as the pins MCLK, BCLK and FSYNC, the power consumption will reach the standby current of typically
16µA. Use the standard procedure for power up (see start-up and initialization procedure) after a hardware power
down and apply your registers setup procedure.
11
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Data Sheet
XE3005/XE3006
3 Serial Communications
3.1 Serial Audio Interface
The Serial Audio Interface is a 4-wire interface for bi-directional communication of audio data. The 4 terminals are
listed below:
•
•
BCLK:
Bit serial clock, one clock cycle corresponds to one data bit transmitted or received.
Frame Synchronization. This signal indicates the start of a data word. The frequency of
the FSYNC corresponds to the sample frequency of the CODEC.
FSYNC:
•
•
SDI:
Serial Data In, data received from external device and sent to DAC.
SDO:
Serial Data Out, data received from ADC and sent to external device.
The same clock (BCLK) and synchronization (FSYNC) signals are used for both sending and receiving. The
synchronization signal FSYNC must have a fixed ratio with the master clock signal MCLK.
The Serial Audio Interface supports two formats that are commonly used for audio/voice CODECs and that are
referred to as SFS (Short Frame Synchronization) and LFS (Long Frame Synchronization). Data can be
transmitted and received in 2 channels. Which channel is selected depends on the programmed values in the
registers. The two interface protocols are shown below.
channel 2, no data
channel 1, sample n+1
channel 1, sample n
FSYNC
BCLK
SDI
-
-
-
-
-
-
n+115
n15 n14
n0
n+115
n15 n14
n0
SDO
msb
msb
lsb
Figure 12: Audio interface timing LFS mode, channel 1
channel 1, sample n+1
channel 1, sample n
channel 2, sample n
FSYNC
BCLK
SDI
-
n+115
n15 n14
n0
-
-
-
-
n+115
-
n15 n14
n0
SDO
msb
msb
lsb
Figure 13: Audio interface timing in SFS mode, channel 1
SDI Data should be changed on the rising edge of BCLK. The SDI data will be read by the CODEC on the falling
edge of BLCK. SDO data will change on the rising edge of the BCLK. The SDO data should be read on the falling
edge of the BLCK. Each rising edge of the FSYNC indicates the start of a new sample.
12
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Data Sheet
XE3005/XE3006
3.1.1 LFS optimization
For transmitting and receiving 32 clock cycles in one frame are always required (figure 12 and 13). This is even
the case when only 16 bits have to be sent or received. In most cases this can be handled easily with a DSP and
microcontroller.
If the user wants to send a minimum of BLCK cycles, it is possible to shorten channel 1 (channel 2 can not be
shortened).
In the LFS mode the possibility exists to shorten the number of BLCK cycles to 17 instead of 32. In this case the
data is transmitted and received in channel 2. Channel 1 is shortened to one BLCK cycle only.
The figure 14 shows this special LFS mode.
channel 1, no data
channel 2, sample n+1
channel 1, no data
channel 2, sample n
FSYNC
BCLK
SDI
n15 n14
n0
-
-
n15 n14
-
-
n15 n14
n15 n14
n0
SDO
lsb
msb
msb
Figure 14: Audio interface timing in LFS mode,17 BLCK cycles, channel 2
3.2 Register Programming
The control registers define the configuration of the CODEC and define the various modes of operation. During
power-up, all registers will be configured with default values. The control register set consists of 16 registers. A
detailed description is provided chapter 7.
The control registers can be changed in the two following ways:
1. Logic values at SPI pins during power-up
There are 3 bits inside the registers which are configured depending on the logic values of the pins SS, SCK and
MOSI during the power up startup sequence as described in section 2.1.10
Value at power up
SS = 1
Influenced bits of registers
Register I(0)=0
comments
MCLKDIV division by 1
MCLKDIV division by 2
SFS protocol
SS = 0
Register I(0)=1
SCK = 0
Register J(0)=1
SCK = 1
Register J(0)=0
LFS protocol
MOSI = 0
MOSI = 1
Register E(2) = 0
Register E(2) = 1
preamplifier gain x5
preamplifier gain x20
Using the SPI pins at startup the user is able to configure the CODEC in the corresponding setups without
reprogramming through the SPI interface and protocol. In best case the SPI interface can then be completely
omitted and the 3 SPI pins can be fixed to ‘0’ or ‘1’.
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Data Sheet
XE3005/XE3006
2. Programming through SPI interface after power-up
Once the device has been powered up, the configuration registers can be modified at all times (also when the
device is active) through the SPI interface.
The following section describes the SPI protocol which is required to change the control registers from their
default values.
3.3 Serial Peripheral Interface - SPI
The serial peripheral interface (SPI) allows the device to communicate synchronously with other devices such as
a microprocessor or a DSP. The CODEC interface only implements a slave controller. This section describes the
communication from master (e.g. DSP) to slave (CODEC pin MOSI) and from slave (CODEC pin MISO) to a
master (e.g. DSP).
Four lines are used to transmit data between the slave and master:
-
-
-
-
MOSI (Master Out, Slave In) data from master to slave, synchronous with the SPI clock (SCK).
MISO (Master In, Slave Out) data from slave to master, synchronous with the SPI clock (SCK).
SCK (Serial Clock) synchronizes the data bits of MOSI and MISO.
SS (Slave Select) Slave devices are selected by activating SS.
3.3.1 Protocol
During SPI communication, data is simultaneously transmitted and received.
trecovery
1/Fsck
tdisable
SS
SCK
MOSI
MISO
14
14
…
…
…
…
15
15
1
1
0
0
Figure 15: SPI signal timing
The master puts data on the MOSI line on the falling edge of SCK; the slave reads the data on the rising edge of
SCK. The slave puts data on the MISO line on the falling edge of SCK; the master reads the data on the rising
edge of SCK. Transmission in either direction is by 2 bytes with MSB first.
The SS pin should be kept low during the whole transfer of data.
There are three timing constraints:
-
-
-
Recovery time (t recovery) between the falling edge of SS and the falling edge of SCK.
Disable time (t disable) between the last rising edge of SCK and the rising edge of SS.
SCK frequency (FSCK
)
Delay
t recover
t disable
F SCK
Min
125
Max
Unit
ns
Comments
-
2 x Tmaster
-
ns
Tmaster = clock period of the master clock MCLK
Fmaster = frequency of the master clock MCLK
0.5 x Fmaster
Hz
14
D0212-116
Data Sheet
XE3005/XE3006
3.3.2 SPI Interface Modes
There are two SPI modes: read and write.
3.3.2.1 Read Mode
Read communication always takes place in pairs of bytes. A read request of 2 bytes is sent on the MOSI line.
The content of the addressed register, one byte, is dumped on the MISO line during the transmission of the
second byte on the MOSI. The formats of one byte are the following:
bit
7
6
5
4
3
2
1
0
mosi
1
1
0
msb
A (4:0)
lsb
bit
7
6
5
4
3
2
1
0
miso
msb
D(7:0)
lsb
ss
sck
mosi
0
1
1
0
A4 A3 A2 A1 A0
1
1
request (read <address A(4:0)>)
miso
msb
lsb
read data D(7:0) of address A(4:0)
Figure 16: SPI signal timing in read mode
3.3.2.2 Write Mode
Write communication always takes place in pairs of bytes. The format of the 2 bytes is:
Bit
7
6
5
4
3
3
2
1
1
0
mosi
1
0
0
msb
A(4:0)
lsb
Bit
7
6
5
4
2
0
mosi
msb
D(7:0)
lsb
ss
sck
lsb
msb
mosi
A4
A3 A2
A0
1
0
0
A1
write data D(7:0) to address A(4:0)
Figure 17: SPI signal timing in write mode
request (write to address A(4:0))
15
D0212-116
Data Sheet
XE3005/XE3006
4 Sandman™ Function (XE3006)
The Sandman™ function analyzes the audio signals in the ADC and DAC. Its output signals indicate whether an
audio signal is present in the ADC or DAC or if the processed signal is just noise. The threshold or reference
value between noise and audio signal as well as the minimum duration of an audio signal is user-programmable
through the SPI interface. If the XE3006 CODEC is used in a system that includes a microcontroller, a DSP or an
RF link, the outputs of the Sandman™ Interface can be used to bring these devices into standby or sleep mode
whenever no audio signal is being processed. In this way, the Sandman™ function contributes to significant
additional power savings on the system level outside the XE3006 chip.
The Sandman™ Interface consists of 2 digital outputs:
•
•
The SMAD detects whether the ADC processes an audio signal. The calculation is made with the digital data
leaving the ADC.
The SMDA detects whether an audio signal is processed by the DAC. The calculation is made with the
digital data entering through the Audio Interface.
The Sandman™ Interface is implemented for the ADC and for the DAC in an identical way. It works with a set of
4 user-defined parameters: off time, on-time, ADC-reference and DAC-reference. The on time and the off time
are the same for ADC and DAC. However, the reference values for the ADC and the DAC are adjusted
separately, as indicated in the table below.
Input parameters
Off-time1(7:0)
Register
Sandman ADC
Sandman DAC
L
M
N
O
P
X
X
X
X
-
X
X
X
-
Off-time2(15:8)
On-time(7:0)
ADC_reference(7:0)
DAC_reference(7:0)
X
The Sandman™ Interface (for the ADC as well as for the DAC) is configured with three parameters:
•
•
•
Reference (7:0): Absolute value under which the signal is considered noise and above which the signal is
considered to be an audio signal. The Sandman™ function is disabled (SMAD or SMDA at logic 1) if this
parameter is zero. The ADC and the DAC have separate Reference values.
Off-time (15:0): Time until power down. The number of sequential samples that have to be lower than the
Reference for the power down signal to become active. The Sandman™ function is disabled (SMAD or
SMDA at logic 1) if this parameter is zero. The ADC and DAC have one common Off-time value.
On-time (7:0): Time until wakeup. The number of sequential samples that have to be higher than the
Reference for the power down signal to become inactive. The Sandman™ function is disabled (SMAD or
SMDA at logic 1) if this parameter is zero. The ADC and DAC have one common On-time value.
All these parameters are set in the registers L, M, N, O and P.
Reference(7:0)
0
On-time(7:0)
don’t care
0
Off-time(15:0) Sandman (SMAD or SMDA) Comments
don’t care
don’t care
0
logic 1 (disable function)
logic 1 (disable function)
logic 1 (disable function)
logic 1 (signal higher than ref)
Sandman disable
Sandman disable
Sandman disable
all registers ≠ zero
time for FSYNC =
20kHz
don’t care
don’t care
1.-.255
don’t care
1.-.255
1 - 65535
corresponds to
128.-.32640
corresponds to corresponds to logic 0 (signal lower than ref)
50 µs – 12 ms 50 µs - 3.2 sec
16
D0212-116
Data Sheet
XE3005/XE3006
The reference (7:0) value is related to the absolute value of the 16 bits input signal. The following format is used
for the comparison:
•
•
16 bit inputs data (2’s-complement) : 0111’1111’1111’1111 = 0x7FFF
8 bit reference (unsigned) : 0111’1111’1000’0000 = 0xFF00/2
max positive value
reference max
So the reference is compared to the 8 most significant bits of the absolute value of the input signal:
reference(7:0)
Absolute reference
AIN (mV) if gain = 4
AIN (mV) if gain = 20
0
1
2
0
0.00
1.10
2.20
0.00
0.27
0.55
128
256
M
M
M
M
70
255
280
255 × 128 = 32640
The values in this table are amplitude values, RMS values can be derived by dividing the numbers by √2.
The working mechanism of the Sandman™ function is the following:
The incoming data is compared to the reference after each time step (1/FSYNC = 50µs if FSYNC = 20kHz).
•
During the On-time phase
If the input data is higher than the reference, a counter will be incremented otherwise the counter is reset.
When the counter reaches the On-time value, then the SMAD or SMDA signal is activated (high level).
•
During the Off-time phase
If the input data is lower than the reference, a counter will be incremented otherwise the counter is reset.
When the counter reaches the Off-time value, then the SMAD or SMDA signal is deactivated (low level).
In a first approximation, the following points are recommended:
•
On-time at least 1ms. If the On-time is shorter than 1 ms, the Sandman™ function becomes sensitive to
spikes in the audio input signal AIN.
•
Off-time at least 10ms, the Off-time should be longer than 1/fmin = 10ms, (code = 200). fmin is the minimum
audio frequency = 100Hz if FSYNC = 20kHz. The value of fmin scales proportionally with the sampling
frequency FSYNC. A high-pass filter in the ADC filters out signals below 100Hz.
•
Reference should be adjusted just above the noise level.
The CODEC bandwidth is around 100 Hz to 10 kHz at the nominal system frequency settings (MCLK = 5 MHz,
CKDIV = 1, FSYNC = 20 kHz).
In digital loop back mode, the data entering into the Audio Interface is not transferred to the DAC. However, the
Sandman™ function (if activated) continues to output the SMDA signal based on the data entered into the Audio
Interface (input terminal SDI).
17
D0212-116
Data Sheet
XE3005/XE3006
5 Specifications
5.1 Absolute Maximum Ratings
Stresses above those listed in the following table may cause permanent failure. Exposure to absolute ratings for
extended periods may affect device reliability.
The values are in accordance with the Absolute Maximum Rating System (IEC 134).
All voltages are referenced to ground (VSSA and VSSD).
Analog and digital grounds are equal (VSSA = VSSD).
Symbol
VDD
Tstg
TA
Parameter
Conditions
Min
-0.3
-65
-20
Max
3.65
150
70
Unit
V
Supply voltage
Storage temperature
°C
°C
V
Operating free-air temperature, TA
Electrostatic discharge protection
Static latchup current
Ves
1)
2)
2)
500
98
Ilus
10
mA
V
Vlud
Dynamic latchup voltage
50
1) Tested according MIL883C Method 3015.6, class JEDEC 1B (Standardized Human Body Model: 100 pF,
1500 Ω, 3 pulses, protection related to substrate).
2) Static and dynamic latchup values are valid at 27 °C.
5.2 Recommended Operating Conditions
All voltages referenced to ground (VSSA and VSSD).
Min
Typ
Max
Unit
Supply voltage, VDD
1.8
3.0
3.6
V
Analog signal peak-to-peak input voltage, AIN (gain = 20x)
Analog signal peak-to-peak input voltage, AIN (gain = 5x)
Differential output load resistance
65
mV
mV
270
16
32
20
Ohm
Master clock frequency
1.024
33
48
70
MHz
kHz
°C
ADC or DAC conversion rate
Operating free-air temperature, TA
-20
18
D0212-116
Data Sheet
XE3005/XE3006
5.3 Electrical Characteristics
The operating conditions in this section are: VDD = 3.0 V, T = 25°C.
5.3.1 Digital Inputs and Outputs, FSYNC = 20 kHz, output not loaded
Parameter
Test
Min
Typ
Max
Unit
Conditions
IO = -360uA
VOH
VOL
IIH
High-level output voltage, DOUT
Low-level output voltage, DOUT
High-level input current, any digital input
Low-level input current, any digital input
Input capacitance
2.4
VDD+0.5
V
IO = 2mA
VIH = 3.3 V
VIL = 0.6 V
VSSD-0.5
0.4
10
10
10
10
V
uA
uA
pF
pF
IIL
Ci
Co
Output capacitance
5.3.2 ADC Dynamic Performance, FSYNC = 20 kHz
Parameter
Test Conditions
Min
72
Typ
Max
Unit
dB
Pre-amp gain = 5x
SNR
THD
Flo
Signal-to-noise ratio
78
0.5
70
10
Vin=250mV (full scale)
Total harmonic distortion
¼ full scale
%
Hz
kHz
us
Low cut-off frequency (-3 dB), See Note 1 FSYNC = 20 kHz
High cut-off frequency (-3 dB), See Note 2 FSYNC = 20 kHz
60
80
Fhi
GD
Group delay
FSYNC = 20 kHz
150
Note 1) Flo is proportional to FSYNC
Note 2) Fhi equals FSYNC/2
5.3.3 ADC Channel Characteristics, FSYNC = 20 kHz
Parameter
Test Conditions
Pre-amp gain = 5x
Min
Typ
Max
270
Unit
Vipp Peak-to-peak input voltage (single ended)
mV
Pre-amp gain = 20x
65
20
5
A-weighted, 100 Hz-10 kHz
pre-amp gain = 5x
Vneq
Equivalent input noise
Dynamic range
µV rms
A-weighted, 100 Hz-10 kHz
pre-amp gain = 20x
Pre-amp gain = 5x
72
1
78
60
50
dB
dB
Vin=250mV (full scale)
PSRR Power supply rejection ratio, input referred
Up to 1 kHz
Preamp-gain = 5x
Preamp gain = 20x
Cin
Input capacitor
pF
200
Rin
Eg
Input resistance VIN – VSSA
gain error
MOhm
[%]
LSB
LSB
LSB
VDD 1.8-3.3V
VDD 1.8-3.3V
VDD 1.8-3.3V
VDD 1.8-3.3V
+/- 0.1
-60
6.7
offset error
input noise
Integral non linearity
INL
+/- 5
DNL
Differential non linearity
VDD 1.8-3.3V
+/- 0.1
LSB
19
D0212-116
Data Sheet
XE3005/XE3006
5.3.4 DAC Dynamic Performance, load is an LC filter at 10 kHz
FSYNC = 20 kHz, MCLK = 5 MHz, for info on the LC filter see chapter 6, Application Information.
Parameter
Test Conditions
Min
Typ
Max
Unit
SNR
THD
Signal-to-noise ratio
Bandwidth 10 kHz
72
78
dB
Total harmonic distortion
Dynamic range
¼ full scale
0.5
78
%
dB
µs
Bandwidth 10 kHz
FSYNC = 20 kHz
72
GD
Group delay
150
5.3.5 Power Supply
5.3.5.1 Regulated supply characteristics @ T = 25°C
Parameter
Test
Conditions
1µF capacitor
load
Min
Typ
Max
Unit
VREF
reference Voltage
1.2
V
VREG11
I_vreg11
R_vreg11
regulated Voltage 1.1V
available current
1.1
35
1
V
50
µA
output impedance
1.5
kOhm
1µF capacitor
VREG16
regulated Voltage 1.6V
1.5
1.6
V
820kΩ resistor
I_vreg16
available output current
1
mA
dB
dB
dB
VREF PSRR
power supply rejection ratio, input referred
up to 1 kHz
up to 1 kHz
up to 1 kHz
60
60
40
VREG11 PSRR power supply rejection ratio, input referred
VREG16 PSRR power supply rejection ratio, input referred
5.3.5.2 Low power mode
Stand-by mode @ VDD = 3.0V, T = 25°C
Parameter
Test Conditions
Min
Min
Typ
Max
Unit
ADC off, DAC off
Istb1
Istb2
Istb3
Supply current in standby mode
28
48
20
56
96
40
µA
MCLK = 5 MHz,
ADC off, DAC off
Supply current in standby mode
Supply current in standby mode
µA
µA
MCLK = 12.2880 MHz
NRESET mode
MCLK = 0
Stand-by mode @ VDD = 1.8V, T = 25°C
Parameter
Test Conditions
Typ
25
Max
50
Unit
µA
ADC off, DAC off
MCLK = 5 MHz,
ADC off, DAC off
MCLK = 12.2880 MHz
NRESET mode
MCLK = 0
Istb1
Istb2
Istb3
Supply current in standby mode
Supply current in standby mode
Supply current in standby mode
31
62
µA
16
32
µA
20
D0212-116
Data Sheet
XE3005/XE3006
5.3.5.3 Normal operation, output load consumption is not included.
Normal operations @ VDD = 3.0V, FSYNC = 20 kHz, T = 25°C, Register C(7:0) = 0xF0
Parameter
Test Conditions
Min
Typ
350
240
120
Max
700
480
240
Unit
µA
ADC on, DAC on
IDD
Supply current CODEC
Supply current ADC
Supply current DAC
FSYNC = 20 kHz, no load
ADC on, DAC off
IADC
IDAC
µA
FSYNC = 20 kHz, no load
ADC off, DAC on
µA
FSYNC = 20 kHz, no load
Normal operations @ VDD = 3.0V, FSYNC = 48 kHz, T = 25°C, Register C(7:0) = 0xC4
Parameter
Test Conditions
Min
Typ
860
600
280
Max
1720
1200
560
Unit
µA
ADC on, DAC on
IDD
Supply current CODEC
Supply current ADC
Supply current DAC
FSYNC = 48 kHz, no load
ADC on, DAC off
IADC
IDAC
µA
FSYNC = 48 kHz, no load
ADC off, DAC on
µA
FSYNC = 48 kHz, no load
Normal operations @ VDD = 1.8V, FSYNC = 20 kHz, T = 25°C, Register C(7:0) = 0xF0
Parameter
Test Conditions
Min
Typ
250
200
65
Max
500
400
130
Unit
µA
ADC on, DAC on
IDD
Supply current CODEC
Supply current ADC
Supply current DAC
FSYNC = 20 kHz, no load
ADC on, DAC off
IADC
IDAC
µA
FSYNC = 20 kHz, no load
ADC off, DAC on
µA
FSYNC = 20 kHz, no load
Normal operations @ VDD = 1.8V, FSYNC = 48 kHz, T = 25°C, Register C(7:0) = 0xC4
Parameter
Test Conditions
Min
Typ
625
505
140
Max
1250
1010
280
Unit
µA
ADC on, DAC on
IDD
Supply current CODEC
Supply current ADC
Supply current DAC
FSYNC = 48 kHz, no load
ADC on, DAC off
IADC
IDAC
µA
FSYNC = 48 kHz, no load
ADC off, DAC on
µA
FSYNC = 48 kHz, no load
21
D0212-116
Data Sheet
XE3005/XE3006
5.3.6 Timing Requirements of serial audio interface
Ref.
Test
Characteristics
No. *
Min
1024
45
Typ
5.12
Max
Unit
Conditions
1
1
Master Clock Frequency for MCLK = 1/ T
33
55
10
10
MHz
%
MCLK Duty Cycle
Rise Time for All Digital Signals
2
ns
Fall Time for All Digital Signals
3
ns
Hold time BCLK or FSYNC high after MCLK low
Setup time BCLK or FSYNC high to MCLK low
Hold time BCLK or FSYNC low after MCLK low
Setup time BCLK or FSYNC low to MCLK low
Bit Clock Frequency for BCLK = 1 / TBCLK
Setup time data input SDI to BCLK low
Hold time data input SDI after BCLK low
Delay time SDO valid after BCLK high
Setup time data input FSYNC to BCLK low
Hold time data input FSYNC after BCLK low
4
T/4
T/4
T/4
T/4
ns
5
ns
6
CLoad = 10pF
ns
7
ns
MCLK/2
TBCLK/4
8
32xFSYNC
MHz
ns
9
TBCLK/4
TBCLK/4
10
11
12
13
ns
ns
TBCLK/4
TBCLK/4
ns
ns
*see figure 18,19 for LFS and 20, 21 for SFS
22
D0212-116
Data Sheet
XE3005/XE3006
5.3.6.1 Timing diagram of the serial audio interface – LFS mode
1
2
3
MCLK
5
7
7
BCLK
6
6
4
FSYNC
SDI
Figure 18: LFS, timing diagram
MCLK
8
BCLK
FSYNC
SDI
11
9
10
D15 D14 D13 D12 D11 D10 D9
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDO
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 19: LFS, zoom timing diagram
23
D0212-116
Data Sheet
XE3005/XE3006
5.3.6.2 Timing diagram of the serial audio interface – SFS mode
1
2
3
MCLK
6
5
4
7
BCLK
FSYNC
SDI
Figure 20: SFS, timing diagram
MCLK
8
BCLK
12
9
13
11
10
FSYNC
D15 D14 D13 D12 D11 D10 D9
D15 D14 D13 D12 D11 D10 D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SDI
SDO
D8
D7
D6
D5
D4
D3
D2
D1
D0
Figure 21: SFS zoom timing diagram
24
D0212-116
Data Sheet
XE3005/XE3006
5.3.7 Timing Requirements of the Serial Peripheral Interface
Test Conditions
Ref. No. *
Characteristics
Serial Clock Frequency for SCK = 1 / TSCK
MCLK Duty Cycle
Recovery Time
Disable Time
Setup time MISO valid to SCK high
Hold time MISO valid after SCK high
Delay time MOSI valid after SCK low
Min
Typ
Max
Unit
1
MCLK/2 MHz
1
45
55
%
ns
ns
ns
ns
ns
2
125
CLoad = 10pF
3
2T
4
TSCK/4
TSCK/4
TSCK/4
5
6
* see figure 22
SS
2
3
1
4
SCK
5
A4
6
M2
M1 M0
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
MISO
MOSI
D7
D6
D5
D4
D3
D2
D1
D0
Figure 22: Serial Peripheral Interface timing
25
D0212-116
Data Sheet
XE3005/XE3006
6 Application Information
6.1 Application Schematics – XE3006
6.1.1 Typical Application schematic
Sandman output
Master Clock
MOSI
SS
1
MCLK
SMAD
SMDA
VDD
24
23
22
21
20
19
18
17
16
15
14
13
2
Vcc
SPI
SCK
3
4
MISO
SDI
0.1µF
5
NRESET
VSSA
SDO
6
7
Serial Audio Interface
BCLK
FSYNC
AOUTP
VDDPA
AOUTN
VSSPA
VREG16
VREF
8
R
L
VSSA
9
Vcc
VSSD
10
11
12
2µ2F
4µ7F
VREG11
AIN
L
R
L=680µH
R=56Ω
820kΩ
1µF
lowpass filter,
1µF
Bluetooth™ voice application
MCLK = 2.048 MHz,
div_factor =1
GND
Figure 23: Typical Application with 3rd order LC output Filter
6.1.2 External components required for optimal performances
The following minimum set-up of external components is required:
•
•
•
Capacitor for Vref: 1 µF
Resistor for Vref: 820 kΩ
Capacitor for VREG16: 1 µF
The low pass filter between the DAC output and the speaker depends on the CODEC settings and the speaker
type.
26
D0212-116
Data Sheet
XE3005/XE3006
7 Register Description
7.1 Register Functional Summary
The following registers can be programmed by the SPI to configure the operation modes. See also section 3.2
Register Programming.
Name
Description
Register C
ADC current setting. The data in this register has the following
functions:
•
•
Adjust the ADC current for FSYNC > 20kHz
0xF0 for FSYNC<= 20 kHz, 0xC4 for FSYNC > 20 kHz.
Register E
Register I
Analog Input. The data in this register has the following functions:
•
•
Enable/disable microphone bias source of 1.1 V
Gain setting of pre-amplifier.
Function enable and clock division. The data in this register has the
following functions:
•
•
•
Enable/disable Sandman function of DAC
Enable/disable DAC channel (DAC, power amplifier)
Enable/disable ADC channel (pre-amplifier, ADC, decimation
filter)
•
Division of master clock
Register J
Audio Interface Configuration. The data in this register has the
following functions:
•
•
•
•
•
•
Enable/disable digital loopback
Channel select receive
Select master / slave mode
Output impedance
Channel select transmit
Select short / long frame sync
Register L
Register M
Register N
Register O
Register P
Sandman™ function, Off-time, low byte. The data in this register has
the following function:
•
Define Off-time (low byte) of the Sandman™ function
Sandman™ function, Off-time, high byte. The data in this register has
the following function:
•
Define Off-time (high byte) of the Sandman™ function
Sandman™ function, On-time. The data in this register has the
following function:
•
Define On-time of the Sandman™ function
Sandman™ function, reference for ADC. The data in this register has
the following function:
•
Define reference amplitude for ADC for Sandman™ function
Sandman™ function, reference for DAC. The data in this register has
the following function:
•
Define reference amplitude for DAC for Sandman™ function
27
D0212-116
Data Sheet
XE3005/XE3006
7.2 Register Definitions
The complete register setup consists of 24 registers of 8 bits each, as shown in the table below. All registers are
preconfigured with the default values and do not have to be programmed by the user if no changes in the setup
are required.
The registers C, E, I and J can be used to configure the XE3005 and XE3006 differently than the default setup.
The registers L, M, N, O, P are related to the Sandman function available in the XE3006.
Register
Address
(hex)
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
Name
Default value (hex)
A
B
C
D
E
F
G
H
I
Reserved
0x48
0x8F
Reserved
ADC current
0xF0
Reserved
0x00
Analog input
0x08/0x0C
0x82
Reserved
Reserved
0x00
Reserved
0x00
Block on/off and clock division
Audio interface configuration
Reserved
0x00/0x01
0x25/0x24
0x00
J
K
L
Sandman™ function, off-time byte 1
Sandman™ function, off-time byte 2
Sandman™ function, on-time
Sandman™ function, reference for ADC
Sandman™ function, reference for DAC
0x00
M
N
O
P
0x00
0x00
0x00
0x00
Register C (7:0)
address 0x02
7:0
ADC
Default value: Description
0xF0
current
ADC
0xF0
0xF0 for FSYNC<= 20 kHz,
0xC4 for FSYNC > 20 kHz.
current
Register E (7:0)
address 0x04
7
ADC input
Default value
0x08/0x0C
0
Description
VMIC_EN
Generation of the microphone supply at pin VREG11:
1: enables VREG11
0: disables VREG11
6:3
2
reserved
PREAMP_
GAIN
0001
reserved
0 or 1
Gain of preamplifier:
0: 5x (280 mV pp)
1: 20x (70 mV pp)
The default is depending on the logic value of the pin MOSI during
startup (see section 3.2)
MOSI=0, default will be set to 0
MOSI=1, default will be set to 1
reserved
1:0
reserved
00
28
D0212-116
Data Sheet
XE3005/XE3006
Register I (7:0)
block on/off and
clock division
Default value
0x00/0x01
0000
Description
address 0x08
7:4
3
reserved
0: enable
EN_DAC
EN_ADC
0
1: disable DA converter (DAC + PA)
2
0
0: enable
1: disable AD converter (Preamp + ADC +
decimator)
1:0
MCLKDIV
00 or 01
Division factor of the master clock:
00: 1
01: 2
10: reserved
11: 4
The default is depending on the logic value of the pin SS
during startup (see Section 3.2)
SS=0, default will be set to 1
SS=1, default will be set to 0
Register J (7:0)
address 0x09
Audio
interface
Default Description
value
0x25/
0x24
configuration
7
6
LOOPBACK
0
0: disable loopback, normal mode
1: enable loopback => The CODEC connects internally the
ADC output to DAC input
RX_FIRST_
SECOND
0
0: Receive audio data in the first 16-bit channel after the
frame synchronization.
1: Receive audio data in the second 16-bit channel after the
frame synchronization.
5
4
reserved
MASTER
1
0
reserved
1: enable audio interface in master mode (only for LFS)
0: enable audio interface in slave mode (LFS or SFS)
0: SDO is continuously in output mode for both data
channels.
3
SDO_HI_EN
0
1: SDO is in output mode when transmitting a channel with
data (J(2) or J(1)=1).
It is switched automatically into high-impedance state
when a channel with no data is transmitted (J(2) or
J(1)=0).
2
1
0
TX_FIRST
TX_SECOND
PROTOCOL
1
0
1: transmit the audio data in the first 16-bit channel after the
frame synchronization.
0: do no transmit data in the first channel.
1: transmit the audio data in the second 16-bit channel after
the frame synchronization.
0: do no transmit data in the second channel.
1: Short Frame Synchronization mode (slave mode).
0: Long Frame Synchronization mode (mode master or
slave).
0 or 1
The default is depending on the logic value of the pin SCK during startup
(see Section 3.2)
SCK=0, default will be set to 1
SCK=1, default will be set to 0
29
D0212-116
Data Sheet
XE3005/XE3006
Register L (7:0)
address 0x0B
Sandman™ function,
off-time,
Default
Description
value 0x00
least significant byte
SM_OFF_LSB
7:0
00000000 Least significant byte of the off-time of
the Sandman™ function
Register M (7:0)
address 0x0C
Sandman™ function,
off-time,
Default
Description
value 0x00
most significant byte
SM_OFF_MSB
7:0
00000000 Most significant byte of the off-time of
the Sandman™ function
Register N (7:0)
address 0x0D
7:0
Sandman™ function,
on-time
Default
Description
value 0x00
SM_ON
00000000 On-time of the Sandman™ function
Register O (7:0)
address 0x0E
7:0
Sandman™ function,
reference for ADC
SMAD_REF
Default
Description
value 0x00
00000000 Reference amplitude for ADC for
Sandman™ function
Register P (7:0)
address 0x0F
7:0
Sandman™ function,
reference for DAC
SMDA _REF
Default
Description
value 0x00
00000000 Reference amplitude for DAC for
Sandman™ function
30
D0212-116
Data Sheet
XE3005/XE3006
8 Mechanical Information
8.1 XE3005 package size (TSSOP20)
D
E
A
X
c
H
v
M
A
y
E
Z
11
20
Q
A
2
(A )
3
A
A
1
pin 1 index
L
p
L
1
1
0
detail X
w
M
b
p
e
DIMENSIONS (mm are the original dimensions)
A
UNIT
A
A
A
b
c
D
E
e
H
L
L
v
w
y
Q
1
2
3
p
E
p
Z
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
6.6
6.4
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Figure 24: TSSOP20
Plastic thin shrink small outline package; 20 leads; body width 4.4 mm
31
D0212-116
Data Sheet
XE3005/XE3006
8.2 XE3006 Package size (TSSOP24)
D
E
A
X
c
H
v
M
A
y
E
Z
13
24
Q
A
2
(A )
3
A
A
1
pin 1 index
L
p
L
1
1
2
detail X
w
M
b
p
e
DIMENSIONS (mm are the originladimensions)
A
Q
y
UNIT
A
A
A
b
c
D
E
e
H
L
L
v
w
1
2
3
p
E
p
Z
max.
8o
0o
0.15
0.05
0.95
0.80
0.30
0.19
0.2
0.1
7.9
7.7
4.5
4.3
6.6
6.2
0.75
0.50
0.4
0.3
0.5
0.2
mm
1.10
0.65
0.25
1.0
0.2
0.13
0.1
Figure 25: TSSOP24
Plastic thin shrink small outline package; 24 leads; body width 4.4 mm
XEMICS, 2002
All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information
presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any
license under patent or other industrial or intellectual property rights.
XEMICS PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT
APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF XEMICS PRODUCTS IN SUCH
APPLICATIONS IS UNDERSTOOD TO BE UNDERTAKEN SOLELY AT THE CUSTOMER’S OWN RISK.
Should a customer purchase or use XEMICS products for any such unauthorized application, the customer shall indemnify and hold XEMICS
and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs damages and attorney fees which could
arise.
32
D0212-116
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