XE88LC01RI000_技术文档

Data Sheet XE88LC01

Data Acquisition Microcontroller

XE88LC01 Sensing Machine

16 + 10 bit Data Acquisition

Ultra Low-Power Microcontroller

General Description

Key product Features

The XE88LC01 is an ultra low-power microcontroller unit

(MCU) associated with a versatile analog-to-digital con-

verter (ADC) including a programmable offset and gain

pre-amplifier (PGA) .

•

Low-power, high resolution ZoomingADC

•

0.5 to 1000 gain with offset cancellation

up to 16 bits ADC

up to 13 input multiplexer

•

Low-voltage low-power controller operation

XE88LC01 is available with on chip Multiple-Time-Pro-

grammable (MTP) Flash program memory and ROM.

•

2 MIPS at 2.4 V to 5.5 V supply voltage

•

300 µA at 1 MIPS, 2.4 V to 5.5 V supply

•

22 kByte (8 kInstruction) MTP, 520 Byte RAM

RC and crystal oscillators

5 reset, 18 interrupt, 8 event sources

100 years MTP Flash retention at 55°C

Applications

•

Internet connected appliances

Portable, battery operated instruments

Piezoresistive bridge sensors

HVAC control

Ordering Information

Motor control

Reference

Memory type Temperature

Package

die

XE88LC01MI000 MTP Flash

XE88LC01MI027 MTP Flash

XE88LC01MI032 MTP Flash

-40°C to 85°C

-40°C to 125°C

LQFP44

PLL-44L

die

XE88LC01RI000

XE88LC01RI027

ROM

LQFP44

Cool Solutions for Wireless Connectivity

XEMICS SA, email: info@xemics.com web: www.xemics.com

Cool Solutions for Wireless Connectivity

XEMICS SA, email: info@xemics.com web: www.xemics.com

Data Sheet XE88LC01

Data Acquisition Microcontroller

1 Detailed Pin Description

42

40

38

36

34

1

2

3

4

5

6

7

8

9

10

packaging date

32

31

30

29

28

27

26

25

24

production

lot identification

device type

22

12

14

16

18

20

Figure 1.1:

Pinout of the XE88LC01 in LQFP44 package

Position

in

TQFP44

Description

Function

name

Second function

name

Type

1

2

PA(5)

PA(6)

PA(7)

PC(0)

PC(1)

PC(2)

PC(3)

PC(4)

PC(5)

PC(6)

PC(7)

Input

Input of Port A

Input

Input of Port A

3

Input

Input of Port A

4

Input/Output

Input-Output of Port C

5

6

7

8

9

10

11

Input-Output-Analog of Port B/

Data output for test and MTP programing/

PWM output

12

PB(0)

testout

Input/Output/Analog

Input-Output-Analog of Port B/

PWM output

13

14

15

PB(1)

PB(2)

PB(3)

Input/Output/Analog

Input-Output-Analog of Port B

Input-Output-Analog of Port B,

Output pin of USRT

SOU

SCL

SIN

Tx

Input-Output-Analog of Port B/

Clock pin of USRT

16

17

18

PB(4)

PB(5)

PB(6)

Input/Output/Analog

Input-Output-Analog of Port B/

Data input or input-output pin of USRT

Input-Output-Analog of Port B/

Emission pin of UART

Input-Output-Analog of Port B/

Reception pin of UART

19

20

21

PB(7)

Rx

Input/Output/Analog

Special

VPP/TEST

AC_R(3)

Vhigh

Test mode/High voltage for MTP programing

Highest potential node for 2nd reference of

ADC

Analog

22

23

24

25

26

AC_R(2)

AC_A(7)

AC_A(6)

AC_A(5)

AC_A(4)

Analog

Lowest potential node for 2nd reference of ADC

ADC input node

Table 1.1:

Pin-out of the XE88LC01 in LQFP44

(see Table “IO pins performances” on page 18 for drive capabilities of the pins)

3

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

Position

Description

Function

name

Second function

name

in

TQFP44

27

Type

AC_A(3)

AC_A(2)

AC_A(1)

AC_A(0)

AC_R(1)

AC_R(0)

VSS

Analog

Power

ADC input node

28

29

ADC input node

30

ADC input node

31

Highest potential node for 1st reference of ADC

Lowest potential node for 1st reference of ADC

Negative power supply, connected to substrate

Positive power supply

32

33

34

Vbat

Power

35

Vreg

Analog

Input

Regulated supply

36

RESET

Vmult

Reset pin (active high)

37

Analog

Pad for optional voltage multiplier capacitor

Connection to Xtal/

CoolRISC clock for test and MTP programing

38

39

OscIn

ck_cr

ptck

Analog/Input

Connection to Xtal/

Peripheral clock for test and MTP programing

OscOut

Input of Port A/

Data input for test and MTP programing/

Counter A input

40

PA(0)

testin

testck

Input

Input of Port A/

Data clock for test and MTP programing/

Counter B input

41

42

PA(1)

PA(2)

Input

Input of Port A/

Counter C input/ Counter capture input

Input of Port A/

Counter D input/ Counter capture input

43

44

PA(3)

PA(4)

Input

Input of Port A

Table 1.1:

Pin-out of the XE88LC01 in LQFP44

(see Table “IO pins performances” on page 18 for drive capabilities of the pins)

4

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

2 Absolute maximum ratings

Stresses beyond these listed in this chapter may cause permanent damage to the device. No

functional operation is implied at or beyond these conditions. Exposure to these conditions for

an extended period may affect the device reliability.

Parameter

VBAT with respect to VSS

Valéue

-0.3V to 6.0V

Input voltage on any input pin

Storage temperature

VSS-0.3V to VBAT+0.3V

-55°C to 125°C

Storage temperature for programmed MTP devices

-40°C to 85°C

Table 2.1:

Absolute maximum ratings

These devices are ESD sensitive. Although these devices feature proprietary ESD protection

structures, permanent damage may occur on devices subjected to high energy electrostatic

discharges. Proper ESD precautions have to be taken to avoid performance degradation or

loss of functionality.

5

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Data Sheet XE88LC01

Data Acquisition Microcontroller

3 Electrical Characteristics

All specification are -40°C to 85°C unless otherwise noted. ROM operates up to 125°C.

Operation conditions

min

2.4

typ

max

5.5

2

Unit

V

Remarks

ROM version

Power supply

MTP version

2.4 V to 5.5 V

any instruction

2.4

V

Operating speed

Instruction cycle

0.032

MHz

ns

500

7

1

CPU running

at 1 MIPS

310

10

uA

CPU running

at 32 kHz

on Xtal,

uA

1

RC off

CPU halt,

timer on Xtal,

RC off

1

uA

1

Current requirement

CPU halt,

timer on Xtal,

RC ready

1.7

CPU halt,

Xtal off

timer on RC

at 100 kHz

1.4

uA

1

CPU halt,

ADC 16 bits

at 4 kHz

190

460

4,6

CPU halt,

ADC 12 bits

at 4 kHz,

PGA gain 100

CPU at 1 MIPS,

ADC 12 bits

at 4 kHz

670

790

uA

3,4,6

Current requirement

CPU at 1 MIPS,

ADC 12 bits at 4 kHz,

PGA gain 10

CPU at 1 MIPS,

ADC 12 bits at 4 kHz,

PGA gain 100

940

CPU at 1 MIPS,

ADC 12 bits at 4 kHz,

PGA gain 1000

1100

Voltage level detection

Prog. voltage

15

10.8

1

uA

V

s

10.3

0.2

10

Erase time

8

MTP Flash

memory

Write/Erase cycles

100

5

10

years

85°C, 2

55°C, 2

Data retention

100

Table 3.1:

Note:

Specifications and current requirement of the XE88LC01

1) Power supply: 2.4 V - 5.5 V, temperature is 27°C.

2) < 10 erase cycles.

3) Output not loaded.

4) Current requirement can be divided by a factor of 2 or 4 by reducing the speed accordingly.

5) More cycles possible during development, with restraint retention

6) Power supply: 3.0V, at 27°C; see chapter Power Consumption on page 30 for variation of current

with voltage and clock speed variation

7) With 2 MHz clock, all instructions are using exactly 1 clock cycle

8) Longer erase time may degrade retention

6

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Data Sheet XE88LC01

Data Acquisition Microcontroller

4 CPU

The XE88LC01 CPU is a low power RISC core. It has 16 internal registers for efficient imple-

mentation of the C compiler. Its instruction set is made of 35 generic instructions, all coded on

22 bits, with 8 addressing modes. All instructions are executed in one clock cycle, including

conditional jumps and 8x8 multiplication.

A complete tool suite for development is available from XEMICS, including programmer, C-

compiler, assembler, simulator, linker, all integrated in a modern and efficient graphical user

interface.

7

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

5 Memory organisation

The CPU uses a Harvard architecture, so that memory is organised in two separated fields:

program memory and data memory. As both memory are separated, the central processing

unit can read/write data at the same time it loads an instruction. Peripherals and system control

registers are mapped on data memory space.

Program memory is fitted onto one page. Data is made of several 256 bytes pages.

0h1FFF / 01hBFF

0h027F

0h0080

RAM

512 Bytes

Program

memory

8k instructions MTP

or

CPU

6k instructions ROM

Peripherals

0h0010

0h0000

CPU

registers

Instruction

pipeline

LP RAM

0h0000

22 bits wide

Memory organization

8 bits wide

Figure 5.1:

5.1 Program memory

The program memory is implemented as Multiple Time Programmable (MTP) Flash memory.

The power consumption of MTP memory is linear with the access frequency (no significant

static current).

Size of the MTP Flash memory is 8192 x 22 bits (= 22 kBytes)

Size of the ROM memory is 6144 x 22 bits (= 17 kBytes)

block

MTP

size

8192 x 22

6144 x 22

address

H0000 - H1FFF

H0000 - H1BFF

ROM

Table 5.1:

Program addresses for MTP or ROM memory

8

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

5.2 Data memory

The data memory is implemented as static Random-Access Memory (RAM). The RAM size is

512 x 8 bits plus 8 low power RAM bytes that require very low current when addressed. Pro-

grams using the low-power RAM instead of RAM will use even less current.

block

LP RAM

RAM

size

8 x 8

address

H0000 - H0007

H0080 - H027F

512 x 8

Table 5.2:

RAM addresses

6

Registers list

Left column include register name and address.

Right columns include bit name, access (r: read, r0: always 0 when read, w: write, c: cleared

by writing any value, c1: cleared by writing 1), and reset status (0 or 1) and signal. Empty bits

are reserved for future use and should not be written, neither should their read value be used

for any purpose as it may change without notice.

6.1 Peripherals mapping

block

LP RAM

System control

Port A

size

8x8

16x8

8x8

4x8

8x8

12x8

8x8

address

Page

H0000-H0007

H0010-H001F

H0020-H0027

H0028-H002F

H0030-H0033

H0034-H0037

H0038-H003B

H003C-H003F

H0040-H0047

H0048-H004F

H0050-H0057

H0058-H005F

H0060-H0067

H0068-H0073

H0074-H007B

Port B

Port C

Reserved

MTP

Event

Interrupts control

reserved

Page 0

UART

Counters

Zooming ADC

Reserved

Other

(VLD)

4x8

H007C-H007F

RAM1

RAM2

RAM3

128x8

256x8

128x8

H0080 - H00FF

H0100 - H01FF

H0200 - H027F

Page 1

Page 2

Table 6.1:

Peripherals addresses

9

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

6.2

Resets

The reset source name is simplified in the following registers description. Name mapping is in

the next table.

name in this

reset source

document

resetsystem

global

resetSynch

resetPOR

resetCold

resetPad

cold

resetPconf

resetSleep

pconf

sleep

Table 6.2:

Reset signal name mapping

6.3

Low power RAM

Low power RAM is a small additionnal RAM area with extremely low power requirement.

Name

7

6

5

4

3

2

1

0

Address

h0000

h0001

h0002

h0003

h0004

h0005

h0006

h0007

rw

Table 6.3:

Low power RAM

10

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Data Sheet XE88LC01

Data Acquisition Microcontroller

6.4

System, oscillators, prescaler and watchdog

Name

7

6

5

4

3

2

1

0

Address

RegSysCtrl

h0010, type 1

RegSysReset

SleepEn

rw, 0 por

Sleep

EnRes-PConf EnBus-Error EnResWD

rw, 0 cold

ResPor

r, 0

rw, 0 cold

ResBus-Error

rc, 0 cold

rw, 0 cold

ResWD

ResPortA

rc, 0 cold

ColdXtal

r, 1 sleep

ResPad-Deb

rc, 0 cold

ColdRC

ResPad

rc, 0 cold

EnableXtal

rw, 0 sleep

w, 0 cold

CpuSel

rc, 0 cold

BiasRC

h0011, type 1

RegSysClock

ExtClk

r, 0 cold

EnExtClk

EnableRC

rw, 1 sleep

rw, 0 sleep

rw, 0 cold

rw, 1 cold

r, 1 sleep

h0012, type 1

Output-

CkXtal

Output-

CkCPU

RegSysMisc

RCOnPA0

DebFast

h0013, type 1

RegSysWD

h0014

rw, 0 sleep

WatchDog(3) WatchDog(2) WatchDog(1) WatchDog(0)

special

ResPre

RegSysPre0

ClearLow-

Prescal (*)

w, 0 cold

h0015

RCFreq-

Range

RCFreq-

Coarse(3)

RCFreq-

Coarse(2)

RCFreq-

Coarse(1)

RCFreq-

Coarse(0)

RegSysRCTrim1

h001B

rw, 0 cold

RCFreq-

Fine(5)

RCFreq-

Fine(4)

RCFreq-

Fine(3)

RCFreq-

Fine(2)

RCFreq-

Fine(1)

RCFreq-

Fine(0)

RegSysRCTrim2

h001C

rw, 1 cold

rw, 0 cold

Table 6.4:

System control registers

6.5

PortA

Name

7

6

5

4

3

2

1

0

Address

RegPAIn

PAIn(7)

r

RegPAIn(6)

r

PAIn(5)

r

PAIn(4)

r

PAIn(3)

r

PAIn(2)

r

PAIn(1)

r

PAIn(0)

r

h0020

RegPADebounce

h0021

RegPAEdge

h0022

RegPAPullup

h0023, type 1

RegPARes0

h0024

RegPARes1

h0025

PADeb(7)

rw, 0 pconf

PAEdge(7)

PADeb(6)

rw, 0 pconf

PAEdge(6)

PADeb(5)

rw, 0 pconf

PAEdge(5)

PADeb(4)

rw, 0 pconf

PAEdge(4)

PADeb(3)

rw, 0 pconf

PAEdge(3)

PADeb(2)

rw, 0 pconf

PAEdge(2)

PADeb(1)

rw, 0 pconf

PAEdge(1)

PADeb(0)

rw, 0 pconf

PAEdge(0)

rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global

PAPullUp(7) PAPullUp(6) PAPullUp(5) PAPullUp(4) PAPullUp(3) PAPullUp(2) PAPullUp(1) PAPullUp(0)

rw, 0 pconf

PARes0(7)

rw, 0 pconf

PARes0(6)

rw, 0 pconf

PARes0(5)

rw, 0 pconf

PARes0(4)

rw, 0 pconf

PARes0(3)

rw, 0 pconf

PARes0(2)

rw, 0 pconf

PARes0(1)

rw, 0 pconf

PARes0(0)

rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global

PARes1(7) PARes1(6) PARes1(5) PARes1(4) PARes1(3) PARes1(2) PARes1(1) PARes1(0)

rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global rw, 0 global

Table 6.5:

Port A registers

11

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

6.6

PortB

Name

7

6

5

4

3

2

1

0

Address

RegPBOut

PBOut(7)

rw, 0 pconf

PBIn(7)

PBOut(6)

rw, 0 pconf

PBIn(6)

PBOut(5)

rw, 0 pconf

PBIn(5)

PBOut(4)

rw, 0 pconf

PBIn(4)

PBOut(3)

rw, 0 pconf

PBIn(3)

PBOut(2)

rw, 0 pconf

PBIn(2)

PBOut(1)

rw, 0 pconf

PBIn(1)

PBOut(0)

rw, 0 pconf

PBIn(0)

h0028

h0029

RegPBIn

r

RegPBDir

PBDir(7)

rw, 0 pconf

PBOpen(7)

rw, 0 pconf

PBDir(6)

rw, 0 pconf

PBOpen(6)

rw, 0 pconf

PBDir(5)

rw, 0 pconf

PBOpen(5)

rw, 0 pconf

PBDir(4)

rw, 0 pconf

PBOpen(4)

rw, 0 pconf

PBDir(3)

rw, 0 pconf

PBOpen(3)

rw, 0 pconf

PBDir(2)

rw, 0 pconf

PBOpen(2)

rw, 0 pconf

PBDir(1)

rw, 0 pconf

PBOpen(1)

rw, 0 pconf

PBDir(0)

rw, 0 pconf

PBOpen(0)

rw, 0 pconf

h002A

RegPBOpen

h002B

RegPBPullup

h002C

RegPBAna

PBPullUp(7) PBPullUp(6) PBPullUp(5) PBPullUp(4) PBPullUp(3) PBPullUp(2) PBPullUp(1) PBPullUp(0)

rw, 0 pconf

PBAna(3)

rw, 0 pconf

PBAna(2)

rw, 0 pconf

PBAna(1)

rw, 0 pconf

PBAna(0)

rw, 0 pconf

h002D

Table 6.6:

Port B registers

6.7

PortC

Name

7

6

5

4

3

2

1

0

Address

RegPCOut

PCOut(7)

rw, 0 pconf

PCIn(7)

r

PCOut(6)

rw, 0 pconf

PCIn(6)

r

PCOut(5)

rw, 0 pconf

PCIn(5)

r

PCOut(4)

rw, 0 pconf

PCIn(4)

r

PCOut(3)

rw, 0 pconf

PCIn(3)

r

PCOut(2)

rw, 0 pconf

PCIn(2)

r

PCOut(1)

rw, 0 pconf

PCIn(1)

r

PCOut(0)

rw, 0 pconf

PCIn(0)

r

h0030

h0031

h0032

RegPCIn

RegPCDir

PCDir(7)

rw, 0 pconf

PCDir(6)

rw, 0 pconf

PCDir)

PCDir(4)

rw, 0 pconf

PCDir(3)

rw, 0 pconf

PCDir(2)

rw, 0 pconf

PCDir(1)

rw, 0 pconf

PCDir(0)

rw, 0 pconf

Table 6.7:

Port C registers

6.8

MTP

Name

7

6

5

4

3

2

1

0

Address

RegEEP

RegEEP1

RegEEP2

RegEEP3

rw

h0038

h0039

h003A

h003B

rw

special

Table 6.8:

MTP control registers

12

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

6.9

Events

Name

7

6

5

4

3

2

1

0

Address

RegEvn

EvnCntA

rc1, 0 global

EvnEnCntA

rw, 0 global

EvnCntC

rc1, 0 global

EvnEnCntC

rw, 0 global

EvnPre1

rc1, 0 global

EvnEnPre1

rw, 0 global

EvnPA(1)

rc1, 0 global

EvnEnPA(1)

rw, 0 global

EvnCntB

rc1, 0 global

EvnEnCntB

rw, 0 global

EvnCntD

rc1, 0 global

EvnEnCntD

rw, 0 global

EvnPre2

rc1, 0 global

EvnEnPre2

rw, 0 global

EvnPA(0)

rc1, 0 global

EvnEnPA(0)

rw, 0 global

h003C

RegEvnEn

h003D

RegEvnPriority

h003E

RegEvnEvn

h003F

EvnPriority(7) EvnPriority(6) EvnPriority(5) EvnPriority(4) EvnPriority(3) EvnPriority(2) EvnPriority(1) EvnPriority(0)

r,1 global

EvnHigh

r, 0 global

r,1 global

EvnLow

r, 0 global

Table 6.9:

Events control registers

6.10 Interrupts

Name

7

6

5

4

3

2

1

0

Address

RegIrqHig

IrqAc

IrqPre1

IrqCntA

rc1, 0 global

IrqPA(4)

IrqCntC

rc1, 0 global

IrqPre2

IrqUartTx

rc1, 0 global

IrqPA(1)

IrqUartRx

rc1, 0 global

IrqPA(0)

rc1, 0 global

h0040

RegIrqMid

IrqPA(5)

rc1, 0 global

IrqCntB

IrqVld

rc1, 0 global

IrqCntD

rc1, 0 global

IrqPA(3)

rc1, 0 global

IrqPA(2)

rc1, 0 global

h0041

RegIrqLow

h0042

RegIrqEnHig

h0043

RegIrqEnMid

h0044

RegIrqEnLow

h0045

RegIrqPriority

h0046

IrqPA(7)

rc1, 0 global

IrqEnAc

IrqPA(6)

rc1, 0 global

IrqEnPre1

rc1, 0 global

IrqEnCntA

rw, 0 global

IrqEnPA(4)

rw, 0 global

IrqEnCntD

rw, 0 global

rc1, 0 global

IrqEnCntC

rw, 0 global

IrqEnPre2

rw, 0 global

IrqEnPA(3)

rw, 0 global

rc1, 0 global

IrqEnUartTx IrqEnUartRx

rw, 0 global

IrqEnPA(1)

rw, 0 global

IrqEnPA(0)

rw, 0 global

IrqEnPA(5)

rw, 0 global

IrqEnCntB

rw, 0 global

IrqEnVld

rw, 0 global

IrqEnPA(2)

rw, 0 global

IrqEnPA(7)

rw, 0 global

IrqEnPA(6)

rw, 0 global

IrqPriority(7) IrqPriority(6) IrqPriority(5) IrqPriority(4) IrqPriority(3) IrqPriority(2) IrqPriority(1) IrqPriority(0)

r, 1 global

IrqHig

r, 1 global

IrqMid

r, 1 global

IrqLow

RegIrqIrq

r, 0 global

h0047

Table 6.10:

Interrupts control registers

6.11 USRT

Name

Address

7

6

5

4

3

2

1

0

RegUsrtSin

h0048

RegUsrtScl

h0049

UsrtSin

rw, 1 global

UsrtScl

rw, 1 global

UsrtEnWait-

Cond1

RegUsrtCtrl

UsrtWaitS0

r, 0 global

UsrtEnWaitS0

rw, 0 global

UsrtEnable

rw, 0 global

UsrtData

r

h004A

RegUsrtData

h004D

RegUsrtEdgeScl

h004E

UsrtEdgeScl

r, 0 global

Table 6.11:

USRT control registers

13

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Data Sheet XE88LC01

Data Acquisition Microcontroller

6.12 UART

Name

Address

7

6

5

4

3

2

1

0

RegUartCtrl

h0050

RegUartCmd

h0051

RegUartTx

h0052

RegUartTxSta

h0053

UartEcho

rw, 0 global

SelXtal

UartEnRx

UartEnTx

UartXRx

UartXTx

UartBR(2)

rw, 1 global

UartPM

UartBR(1)

rw, 0 global

UartPE

UartBR(0)

rw, 1 global

UartWL

rw, 0 global

UartWakeup UartRCSel(2) UartRCSel(1) UartRCSel(0)

rw, 0 global

UartTx(7)

rw, 0 global

UartTx(6)

rw, 0 global

UartTx(5)

rw, 0 global

UartTx(4)

rw, 0 global

UartTx(3)

rw, 0 global

UartTx(2)

rw, 0 global

UartTx(1)

rw, 0 global

UartTxBusy

r, 0 global

UartRx(1)

r

rw, 1 global

UartTx(0)

rw, 0 global

UartTxFull

r, 0 global

UartRx(0)

r

rw, 0 global

RegUartRx

h0054

UartRx(7)

r

UartRx(6)

r

UartRx(5)

UartRx(4)

UartRx(3)

UartRx(2)

r

RegUartRxSta

h0055

UartRxSErr

r

UartRxPErr

r

UartRxFErr

r

UartRxOErr

c

UartRxBusy

r

UartRxFull

r

Table 6.12:

UART control registers

6.13 Counters

Name

7

6

5

4

3

2

1

0

Address

RegCntA

RegCntB

RegCntC

RegCntD

CounterA(7)

CounterA(6)

CounterA(5)

CounterA(4)

CounterA(3)

rw

CounterA(2)

CounterA(1)

rw

CounterA(0)

rw

CounterB(7)

rw

CounterB(6)

rw

CounterB(5)

rw

CounterB(4)

rw

CounterB(2)

rw

h0058

h0059

h005A

h005B

CounterB(3)

rw

CounterB(1)

rw

CounterB(0)

rw

CounterC(7)

rw

CounterC(6)

rw

CounterC(5)

rw

CounterC(4)

rw

CounterC(3)

rw

CounterC(2)

rw

CounterC(1)

rw

CounterC(0)

rw

CounterD(7)

rw

CounterD(6)

rw

CounterD(5)

rw

CounterD(4)

rw

CounterD(3)

rw

CounterD(2)

rw

CounterD(1)

rw

CounterD(0)

rw

RegCntCtrlCk

h005C

RegCntConfig1

h005D

RegCntConfig2

h005E

RegCntOn

h005F

CntDSel(1)

rw

CntDSel(0)

rw

CntCSel(1)

rw

CntCSel(0)

rw

CntBSel(1)

rw

CntBSel(0)

rw

CntASel(1)

rw

CntASel(0)

rw

CntDDownUp CntCDownUp CntBDownUp CntADownUp CascadeCD

CascadeAB

rw

CntPWM1

rw, 0 global

CntPWM0

rw, 0 global

rw

CapSel(1)

rw, 0 global

CapSel(0)

rw, 0 global

CapFunc(1)

rw, 0 global

CapFunc(0) PWM1Size(1) PWM1Size(0) PWM0Size(1) PWM0Size(0)

rw, 0 global

rw

CntDEnable

rw, 0 global

CntCEnable

rw, 0 global

CntBEnable

rw, 0 global

CntAEnable

rw, 0 global

Table 6.13:

Counters control registers

14

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

6.14 Acquisition chain

Name

Address

RegAcOutLsb

h0060

RegAcOutMsb

h0061

RegAcCfg0

h0062

RegAcCfg1

h0063

RegAcCfg2

h0064

RegAcCfg3

h0065

RegAcCfg4

h0066

RegAcCfg5

h0067

7

6

5

4

3

2

1

0

AdcOutL(7)

r

AdcOutL(6)

r

AdcOutL(5)

r

AdcOutL(4)

r

AdcOutL(3)

r

AdcOutL(2)

r

AdcOutL(1)

r

AdcOutL(0)

r

AdcOutM(7) AdcOutM(6) AdcOutM(5) AdcOutM(4) AdcOutM(3) AdcOutM(2) AdcOutM(1) AdcOutM(0)

r

Start

NelConv(1)

rw, 0 global

NelConv(0)

rw, 1 global

OSR(2)

OSR(1)

OSR(0)

Cont

r0w, 0 global

rw, 0 global

rw, 1 global

Enable(3)

rw, 0 global

Enable(2)

rw, 0 global

Enable(1)

rw, 0 global

Pga2Off(1)

rw, 0 global

Pga3Gain(1)

rw, 0 global

Pga3Off(1)

rw, 0 global

AMux(0)

IbAmpADC(1) IbAmpAdc(0) IbAmpPga(1) IbAmpPga(0)

Enable(0)

rw, 1 global

Pga2Off(0)

rw, 0 global

Pga3Gain(0)

rw, 0 global

Pga3Off(0)

rw, 0 global

VMux

rw, 1 global

Fin(1)

rw, 1 global

Fin(0)

rw, 1 global

Pga2Gain(1)

rw, 0 global

Pga3Gain(5)

rw, 0 global

Pga3Off(5)

rw, 0 global

AMux(4)

rw, 1 global

Pga2Gain(0)

rw, 0 global

Pga3Gain(4)

rw, 0 global

Pga3Off(4)

rw, 0 global

AMux(3)

rw, 0 global

Pga2Off(3)

rw, 0 global

Pga3Gain(3)

rw, 1 global

Pga3Off(3)

rw, 0 global

AMux(2)

rw, 0 global

Pga2Off(2)

rw, 0 global

Pga3Gain(2)

rw, 1 global

Pga3Off(2)

rw, 0 global

AMux(1)

rw, 0 global

Pga1Gain

rw, 0 global

Pga3Gain(6)

rw, 0 global

Pga3Off(6)

rw, 0 global

Def

Busy

r, 0 global

wr0

rw, 0 global

Table 6.14:

Acquisition chain control registers

6.15 Vmult and Vld registers

Name

Address

RegVmultCfg0

h007C

RegVldCtrl

h007E

RegVldStat

h007F

7

6

5

4

3

2

1

0

Enable

rw, 0 global

VldTune(2)

rw, 0 cold

VldIrq

Fin(1)

Fin(0)

rw, 0 global

VldTune(1)

rw, 0 cold

VldValid

rw, 0 global

VldTune(0)

rw, 0 cold

VldEn

VldMult

rw, 0 cold

r, 0 global

rw, 0 global

Table 6.15:

Vmult and Vld control registers

15

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

7 Peripherals

The XE88LC01 includes usual microcontroller peripherals and some other blocks more spe-

cific to low-voltage or mixed-signal operation. They are 3 parallel ports, one input port (A), one

IO and analog port (B) with analog switching capabilities and one general purpose IO port (C).

A watchdog is available, connected to a prescaler. Four 8-bit counters, with capture, PWM and

chaining capabilities are available. The UART can handle transmission speeds as high as

115kbaud.

Low-power low-voltage blocks include a voltage level detector, two oscillators (one internal

0.1-2 MHz RC oscillator and a 32 kHz crystal oscillator) and a specific regulation scheme that

largely uncouples current requirement from external power supply (usual CMOS ASICs re-

quire much more current at 5.5 V than they need at 2.4 V. This is not the case for the

XE88LC01).

Analog blocks (ZoomingADC (acquisition path)) are defined below. All these blocks operate

on 2.4 - 5.5 V power supply range.

7.1 Counters

•

4 8-bit counters

Daisy chain on 16 bits

PWM on 8-16 bits

Capture - compare on 16 bits

Events and interrupts generation

7.2 Prescaler

7.3 Watchdog

7.4 UART

•

Interrupt generated with 1 second period for ultra low power hibernation mode

2 seconds watchdog

•

full duplex operation with buffered receiver and transmitter.

Internal baudrate generator with programmable baudrate (300 - 115000 bauds).

7 or 8 bits word length.

even, odd, or no-parity bit generation and detection

1 stop bit

error receive detection : Start, Parity, Frame and Overrun

receiver echo mode

2 interrupts (receive full and transmit empty)

enable receive and/or transmit

invert pad Rx and/or Tx

16

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

7.5 Xtal clock

The Xtal Oscillator operates with an external crystal of 32’768 Hz.

symbol

f_clk32k

description

nominal frequency

min

typ

32768

1

max

unit

Hz

s

comments

st_x32k

oscillator start-up time

2

for full precision

duty_clk32k

duty cycle on the digital output

30

50

70

%

relative frequency deviation from

nominal, for a crystal with CL=8.2 pF

and temperature between -40° and

+85°C

not included:

crystal frequency tolerance and aging

crystal frequency - temperature dependence

fstab_1

-100

+300

ppm

Table 7.1:

Note:

Xtal oscillator specifications.

Board layout recommendations for safer crystal oscillation and lower current consumption:

Keep lines xtal_in and xtal_out short and insert a VSS line between them.

Connect package of the crystal to VSS.

No noisy or digital lines near xtal_in and xtal_out.

Insert guards at VSS where needed.

7.6 RC oscillator

The RC Oscillator is always turned on at power-on reset and can be turned off after the option-

al Xtal oscillator has been started. The RC oscillator has two frequency ranges: sub-MHz

(100KHz to 1MHz) and above-MHz (1MHz to max MCU frequency). Inside a range, the fre-

quency can be tuned by software for coarse and fine adjustment.

Note:

No external component is required for the RC oscillator.

The RC oscillator can be in 3 modes. In mode 1(RC on), the RC oscillator and its bias are on.

In mode 2 (RC ready), the RC oscillator is off and the bias is on. In mode 3 (RC off), the RC

oscillator and the bias are off. RC ready mode is a compromise between power consumption

and start-up time.

Figure 7.1:

RC frequencies programming example for low range (typical values)

17

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

symbol

F_st

description

frequency at start-up

range selection

min

50

typ

80

max

110

10

16

1.5

2

unit

kHz

comments

multiplies F_st

range

1

4 bits, multiplies F_st* range

6 bits, multiplies F_st* range * mult

mult[3:0]

coarse tuning range

fine tuning range

fine tuning step

1

0.65

tune[5:0]

1.4

30

%

µs

%

µs

T_st

O_st

start-up time

50

5

bias current is off (RC off)

bias current is on (RC ready)

overshoot at start-up

wakeup time

T_wu

O_wu

3

2

overshoot at wakeup

50

%

o

jit

jitter rms

/

oo

Table 7.2:

RC specifications

7.7 Parallel IO ports

•

8 bit input port A with interrupt, reset and event generation.

8 bit input-output-analog port B with analog switching capabilities.

8 bit input-output port C.

sym

description

Port A: low threshold limit

condition

min

typ

max

unit

V

Comments

Port A: high threshold limit

output drop when sinking 1 mA

output drop when sourcing 1 mA

Port A: low threshold limit

V

Vbat =

1.2 V

0.4

V

1

V

Port A: high threshold limit

output drop when sinking 1 mA

output drop when sinking 8 mA

output drop when sourcing 1 mA

output drop when sourcing 8 mA

Port A: low threshold limit

1.5

V

Vbat =

2.4 V

0.4

V

2

3

V

Port A: high threshold limit

output drop when sinking 1 mA

output drop when sinking 8 mA

output drop when sourcing 1 mA

output drop when sourcing 8 mA

pull-up, pull-down resistor

V

Vbat =

5.0 V

0.4

V

0.4

V

50

150

kohm

Table 7.3:

IO pins performances

18

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

7.8 Voltage level detector

•

Can be switched off, on or simultaneously with CPU activities

Generates an interrupt if power supply is below a pre-determined level

The Voltage Level Detector monitors the state of the system battery. It returns a logical high

value (an interrupt) in the status register if the supplied voltage drops below the user defined

level.

symbol

description

min

typ

max

unit

comments

trimming values:

Note 1

VldRange

VldTune

000

001

010

011

100

101

110

111

000

001

010

011

100

101

110

111

1.53

1.44

1.36

1.29

1.22

1.16

1.11

1.06

3.06

2.88

2.72

2.57

2.44

2.33

2.22

2.13

2.0

0

1

Vth

Threshold voltage

V

T_EOM

T_PW

duration of measurement

2.5

ms

us

Note 2

Minimum pulse width detected

875

1350

Table 7.4:

Note:

Voltage level detector operation

1) Absolute precision of the threshold voltage is 10%.

2) This timing is respected in case the internal RC or crystal oscillators are selected. Refer to the clock

block documentation in case the external clock is used.

19

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

8 ZoomingADC

The fully differential acquisition chain is formed of a programmable gain (0.5 - 1000) and offset

amplifier and a programmable speed and resolution ADC (example: 12 bits at 4 kHz, 16 bits

at 1 kHz). It can handle inputs with very low full scale signal and large offsets.

reference selection

AC_R(0)

AC_R(1)

AC_R(2)

AC_R(3)

AC_A(0)

AC_A(1)

AC_A(2)

AC_A(3)

ADC

AC_A(4)

AC_A(5)

AC_A(6)

gain1

mode output

code

gain2

offset2

gain3

offset3

AC_A(7)

input selection

Figure 8.1:

Acquisition channel block diagram

Input selection is made from 1 of 4 differential pairs or 1 of seven single signal versus AC_A(0).

Reference is chosen from the 2 differential references. Acquisition path offset can be sup-

pressed by inverting input polarity.

The gain of each amplifier is programmed individually. Each amplifier is powered on and off on

command to minimize the total current requirement. All blocks can be set to low frequency op-

eration and lower their current requirement by a factor 2 or 4.

The ADC can run continuously (end of conversion signalled by an interrupt, event or by pooling

the ready bit), or it can be started on request.

8.1 PGA 1

symbol

GD1

description

PGA1 Signal Gain

min

1

typ

max

10

unit

-

Comments

GD1 = 1 or 10

GD_preci

GD_TC

fs

Precision on gain settings

Temperature dependency of gain settings

input sampling frequency

Input impedance

-5

+5

%

-5

+5

ppm/°C

kHz

kΩ

512

Zin1

150

1

Zin1p

Input impedance for gain 1

1500

kΩ

nV/

sqrt(Hz)

VN1

Input referred noise

28.6

2

Table 8.1:

Note:

PGA1 Performances

1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequen-

cy for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs

= 128 kHz.

2) Input referred rms noise is 205 uV per input sample with gain = 1, 20.5 uV with gain = 10. This cor-

responds to 28.6 nV/sqrt(Hz) for fs = 512 kHz and gain = 10.

20

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

8.2 PGA2

sym

GD2

description

PGA2 Signal Gain

min

1

typ

0.2

max

10

unit

-

FS

Comments

GD2 = 1, 2, 5 or 10

GDoff2

GDoff2_step

GD_preci

GD_TC

fs

PGA2 Offset Gain

-1

1

GDoff2(code+1) – GDoff2(code)

Precision on gain settings

Temperature dependency of gain settings

Input sampling frequency

Input impedance

0.18

-5

0.22

+5

-

%

valid for GD2 and GDoff2

-5

+5

ppm/°C

kHz

kΩ

nV/

sqrt(Hz)

512

Zin2

150

1

2

VN2

Input referred noise

47.5

Table 8.2:

Note:

PGA2 Performances

1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequen-

cy for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs

= 128 kHz.

2) Input referred rms noise is 340 uV per input sample with gain = 1, 34 uV with gain = 10.This corre-

sponds to 47.5 nV/sqrt(Hz) for fs = 512 kHz and gain = 10.

8.3 PGA3

sym

GD3

description

PGA3 Signal Gain

min

0

typ

max

10

unit

-

Comments

GDoff3

GD3_step

GDoff3_step

GD_preci

GD_TC

fs

PGA3 Offset Gain

-5

5

FS

GD3(code+1) - GD3(code)

GDoff2(code+1) – GDoff2(code)

Precision on gain settings

Temperature dependency of gain settings

Input sampling frequency

0.075

-5

0.08

0.085

+5

-

%

valid for GD3 and GDoff3

-5

+5

ppm/°C

kHz

512

Zin3

VN3

Input impedance

150

kΩ

1

2

nV/

sqrt(Hz)

Input referred noise

51.0

Table 8.3:

Note:

PGA3 Performances

1) Measured with block connected to inputs through AMUX block. Normalized input sampling frequen-

cy for input impedance is 512 kHz. This figure has to be multiplied by 2 for fs = 256 kHz and 4 for fs

= 128 kHz.

2) Input referred rms noise is 365 uV per imput sample with gain = 1, 36.5 uV with gain = 10. This cor-

responds to 51.0 nV/sqrt(Hz) for fs = 512 kHz.

21

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

8.4 Analog to digital converter (ADC)

The whole analog to digital conversion sequence is basically made of an initialisation, a set of

Nelconv elementary incremental conversions and finally a termination phase(N is set

umCONV

by 2 bits on RegACCfg0). The result is a mean of the results of the elementary conversions.

1 2

smax 1 2

smax

1 2

smax

input

sample

1st elementary

conversion

2nd elementary

conversion

elementary

conversion

elementary

conversion

END

START

conversion

1

2

N

_umConv-1

N_umConv

index

Figure 8.2:

Conversion sequence. smax is the oversampling rate.

Note: N_umCONVelementary conversions are performed, each elementary conversion being made of

smax input samples.

N

_umCONV= 2^NELCONV

smax = 8*2^OSR

During the elementary conversions, the operation of the converter is the same as in a sigma

delta modulator. During one conversion sequence, the elementary conversions are alterna-

tively performed with direct and crossed PGA-ADC differential inputs, so that when two ele-

mentary conversions or more are performed, the offset of the converter is cancelled.

Some additional clock cycles (N

conversion properly.

+N

) clock cycles are used to initiate and terminate the

INIT

END

8.5 ADC performances

sym

VINR

Resol

NResol

DNL

INL

description

Input range

min

-0.5

6

typ

max

0.5

16

unit

Vref

bits

LSB

kHz

-

Comments

Resolution

Numerical resolution

Differential non-linearity

Integral non-linearity

sampling frequency

Oversampling Ratio

16

3

-0.1

-3

0.1

2

LSB at 16 bits

2, LSB at 16 bits

fs

10

8

512

1024

smax

1

Number of elementary conversions in

incremental mode

N_UMCONV

Ninit

1

8

5

-

Number of periods for incremental conversion

initialization

Number of periods for incremental conversion

termination

Nend

Table 8.4:

ADC Performances

1) Only powers of 2

Note:

2) INL is defined as the deviation of the DC transfer curve from the best fit straight line. This specifi-

22

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

cation holds over 100% of the full scale.

3) NResol is the maximal readable resolution of the digital filter.

8.6

resolution

6

conditions

oversampling per convertion = 8

1 conversion (no offset rejection)

input frequency. convertion time. output frequency.

512 kHz

40 us

50 us

25 kHz

20 kHz

6.7 kHz

3.6 kHz

2 kHz

oversampling per convertion = 16

1 conversion (no offset rejection)

8

oversampling per convertion = 64

1 conversion (no offset rejection)

12

13

16

150 us

275 us

500 us

1 ms

oversampling per convertion = 64

2 convertions (offset rejection)

oversampling per convertion = 256

1 convertion (no offset rejection)

oversampling per convertion = 256

2 convertions (offset rejection)

1 kHz

oversampling per convertion = 1024

8 convertions (offset rejection)

16.5 ms

60 Hz

Table 8.5:

ADC performances examples

8.7 Linearity

To quantify linearity errors, Integral Non-Linearity (INL) and Differential Non-Linearity (DNL)

were measured for the ADC alone and for gains of 1, 5, 10, 20, 100, 1000, and a resolution of

12 bits and 16 bits.

INL is defined as the deviation (in LSB) of the DC transfer curve of each individual code from

the best-fit straight line. This specification holds over the full scale.

DNL is defined as the difference (in LSB) between the ideal (1 LSB) and measured code tran-

sitions for successive codes. INL and DNL are specified after gain and offset errors have been

removed.

8.8 Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) for 12-bit reso-

lution

12 bits - ADC converter (No PGA; ADC only) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV =

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

4

f

0.50

0.40

0.30

0.20

0.10

0.00

-0.10

-0.20

-0.30

1.0

0.8

0.6

0.4

0.2

0.0

-0.2

-0.4

-0.6

-0.8

-1.0

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

V_IN[mV]

Figure 8.3:

NO GAIN (ONLY ADC), 12 bit ADC setting

23

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

12 bits - ADC converter (GDtot = 1) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV =

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

4

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

2.0

1.5

0.50

0.40

0.30

0.20

0.10

0.00

-0.10

-0.20

-0.30

1.0

0.5

INL

0.0

-0.5

-1.0

-1.5

-2.0

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

V_IN[mV]

Figure 8.4:

GAIN=1, 12 bit ADC setting

12 bits - ADC converter (GDtot = 5) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

^RC= 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

N

f

0.50

0.40

0.30

0.20

0.10

0.00

-0.10

-0.20

-0.30

1.0

0.5

0.0

-0.5

-1.0

-1.5

0

100

200

V_IN[mV]

300

400

500

0

100

200

300

400

500

V_IN[mV]

Figure 8.5:

GAIN=5, 12 bit ADC setting

12 bits - ADC converter (GDtot = 10) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

^RC= 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

0.50

2.0

1.5

0.40

0.30

1.0

0.20

0.5

0.10

0.00

0.0

-0.10

-0.20

-0.30

-0.40

-0.50

-0.5

-1.0

-1.5

-2.0

0

50

100

150

200

250

0

50

100

150

200

250

V_IN[mV]

Figure 8.6:

GAIN=10, 12 bit ADC setting

24

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

12 bits - ADC converter (GDtot = 20) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

0.60

0.40

0.8

0.6

0.4

0.20

0.2

0.00

0.0

-0.20

-0.40

-0.60

-0.80

-0.2

-0.4

-0.6

-0.8

0

20

40

60

V_IN[mV]

80

100

120

0

20

40

60

80

100

120

V_IN[mV]

Figure 8.7:

GAIN=20, 12 bit ADC setting

12 bits - ADC converter (GDtot = 100) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat

=

Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

1.00

0.50

4.0

3.0

2.0

1.0

0.00

0.0

-0.50

-1.00

-1.50

-1.0

-2.0

-3.0

-4.0

0

5

10

15

20

25

0

5

10

15

20

25

V_IN[mV]

Figure 8.8:

GAIN=100, 12 bit ADC setting

12 bits - ADC converter (GDtot = 1000) (version v5a)

Vbat

=

Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

^RC= 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 32; NELCONV = 4

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

6.0

4.0

2.0

1.5

1.0

2.0

0.5

0.0

-0.5

-1.0

-1.5

-2.0

-4.0

-6.0

0

5

10

15

20

25

0

5

10 15

10*V_IN[mV]

20

25

10*V_IN[mV]

Figure 8.9:

GAIN=1000, 12 bit ADC setting

25

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

8.9 Integral Non-Linearity (INL) and Differential Non-Linearity (DNL) for 16-bit reso-

lution

16 bits - ADC converter (No PGA; ADC only) (version v5a)

16 bits- ADC converter (No PGA; ADC only) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

sweep = 1201; average on 4 samples

f

=

f

N

3

2

0.10

0.05

1

0.00

0

-0.05

-0.10

-0.15

-1

-2

-3

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

V_IN[mV]

Figure 8.10:

NO GAIN (ONLY ADC), 16 bit ADC setting

16 bits - ADC converter (GDtot = 1) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

25.0

0.10

0.08

0.06

0.04

0.02

0.00

-0.02

-0.04

-0.06

-0.08

-0.10

20.0

15.0

10.0

5.0

0.0

-5.0

-10.0

-15.0

-20.0

-25.0

0

500

1000

1500

2000

2500

0

500

1000

1500

2000

2500

V_IN[mV]

Figure 8.11:

GAIN=1, 16 bit ADC setting

16 bits - ADC converter (GDtot = 5) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

16 bits - ADC converter (GDtot = 5) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

f

N sweep = 1201; average on 4 samples

10.0

5.0

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

0.0

-5.0

-10.0

-15.0

-20.0

0

100

200

300

400

500

0

100

200

300

400

500

V_IN[mV]

Figure 8.12:

GAIN=5, 16 bit ADC setting

26

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

16 bits - ADC converter (GDtot = 10) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

^RC= 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

30

20

10

0

0.25

0.20

0.15

0.10

0.05

0.00

-0.05

-0.10

-0.15

-0.20

-0.25

-10

-20

-30

0

50

100

150

200

250

0

50

100

V_IN[mV]

150

200

250

V_IN[mV]

Figure 8.13:

GAIN=10, 16 bit ADC setting

16 bits - ADC converter (GDtot = 20) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

^RC= 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

0.6

0.4

10

8

6

4

0.2

2

0.0

0

-2

-4

-6

-8

-0.2

-0.4

-0.6

0

-10

20

40

60

V_IN[mV]

80

100

120

0

20

40

60

80

100

120

V_IN[mV]

Figure 8.14:

GAIN=20, 16 bit ADC setting

16 bits - ADC converter (GDtot = 100) (version v5a)

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV =

RC 2MHz; IB_AMP(1:0) = 11; Vinn=0V

sweep = 1201; average on 4 samples

2

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC

2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

f

=

f

=

N

40

30

0.8

0.6

0.4

20

0.2

10

0.0

0

-0.2

-0.4

-0.6

-0.8

-1.0

-10

-20

-30

-40

0

5

10

15

20

25

0

5

10

15

20

25

V_IN[mV]

Figure 8.15:

GAIN=100, 16 bit ADC setting

27

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

16 bits - ADC converter (GDtot = 1000) (version v5a)

2

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV = 2

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

N sweep = 1201; average on 4 samples

Vbat = Vref = 5.0V; fs = 500kHz; OSR = 512; NELCONV =

RC = 2MHz; IB_AMP(1:0) = 11; Vinn=0V

f

N

sweep = 1201; average on 4 samples

80

60

2.0

1.5

40

1.0

20

0.5

0

0.0

-20

-40

-60

-80

-0.5

-1.0

-1.5

-2.0

0

5

10

15

20

25

0

5

10 15

10*V_IN[mV]

20

25

10*V_IN[mV]

Figure 8.16:

GAIN=1000, 16 bit ADC setting

The gain settings of each PGA stage for the plots of above figure are those of the table below.

PGA Gain

PGA1 Gain

GD1

PGA2 Gain

GD2

PGA3 Gain

GD3

GD

TOT

(V/V)

1

bypassed

10

5

1

5

10

bypassed

20

2

100

1000

10

Table 8.6:

Table 8.7:

Individual PGA gains for INL & DNL measurements

8.10 Noise

Ideally, a constant input voltage V should result in a constant output code. However, because

IN

of circuit noise, the output code may vary for a fixed input voltage. The figure shows the distri-

bution for the ADC alone (PGA1, 2, and 3 bypassed) and of several configurations of the

PGAs. Quantization noise is dominant in this case of ADC only, and, thus, the ADC thermal

noise is negligible.

One has to considere two points when computing final noise of the acquisition chain:

•

this is a type of amplifier (switched-cap with constant capacitive load) that maintains its output

noise when changing the gain. Therefore input refered noise is lowered when the gain of an

amplifier is increased.

the ADC is oversampled, and the number of samples taken lowers the thermal noise

Total input refered noise can be computed using the following equation:

2













²







²



V_{n, out1}

-----------------

gain1

V_{n, out2}

V_{n, out3}

----------------------------------

gain1 ⋅ gain2

-----------------------------------------------------

gain1 ⋅ gain2 ⋅ gain3

+

V²

=

-----------------------------------------------------------------------------------------------------------------------------------------------

n, in

numconv ⋅ smax

28

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

Where V

is the rms output noise of amplifier x.

n,outx

Typical output noise per

over-sample

205

Amplifier

Symbol

Unit

V_n,out1

V_n,out2

V_n,out3

PGA1

PGA2

PGA3

uVrms

340

365

Typical output noise of ZoomingADC preamplifiers

ADC only

PGA1: 1

PGA2: 10

PGA3: off

PGA1: off

PGA2: 1

PGA3: 10

PGA1: 1

PGA2: 10

PGA3: 10

PGA1: 10

PGA2: 10

PGA3: off

Figure 8.17:

Noise measured at the output of the ZoomingADC

As one can see on the figures above, increase the gain of the first amplifier lowers the output

noise for constant global gain. It also lowers sensitivity to temperature drift as offset is better

compensated on first amplifier.

8.11 Gain Error and Offset Error

Gain error is defined as the amount of deviation between the ideal transfer function and the

measured transfer function (with the offset error removed). The left figure shows gain error vs.

temperature for different PGA gains. The curves are expressed in % of Full-Scale Range

(FSR) normalized to 25°C.

29

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

Offset error is defined as the output code error for a zero volt input (ideally, output code = 0).

The measured offset errors vs. temperature curves for different PGA gains are depicted in the

right figure below. The output offset error, expressed in (LSB), is normalized to 25°C.

0.2

0.1

100

1

5

20

100

80

60

40

20

0

0.0

-0.1

-0.2

-0.3

-0.4

1

5

20

100

-20

-40

-50

-25

0

25

50

75

100

-50

-25

0

25

50

75

100

Temperature [°C]

Figure 8.18:

Gain and offset error vs temperature for several gains, normalized to 25°C, offset cancellation

disabled. When the offset cancellation is enabled, the offset remains below the LSB in all

temperature situations.

8.12 Power Consumption

Left figure below plots the variation of quiescent current consumption with supply voltage V

,

DD

as well as the distribution between the 3 PGA stages and the ADC. As shown in the right figure,

quiescent current consumption is not greatly affected by sampling frequency. It can be seen

that the quiescent current varies by about 20% between 100kHz and 2MHz. Quiescent current

consumption vs. temperature is shown in the second set of figures, showing a relative increase

of nearly 40% between -45 and +85°C.

800

700

600

500

400

300

200

100

750

PGA1, 2 & 3

500kHz

250kHz

62.5kHz

Sampling Frequency f_S

:

700

650

600

550

500

PGA1 & 2 only

PGA1 only

No PGAs, ADC only

2.5

3.0

3.5

4.0

4.5

5.0

5.5

2.5

3.0

3.5

4.0

4.5

5.0

5.5

Supply Voltage - V_DDA[V]

Figure 8.19:

Quiescent current versus supply voltage for different gains and clock speed (not using the PGA and

ADC low power modes)

Supply

V_DD= 5V

ADC

250

PGA1

165

PGA2

130

PGA3

175

TOTAL

720

Unit

µA

V

_DD= 3V

190

150

120

160

620

µA

Table 8.8:

Typical quiescent current distributions in acquisition chain (n = 16 bits, f = 500kHz)

S

30

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

20

15

10

5

900

850

800

750

700

650

600

550

500

0

-5

-10

-15

-20

-25

-50

-25

0

25

50

75

100

125

-50

-25

0

25

50

75

100

125

Temperature [°C]

Figure 8.20:

Absolute and (b) relative change in quiescent current consumption vs. temperature

15

10

5

850

800

750

700

650

600

550

0

-5

-10

-15

-20

500

0

500

1000

1500

2000

2500

3000

3500

0

500

1000

1500

2000

2500

3000

3500

Frequency - f_RC[kHz]

Figure 8.21:

Absolute and (b) relative change in quiescent current consumption vs. clock speed

8.13 Power Supply Rejection Ratio

Figure below shows power supply rejection ratio (PSRR) at 3V and 5V supply voltage, and for

various PGA gains. PSRR is defined as the ratio (in dB) of voltage supply change (in V) to the

change in the converter output (in V). PSRR depends on both PGA gain and supply voltage

V

.

DD

31

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

105

100

95

VDD=3V

VDD=5V

90

85

80

75

70

65

60

1

5

10

20

100

PGA Gain [V/V]

Figure 8.22:

Power supply rejection ratio (PSRR)

Supply

GAIN = 1

GAIN =5

GAIN = 10

GAIN = 20

GAIN =100

Unit

dB

V_DD= 5V

79

72

78

79

100

90

99

90

97

86

V_DD= 3V

dB

Table 8.9:

PSRR (n = 16 bits, V = V

= 2.5V, f = 500kHz)

REF S

IN

8.14 Frequency Response

The incremental ADC of the XE88LC01 is an over-sampled converter with two main blocks:

an analog modulator and a low-pass digital filter. The main function of the digital filter is to re-

move the quantization noise introduced by the modulator. As shown below, this filter deter-

mines the frequency response of the transfer function between the output of the ADC and the

analog input V . Notice that the frequency axes are normalized to one elementary conversion

IN

period OSR/f . The plots below also show that the frequency response changes with the

S

number of elementary conversions N

performed. In particular, notches appear for

ELCONV

N

≥ 2. These notches occur at:

ELCONV

i ⋅ f_S

OSR ⋅ N_ELCONV

f_NOTCH(i) =

i = 1,2,...,(N_ELCONV−1)

(Hz)for

and are repeated every f /OSR.

S

Information on the location of these notches is particularly useful when specific frequencies

must be filtered out by the acquisition system. For example, consider a 5Hz-bandwidth, 16-bit

sensing system where 50Hz line rejection is needed. Using the above equation and the plots

below, we set the 4th notch for N

frequency is then calculated as f = 20.48kHz for OSR = 512. Notice that this choice yields

= 4 to 50Hz, i.e. 1.25⋅f /OSR = 50Hz. The sampling

ELCONV

S

also good attenuation of 50Hz harmonics.

32

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

1.2

1

1.2

1

N_ELCONV= 2

N_ELCONV= 1

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

1

2

3

4

0

1

2

3

4

Normalized Frequency - f *(OSR/f_S) [-]

1.2

1

1.2

1

N_{EL CONV}= 8

N_ELCONV= 4

0.8

0.6

0.4

0.2

0

0.8

0.6

0.4

0.2

0

1

2

3

4

0

1

2

3

4

Normalized Frequency - f *(OSR/f_S) [-]

Figure 8.23:

Frequency response: normalized magnitude vs. frequency for different N

ELCONV

33

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

9 Physical description

9.1 LQFP44 package

Figure 9.1:

LQFP44 package, size in mm.

9.2 PLL-44L package

Figure 9.2:

PLL-44L package,

34

D0202-60

Data Sheet XE88LC01

Data Acquisition Microcontroller

9.3 Die form

pin 1

2

Figure 9.3:

XE88LC01 in die: 4.1 x 4.6 mm

9.3.1 Bonding pads location

Coordinates start with a point near to the bottom left border (with respect to above picture). X

is horizontal, Y is vertical.

Pad size is 85 x 85 um.

Symbol

Pad

X

Y

Symbol

Pad

X

Y

um

1

PA(4)

PA(5)

NC

52.6

4075.5

3795.5

3515.5

3235.5

2955.5

2675.5

2395.5

2115.5

1835.5

1555.5

1275.5

995.5

715.5

435.5

47.6

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

AC_R(2)

AC_A(7)

NC

3314.1

3958.4

3597.6

3332.6

3067.6

2802.6

2537.0

2007.6

1742.6

1477.6

1212.6

947.6

47.6

2

52.6

522.4

3

52.6

807.4

4

PA(6)

PA(7)

PC(0)

PC(1)

PC(2)

PC(3)

NC

52.6

AC_A(6)

AC_A(5)

AC_A(4)

AC_A(3)

AC_A(2)

NC

1092.4

1377.4

1662.4

1947.4

2232.4

2517.4

2802.4

3087.4

3372.4

3657.4

3942.4

4453.4

5

52.6

6

52.6

7

52.6

8

52.6

9

52.6

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

52.6

AC_A(1)

AC_A(0)

AC_R(1)

AC_R(0)

Vss

PC(4)

PC(5)

PC(6)

PC(7)

PB(0)

PB(1)

PB(2)

PB(3)

PB(4)

NC

52.6

398.5

533.5

668.5

798.5

933.5

1063.5

1198.5

1328.5

1463.5

1934.1

2394.1

2854.1

Vbat

47.6

NC

47.6

Vreg

47.6

RESET

Vmult

47.6

OscIn

PB(5)

PB(6)

PB(7)

TEST

NC

47.6

NC

47.6

OscOut

PA(0)

47.6

PA(1)

47.6

PA(2)

682.6

AC_R(3)

47.6

PA(3)

417.6

Table 9.1:

Bonding pads location. Do not connect pads named NC. Connect Vss pad and substrate to Vss.

35

D0202-60


型号：	XE88LC01RI000
厂家：	ETC
描述：	Sensing Machine 16 + 10 bit Data Acquisition Ultra Low-Power Microcontroller 感应机16 + 10位数据采集超低功耗微控制器微控制器
文件：	总36页 (文件大小：877K)
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