XR-2211P [ETC]
ASK/FSK Demodulator ; ASK / FSK解调器\n
| 型号： | XR-2211P |
| 厂家： | 
ETC |
| 描述： | ASK/FSK Demodulator
|
| 文件： | 总24页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XR-2211
FSK Demodulator/
Tone Decoder
...the analog plus companyTM
June 1997-3
FEATURES
APPLICATIONS
D Wide Frequency Range, 0.01Hz to 300kHz
D Wide Supply Voltage Range, 4.5V to 20V
D HCMOS/TTL/Logic Compatibility
D Caller Identification Delivery
D FSK Demodulation
D Data Synchronization
D Tone Decoding
D FSK Demodulation, with Carrier Detection
D Wide Dynamic Range, 10mV to 3V rms
D Adjustable Tracking Range, +1% to 80%
D Excellent Temp. Stability, +50ppm/°C, max.
D FM Detection
D Carrier Detection
GENERAL DESCRIPTION
The XR-2211 is a monolithic phase-locked loop (PLL)
system especially designed for data communications
applications. It is particularly suited for FSK modem
applications. It operates over a wide supply voltage range
of 4.5 to 20V and a wide frequency range of 0.01Hz to
300kHz. It can accommodate analog signals between
10mV and 3V, and can interface with conventional DTL,
TTL, and ECL logic families. The circuit consists of a basic
PLL for tracking an input signal within the pass band, a
quadrature phase detector which provides carrier
detection, and an FSK voltage comparator which provides
FSK demodulation. External components are used to
independently set center frequency, bandwidth, and output
delay. An internal voltage reference proportional to the
power supply is provided at an output pin.
The XR-2211 is available in 14 pin packages specified for
military and industrial temperature ranges.
ORDERING INFORMATION
Operating
Temperature Range
Part No.
XR-2211M
XR-2211N
XR-2211P
XR-2211ID
Package
14 Pin CDIP (0.300”)
-55°C to +125°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
14 Pin CDIP (0.300”)
14 Pin PDIP (0.300”)
14 Lead SOIC (Jedec, 0.150”)
Rev. 3.01
E1992
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z FAX (510) 668-7017
1
XR-2211
BLOCK DIAGRAM
V
GND
4
NC
9
CC
1
Pre Amplifier
11
3
LDO
LDF
INP
2
Loop
q-Det
TIM C1 14
Lock
Detect
Comparator
6
5
LDOQ
VCO
13
12
TIM C2
TIM R
Quad
q-Det
LDOQN
Internal
10
8
V
V
REF
REF
7
DO
FSK Comp
Reference
COMP I
Figure 1. XR-2211 Block Diagram
Rev. 3.01
2
XR-2211
PIN CONFIGURATION
1
2
3
4
5
14
13
12
11
10
V
CC
TIM C1
TIM C2
1
2
3
4
5
6
7
14
13
12
11
10
9
V
INP
TIM C1
TIM C2
CC
INP
LDF
GND
LDOQN
LDOQ
DO
TIM R
LDO
LDF
GND
LDOQN
TIM R
LDO
V
REF
V
REF
6
7
9
8
NC
COMP I
LDOQ
DO
NC
COMP I
8
14 Lead CDIP, PDIP (0.300”)
14 Lead SOIC (Jedec, 0.150”)
PIN DESCRIPTION
Pin #
1
Symbol
VCC
Type Description
Positive Power Supply.
2
INP
I
Receive Analog Input.
Lock Detect Filter.
Ground Pin.
3
LDF
O
4
GND
5
LDOQN
LDOQ
DO
O
O
O
I
Lock Detect Output Not. This output will be low if the VCO is in the capture range.
Lock Detect Output. This output will be high if the VCO is in the capture range.
Data Output. Decoded FSK output.
6
7
8
COMP I
NC
FSK Comparator Input.
9
Not Connected.
10
11
12
13
14
VREF
O
O
I
Internal Voltage Reference. The value of VREF is VCC/2 - 650mV.
Loop Detect Output. This output provides the result of the quadrature phase detection.
Timing Resistor Input. This pin connects to the timing resistor of the VCO.
Timing Capacitor Input. The timing capacitor connects between this pin and pin 14.
Timing Capacitor Input. The timing capacitor connects between this pin and pin 13.
LDO
TIM R
TIM C2
TIM C1
I
I
Rev. 3.01
3
XR-2211
ELECTRICAL CHARACTERISTICS
Test Conditions: V = 12V, T = +25°C, R = 30KW, C = 0.033mF, unless otherwise specified.
CC
A
O
O
Parameter
Min.
4.5
Typ.
Max.
Unit
Conditions
General
Supply Voltage
Supply Current
Oscillator Section
Frequency Accuracy
Frequency Stability
Temperature
20
7
V
4
mA
R0 > 10KW. See Figure 4.
+1
+3
%
Deviation from fO = 1/R0 C0
+20
0.05
0.2
+50
ppm/°C See Figure 8.
Power Supply
0.5
%/V
%/V
kHz
Hz
VCC = 12 +1V. See Figure 7.
VCC = + 5V. See Figure 7.
R0 = 8.2KW, C0 = 400pF
R0 = 2MW, C0 = 50mF
Upper Frequency Limit
100
300
Lowest Practical Operating
Frequency
0.01
Timing Resistor, R0 - See
Figure 5
Operating Range
Recommended Range
Loop Phase Dectector Section
Peak Output Current
Output Offset Current
Output Impedance
5
2000
KW
KW
5
See Figure 7 and Figure 8.
Measured at Pin 11
+150
+200
1
+300
mA
mA
MW
V
1
Maximum Swing
+4
+ 5
Referenced to Pin 10
Measured at Pin 3
Quadrature Phase Detector
Peak Output Current
Output Impedance
100
300
1
mA
MW
VPP
Maximum Swing
11
Input Preampt Section
Input Impedance
Measured at Pin 2
20
2
KW
Input Signal
Voltage Required to
Cause Limiting
10
mV rms
Notes
Parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production.
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Rev. 3.01
4
XR-2211
DC ELECTRICAL CHARACTERISTICS (CONT’D)
Test Conditions: VCC = 12V, TA = +25°C, RO = 30KW, CO = 0.033mF, unless otherwise specified.
Parameter
Min.
Typ.
Max.
Unit
Conditions
Voltage Comparator Section
Input Impedance
2
MW
nA
Measured at Pins 3 and 8
Input Bias Current
Voltage Gain
100
70
55
dB
RL = 5.1KW
IC = 3mA
Output Voltage Low
Output Leakage Current
Internal Reference
Voltage Level
300
0.01
500
10
mV
mA
VO = 20V
4.9
5.3
100
80
5.7
V
W
Measured at Pin 10
AC Small Signal
Output Impedance
Maximum Source Current
mA
Notes
Parameters are guaranteed over the recommended operating conditions, but are not 100% tested in production.
Bold face parameters are covered by production test and guaranteed over operating temperature range.
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Input Signal Level . . . . . . . . . . . . . . . . . . . . . . . . 3V rms
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . 900mW
Package Power Dissipation Ratings
CDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 750mW
Derate Above T = 25°C . . . . . . . . . . . . . . . 8mW/°C
A
PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 800mW
Derate Above T = 25°C . . . . . . . . . . . . . . 60mW/°C
A
SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 390mW
Derate Above T = 25°C . . . . . . . . . . . . . . . 5mW/°C
A
SYSTEM DESCRIPTION
The main PLL within the XR-2211 is constructed from an
input preamplifier, analog multiplier used as a phase
detector and a precision voltage controlled oscillator
(VCO). The preamplifier is used as a limiter such that
input signals above typically 10mV rms are amplified to a
constant high level signal. The multiplying-type phase
detector acts as a digital exclusive or gate. Its output
(unfiltered) produces sum and difference frequencies of
the input and the VCO output. The VCO is actually a
current controlled oscillator with its normal input current
(internally connected). When in lock, these frequencies
are f + f
(2 times f when in lock) and f - f
(0Hz
IN VCO
IN
IN VCO
when lock). By adding a capacitor to the phase detector
output, the 2 times f component is reduced, leaving a
IN
DC voltage that represents the phase difference between
the two frequencies. This closes the loop and allows the
VCO to track the input frequency.
The FSK comparator is used to determine if the VCO is
driven above or below the center frequency (FSK
comparator). This will produce both active high and
active low outputs to indicate when the main PLL is in lock
(quadrature phase detector and lock detector
comparator).
(f ) set by a resistor (R ) to ground and its driving current
O
0
with a resistor (R ) from the phase detector.
1
The output of the phase detector produces sum and
difference of the input and the VCO frequencies
Rev. 3.01
5
XR-2211
PRINCIPLES OF OPERATION
Signal Input (Pin 2): Signal is AC coupled to this
terminal. The internal impedance at pin 2 is 20KW.
Recommended input signal level is in the range of 10mV
rms to 3V rms.
10 must be bypassed to ground with a 0.1mF capacitor for
proper operation of the circuit.
Loop Phase Detector Output (Pin 11): This terminal
provides a high impedance output for the loop phase
detector. The PLL loop filter is formed by R and C
connectedtopin11(seeFigure 3.)Withnoinputsignal, or
withnophaseerrorwithinthePLL, theDClevelatpin11is
1
1
Quadrature Phase Detector Output (Pin 3): This is the
high impedance output of quadrature phase detector and
is internally connected to the input of lock detect voltage
comparator. In tone detection applications, pin 3 is
very nearly equal to V . The peak to peak voltage swing
REF
available at the phase detector output is equal to 2 x V
.
REF
connected to ground through a parallel combination of R
D
and C (see Figure 3) to eliminate the chatter at lock
detect outputs. If the tone detect section is not used, pin 3
can be left open.
D
VCO Control Input (Pin 12): VCO free-running
frequency is determined by external timing resistor, R ,
0
connected from this terminal to ground. The VCO
free-running frequency, f , is:
O
Lock Detect Output, Q (Pin 6): The output at pin 6 is at
“low” state when the PLL is out of lock and goes to “high”
state when the PLL is locked. It is an open collector type
1
fO +
Hz
R0·C0
output and requires a pull-up resistor, R , to V
for
L
CC
proper operation. At “low” state, it can sink up to 5mA of
load current.
where C is the timing capacitor across pins 13 and 14.
0
For optimum temperature stability, R must be in the
0
range of 10KW to 100KW (see Figure 9.)
Lock Detect Complement, (Pin 5): The output at pin 5 is
the logic complement of the lock detect output at pin 6.
This output is also an open collector type stage which can
sink 5mA of load current at low or “on” state.
This terminal is a low impedance point, and is internally
biased at a DC level equal to V . The maximum timing
REF
current drawn from pin 12 must be limited to < 3mA for
proper operation of the circuit.
FSK Data Output (Pin 7):Thisoutputisanopencollector
VCO Timing Capacitor (Pins 13 and 14): VCO
frequency is inversely proportional to the external timing
logic stage which requires a pull-up resistor, R , to V for
L
CC
proper operation. It can sink 5mA of load current. When
decoding FSK signals, FSK data output is at “high” or “off”
state for low input frequency, and at “low” or “on” state for
high input frequency. If no input signal is present, the logic
state at pin 7 is indeterminate.
capacitor, C , connected across these terminals (see
0
Figure 6.) C must be non-polar, and in the range of
0
200pF to 10mF.
VCO Frequency Adjustment: VCO can be fine-tuned by
connecting a potentiometer, R , in series with R at pin 12
(see Figure 10.)
X
0
FSK Comparator Input (Pin 8): This is the high
impedance input to the FSK voltage comparator.
Normally, an FSK post-detection or data filter is
connected between this terminal and the PLL phase
VCO Free-Running Frequency, f : XR-2211 does not
O
have a separate VCO output terminal. Instead, the VCO
outputs are internally connected to the phase detector
sections of the circuit. For set-up or adjustment purposes,
the VCO free-running frequency can be tuned by using
the generalized circuit in Figure 3, and applying an
alternating bit pattern of O’s and 1’s at the known mark
detector output (pin 11). This data filter is formed by R
F
and C (see Figure 3.) The threshold voltage of the
F
comparator is set by the internal reference voltage, V
available at pin 10.
,
REF
Reference Voltage, V
(Pin 10): This pin is internally
and space frequencies. By adjusting R , the VCO can
REF
0
biased at the reference voltage level, V :V
REF REF
= V /2
then be tuned to obtain a 50% duty cycle on the FSK
CC
- 650mV. The DC voltage level at this pin forms an internal
reference for the voltage levels at pins 5, 8, 11 and 12. Pin
output (pin 7). This will ensure that the VCO f value is
accuratelyreferencedtothemarkandspacefrequencies.
O
Rev. 3.01
6
XR-2211
Loop
Filter
Data
Filter
FSK
Output
φ
Det
FSK
Comp
φ
VCO
Input
Preamp
φ
Lock Detect
Outputs
φ
Det
Lock Detect
Filter
Lock Detect
Comp
Figure 2. Functional Block Diagram of a Tone and FSK
Decoding System Using XR-2211
V
CC
R
B
R
l
11
R
F
8
Loop
Phase
Detect
7
+
C
C
1
F
FSK
Comp.
10
R
1
2
Internal
Reference
12
Input
VCO
0.1mF
Signal
0.1mF
14
13
R
0
6
C
0
+
LDOQ
LDOQN
Quad
Phase
Detect
5
3
Lock
Detect
Comp.
R
C
D
D
Figure 3. Generalized Circuit Connection for
FSK and Tone Detection
Rev. 3.01
7
XR-2211
DESIGN EQUATIONS
(All resistance in W, all frequency in Hz and all capacitance in farads, unless otherwise specified)
(See Figure 3 for definition of components)
1. VCO Center Frequency, f :
O
1
fO +
R0·C0
2. Internal Reference Voltage, V
(measured at pin 10):
REF
VCC
2
+ ǒ Ǔ–650mV in volts
VREF
3. Loop Low-Pass Filter Time Constant, t:
t + C1·RPP (seconds)
where:
R1·RF
R1 ) RF
+ ǒ Ǔ
RPP
if R is 1 or C reactance is 1, then R = R1
F
F
PP
4. Loop Damping, j:
1250·C0
R1·C1
ǒ Ǔ
z +
Ǹ
Note: For derivation/explanation of this equation, please see TAN-011.
5. Loop-tracking
Df
f0
"+
bandwidth,
R0
R1
Df
f0
+
Tracking
Bandwidth
Df
Df
f
LL
f
1
f
O
f
2
f
LH
Rev. 3.01
8
XR-2211
6. FSK Data filter time constant, tF:
RB · RF
tF +
·CF (seconds)
(
)
RB ) RF
7. Loop phase detector conversion gain, Kd: (Kd is the differential DC voltage across pin 10 and pin11, per unit of
phase error at phase detector input):
VREF · R1
10, 000·p
volt
radian
ƪ ƫ
Kd +
Note: For derivation/explanation of this equation, please see TAN-011.
8. VCO conversion gain, Ko: (Ko is the amount of change in VCO frequency, per unit of DC voltage change at pin 11):
radianńsecond
–2p
+ ǒ
Ǔ
K0 +
volt
VREF ·C0 · R1
9. The filter transfer function:
1
F(s) +
10. Total loop gain. K :
at 0 Hz.
S = Jw and w = 0
1 ) SR1·C1
T
RF
1
ƪ
ƫ
K + K ·K ·F(s) + ǒ
Ǔ
T
O
d
5, 000·C0·(R1 ) RF) seconds
11. Peak detector current I :
A
VREF
20, 000
IA +
(VREF in volts and IA in amps)
Note: For derivation/explanation of this equation, please see TAN-011.
Rev. 3.01
9
XR-2211
APPLICATIONS INFORMATION
FSK Decoding
Figure 10 shows the basic circuit connection for FSK decoding. With reference to Figure 3 and Figure 10, the functions
of external components are defined as follows: R and C set the PLL center frequency, R sets the system bandwidth,
0
0
1
and C sets the loop filter time constant and the loop damping factor. C and R form a one-pole post-detection filter for
1
F
F
the FSK data output. The resistor R from pin 7 to pin 8 introduces positive feedback across the FSK comparator to
B
facilitate rapid transition between output logic states.
Design Instructions:
ThecircuitofFigure 10canbetailoredforanyFSKdecodingapplicationbythechoiceoffivekeycircuitcomponents:R ,
0
R , C , C and C . For a given set of FSK mark and space frequencies, f and f , these parameters can be calculated as
1
0
1
F
O
1
follows:
(All resistance in W’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
a) Calculate PLL center frequency, f :
O
Ǹ
fO + F1·F2
b) ChoosevalueoftimingresistorR , tobeintherangeof10KW to100KW. Thischoiceisarbitrary. Therecommended
0
value is R = 20KW. The final value of R is normally fine-tuned with the series potentiometer, R .
0
0
X
RX
2
RO + RO )
c) Calculate value of C0 from design equation (1) or from Figure 7:
1
CO +
R0 · f0
d) Calculate R1 to give the desired tracking bandwidth (See design equation 5).
R0·f0
R1 +
·2
(f1–f2)
e) Calculate C1 to set loop damping. (See design equation 4):
Normally, j = 0.5 is recommended.
1250·C0
C1 +
R1 · j2
Rev. 3.01
10
XR-2211
f) The input to the XR-2211 may sometimes be too sensitive to noise conditions on the input line. Figure 4 illustrates
a method of de-sensitizing the XR-2211 from such noisy line conditions by the use of a resistor, Rx, connected
from pin 2 to ground. The value of Rx is chosen by the equation and the desired minimum signal threshold level.
VREF
DV
20, 000
ǒ Ǔ
VIN minimum (peak) + Va–Vb + DV " 2.8mV offset + V
or RX + 20, 000
–1
REF (20, 000 ) RX)
V
IN
minimum (peak) input voltage must exceed this value to be detected (equivalent to adjusting V threshold)
V
CC
To Phase
Detector
Va
Vb
Input
2
20K
20K
Rx
10
V
REF
Figure 4. Desensitizing Input Stage
g) Calculate Data Filter Capacitance, C :
F
(
)
RF ) R1 ·RB
Rsum
+
(
)
R1 ) RF ) RB
0.25
(Rsum·Baud Rate
1
CF +
Baud rate in
)
seconds
Note: All values except R0 can be rounded to nearest standard value.
Rev. 3.01
11
XR-2211
20
1.0
0.1
R =5KW
0
15
R =10KW
0
R =5KΩ
0
10
5
R =20KW
0
R =10KΩ
0
R =40KW
0
R =80KW
0
R >100K
0
R =160KW
0
0
0.01
4
6
8
10 12 14 16 18 20 22 24
100
1000
f (HZ)
10000
+
O
Supply Voltage, V (Volts)
Figure 5. Typical Supply Current vs. V+
(Logic Outputs Open Circuited)
Figure 6. VCO Frequency vs. Timing Resistor
1,000
C =0.001mF
0
1.02
f
= 1kHz
O
5
3
1
R = 10R
F
0
5
1.01
C =0.0033mF
0
4
2
1.00
0.99
100
4
C =0.01mF
0
3
C =0.1mF
0
Curve
R
0
2
1
2
3
4
5
5K
10K
0.98
0.97
C =0.0331mF
0
30K
100K
300K
1
C =0.33mF
0
10
4
6
8
10 12 14 16 18
20 22 24
0
1000
10000
V+ (Volts)
f (Hz)
O
Figure 7. VCO Frequency vs. Timing Capacitor
Figure 8. Typical f vs. Power Supply
O
Characteristics
+1.0
1MΩ
R =10K
0
+0.5
0
500K
R =50K
0
50K
10K
R =500K
0
-0.5
-1.0
V+ = 12V
R =1MΩ
0
R = 10 R
0
1
f
= 1 kHz
O
-50
-25
0
25
50
75
100 125
Temperature (°C)
Figure 9. Typical Center Frequency Drift vs. Temperature
Rev. 3.01
12
XR-2211
Design Example:
1200 Baud FSK demodulator with mark and space frequencies of 1200/2200.
Step 1: Calculate f : from design instructions
O
Ǹ
(a) fO + 1200·2200 =1624
Step 2: Calculate R : R =10K with a potentiometer of 10K. (See design instructions (b))
0
0
10
2
ǒ Ǔ + 15K
(b) RT + 10 )
Step 3: Calculate C from design instructions
0
1
(c) CO +
+ 39nF
15000·1624
Step 4: Calculate R : from design instructions
1
20000·1624·2
(d) R1 +
+ 51, 000
)
(
2200–1200
Step 5: Calculate C : from design instructions
1
1250·39nF
(e) C1 +
+ 3.9nF
51000·0.52
Step 6: Calculate R : R should be at least five times R , R = 51,000 5 = 255 KW
F
F
1
F
Step 7: Calculate R : R should be at least five times R , R = 255,000 5 = 1.2 MW
B
B
F
B
Step 8: Calculate R
SUM :
(
)
RF ) R1 ·RB
RSUM
+
+ 240KW
(
)
RF ) R1 ) RB
Step 9: Calculate C
F :
0.25
RSUM·Baud Rate
CF +
+ 1nF
ǒ
Ǔ
Note: All values except R0 can be rounded to nearest standard value.
Rev. 3.01
13
XR-2211
V
CC
R
B
R
L
5.1K
5%
1.8m 5%
Loop
Phase
Detect
11
8
R
178K
5%
F
7
C
Data
C
1
F
1nF
Output
2.7nF
5%
10%
FSK
Comp.
R
1
35.2K
1%
10
Internal
Reference
2
12
Input
Signal
0.1µF
VCO
R
0
0.1µF
13
20K
1%
14
C
O
27nF
5%
VCO
Fine
Tune
Rx
20K
6
LDOQ
LDOQN
+
Quad
Phase
Detect
5
Lock
Detect
Comp.
Figure 10. Circuit Connection for FSK Decoding of Caller Identification Signals
(Bell 202 Format)
V
CC
R
B
R
L
11
8
5.1k
Loop
Phase
Detect
R
F
7
+
C
C
1
F
FSK
Comp.
R
10
1
12
Internal
Reference
2
Input
Signal
VCO
0.1µF
0.1µF
14
13
R
0
C
0
Rx
6
LDOQ
Quad
Phase
Detect
LDOQN
5
3
Lock
Detect
Comp.
R
C
D
D
Between 400K and 600K
Figure 11. External Connectors for FSK Demodulation with Carrier
Detect Capability
Rev. 3.01
14
XR-2211
V
CC
8
Loop
Phase
Detect
11
7
+
C
1
FSK
Comp.
220pF
5%
R
1
200K
10
12
1%
Internal
Reference
2
0.1µF
VCO
R
20K
1%
0.1µF
0
14
13
V
CC
C
50nF
0
Tone
Input
5%
VCO
Fine
Tune
Rx
5K
RL2
5.1K
RL3
5.1K
6 LDOQ
+
Logic Output
Quad
Phase
Detect
5 LDOQN
3
Lock
Detect
Comp.
C
D
R
470K
D
80nF
Figure 12. Circuit Connection for Tone Detection
FSK Decoding with Carrier Detect
The lock detect section of XR-2211 can be used as a
frequency approaches the capture bandwidth.
carrier detect option for FSK decoding.
The
ExcessivelylargevaluesofC willslowtheresponsetime
D
recommended circuit connection for this application is
shown in Figure 11. The open collector lock detect output,
pin 6, is shorted to data output (pin 7). Thus, data output
will be disabled at “low” state, until there is a carrier within
the detection band of the PLL and the pin 6 output goes
“high” to enable the data output.
of the lock detect output. For Caller I.D. applications
choose C = 0.1mF.
D
Tone Detection
Figure 12 shows the generalized circuit connection for
tone detection. The logic outputs, LDOQN and LDOQ at
pins 5 and 6 are normally at “high” and “low” logic states,
respectively. When a tone is present within the detection
band of the PLL, the logic state at these outputs become
reversed for the duration of the input tone. Each logic
output can sink 5mA of load current.
Note: Data Output is “Low” When No Carrier is Present.
The minimum value of the lock detect filter capacitance
C is inversely proportional to the capture range, +Dfc.
D
This is the range of incoming frequencies over which the
loop can acquire lock and is always less than the tracking
range. ItisfurtherlimitedbyC . Formostapplications, Dfc
1
> Df/2. For R = 470KW, the approximate minimum value
D
Both outputs at pins 5 and 6 are open collector type
of C can be determined by:
D
stages, and require external pull-up resistors R and
L2
R , as shown in Figure 12.
L3
16
Df
C in mF and f in Hz.
CD §
With reference to Figure 3 and Figure 12, the functions of
the external circuit components can be explained as
C in mF and f in Hz.
follows: R and C set VCO center frequency; R sets the
0
0
1
With values of C that are too small, chatter can be
detection bandwidth; C sets the low pass-loop filter time
D
1
observed on the lock detect output as an incoming signal
constant and the loop damping factor.
Rev. 3.01
15
XR-2211
Design Instructions:
ThecircuitofFigure 12canbeoptimizedforanytonedetectionapplicationbythechoiceofthe5keycircuitcomponents:
R , R , C , C and C . For a given input, the tone frequency, f , these parameters are calculated as follows:
0
1
0
1
D
S
(All resistance in W’s, all frequency in Hz and all capacitance in farads, unless otherwise specified)
a) Choose value of timing resistor R to be in the range of 10KW to 50KW. This choice is dictated by the max./min.
0
current that the internal voltage reference can deliver. The recommended value is R = 20KW. The final value of R
0
0
is normally fine-tuned with the series potentiometer, R .
X
b) Calculate value of C from design equation (1) or from Figure 7 f = f :
0
S
O
1
R0·fs
CO +
c) Calculate R to set the bandwidth +Df (See design equation 5):
1
R0·f0·2
R1 +
Df
Note: The total detection bandwidth covers the frequency range of fO +Df
d) Calculate value of C for a given loop damping factor:
1
Normally, j = 0.5 is recommended.
1250·C0
C1 +
R1·j2
Increasing C improves the out-of-band signal rejection, but increases the PLL capture time.
1
e) Calculate value of the filter capacitor C . To avoid chatter at the logic output, with R = 470KW, C must be:
D
D
D
16
Df
CD §
C in mF
Increasing C slows down the logic output response time.
D
Design Examples:
Tone detector with a detection band of + 100Hz:
a) Choose value of timing resistor R to be in the range of 10KW to 50KW. This choice is dictated by the max./min.
0
current that the internal voltage reference can deliver. The recommended value is R = 20 KW. The final value of R
0
0
is normally fine-tuned with the series potentiometer, R .
X
b) Calculate value of C from design equation (1) or from Figure 6 f = f :
0
S
O
1
R0·fS
1
C0 +
+
+ 50nF
20, 000·1, 000
Rev. 3.01
16
XR-2211
c) Calculate R to set the bandwidth +Df (See design equation 5):
1
R0·fO·2
20, 000·1, 000·2
100
R1 +
+
+ 400K
Df
Note: The total detection bandwidth covers the frequency range of fO +Df
d) Calculate value of C for a given loop damping factor:
0
Normally, j = 0.5 is recommended.
1250·50·10–9
400, 000·0.52
1250·C0
R1·j2
C1 +
+
+ 6.25pF
Increasing C improves the out-of-band signal rejection, but increases the PLL capture time.
1
e) Calculate value of the filter capacitor C . To avoid chatter at the logic output, with R = 470KW, C must be:
D
D
D
16
Df
16
200
CD +
w
w 80nF
Increasing C slows down the logic output response time.
D
f) Fine tune center frequency with 5KW potentiometer, R .
X
V
+
CC
V
CC
R
F
0.1µF
100K
4
3
2
Loop
Phase
Detect
8
11
1
7
C
+
F
Demodulated
Output
C
1
FSK
Comp
.
Internal
Reference
11 LM324
R
10
1
2
12
0.1µF
VCO
0.1µF
R
0
FM
Input
14
13
6
C
0
LDOQ
LDOQN
+
Quad
Phase
Detect
5
Lock
Detect
Comp.
Figure 13. Linear FM Detector Using XR-2211 and an External Op Amp.
(See Section on Design Equation for Component Values.)
Rev. 3.01
17
XR-2211
Linear FM Detection
XR-2211 can be used as a linear FM detector for a wide
range of analog communications and telemetry
applications. The recommended circuit connection for
this application is shown in Figure 13. The demodulated
output is taken from the loop phase detector output (pin
The FM detector gain, i.e., the output voltage change per
unit of FM deviation can be given as:
R1·VREF
VOUT
+
100·R0
11), through a post-detection filter made up of R and C ,
F
F
and an external buffer amplifier. This buffer amplifier is
necessary because of the high impedance output at pin
11. Normally, a non-inverting unity gain op amp can be
used as a buffer amplifier, as shown in Figure 13.
where VR is the internal reference voltage (V
- 650mV). For the choice of external components R , R ,
= V /2
CC
REF
1
0
C , C and C , see the section on design equations.
D
1
F
+
V
1
REF
20K
20K
Voltage
Output
Input
2
Lock
Detect
Filter
10
B
From
VCO
B’
3
10K
10K
6
Lock Detect
Outputs
5
Internal Voltage
Reference
Input Preamplifier
and Limiter
Quadrature
Phase Detector
Lock Detect
Comparator
2K
2K
A’
8
Timing
Capacitor
A
11
FSK
Comparator
Input
A
Loop
Detector
Output
From
VCO
13
B
14
B’
C
0
7
A’
FSK
Data
Output
12
Timing
8K
R
0
4
Resistor
Ground
Voltage Controlled
Oscillator
Loop Phase Detector
FSK Comparator
Figure 14. Equivalent Schematic Diagram
Rev. 3.01
18
XR-2211
14 LEAD CERAMIC DUAL-IN-LINE
(300 MIL CDIP)
Rev. 1.00
14
1
8
7
E
E
1
D
A
1
Base
A
Plane
Seating
Plane
L
e
c
B
α
B1
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.100
0.015
0.014
0.045
0.008
0.685
0.250
0.200
0.060
0.026
0.065
0.018
0.785
0.310
2.54
0.38
0.36
1.14
0.20
5.08
1.52
0.66
1.65
0.46
19.94
7.87
A
1
B
B1
c
D
E1
E
17.40
6.35
0.300 BSC
0.100 BSC
7.62 BSC
2.54 BSC
e
L
0.125
0.200
3.18
5.08
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 3.01
19
XR-2211
14 LEAD PLASTIC DUAL-IN-LINE
(300 MIL PDIP)
Rev. 1.00
8
7
14
1
E
1
E
D
A
2
A
L
Seating
Plane
C
A
α
1
B
e
A
e
B
B
e
1
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.145
0.015
0.115
0.014
0.030
0.008
0.725
0.300
0.240
0.210
0.070
0.195
0.024
0.070
0.014
0.795
0.325
0.280
3.68
0.38
2.92
0.36
0.76
0.20
5.33
1.78
4.95
0.56
1.78
0.38
20.19
8.26
7.11
A
A
B
B
1
2
1
C
D
E
18.42
7.62
6.10
E
e
1
0.100 BSC
0.300 BSC
2.54 BSC
7.62 BSC
e
A
e
B
L
0.310
0.430
0.160
7.87
10.92
4.06
0.115
2.92
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 3.01
20
XR-2211
14 LEAD SMALL OUTLINE
(150 MIL JEDEC SOIC)
Rev. 1.00
D
14
1
8
7
E
H
C
A
Seating
Plane
α
A
1
e
B
L
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.069
0.010
0.020
0.010
0.344
0.157
MIN
1.35
0.10
0.33
0.19
8.55
3.80
MAX
1.75
0.25
0.51
0.25
8.75
4.00
A
0.053
0.004
0.013
0.007
0.337
0.150
A
B
1
C
D
E
e
0.050 BSC
1.27 BSC
H
L
0.228
0.244
0.050
5.80
0.40
6.20
1.27
0.016
α
0°
8°
0°
8°
Note: The control dimension is the millimeter column
Rev. 3.01
21
XR-2211
Notes
Rev. 3.01
22
XR-2211
Notes
Rev. 3.01
23
XR-2211
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 1995 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 3.01
24
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