XR16C850IP_技术文档

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

APRIL 2002

REV.2.0

FEATURES

GENERAL DESCRIPTION

• Pin-to-pin compatible with the industry standard

ST16C554 and ST16C654 and TI’s TL16C554N

and TL16C754BFN

The XR16C854/854D¹(854) is an enhanced quad

Universal Asynchronous Receiver and Transmitter

(UART) each with 128 bytes of transmit and receive

FIFOs, transmit and receive FIFO counters and trig-

ger levels, automatic hardware and software flow con-

trol, and data rates of up to 2 Mbps. Each UART has

a set of registers that provide the user with operating

status and control, receiver error indications, and mo-

dem serial interface controls. Selectable interrupt po-

larity provides flexibility to meet design require-

ments. An internal loopback capability allows on-

board diagnostics. The 854 is available in 64

pinTQFP, 68 pin PLCC, and 100 pin QFP packages.

The 64 pin package only offers the 16 mode interface,

but the 68 and 100 pin packages offer an additional

68 mode interface which allows easy integration with

Motorola processors. The XR16C854CV (64 pin) of-

fers three state interrupt output while the

XR16C854DV provides continuous interrupt output.

The 100 pin package provides additional FIFO status

outputs (TXRDY# and RXRDY# A-D), separate infra-

red transmit data outputs (IRTX A-D) and channel C

external clock input (CHCCLK). The XR16C854/

854D is compatible with the industry standard

ST16C554/554D and ST16C654/654D.

• Intel or Motorola Data Bus Interface

• Four independent UART channels

• Register Set Compatible to 16C550

• Data rates of up to 2 Mbps

• Transmit and Receive FIFOs of 128 bytes

• Programmable TX and RX FIFO Trigger Levels

• Transmit and Receive FIFO Level Counters

• Automatic Hardware (RTS/CTS) Flow Control

• Selectable Auto RTS Flow Control Hysteresis

• Automatic Software (Xon/Xoff) Flow Control

• Wireless Infrared (IrDA 1.0) Encoder/Decoder

• Full modem interface

• 3.3 V and 5.0 V supply operation

• Sleep Mode (200 uA typical)

• Crystal oscillator or external clock input

APPLICATIONS

• Portable Appliances

• Telecommunication Network Routers

• Ethernet Network Routers

• Cellular Data Devices

NOTE: 1 Covered by U.S. Patent #5,649,122.

• Factory Automation and Process Controls

FIGURE 1. XR16C854 BLOCK DIAGRAM

3.3V or 5V VCC

GND

A2:A0

D7:D0

IOR#

IOW#

CSA#

CSB#

CSC#

UART Channel A

128 Byte TX FIFO

UART

TXA, RXA, IRTXA, DTRA#,

DSRA#, RTSA#, CTSA#,

CDA#, RIA#, OP2A#

Regs

IR

ENDEC

TX & RX

BRG

128 Byte RX FIFO

TXB, RXB, IRTXB, DTRB#,

DSRB#, RTSB#, CTSB#,

CDB#, RIB#, OP2B#

CSD#

INTA

INTB

INTC

UART Channel B

(same as Channel A)

Data Bus

Interface

TXC, RXC, IRTXC, DTRC#,

DSRC#, RTSC#, CTSC#,

CDC#, RIC#, OP2C#

UART Channel C

(same as Channel A)

INTD

TXRDY# A-D

RXRDY# A-D

TXD, RXD, IRTXD, DTRD#,

DSRD#, RTSD#, CTSD#,

CDD#, RID#, OP2D#

UART Channel C

(same as Channel A)

Reset

CHCCLK

16/68#

INTSEL

XTAL1

Crystal Osc/Buffer

XTAL2

854 BLK

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

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REV. 2.0

FIGURE 2. PIN OUT ASSIGNMENT FOR 100-PIN QFP PACKAGES IN 16 AND 68 MODE

TXRDYD#

RXRDYD#

CDD#

RID#

RXD

VCC

INTSEL

D0

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

RXRDYC#

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

CDC#

RIC#

RXC

GND

TXRDY#

RXRDY#

RESET

XR16C854

100-pin QFP

16 Mode

D1

CHCCLK

XTAL2

D2

Connect 16/68# pin to VCC

D3

XTAL1

A0

D4

D5

A1

D6

A2

D7

16/68#

GND

RXA

CLKSEL

RXB

RIA#

CDA#

RXRDYA#

RIB#

CDB#

RXRDYB#

TXRDYD#

RXRDYD#

CDD#

RID#

RXD

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

RXRDYC#

CDC#

RIC#

RXC

GND

VCC

TXRDY#

RXRDY#

RESET#

CHCCLK

GND

D0

XR16C854

100-pin QFP

68 Mode

D1

D2

XTAL2

XTAL1

D3

Connect 16/68# pin to GND

D4

A0

A1

A2

D5

D6

D7

16/68#

GND

RXA

CLKSEL

RXB

RIA#

CDA#

RXRDYA#

RIB#

CDB#

RXRDYB#

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

FIGURE 3. PIN OUT ASSIGNMENT FOR PLCC PACKAGES IN 16 AND 68 MODE AND TQFP PACKAGES

DSRA# 10

60 DSRD#

59 CTSD#

58 DTRD#

57 GND

DSRA# 10

CTSA# 11

DTRA# 12

VCC 13

60 DSRD#

59 CTSD#

58 DTRD#

57 GND

CTSA# 11

DTRA# 12

VCC 13

RTSA# 14

56 RTSD#

RTSA# 14

INTA 15

56 RTSD#

55 INTD

54 CSD#

53 TXD

15

16

55

54

IRQ#

CS#

N.C.

XR16C854

68-pin PLCC

68 Mode

CSA# 16

TXA 17

XR16C854

68-pin PLCC

16 Mode

TXA 17

R/W# 18

TXB 19

53 TXD

52 N.C.

51 TXC

IOW# 18

TXB 19

52 IOR#

51 TXC

(16/68# pin connected to GND)

(16/68# pin connected to VCC)

20

50

A3

A4

CSB# 20

INTB 21

50 CSC#

49 INTC

48 RTSC#

47 VCC

N.C. 21

RTSB# 22

GND 23

49 N.C.

48 RTSC#

47 VCC

RTSB# 22

GND 23

24

DTRB#

46 DTRC#

45 CTSC#

44 DSRC#

DTRB# 24

CTSB# 25

DSRB# 26

46 DTRC#

45 CTSC#

44 DSRC#

CTSB# 25

DSRB# 26

1

2

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

DSRD#

CTSD#

DTRD#

GND

DSRA#

CTSA#

DTRA#

VCC

3

4

RTSA#

INTA

5

RTSD#

INTD

6

XR16C854

CSA#

TXA

7

CSD#

TXD

XR16C854D

64-pin TQFP

16 Mode Only

8

IOR#

IOW#

TXB#

CSB#

INTB

9

TXC

10

11

12

13

14

15

16

CSC#

INTC

RTSC#

VCC

RTSB#

GND

DTRB#

CTSB#

DTRC#

CTSC#

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

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REV. 2.0

ORDERING INFORMATION

PART NUMBER

PACKAGE

OPERATING TEMPERATURE RANGE

XR16C854CJ

XR16C854IJ

68-PLCC

64-TQFP

100-QFP

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

0°C to +70°C

-40°C to +85°C

XR16C854CV

XR16C854IV

XR16C854DCV

XR16C854DIV

XR16C854CQ

XR16C854IQ

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

PIN DESCRIPTIONS

Pin Description

64-TQFP 68-PLCC 100-QFP

NAME

TYPE

DESCRIPTION

PIN #

PIN#

PIN #

DATA BUS INTERFACE

A2

A1

A0

22

23

24

32

33

34

37

38

39

I

Address data lines [2:0]. These 3 address lines select one of the

internal registers in UART channel A-D during a data bus transaction.

D7

D6

D5

D4

D3

D2

D1

D0

60

59

58

57

56

55

54

53

5

4

3

2

1

68

67

66

95

94

93

92

91

90

89

88

I/O Data bus lines [7:0] (bidirectional).

IOR#

(VCC)

40

52

66

I

When 16/68# pin is at logic 1, the Intel bus interface is selected and

this input becomes read strobe (active low). The falling edge insti-

gates an internal read cycle and retrieves the data byte from an inter-

nal register pointed by the address lines [A2:A0], puts the data byte

on the data bus to allow the host processor to read it on the rising

edge.

When 16/68# pin is at logic 0, the Motorola bus interface is selected

and this input is not used and should be connected to VCC.

IOW#

(R/W#)

9

18

15

I

When 16/68# pin is at logic 1, it selects Intel bus interface and this

input becomes write strobe (active low). The falling edge instigates

the internal write cycle and the rising edge transfers the data byte on

the data bus to an internal register pointed by the address lines.

When 16/68# pin is at logic 0, the Motorola bus interface is selected

and this input becomes read (logic 1) and write (logic 0) signal.

Motorola bus interface is not available on the 64 pin package.

CSA#

(CS#)

7

16

20

50

54

13

17

64

68

I

When 16/68# pin is at logic 1, this input is chip select A (active low) to

enable channel A in the device.

When 16/68# pin is at logic 0, this input becomes the chip select

(active low) for the Motorola bus interface.

Motorola bus interface is not available on the 64 pin package.

CSB#

(A3)

11

38

42

When 16/68# pin is at logic 1, this input is chip select B (active low) to

enable channel B in the device.

When 16/68# pin is at logic 0, this input becomes address line A3

which is used for channel selection in the Motorola bus interface.

Motorola bus interface is not available on the 64 pin package.

CSC#

(A4)

When 16/68# pin is at logic 1, this input is chip select C (active low) to

enable channel C in the device.

When 16/68# pin is at logic 0, this input becomes address line A4

which is used for channel selection in the Motorola bus interface.

Motorola bus interface is not available on the 64 pin package.

CSD#

(VCC)

When 16/68# pin is at logic 1, this input is chip select D (active low) to

enable channel D in the device.

When 16/68# pin is at logic 0, this input is not used and should be

connected VCC.

Motorola bus interface is not available on the 64 pin package.

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

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REV. 2.0

Pin Description

64-TQFP 68-PLCC 100-QFP

NAME

TYPE

DESCRIPTION

PIN #

PIN#

PIN #

INTA

6

15

12

O

When 16/68# pin is at logic 1 for Intel bus interface, this ouput

(IRQ#)

(OD) becomes channel A interrupt output.

The output state is defined by

the user and through the software setting of MCR[3]. INTA is set to

the active mode when MCR[3] is set to a logic 1. INTA is set to the

three state mode when MCR[3] is set to a logic 0 (default). See

MCR[3].

When 16/68# pin is at logic 0 for Motorola bus interface, this output

becomes device interrupt output (active low, open drain). An external

pull-up resistor is required for proper operation.

Motorola bus interface is not available on the 64 pin package.

INTB

INTC

INTD

(N.C.)

12

37

43

21

49

55

18

63

69

O

When 16/68# pin is at logic 1 for Intel bus interface, these ouputs

become the interrupt outputs for channels B, C, and D.

The output

state is defined by the user through the software setting of MCR[3].

The interrupt outputs are set to the active mode when MCR[3] is set

to a logic 1 and are set to the three state mode when MCR[3] is set to

a logic 0 (default). See MCR[3].

When 16/68# pin is at logic 0 for Motorola bus interface, these out-

puts are unused and will stay at logic zero level. Leave these outputs

unconnected.

Motorola bus interface is not available on the 64 pin package.

INTSEL

-

65

87

I

Interrupt Select (active high, input with internal pull-down).

When 16/68# pin is at logic 1 for Intel bus interface, this pin can be

used in conjunction with MCR bit-3 to enable or disable the INT A-D

pins or override MCR bit-3 and enable the interrupt outputs. Interrupt

outputs are enabled continuously by making this pin a logic 1. Mak-

ing this pin a logic 0 allows MCR bit-3 to enable and disable the inter-

rupt output pins. In this mode, MCR bit-3 is set to a logic 1 to enable

the continuous output. See MCR bit-3 description for full detail. This

pin must be at logic 0 in the Motorola bus interface mode. Due to pin

limitations on 64 pin packages, this pin is not available. To cover this

limitation, two 64 pin TQFP packages versions are offered. The

XR16C854D operates in the continuous interrupt enable mode by

bonding this pin to VCC internally.

TXRDYA#

TXRDYB#

TXRDYC#

TXRDYD#

-

5

O

UART channels A-D Transmitter Ready (active low). The out-

puts provide the TX FIFO/THR status for transmit channels A-

D. See Table 5 . If these outputs are unused, leave them un-

connected.

25

56

81

RXRDYA#

RXRDYB#

RXRDYC#

RXRDYD#

-

100

31

50

UART channels A-D Receiver Ready (active low). This output pro-

vides the RX FIFO/RHR status for receive channels A-D. See Table 5

. If these outputs are unused, leave them unconnected.

82

TXRDY#

-

39

45

O

Transmitter Ready (active low). This output is a logically wire-ORed

status of TXRDY# A-D. See Table 5 . If this output is unused, leave

it unconnected.

RXRDY#

-

38

44

Receiver Ready (active low). This output is a logically wire-ORed sta-

tus of RXRDY# A-D. See Table 5 . If this output is unused, leave it

unconnected.

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

Pin Description

64-TQFP 68-PLCC 100-QFP

NAME

TYPE

DESCRIPTION

PIN #

PIN#

PIN #

FSRS#

-

76

I

FIFO Status Register Select (active low, input with internal pull-up).

The content of the FSTAT register is placed on the data bus when this

pin becomes active. However it should be noted, D0-D3 contain the

inverted logic states of TXRDY# A-D pins, and D4-D7 the logic states

(un-inverted) of RXRDY# A-D pins. Address line is not required when

reading this status register.

MODEM OR SERIAL I/O INTERFACE

TXA

TXB

TXC

TXD

8

17

19

51

53

14

16

65

67

O

UART channels A-D Transmit Data and infrared transmit data. Stan-

dard transmit and receive interface is enabled when MCR[6] = 0. In

this mode, the TX signal will be a logic 1 during reset, or idle (no

data). Infrared IrDA transmit and receive interface is enabled when

MCR[6] = 1. In the Infrared mode, the inactive state (no data) for the

Infrared encoder/decoder interface is a logic 0.

10

39

41

IRTXA

IRTXB

IRTXC

IRTXD

-

6

UART channel A-D Infrared Transmit Data. The inactive state (no

data) for the Infrared encoder/decoder interface is a logic 0. Regard-

less of the logic state of MCR bit-6, this pin will be operating in the

Infrared mode. Caution, this pin is a logic 1 after power up and prior

to initialization.

24

57

75

RXA

RXB

RXC

RXD

62

20

29

51

7

97

34

47

85

I

UART channel A-D Receive Data or infrared receive data. Normal

receive data input must idle at logic 1 condition. The infrared receiver

pulses typically idles at logic 0 but can be inverted by software con-

trol prior going in to the decoder, see FCTR[2].

29

41

63

RTSA#

RTSB#

RTSC#

RTSD#

5

14

22

48

56

11

19

62

70

O

UART channels A-D Request-to-Send (active low) or general pur-

pose output. This output must be asserted prior to using auto RTS

flow control, see EFR[6], MCR[1], FCTR[1:0], EMSR[5:4] and IER[6].

Also see Figure 11. If these outputs are not used, leave them uncon-

nected.

13

36

44

CTSA#

CTSB#

CTSC#

CTSD#

2

11

25

45

59

8

I

O

I

UART channels A-D Clear-to-Send (active low) or general purpose

input. It can be used for auto CTS flow control, see EFR[7], and

IER[7]. Also see Figure 11. These inputs should be connected to

VCC when not used.

16

33

47

22

59

73

DTRA#

DTRB#

DTRC#

DTRD#

3

12

24

46

58

9

UART channels A-D Data-Terminal-Ready (active low) or general

purpose output. If these outputs are not used, leave them uncon-

nected.

15

34

46

21

60

72

DSRA#

DSRB#

DSRC#

DSRD#

1

10

26

44

60

7

UART channels A-D Data-Set-Ready (active low) or general purpose

input. This input should be connected to VCC when not used. This

input has no effect on the UART.

17

32

48

23

58

74

CDA#

CDB#

CDC#

CDD#

64

18

31

49

9

99

32

49

83

I

UART channels A-D Carrier-Detect (active low) or general purpose

27

43

61

input.

This input should be connected to VCC when not used. This

input has no effect on the UART.

RIA#

RIB#

RIC#

RID#

63

19

30

50

8

98

33

48

84

I

UART channels A-D Ring-Indicator (active low) or general purpose

28

42

62

input.

This input should be connected to VCC when not used. This

input has no effect on the UART.

ANCILLARY SIGNALS

XTAL1 25

35

40

I

Crystal or external clock input.

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

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REV. 2.0

Pin Description

64-TQFP 68-PLCC 100-QFP

NAME

TYPE

DESCRIPTION

PIN #

PIN#

PIN #

XTAL2

16/68#

26

-

36

16

41

13

O

Crystal or buffered clock output.

Intel or Motorola Bus Select (input with internal pull-up).

When 16/68# pin is at logic 1, 16 or Intel Mode, the device will oper-

ate in the Intel bus type of interface.

When 16/68# pin is at logic 0, 68 or Motorola mode, the device will

operate in the Motorola bus type of interface.

Motorola bus interface is not available on the 64 pin package.

CLKSEL

CHCCLK

21

30

35

42

43

I

Baud-Rate-Generator Input Clock Prescaler Select for channels A-D.

This input is only sampled during power up or a reset. Connect to

VCC for divide by 1 (default) and GND for divide by 4. MCR[7] can

override the state of this pin following a reset or initialization. See

MCR bit-7 and Figure 6 in the Baud Rate Generator section.

-

This input provides the clock for UART channel C. An external 16X

baud clock or the crystal oscillator’s output, XTAL2, must be con-

nected to this pin for normal operation. This input may also be used

with MIDI (Musical Instrument Digital Interface) applications when an

external MIDI clock is provided.

RESET

27

37

When 16/68# pin is at logic 1 for Intel bus interface, this ouput

(RESET#)

becomes the

Reset pin (active high). In this case, a 40 ns minimum

logic 1 pulse on this pin will reset the internal registers and all out-

puts. The UART transmitter output will be held at logic 1, the receiver

input will be ignored and outputs are reset during reset period

(Table 18 ). When 16/68# pin is at a logic 0 for Motorola bus inter-

face, this output becomes Reset# pin (active low). This pin functions

similarly, but instead of a logic 1 pulse, a 40 ns minimum logic 0 pulse

will reset the internal registers and outputs.

Motorola bus interface is not available on the 64 pin package.

VCC

GND

N.C.

4, 21, 35, 13, 47, 64 10, 61, 86 Pwr 3.3V or 5V power supply. Please note that the inputs are not 5V toler-

52 ant when operating at 3.3V.

14, 28, 45, 6, 23, 40, 20, 46, 71, Pwr Power supply common, ground.

61

57

96

-

1, 2, 3, 4,

26, 27, 28,

29, 30, 51,

52, 53, 54,

55, 77, 78,

79, 80

No Connection. These pins are not used in either the Intel or Motor-

ola bus modes. These pins are open, but typically, should be con-

nected to GND for good design practice.

Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.

Please note that if the IOR#, IOW# and CS# pins are all asserted (at a logic 0), the 854 will enter a Factory Test Mode.

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

1.0 PRODUCT DESCRIPTION

source of 32 MHz on XTAL1 pin. With a typical crystal

of 14.74128 MHz and through a software option, the

user can set the prescaler bit for data rates of up to

921.6 kbps.

integrates the functions of 4 en-

The XR16C854 (854)

hanced 16C550 Universal Asynchrounous Receiver

and Transmitter (UART). Each UART is independently

controlled having its own set of device configuration Enhanced Features

registers. The configuration registers set is 16550

The rich feature set of the 854 is available through the

UART compatible for control, status and data transfer.

Additionally, each UART channel has 128-bytes of

transmit and receive FIFOs, automatic RTS/CTS

hardware flow control with hysteresis control, auto-

matic Xon/Xoff and special character software flow

control, programmable transmit and receive FIFO

trigger levels, FIFO level counters, infrared encoder

and decoder (IrDA ver 1.0), programmable baud rate

generator with a prescaler of divide by 1 or 4, and da-

ta rate up to 2 Mbps. The XR16C854 can operate at

3.3 or 5 volts. The 854 is fabricated with an advanced

CMOS process.

internal registers. Automatic hardware/software flow

control, selectable transmit and receive FIFO trigger

levels, selectable baud rates, infrared encoder/decod-

er interface, modem interface controls, and a sleep

mode are all standard features. MCR bit-5 provides a

facility for turning off (Xon) software flow control with

any incoming (RX) character. In the 16 mode INT-

SEL and MCR bit-3 can be configured to provide a

software controlled or continuous interrupt capability.

Due to pin limitations for the 64 pin 854 this feature is

offered by two different TQFP packages.

The

XR16C854DCV operates in the continuous interrupt

enable mode by internally bonding INTSEL to VCC.

The XR16C854CV operates in conjunction with MCR

bit-3 by internally bonding INTSEL to GND.

Enhanced FIFO

The 854 QUART provides a solution that supports

128 bytes of transmit and receive FIFO memory, in-

stead of 64 bytes provided in the ST16C654 and 16 The 68 and 100 pin XR16C854 packages offer a

bytes in the ST16C554, or one byte in the clock prescaler select pin to allow system/board de-

ST16C454. The 854 is designed to work with high signers to preset the default baud rate table on power

performance data communication systems, that re- up. The CLKSEL pin selects the div-by-1 or div-by-4

quire fast data processing time. Increased perfor- prescaler for the baud rate generator. It can then be

mance is realized in the 854 by the larger transmit overridden following initializatioin by MCR bit-7.

and receive FIFOs, FIFO trigger level control, FIFO

The 100 pin packages offer several other enhanced

level counters and automatic flow control mecha-

features. These features include a CHCCLK clock in-

nism. This allows the external processor to handle

put, FSTAT register and separate IrDA TX outputs.

more networking tasks within a given time. For exam-

The CHCCLK must be connected to the XTAL2 pin for

ple, the ST16C554 with a 16 byte FIFO, unloads 16

normal operation or to external MIDI (Music Instru-

bytes of receive data in 1.53 ms (This example uses a

ment Digital Interface) oscillator for MIDI applications.

character length of 11 bits, including start/stop bits at

A separate register (FSTAT) is provided for monitoring

115.2Kbps). This means the external CPU will have

the real time status of the FIFO signals TXRDY# and

to service the receive FIFO at 1.53 ms intervals. How-

RXRDY# for each of the four UART channels (A-D).

ever with the 128 byte FIFO in the 854, the data buffer

This reduces polling time involved in accessing indi-

will not require unloading/loading for 12.2 ms. This in-

vidual channels. The 100 pin QFP package also of-

creases the service interval giving the external CPU

fers four separate IrDA (Infrared Data Association

additional time for other applications and reducing the

Standard) TX outputs for Infrared applications. These

overall UART interrupt servicing time. In addition, the

outputs are provided in addition to the standard asyn-

programmable FIFO level trigger interrupt and auto-

chronous modem data outputs.

matic hardware/software flow control is uniquely pro-

2.0 FUNCTIONAL DESCRIPTIONS

2.1 CPU INTERFACE

vided for maximum data throughput performance es-

pecially when operating in a multi-channel system.

The combination of the above greatly reduces the

CPU’s bandwidth requirement, increases perfor-

mance, and reduces power consumption.

The CPU interface is 8 data bits wide with 3 address

lines and control signals to execute data bus read and

write transactions. The 854 data interface supports

the Intel compatible types of CPUs and it is compati-

ble to the industry standard 16C550 UART. No clock

(oscillator nor external clock) is required to operate a

data bus transaction. Each bus cycle is asynchronous

using CS# A-D, IOR# and IOW# or CS#, R/W#, A4

Data Rate

The 854 is capable of operation up to 2 Mbps at 5V

with 16x internal sampling clock rate. The device can

operate with a crystal oscillator of up to 24 MHz crys-

tal on pins XTAL1 and XTAL2, or external clock

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and A3 inputs. All four UART channels share the interconnection for Intel and Motorola mode is shown

same data bus for host operations. A typical data bus in Figure 4.

FIGURE 4. XR16C854/854D TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

VCC

TXA

RXA

DTRA#

RTSA#

CTSA#

DSRA#

CDA#

RIA#

UART

Channel A

Serial Interface of

RS-232

A0

A1

A0

A1

A2

IOR#

IOW#

UART

IOW#

Channel B

Similar

CSA#

CSB#

CSC#

CSD#

UART_CSA#

UART_CSB#

UART_CSC#

UART_CSD#

to Ch A

UART

Channel C

Serial Interface of

RS-232

Similar

to Ch A

UART_INTA

UART_INTB

UART_INTC

UART_INTD

INTA

INTB

INTC

INTD

UART

Channel D

Similar

to Ch A

UART_RESET

VCC

RESET

16/68#

GND

Intel Data Bus (16 Mode) Interconnections

VCC

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

TXA

RXA

DTRA#

RTSA#

CTSA#

DSRA#

CDA#

UART

Channel A

Serial Interface of

RS-232

A0

A1

A2

A0

A1

A2

RIA#

A3

A4

CSB#

CSC#

CSD#

UART

Channel B

VCC

Similar

to Ch A

IOR#

IOW#

R/W#

UART

Channel C

CSA#

INTA

UART_CS#

UART_IRQ#

Similar

to Ch A

Serial Interface of

RS-232

INTB

INTC

INTD

(no connect)

UART

Channel D

Similar

to Ch A

UART_RESET#

RESET#

16/68#

GND

Motorola Data Bus (68 Mode) Interconnections

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3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

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2.2 DEVICE RESET

During Motorola Bus Mode (16/68# pin is connected

to GND), the package interface pins are configured

for connection with Motorola, and other popular mi-

croprocessor bus types. In this mode the 854 de-

codes two additional addresses, A3 and A4, to select

one of the four UART ports. The A3 and A4 address

decode function is used only when in the Motorola

Bus Mode. See Table 2.

The RESET input resets the internal registers and the

serial interface outputs in both channels to their de-

fault state (see Table 18 ). An active high pulse of

longer than 40 ns duration will be required to activate

the reset function in the device. Following a power-on

reset or an external reset, the 854 is software com-

patible with previous generation of UARTs, 16C454

and 16C554 and 16C654.

TABLE 2: CHANNEL A-D SELECT IN 68 MODE

2.3 DEVICE IDENTIFICATION AND REVISION

CS# A4

A3

FUNCTION

The XR16C854 provides a Device Identification code

and a Device Revision code to distinguish the part

from other devices and revisions. To read the identifi-

cation code from the part, it is required to set the

baud rate generator registers DLL and DLM both to

0x00. Now reading the content of the DLM will pro-

vide 0x14 for the XR16C854 and reading the content

of DLL will provide the revision of the part; for exam-

ple, a reading of 0x01 means revision A.

1

0

N/A N/A

UART de-selected

Channel A selected

Channel B selected

Channel C selected

Channel D selected

0

1

0

1

0

1

2.5 CHANNELS A-D INTERNAL REGISTERS

Each UART channel in the 854 has a set of enhanced

registers for control, monitoring and data loading and

unloading. The configuration register set is compati-

ble to those already available in the standard single

16C550. These registers function as data holding

registers (THR/RHR), interrupt status and control reg-

isters (ISR/IER), a FIFO control register (FCR), re-

ceive line status and control registers (LSR/LCR),

modem status and control registers (MSR/MCR), pro-

grammable data rate (clock) divisor registers (DLL/

DLM), and a user accessible scratchpad register

(SPR).

2.4 CHANNEL SELECTION

The UART provides the user with the capability to bi-

directionally transfer information between an external

CPU and an external serial communication device.

During Intel Bus Mode (16/68# pin is connected to

VCC), a logic 0 on chip select pins, CSA#, CSB#,

CSC# or CSD# allows the user to select UART chan-

nel A, B, C or D to configure, send transmit data and/

or unload receive data to/from the UART. Selecting all

four UARTs can be useful during power up initializa-

tion to write to the same internal registers, but do not

attempt to read from all four uarts simultaneously. In-

dividual channel select functions are shown in

Table 1.

Beyond the general 16C550 features and capabilities,

the 854 offers enhanced feature registers (EMSR,

FLVL, EFR, Xon/Xoff 1, Xon/Xoff 2, FCTR, TRG, FC)

that provide automatic RTS and CTS hardware flow

control, Xon/Xoff software flow control, automatic RS-

485 half-duplex direction output enable/disable, FIFO

trigger level control, and FIFO level counters. All the

register functions are discussed in full detail later in

“UART INTERNAL REGISTERS” on page 22.

TABLE 1: CHANNEL A-D SELECT IN 16 MODE

CSA# CSB# CSC# CSD#

FUNCTION

1

0

1

0

1

0

1

0

1

0

1

0

1

0

UART de-selected

Channel A selected

Channel B selected

Channel C selected

Channel D selected

Channels A-D selected

2.6 INT OUPUTS FOR CHANNELS A-D

The interrupt outputs change according to the operat-

ing mode and enhanced features setup. Table 3 and 4

summarize the operating behavior for the transmitter

and receiver. Also see Figure 20 through 25 .

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TABLE 3: INT PINS OPERATION FOR TRANSMITTER FOR CHANNELS A-D

FCTR

Bit-3

FCR BIT-0 = 0

(FIFO DISABLED)

FCR BIT-0 = 1 (FIFO ENABLED)

FCR Bit-3 = 0 FCR Bit-3 = 1

(DMA Mode Disabled)

(DMA Mode Enabled)

0 = a byte in THR

1 = THR empty

INT Pin

0

1

0 = FIFO above trigger level

1 = FIFO below trigger level or FIFO

empty

0 = FIFO above trigger level

1 = FIFO below trigger level or FIFO

empty

0 = a byte in THR

1 = transmitter empty

0 = FIFO above trigger level

1 = FIFO below trigger level or transmit- 1 = FIFO below trigger level or trans-

ter empty mitter empty

0 = FIFO above trigger level

TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D

FCR BIT-0 = 0

(FIFO DISABLED)

FCR BIT-0 = 1 (FIFO ENABLED)

FCR Bit-3 = 0

FCR Bit-3 = 1

(DMA Mode Disabled)

(DMA Mode Enabled)

INT Pin

0 = no data

1 = 1 byte

0 = FIFO below trigger level

1 = FIFO above trigger level

0 = FIFO below trigger level

1 = FIFO above trigger level

2.7 DMA MODE

the transmit and receive FIFO in the DMA mode

(FCR bit-3=1). When the transmit and receive FIFO

are enabled and the DMA mode is disabled (FCR bit-

3 = 0), the 854 is placed in single-character mode for

data transmit or receive operation. When DMA mode

is enabled (FCR bit-3 = 1), the user takes advantage

of block mode operation by loading or unloading the

FIFO in a block sequence determined by the pro-

grammed trigger level. The following table show their

behavior. Also see Figure 20 through 25 .

The device does not support direct memory access.

The DMA Mode (a legacy term) in this document

doesn’t mean “direct memory access” but refers to

data block transfer operation. The DMA mode affects

the state of the RXRDY# A-D and TXRDY# A-D out-

put pins. The transmit and receive FIFO trigger levels

provide additional flexibility to the user for block mode

operation. The LSR bits 5-6 provide an indication

when the transmitter is empty or has an empty loca-

tion(s) for more data. The user can optionally operate

TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D

FCR BIT-0=0

PINS

FCR BIT-0=1 (FIFO ENABLED)

(FIFO DISABLED)

FCR Bit-3 = 0

FCR Bit-3 = 1

(DMA Mode Disabled)

(DMA Mode Enabled)

RXRDY#

TXRDY#

0 = 1 byte

1 = no data

0 = at least 1 byte in FIFO

1 = FIFO empty

1 to 0 transition when FIFO reaches the trigger

level, or timeout occurs.

0 to 1 transition when FIFO empties.

0 = THR empty

1 = byte in THR

0 = FIFO empty

1 = at least 1 byte in FIFO

0 = FIFO has at least 1 empty location.

1 = FIFO is full.

2.8 CRYSTAL OSCILLATOR OR EXT. CLOCK INPUT

a system clock to the Baud Rate Generators (BRG)

section found in each of the UART. XTAL1 is the input

to the oscillator or external clock buffer input with

XTAL2 pin being the output. For programming details,

see “Programmable Baud Rate Generator.”

The 854 includes an on-chip oscillator (XTAL1 and

XTAL2) to produce a clock for both UART sections in

the device. The CPU data bus does not require this

clock for bus operation. The crystal oscillator provides

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3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

FIGURE 5. TYPICAL OSCILLATOR CONNECTIONS

18.432, and 22.1184 MHz. Alternatively, an external

clock can be connected to the XTAL1 pin to clock the

internal baud rate generator for standard or custom

rates. Typical oscillator connections are shown in

Figure 5. For further reading on oscillator circuit

please see application note DAN108 on EXAR’s web

site.

R=300K to 400K

14.7456

M Hz

XTAL2

XTAL1

2.9 PROGRAMMABLE BAUD RATE GENERATOR

Each UART has its own Baud Rate Generator (BRG)

with a prescaler. The prescaler is controlled by a soft-

ware bit in the MCR register. The MCR register bit-7

sets the prescaler to divide the input crystal or exter-

nal clock by 1 or 4. The clock output of the prescaler

goes to the BRG. The BRG further divides this clock

by a programmable divisor between 1 and (2¹⁶-1) to

obtain a 16X sampling rate clock of the serial data

rate. The sampling rate clock is used by the transmit-

ter for data bit shifting and receiver for data sampling.

C1

22-47pF

C2

22-47pF

The on-chip oscillator is designed to use an industry

standard microprocessor crystal (parallel resonant,

fundamental frequency with 10-22 pF capacitance

load, ESR of 20-80 ohms and 100ppm frequency tol-

erance) connected externally between the XTAL1 and

XTAL2 pins (see Figure 5). Typical standard crystal

frequencies are: 1.8432, 3.6864, 7.3728, 14.7456,

FIGURE 6. BAUD RATE GENERATOR AND PRESCALER

DLL and DLM

Registers

M CR Bit-7=0

(default)

Prescaler

Divide by 1

16X

Crystal

O sc/

Buffer

XTAL1

XTAL2

Sam pling

Rate Clock to

Transm itter

Baud Rate

G enerator

Logic

Prescaler

Divide by 4

M CR Bit-7=1

Table 6 shows the standard data rates available with crystal or external clock, the divisor value can be cal-

a 14.7456 MHz crystal or external clock at 16X sam- culated for DLL/DLM with the following equation.

pling rate. When using a non-standard frequency

divisor (decimal) = (XTAL1 clock frequency / prescaler) / (serial data rate x 16)

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TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK

OUTPUT Data Rate OUTPUT Data Rate

DLM

PROGRAM

VALUE (HEX) VALUE (HEX)

DLL

PROGRAM

DIVISOR FOR 16x DIVISOR FOR 16x

Clock (Decimal) Clock (HEX)

DATA RATE

ERROR (%)

MCR Bit-7=1

MCR Bit-7=0

(DEFAULT)

100

600

400

2400

4800

9600

19.2k

38.4k

76.8k

153.6k

230.4k

460.8k

921.6k

2304

384

192

96

48

24

12

6

900

180

C0

60

30

18

0C

06

04

02

01

09

01

00

80

C0

60

30

18

0C

06

04

02

01

0

1200

2400

4800

9600

19.2k

38.4k

57.6k

115.2k

230.4k

4

2

1

2.10 TRANSMITTER

into a serial data stream including start-bit, data bits,

parity-bit and stop-bit(s). The least-significant-bit (Bit-

0) becomes first data bit to go out. The THR is the in-

put register to the transmit FIFO of 128 bytes when

FIFO operation is enabled by FCR bit-0. Every time a

write operation is made to the THR, the FIFO data

pointer is automatically bumped to the next sequential

data location.

The transmitter section comprises of an 8-bit Transmit

Shift Register (TSR) and 128 bytes of FIFO which in-

cludes a byte-wide Transmit Holding Register (THR).

TSR shifts out every data bit with the 16X internal

clock. A bit time is 16 clock periods. The transmitter

sends the start-bit followed by the number of data

bits, inserts the proper parity-bit if enabled, and adds

the stop-bit(s). The status of the FIFO and TSR are

reported in the Line Status Register (LSR bit-5 and

bit-6).

2.10.2 Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at

a time. The THR empty flag (LSR bit-5) is set when

2.10.1 Transmit Holding Register (THR) - Write the data byte is transferred to TSR. THR flag can

Only

generate a transmit empty interrupt (ISR bit-1) when

it is enabled by IER bit-1. The TSR flag (LSR bit-6) is

set when TSR becomes completely empty.

The transmit holding register is an 8-bit register pro-

viding a data interface to the host processor. The host

writes transmit data byte to the THR to be converted

FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE

Transmit

Holding

Register

(THR)

Data

Byte

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

16X

Clock

M

S

B

L

S

B

Transmit Shift Register (TSR)

TXNOFIFO1

2.10.3 Transmitter Operation in FIFO Mode

5) is set whenever the FIFO is empty. The THR empty

flag can generate a transmit empty interrupt (ISR bit-

The host may fill the transmit FIFO with up to 128

bytes of transmit data. The THR empty flag (LSR bit-

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

1) when the FIFO becomes empty. The transmit

empty interrupt is enabled by IER bit-1. The TSR flag

(LSR bit-6) is set when TSR/FIFO becomes empty.

FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE

RX FIFO

THR

Data Byte

THR Interrupt (ISR bit-1) falls

below the programmed Trigger

Level and then when becomes

empty. FIFO is Enabled by FCR

bit-0=1

Auto CTS Flow Control (CTS# pin)

Flow Control Characters

(Xoff1/2 and Xon1/2 Reg.

Auto Software Flow Control

16X Clock

Transmit Data Shift Register

(TSR)

TXFIFO1

2.11 RECEIVER

reaches the FIFO trigger level. Furthermore, data de-

livery to the host is guaranteed by a receive data

ready time-out interrupt when data is not received for

4 word lengths as defined by LCR[1,0] plus 12 bits

time. This is equivalent to 3.7-4.6 character times.

The RHR interrupt is enabled by IER bit-0.

The receiver section contains an 8-bit Receive Shift

Register (RSR) and 128 bytes of FIFO which includes

a byte-wide Receive Holding Register (RHR). The

RSR uses the 16X clock for timing. It verifies and vali-

dates every bit on the incoming character in the mid-

dle of each data bit. On the falling edge of a start or

false start bit, an internal receiver counter starts

counting at the 16X clock rate. After 8 clocks the start

bit period should be at the center of the start bit. At

this time the start bit is sampled and if it is still a logic

0 it is validated. Evaluating the start bit in this manner

prevents the receiver from assembling a false charac-

ter. The rest of the data bits and stop bits are sam-

pled and validated in this same manner to prevent

false framing. If there were any error(s), they are re-

ported in the LSR register bits 2-4. Upon unloading

the receive data byte from RHR, the receive FIFO

pointer is bumped and the error tags are immediately

updated to reflect the status of the data byte in RHR

register. RHR can generate a receive data ready in-

terrupt upon receiving a character or delay until it

2.11.1 Receive Holding Register (RHR) - Read-

Only

The Receive Holding Register is an 8-bit register that

holds a receive data byte from the Receive Shift Reg-

ister. It provides the receive data interface to the host

processor. The RHR register is part of the receive

FIFO of 128 bytes by 11-bits wide, the 3 extra bits are

for the 3 error tags to be reported in LSR register.

When the FIFO is enabled by FCR bit-0, the RHR

contains the first data character received by the FIFO.

After the RHR is read, the next character byte is load-

ed into the RHR and the errors associated with the

current data byte are immediately updated in the LSR

bits 2-4.

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FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE

16X Clock

Receive Data Shift

Data Bit

Register (RSR)

Validation

Receive Data Characters

Error

Tags in

LSR bits

4:2

Receive

Data Byte

and Errors

Receive Data

Holding Register

(RHR)

RHR Interrupt (ISR bit-2)

RXFIFO1

FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE

16X Clock

Receive Data Shift

Register (RSR)

Data Bit

Validation

Receive Data Characters

Example:

- RX FIFO trigger level selected at 16 bytes

(See Note Below)

64 bytes by 11-bit

wide FIFO

RTS# re-asserts when data falls below the flow

Data falls to 8

FIFO Trigger=16

Data fills to 24

control trigger level to restart remote transmitter.

Enable by EFR bit-6=1, MCR bit-1.

Receive

Data FIFO

RHR Interrupt (ISR bit-2) programmed for

desired FIFO trigger level.

FIFO is Enabled by FCR bit-0=1

RTS# de-asserts when data fills above the flow

control trigger level to suspend remote transmitter.

Enable by EFR bit-6=1, MCR bit-1.

Receive

Data

Receive Data

Byte and Errors

RXFIFO1

NOTE: Table-B selected as Trigger Table for Figure 10

(Table 11 ).

- The auto RTS function must be started by asserting

RTS# output pin (MCR bit-1 to logic 1 after it is en-

abled).

2.12 AUTO RTS HARDWARE FLOW CONTROL

- Enable RTS interrupt through IER bit-6 (after setting

EFR bit-4). The UART issues an interrupt when the

RTS# pin makes a transition from low to high: ISR bit-

5 will be set to logic 1.

Automatic RTS hardware flow control is used to pre-

vent data overrun to the local receiver FIFO. The

RTS# output is used to request remote unit to sus-

pend/resume data transmission. The auto RTS flow

control features is enabled to fit specific application

requirement (see Figure 11):

2.13 AUTO RTS HYSTERESIS

The 854 has a new feature that provides flow control

trigger hysteresis while maintaining compatibility with

the XR16C850, ST16C650A and ST16C550 family of

- Enable auto RTS flow control using EFR bit-6.

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3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

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UARTs. With the Auto RTS function enabled, an in-

terrupt is generated when the receive FIFO reaches

the programmed RX trigger level. The RTS# pin will

not be forced to a logic 1 (RTS off), until the receive

FIFO reaches the upper limit of the hysteresis level.

The RTS# pin will return to a logic 0 after the RX

FIFO is unloaded to the lower limit of the hysteresis

level. Under the above described conditions, the 854

2.14 AUTO CTS FLOW CONTROL

Automatic CTS flow control is used to prevent data

overrun to the remote receiver FIFO. The CTS# input

is monitored to suspend/restart the local transmitter.

The auto CTS flow control feature is selected to fit

specific application requirement (see Figure 11):

- Enable auto CTS flow control using EFR bit-7.

will continue to accept data until the receive FIFO - Enable CTS interrupt through IER bit-7 (after setting

gets full. The Auto RTS function is initiated when the EFR bit-4). The UART issues an interrupt when the

RTS# output pin is asserted to a logic 0 (RTS On). CTS# pin is de-asserted (logic 1): ISR bit-5 will be set

Table 15 shows the complete details for the Auto to 1, and UART will suspend transmission as soon as

RTS# Hysteresis levels. Please note that this table is the stop bit of the character in process is shifted out.

for programmable trigger levels only (Table D). The Transmission is resumed after the CTS# input is re-

hysteresis values for Tables A-C are the next higher asserted (logic 0), indicating more data may be sent.

and next lower trigger levels in Tables A-C (See

Table 15 ).

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FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION

Local UART

UARTA

Remote UART

UARTB

RXA

TXB

Receiver FIFO

Trigger Reached

Transmitter

RTSA#

TXA

CTSB#

RXB

Auto RTS

Auto CTS

Monitor

Trigger Level

Receiver FIFO

Trigger Reached

Transmitter

CTSA#

RTSB#

Auto CTS

Monitor

Auto RTS

Trigger Level

Assert RTS# to Begin

Transmission

1

10

ON

RTSA#

OFF

7

2

ON

11

OFF

CTSB#

TXB

8

3

Restart

Data Starts

6

Suspend

9

4

RXA FIFO

Receive

Data

RX FIFO

Trigger Level

RTS High

Threshold

RTS Low

Threshold

5

RX FIFO

Trigger Level

12

INTA

(RXA FIFO

Interrupt)

RTSCTS1

The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of

remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO

(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-

tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA

monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows

(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-

mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),

UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until

next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB

with RTSB# and CTSA# controlling the data flow.

2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL

to the Xon-1,2 character. If a match is found, the 854

will resume operation and clear the flags (ISR bit-4).

When software flow control is enabled (See

Table 17), the 854 compares one or two sequential Reset initially sets the contents of the Xon/Xoff 8-bit

receive data characters with the programmed Xon or flow control registers to a logic 0. Following reset the

Xoff-1,2 character value(s). If receive character(s) user can write any Xon/Xoff value desired for soft-

(RX) match the programmed values, the 854 will halt ware flow control. Different conditions can be set to

transmission (TX) as soon as the current character detect Xon/Xoff characters (See Table 17) and sus-

has completed transmission. When a match occurs, pend/resume transmissions. When double 8-bit Xon/

the Xoff (if enabled via IER bit-5) flag will be set and Xoff characters are selected, the 854 compares two

the interrupt output pin will be activated. Following a consecutive receive characters with two software flow

suspension due to a match of the Xoff character, the control 8-bit values (Xon1, Xon2, Xoff1, Xoff2) and

854 will monitor the receive data stream for a match controls TX transmissions accordingly. Under the

above described flow control mechanisms, flow con-

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3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

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trol characters are not placed (stacked) in the user clear this condition, the 854 will transmit the pro-

accessible RX data buffer or FIFO.

grammed Xon-1,2 characters as soon as receive

FIFO is less than one trigger level below the pro-

grammed trigger level (for Trigger Tables A, B, and C)

or when receive FIFO is less than the trigger level mi-

nus the hysteresis value (for Trigger Table D). This

hysteresis value is the same as the Auto RTS Hyster-

esis value in Table 15. Table 7 below explains this

when Trigger Table-B (See Table 11) is selected.

In the event that the receive buffer is overfilling and

flow control needs to be executed, the 854 automati-

cally sends an Xoff message (when enabled) via the

serial TX output to the remote modem. The 854

sends the Xoff-1,2 characters two-character-times (=

time taken to send two characters at the programmed

baud rate) after the receive FIFO crosses the pro-

grammed trigger level (for all trigger tables A-D). To

TABLE 7: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL

XOFF CHARACTER(S) SENT

(CHARACTERS IN RX FIFO)

XON CHARACTER(S) SENT

(CHARACTERS IN RX FIFO)

RX TRIGGER LEVEL

INT PIN ACTIVATION

8

8*

0

8

16

24

28

16

24

28

16*

24*

28*

16

24

* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2

characters); for example, after 2.083ms has elapsed for 9600 baud and 10-bit word length setting.

2.16 SPECIAL CHARACTER DETECT

2.17 INFRARED MODE

A special character detect feature is provided to de- The 854 UART includes the infrared encoder and de-

tect an 8-bit character when bit-5 is set in the En-

hanced Feature Register (EFR). When this character

coder compatible to the IrDA (Infrared Data Associa-

tion) version 1.0. The IrDA 1.0 standard that stipu-

(Xoff2) is detected, it will be placed in the FIFO along lates the infrared encoder sends out a 3/16 of a bit

with normal incoming RX data.

wide HIGH-pulse for each “0” bit in the transmit data

stream. This signal encoding reduces the on-time of

the infrared LED, hence reduces the power consump-

tion. See Figure 12 below.

The 854 compares each incoming receive character

with Xoff-2 data. If a match exists, the received data

will be transferred to FIFO and ISR bit-4 will be set to

indicate detection of special character. Although the The infrared encoder and decoder are enabled by

Internal Register Table shows Xon, Xoff Registers setting MCR register bit-6 to a ‘1’. When the infrared

with eight bits of character information, the actual feature is enabled, the transmit data output, TX, idles

number of bits is dependent on the programmed word at logic zero level. Likewise, the RX input assumes an

length. Line Control Register (LCR) bits 0-1 defines idle level of logic zero from a reset and power up, see

the number of character bits, i.e., either 5 bits, 6 bits, Figure 12.

7 bits, or 8 bits. The word length selected by LCR bits

Typically, the wireless infrared decoder receives the

0-1 also determines the number of bits that will be

input pulse from the infrared sensing diode on the RX

used for the special character comparison. Bit-0 in

pin. Each time it senses a light pulse, it returns a logic

the Xon, Xoff Registers corresponds with the LSB bit

1 to the data bit stream. However, this is not true with

some infrared modules on the market which indicate

for the receive character.

a logic 0 by a light pulse. So the 854 has a provision

to invert the input polarity to accomodate this. In this

case user can enable FCTR bit-2 to invert the input

signal.

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FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING

Character

Data Bits

1

0

TX Data

Transm it

IR Pulse

(TX Pin)

1/2 Bit Tim e

Bit Tim e

3/16 Bit Tim e

IrEncoder-1

Receive

IR Pulse

(RX pin)

Bit Time

1/16 Clock Delay

1

0

RX Data

Data Bits

Character

IRdecoder-1

2.18 SLEEP MODE WITH AUTO WAKE-UP

turn to the sleep mode automatically after all inter-

rupting condition have been serviced and cleared. In

any case, the sleep mode will not be entered while an

interrupt is pending from any of the channels. The

854 will stay in the sleep mode of operation until it is

disabled by setting IER bit-4 to a logic 0.

The 854 supports low voltage system designs, hence,

a sleep mode is included to reduce its power con-

sumption when the chip is not actively used. With

EFR bit-4 and IER bit-4 of both channels enabled (set

to a logic 1), the 854 DUART enters sleep mode

when no interrupt is pending for both channels. The A word of caution: owing to the starting up delay of

854 stops its crystal oscillator to further conserve the crystal oscillator after waking up from sleep

power in the sleep mode. User can check the XTAL2 mode, the first few receive characters may be lost. Al-

pin for no clock output as an indication that the device so, make sure the RX A-D inputs are idling at logic 1

has entered the sleep mode. The 854 resumes nor- or “marking” condition during sleep mode to avoid re-

mal operation by any of the following: a receive data ceiving a “break” condition upon the restart. This may

start bit transition (logic 1 to 0), a change of logic occur when the extermal interface transceivers (RS-

state on any of the modem or general purpose input 232 or another type) are also put to sleep mode and

pins: CTS#, DSR#, CD#, RI# or a transmit data byte can not maintain the “marking” condition. To avoid

is loaded to the THR/FIFO by the user. If the 854 is this, the system design engineer can use a 47k ohm

awakened by one of the above conditions, it will re- pull-up resistor on the RX A-D pins.

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2.19 INTERNAL LOOPBACK

ister input allowing the system to receive the same

data that it was sending. The TX pin is held at logic 1

or mark condition while RTS# and DTR# are de-as-

serted, and CTS#, DSR# CD# and RI# inputs are ig-

nored. Caution: the RX input must be held to a logic 1

during loopback test else upon exiting the loopback

test the UART may detect and report a false “break”

signal.

The 854 UART provides an internal loopback capabil-

ity for system diagnostic purposes. The internal loop-

back mode is enabled by setting MCR register bit-4 to

logic 1. All regular UART functions operate normally.

Figure 13 shows how the modem port signals are re-

configured. Transmit data from the transmit shift reg-

ister output is internally routed to the receive shift reg-

FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B

VCC

TXA/TXB

Transmit Shift Register

(THR/FIFO)

MCR bit-4=1

Receive Shift Register

(RHR/FIFO)

RXA/RXB

VCC

RTSA#/RTSB#

RTS#

CTS#

VCC

CTSA#/CTSB

DTRA#/DTRB#

DTR#

DSR#

DSRA#/DSRB#

OP1#

RI#

RIA#/RIB#

OP2#

CD#

CDA#/CDB#

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REV. 2.0

3.0 UART INTERNAL REGISTERS

and A2 with a specific channel selected (See Table 1

and Table 2). The complete register set is shown on

Table 8 and Table 9.

Each UART channel in the 854 has its own set of con-

figuration registers selected by address lines A0, A1

TABLE 8: UART CHANNEL A AND B UART INTERNAL REGISTERS

A2,A1,A0 ADDRESSES

REGISTER

READ/WRITE

COMMENTS

16C550 COMPATIBLE REGISTERS

0

0 0

RHR - Receive Holding Register

THR - Transmit Holding Register

Read-only

Write-only

LCR[7] = 0

0

0 0

0 1

0 0

DLL - Div Latch Low Byte

Read/Write

Read-only

LCR[7] = 1, LCR ≠ 0xBF

DLM - Div Latch High Byte

DREV - Device Revision Code

DLL, DLM = 0x00,

LCR[7] = 1, LCR ≠ 0xBF

0

0 1

DVID - Device Identification Code

Read-only

DLL, DLM = 0x00,

LCR[7] = 1, LCR ≠ 0xBF

0

0 1

1 0

IER - Interrupt Enable Register

Read/Write

LCR[7] = 0

ISR - Interrupt Status Register

FCR - FIFO Control Register

Read-only

Write-only

0

1

1 1

0 0

0 1

LCR - Line Control Register

Read/Write

MCR - Modem Control Register

LCR[7] = 0

LSR - Line Status Register

Reserved

Read-only

Write-only

1

1 0

MSR - Modem Status Register

Reserved

Read-only

Write-only

LCR[7] = 0

1

1 1

SPR - Scratch Pad Register

Read/Write

Read-only

Write-only

LCR[7] = 0, FCTR[6] = 0

LCR[7] = 0, FCTR[6] = 1

FLVL - TX/RX FIFO Level Counter Register

EMSR - Enhanced Mode Select Register

ENHANCED REGISTERS

0

0 0

TRG - TX/RX FIFO Trigger Level Reg

FC - TX/RX FIFO Level Counter Register

Write-only

Read-only

LCR = 0xBF

0

1

0 1

1 0

0 0

0 1

1 0

1 1

FCTR - Feature Control Reg

EFR - Enhanced Function Reg

Xon-1 - Xon Character 1

Xon-2 - Xon Character 2

Xoff-1 - Xoff Character 1

Xoff-2 - Xoff Character 2

Read/Write

LCR = 0xBF

X

X X

FSTAT - FIFO Status Register

Read-only

FSRS# pin is logic 0

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.

TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1

ADDRESS

A2-A0

REG

NAME

READ/

WRITE

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

COMMENT

16C550 Compatible Registers

0 0 0

0 0 1

RHR

THR

RD

Bit-7

0/

Bit-6

0/

Bit-5

0/

Bit-4

0/

Bit-3

Bit-2

Bit-1

Bit-0

WR

IER RD/WR

Modem RXLine

Stat. Int.

Enable

TX

Empty

Int

RX

Data

Int.

Stat.

Int.

CTS#

Int.

Enable Enable

RTS#

Int.

Xoff Int. Sleep

Enable

Mode

Enable

Enable Enable Enable

LCR[7] = 0

0 1 0

ISR

RD

FIFOs FIFOs

Enabled Enabled

0/

INT

INT INT INT

Source Source Source Source

Bit-3

INT

Bit-2

Bit-1

Bit-0

Source Source

Bit-5

Bit-4

FCR

WR RXFIFO RXFIFO

Trigger Trigger

0/

DMA

Mode

Enable

TX

RX

FIFOs

FIFO

FIFO Enable

TXFIFO TXFIFO

Trigger Trigger

Reset Reset

0 1 1

1 0 0

LCR RD/WR Divisor Set TX Set Par-

Even

Parity

Enable

Stop

Bits

Word

Length Length

Bit-1 Bit-0

Word

Enable

Break

ity

MCR RD/WR

0/

Internal INT Out- Rsvd

RTS# DTR#

Lopback

Enable

put

Enable

(OP2#)

(OP1#) Output Output

Control Control

BRG

Pres-

caler

IR Mode XonAny

ENable

1 0 1

LSR

RD

RXFIFO THR &

THR

Empty

RX

Break

RX Fram-

ing Error Parity

Error

RX

Over-

run

RX

Data

Ready

LCR[7] = 0

Global

Error

TSR

Empty

Error

1 1 0

1 1 1

MSR

CD#

RI#

DSR#

Input

CTS#

Input

Delta

CD#

Delta

RI#

Delta

DSR# CTS#

Delta

Input

SPR RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1 Bit-0

LCR[7] = 0

FCTR bit-

6=0

1 1 1

EMSR

FLVL

WR

RD

Rsvd

Auto

RTS

Hyst.

bit-3

Auto

RTS

Hyst.

bit-2

Rsvd

Rx/Tx Rx/Tx

FIFO FIFO

Count Count

LCR[7] = 0

FCTR bit-6=1

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

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3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

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TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1

ADDRESS

A2-A0

REG

NAME

READ/

WRITE

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

COMMENT

Baud Rate Generator Divisor

LCR[7] = 1

LCR ≠ 0xBF

0 0 0

0 0 1

0 0 0

0 0 1

DLL RD/WR

DLM RD/WR

Bit-7

0

Bit-6

0

Bit-5

0

Bit-4

1

Bit-3

0

Bit-2

1

Bit-1

0

Bit-0

0

DREV

DVID

RD

LCR[7] = 1

LCR≠0xBF

DLL=0x00

DLM=0x00

Enhanced Registers

0 0 0

0 0 1

TRG

FC

WR

RD

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

FCTR RD/WR RX/TX SCPAD

Trig

Table

Bit-1

Trig

Table

Bit-0

Auto

RX IR

Input

Inv.

Auto

RTS

Hyst

Bit-1

Auto

RTS

Hyst

Bit-0

Mode

Swap

RS485

Direction

Control

Enable

0 1 0

EFR RD/WR

Auto

CTS#

Enable Enable

Auto

RTS#

Special

Char

Select

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

IER [7:4],

ISR [5:4],

FCR[5:4],

MCR[7:5]

LCR=0XBF

Bit-3

Bit-2

Bit-1

Bit-0

1 0 0

1 0 1

1 1 0

1 1 1

XON1 RD/WR

XON2 RD/WR

XOFF1 RD/WR

XOFF2 RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

FSRS# pin is

a logic 0. No

address lines

required.

X X X

FSTAT

RD

RX-

TX-

RDYD# RDYC# RDYB# RDYA#

4.0 INTERNAL REGISTER DESCRIPTIONS

status and modem status registers. These interrupts

are reported in the Interrupt Status Register (ISR).

4.1 RECEIVE HOLDING REGISTER (RHR) - READ-

ONLY

4.3.1 IER versus Receive FIFO Interrupt Mode

Operation

See “Receiver” on page 15..

When the receive FIFO (FCR BIT-0 = 1) and receive

interrupts (IER BIT-0 = 1) are enabled, the RHR inter-

rupts (see ISR bits 2 and 3) status will reflect the fol-

lowing:

4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-

ONLY

See “Transmitter” on page 14..

4.3 INTERRUPT ENABLE REGISTER (IER) - READ/

WRITE

A. The receive data available interrupts are issued

to the host when the FIFO has reached the pro-

grammed trigger level. It will be cleared when the

FIFO drops below the programmed trigger level.

The Interrupt Enable Register (IER) masks the inter-

rupts from receive data ready, transmit empty, line

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3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

B. FIFO level will be reflected in the ISR register ler about the error status of the current data byte in

when the FIFO trigger level is reached. Both the FIFO. These LSR bits generate an interrupt immedi-

ISR register status bit and the interrupt will be ately when the character has been received.

cleared when the FIFO drops below the trigger

level.

• Logic 0 = Disable the receiver line status interrupt

(default).

C. The receive data ready bit (LSR BIT-0) is set as

• Logic 1 = Enable the receiver line status interrupt.

soon as a character is transferred from the shift

IER[3]: Modem Status Interrupt Enable

register to the receive FIFO. It is reset when the

• Logic 0 = Disable the modem status register inter-

rupt (default).

FIFO is empty.

4.3.2 IER versus Receive/Transmit FIFO Polled

Mode Operation

• Logic 1 = Enable the modem status register inter-

rupt.

When FCR BIT-0 equals a logic 1 for FIFO enable; re-

setting IER bits 0-3 enables the XR16C854 in the

IER[4]: Sleep Mode Enable (requires EFR[4] = 1)

FIFO polled mode of operation. Since the receiver • Logic 0 = Disable Sleep Mode (default).

and transmitter have separate bits in the LSR either

or both can be used in the polled mode by selecting

section for further details.

respective transmit or receive control bit(s).

• Logic 1 = Enable Sleep Mode. See Sleep Mode

IER[5]: Xoff Interrupt Enable (requires EFR[4]=1)

A. LSR BIT-0 indicates there is data in RHR or RX

• Logic 0 = Disable the software flow control, receive

FIFO.

Xoff interrupt. (default)

B. LSR BIT-1 indicates an overrun error has oc-

• Logic 1 = Enable the software flow control, receive

curred and that data in the FIFO may not be valid.

Xoff interrupt. See Software Flow Control section

C. LSR BIT 2-4 provides the type of receive data er-

for details.

rors encountered for the data byte in RHR, if any.

IER[6]: RTS# Output Interrupt Enable (requires

EFR[4]=1)

D. LSR BIT-5 indicates THR is empty.

E. LSR BIT-6 indicates when both the transmit FIFO • Logic 0 = Disable the RTS# interrupt (default).

and TSR are empty.

• Logic 1 = Enable the RTS# interrupt. The UART

issues an interrupt when the RTS# pin makes a

transition from low to high.

F. LSR BIT-7 indicates a data error in at least one

character in the RX FIFO.

IER[7]: CTS# Input Interrupt Enable (requires

EFR[4]=1)

IER[0]: RHR Interrupt Enable

The receive data ready interrupt will be issued when

RHR has a data character in the non-FIFO mode or

when the receive FIFO has reached the programmed

trigger level in the FIFO mode.

• Logic 0 = Disable the CTS# interrupt (default).

• Logic 1 = Enable the CTS# interrupt. The UART

issues an interrupt when CTS# pin makes a transi-

tion from low to high.

Logic 0 = Disable the receive data ready interrupt (de-

fault).

4.4 INTERRUPT STATUS REGISTER (ISR) - READ-

ONLY

Logic 1 = Enable the receiver data ready interrupt.

The UART provides multiple levels of prioritized inter-

rupts to minimize external software interaction. The

Interrupt Status Register (ISR) provides the user with

six interrupt status bits. Performing a read cycle on

the ISR will give the user the current highest pending

interrupt level to be serviced, others are queued up to

be serviced next. No other interrupts are acknowl-

edged until the pending interrupt is serviced. The In-

terrupt Source Table, Table 10, shows the data values

(bit 0-5) for the interrupt priority levels and the inter-

rupt sources associated with each of these interrupt

levels.

IER[1]: THR Interrupt Enable

This bit enables the Transmit Ready interrupt which is

issued whenever the THR becomes empty in the non-

FIFO mode or when data in the FIFO falls below the

programmed trigger level in the FIFO mode. If the

THR is empty when this bit is enabled, an interrupt

will be generated.

Logic 0 = Disable Transmit Ready interrupt (default).

Logic 1 = Enable Transmit Ready interrupt.

IER[2]: Receive Line Status Interrupt Enable

If any of the LSR register bits 1, 2, 3 or 4 is a logic 1,

it will generate an interrupt to inform the host control-

4.4.1 Interrupt Generation:

• LSR is by any of the LSR bits 1, 2, 3 and 4.

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REV. 2.0

• RXRDY is by RX trigger level.

4.4.2 Interrupt Clearing:

• LSR interrupt is cleared by a read to the LSR regis-

ter (but flags and tags not cleared until character(s)

that generated the interrupt(s) has been emptied or

cleared from FIFO).

• RXRDY Time-out is by a 4-char plus 12 bits delay

timer.

• TXRDY is by TX trigger level or TX FIFO empty (or

transmitter empty in auto RS-485 control).

• RXRDY interrupt is cleared by reading data until

FIFO falls below the trigger level.

• MSR is by any of the MSR bits 0, 1, 2 and 3.

• Receive Xoff/Special character is by detection of a

Xoff or Special character.

• RXRDY Time-out interrupt is cleared by reading

RHR.

• CTS# is when its transmitter toggles the input pin

(from low to high) during auto CTS flow control

enabled by EFR bit-7.

• TXRDY interrupt is cleared by a read to the ISR

register or writing to THR.

• MSR interrupt is cleared by a read to the MSR reg-

ister.

• RTS# is when its receiver toggles the output pin

(from low to high) during auto RTS flow control

enabled by EFR bit-6.

• Xoff or Special character interrupt is cleared by a

read to ISR.

• RTS# and CTS# flow control interrupts are cleared

by a read to the MSR register.

TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL

PRIORITY

ISR REGISTER STATUS BITS

SOURCE OF INTERRUPT

LEVEL

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

1

2

3

4

5

6

7

-

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LSR (Receiver Line Status Register)

RXRDY (Receive Data Time-out)

RXRDY (Received Data Ready)

TXRDY (Transmit Ready)

MSR (Modem Status Register)

RXRDY (Received Xoff or Special character)

CTS#, RTS# change of state

None (default)

ISR[0]: Interrupt Status

• Logic 0 = An interrupt is pending and the ISR con-

Xon character is received. ISR bit-5 indicates that

CTS# or RTS# has changed state.

tents may be used as a pointer to the appropriate ISR[7:6]: FIFO Enable Status

interrupt service routine.

These bits are set to a logic 0 when the FIFOs are

• Logic 1 = No interrupt pending (default condition).

disabled. They are set to a logic 1 when the FIFOs

are enabled.

ISR[3:1]: Interrupt Status

4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY

These bits indicate the source for a pending interrupt

at interrupt priority levels (See Interrupt Source

Table 10).

This register is used to enable the FIFOs, clear the

FIFOs, set the transmit/receive FIFO trigger levels,

and select the DMA mode. The DMA, and FIFO

modes are defined as follows:

ISR[5:4]: Interrupt Status

These bits are enabled when EFR bit-4 is set to a log-

ic 1. ISR bit-4 indicates that the receiver detected a

data match of the Xoff character(s). Note that once

set to a logic 1, the ISR bit-4 will stay a logic 1 until a

FCR[0]: TX and RX FIFO Enable

• Logic 0 = Disable the transmit and receive FIFO

(default).

26

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3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

• Logic 1 = Enable the transmit and receive FIFOs. FCR[5:4]: Transmit FIFO Trigger Select

This bit must be set to logic 1 when other FCR bits

are written or they will not be programmed.

(logic 0 = default, TX trigger level = one)

These 2 bits set the trigger level for the transmit FIFO.

The UART will issue a transmit interrupt when the

FCR[1]: RX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

number of characters in the FIFO falls below the se-

lected trigger level, or when it gets empty in case that

the FIFO did not get filled over the trigger level on last

re-load. Table 11 below shows the selections. EFR

bit-4 must be set to ‘1’ before these bits can be ac-

cessed. Note that the receiver and the transmitter

cannot use different trigger tables. Whichever selec-

tion is made last applies to both the RX and TX side.

• Logic 0 = No receive FIFO reset (default)

• Logic 1 = Reset the receive FIFO pointers and

FIFO level counter logic (the receive shift register is

not cleared or altered). This bit will return to a logic

0 after resetting the FIFO.

FCR[2]: TX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

• Logic 0 = No transmit FIFO reset (default).

FCR[7:6]: Receive FIFO Trigger Select

(logic 0 = default, RX trigger level =1)

• Logic 1 = Reset the transmit FIFO pointers and

FIFO level counter logic (the transmit shift register

is not cleared or altered). This bit will return to a

logic 0 after resetting the FIFO.

The FCTR Bits 5-4 are associated with these 2 bits.

These 2 bits are used to set the trigger level for the

receive FIFO. The UART will issue a receive interrupt

when the number of the characters in the FIFO cross-

es the trigger level. Table 11 shows the complete se-

lections. Note that the receiver and the transmitter

cannot use different trigger tables. Whichever selec-

tion is made last applies to both the RX and TX side.

FCR[3]: DMA Mode Select

Controls the behavior of the -TXRDY and -RXRDY

pins. See DMA operation section for details.

• Logic 0 = Normal Operation (default).

• Logic 1 = DMA Mode.

TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION

FCTR FCTR

FCR

BIT-7

FCR

BIT-6

FCR

BIT-5

FCR

RECEIVE

TRANSMIT

COMPATIBILITY

BIT-5

BIT-4

BIT-4 TRIGGER LEVEL TRIGGER LEVEL

0

1 (default)

Table-A. 16C550, 16C2550,

16C2552, 16C554, 16C580

compatible.

0

1

0

1

0

1

1 (default)

4

8

14

0

1

0

1

0

1

0

1

0

1

16

8

24

30

Table-B. 16C650A compatible.

0

1

0

1

0

1

8

16

24

28

0

1

0

1

0

1

8

Table-C. 16C654 compatible.

16

32

56

0

1

0

1

0

1

8

16

56

60

X

Programmable Programmable Table-D. 16L2750, 16C2850,

via TRG

register.

via TRG

register.

16C2852, 16C854, 16C864,

16C872 compatible.

FCTR[7] = 0. FCTR[7] = 1.

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4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE

If the parity bit is enabled, LCR BIT-5 selects the

forced parity format.

The Line Control Register is used to specify the asyn-

chronous data communication format. The word or • LCR BIT-5 = logic 0, parity is not forced (default).

character length, the number of stop bits, and the par-

ity are selected by writing the appropriate bits in this

register.

• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity

bit is forced to a logical 1 for the transmit and

receive data.

LCR[1-0]: TX and RX Word Length Select

• LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity

bit is forced to a logical 0 for the transmit and

receive data.

These two bits specify the word length to be transmit-

ted or received.

BIT-1

BIT-0

WORD LENGTH

TABLE 12: PARITY SELECTION

0

1

0

1

0

1

5 (default)

LCR BIT-5 LCR BIT-4 LCR BIT-3

PARITY SELECTION

No parity

6

7

8

X

0

1

X

0

1

0

1

Odd parity

Even parity

Force parity to mark,

“1”

LCR[2]: TX and RX Stop-bit Length Select

The length of stop bit is specified by this bit in con-

junction with the programmed word length.

1

Forced parity to

space, “0”

WORD

LENGTH

STOP BIT LENGTH

(BIT TIME(S))

BIT-2

LCR[6]: Transmit Break Enable

• When enabled, the Break control bit causes a

break condition to be transmitted (the TX output is

forced to a “space’, logic 0, state). This condition

remains, until disabled by setting LCR bit-6 to a

logic 0.

0

1

5,6,7,8

5

1 (default)

1-1/2

2

6,7,8

• Logic 0 = No TX break condition. (default)

LCR[3]: TX and RX Parity Select

• Logic 1 = Forces the transmitter output (TX) to a

“space”, logic 0, for alerting the remote receiver of a

line break condition.

Parity or no parity can be selected via this bit. The

parity bit is a simple way used in communications for

data integrity check. See Table 12 for parity selection

summary below.

LCR[7]: Baud Rate Divisors Enable

Baud rate generator divisor (DLL/DLM) enable.

• Logic 0 = Data registers are selected. (default)

• Logic 1 = Divisor latch registers are selected.

• Logic 0 = No parity.

• Logic 1 = A parity bit is generated during the trans-

mission while the receiver checks for parity error of

the data character received.

4.7 MODEM CONTROL REGISTER (MCR) OR GEN-

ERAL PURPOSE OUTPUTS CONTROL - READ/

WRITE

LCR[4]: TX and RX Parity Select

If the parity bit is enabled with LCR bit-3 set to a logic

1, LCR BIT-4 selects the even or odd parity format.

The MCR register is used for controlling the serial/

modem interface signals or general purpose inputs/

outputs.

• Logic 0 = ODD Parity is generated by forcing an

odd number of logic 1’s in the transmitted character.

The receiver must be programmed to check the

same format (default).

MCR[0]: DTR# Output

The DTR# pin is a modem control output. If the mo-

• Logic 1 = EVEN Parity is generated by forcing an dem interface is not used, this output may be used as

even number of logic 1’s in the transmitted charac- a general purpose output.

ter. The receiver must be programmed to check the

• Logic 0 = Force DTR# output to a logic 1 (default).

same format.

• Logic 1 = Force DTR# output to a logic 0.

LCR[5]: TX and RX Parity Select

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MCR[1]: RTS# Output

MCR[6]: Infrared Encoder/Decoder Enable

The RTS# pin is a modem control output and may be • Logic 0 = Enable the standard modem receive and

used for automatic hardware flow control by enabled

by EFR bit-6. If the modem interface is not used, this

output may be used as a general purpose output.

transmit input/output interface. (Default)

• Logic 1 = Enable infrared IrDA receive and transmit

inputs/outputs. The TX/RX output/input are routed

to the infrared encoder/decoder. The data input and

output levels conform to the IrDA infrared interface

requirement. The RX FIFO may need to be flushed

upon enable. While in this mode, the infrared TX

output will be a logic 0 during idle data conditions.

• Logic 0 = Force RTS# output to a logic 1 (default).

• Logic 1 = Force RTS# output to a logic 0.

MCR[2]: Reserved

OP1# is not available as an output pin on the 854.

But it is available for use during Internal Loopback

Mode. In the Loopback Mode, this bit is used to write

the state of the modem RI# interface signal. If OP1#

output is required for RS485 operation, use the

XR16C864.

MCR[7]: Clock Prescaler Select

• Logic 0 = Divide by one. The input clock from the

crystal or external clock is fed directly to the Pro-

grammable Baud Rate Generator without further

modification, i.e., divide by one (default).

MCR[3]: INT Output Enable

• Logic 1 = Divide by four. The prescaler divides the

input clock from the crystal or external clock by four

and feeds it to the Programmable Baud Rate Gen-

erator, hence, data rates become one forth.

Enable or disable INT outputs to become active or in

three-state. This function is associated with the INT-

SEL input, see below table for details. This bit is also

used to control the OP2# signal during internal loop-

back mode. INTSEL pin must be set to a logic zero

during 68 mode.

4.8 LINE STATUS REGISTER (LSR) - READ ONLY

This register provides the status of data transfers be-

tween the UART and the host. If LSR bits 1-4 are as-

serted, an interrupt will be generated immediately if

IER bit-2 is enabled.

• Logic 0 = INT (A-D) outputs disabled (three state) in

the 16 mode (default). During loopback mode, it

sets OP2# internally to a logic 1.

LSR[0]: Receive Data Ready Indicator

• Logic 1 = INT (A-D) outputs enabled (active) in the

16 mode. During loopback mode, it sets OP2# • Logic 0 = No data in receive holding register or

internally to a logic 0.

FIFO (default).

• Logic 1 = Data has been received and is saved in

TABLE 13: INT OUTPUT MODES

the receive holding register or FIFO.

INTSEL MCR

INT A-D OUTPUTS IN 16 MODE

LSR[1]: Receiver Overrun Flag

BIT-3

• Logic 0 = No overrun error (default).

0

1

X

Three-State

Active

• Logic 1 = Overrun error. A data overrun error condi-

tion occurred in the receive shift register. This hap-

pens when additional data arrives while the FIFO is

full. In this case the previous data in the receive

shift register is overwritten. Note that under this

condition the data byte in the receive shift register

is not transferred into the FIFO, therefore the data

in the FIFO is not corrupted by the error.

0

1

Active

MCR[4]: Internal Loopback Enable

• Logic 0 = Disable loopback mode (default).

• Logic 1 = Enable local loopback mode, see loop-

back section and Figure 13.

LSR[2]: Receive Data Parity Error Tag

• Logic 0 = No parity error (default).

MCR[5]: Xon-Any Enable

• Logic 1 = Parity error. The receive character in RHR

does not have correct parity information and is sus-

pect. This error is associated with the character

available for reading in RHR.

• Logic 0 = Disable Xon-Any function (for 16C550

compatibility, default).

• Logic 1 = Enable Xon-Any function. In this mode,

any RX character received will resume transmit

operation. The RX character will be loaded into the

LSR[3]: Receive Data Framing Error Tag

RX FIFO , unless the RX character is an Xon or • Logic 0 = No framing error (default).

Xoff character and the 854 is programmed to use

the Xon/Xoff flow control.

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• Logic 1 = Framing error. The receive character did • Logic 1 = The DSR# input has changed state since

not have a valid stop bit(s). This error is associated

with the character available for reading in RHR.

the last time it was monitored. A modem status

interrupt will be generated if MSR interrupt is

enabled (IER bit-3).

LSR[4]: Receive Break Tag

MSR[2]: Delta RI# Input Flag

• Logic 0 = No break condition (default).

• Logic 1 = The receiver received a break signal (RX

• Logic 0 = No change on RI# input (default).

was a logic 0 for at least one character frame time). • Logic 1 = The RI# input has changed from a logic 0

In the FIFO mode, only one break character is

loaded into the FIFO. The break indication remains

until the RX input returns to the idle condition,

“mark” or logic 1.

to a logic 1, ending of the ringing signal. A modem

status interrupt will be generated if MSR interrupt is

enabled (IER bit-3).

MSR[3]: Delta CD# Input Flag

LSR[5]: Transmit Holding Register Empty Flag

• Logic 0 = No change on CD# input (default).

This bit is the Transmit Holding Register Empty indi-

cator. The THR bit is set to a logic 1 when the last da-

ta byte is transferred from the transmit holding regis-

ter to the transmit shift register. The bit is reset to log-

ic 0 concurrently with the data loading to the transmit

holding register by the host. In the FIFO mode this bit

is set when the transmit FIFO is empty, it is cleared

when the transmit FIFO contains at least 1 byte.

• Logic 1 = Indicates that the CD# input has changed

state since the last time it was monitored. A modem

status interrupt will be generated if MSR interrupt is

enabled (IER bit-3).

MSR[4]: CTS Input Status

CTS# pin may function as automatic hardware flow

control signal input if it is enabled and selected by Au-

to CTS (EFR bit-7). Auto CTS flow control allows

starting and stopping of local data transmissions

based on the modem CTS# signal. A logic 1 on the

CTS# pin will stop UART transmitter as soon as the

current character has finished transmission, and a

logic 0 will resume data transmission. Normally MSR

bit-4 bit is the compliment of the CTS# input. However

in the loopback mode, this bit is equivalent to the

RTS# bit in the MCR register. The CTS# input may be

used as a general purpose input when the modem in-

terface is not used.

LSR[6]: THR and TSR Empty Flag

This bit is set to a logic 1 whenever the transmitter

goes idle. It is set to logic 0 whenever either the THR

or TSR contains a data character. In the FIFO mode

this bit is set to a logic 1 whenever the transmit FIFO

and transmit shift register are both empty.

LSR[7]: Receive FIFO Data Error Flag

• Logic 0 = No FIFO error (default).

• Logic 1 = A global indicator for the sum of all error

bits in the RX FIFO. At least one parity error, fram-

ing error or break indication is in the FIFO data.

This bit clears when there is no more error(s) in any

of the bytes in the RX FIFO.

MSR[5]: DSR Input Status

DSR# (active high, logical 1). Normally this bit is the

compliment of the DSR# input. In the loopback mode,

this bit is equivalent to the DTR# bit in the MCR regis-

ter. The DSR# input may be used as a general pur-

pose input when the modem interface is not used.

4.9 MODEM STATUS REGISTER (MSR) - READ ONLY

This register provides the current state of the modem

interface input signals. Lower four bits of this register

are used to indicate the changed information. These

bits are set to a logic 1 whenever a signal from the

modem changes state. These bits may be used for

general purpose inputs when they are not used with

modem signals.

MSR[6]: RI Input Status

RI# (active high, logical 1). Normally this bit is the

compliment of the RI# input. In the loopback mode

this bit is equivalent to bit-2 in the MCR register. The

RI# input may be used as a general purpose input

when the modem interface is not used.

MSR[0]: Delta CTS# Input Flag

MSR[7]: CD Input Status

• Logic 0 = No change on CTS# input (default).

CD# (active high, logical 1). Normally this bit is the

compliment of the CD# input. In the loopback mode

this bit is equivalent to bit-3 in the MCR register. The

CD# input may be used as a general purpose input

when the modem interface is not used.

• Logic 1 = The CTS# input has changed state since

the last time it was monitored. A modem status

interrupt will be generated if MSR interrupt is

enabled (IER bit-3).

MSR[1]: Delta DSR# Input Flag

4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE

• Logic 0 = No change on DSR# input (default).

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This is a 8-bit general purpose register for the user to EMSR[5:4]: Extended RTS Hysteresis

store temporary data. The content of this register is

preserved during sleep mode but becomes 0xFF (de-

TABLE 15: AUTO RTS HYSTERESIS

fault) after a reset or a power off-on cycle.

RTS#

HYSTERESIS

(CHARACTERS)

EMSR

BIT-5

EMSR

BIT-4

FCTR

BIT-1

FCTR

BIT-0

4.11 ENHANCED MODE SELECT REGISTER (EMSR)

This register replaces SPR (during a Write) and is ac-

cessible only when FCTR[6] = 1.

0

1

0

1

0

1

0

±4

±6

±8

EMSR[1:0]: Receive/Transmit FIFO Count (Write-

Only)

When Scratchpad Swap (FCTR[6]) is asserted, EM-

SR bits 1-0 controls what mode the FIFO Level

Counter is operating in.

0

1

0

1

0

1

0

1

±8

±16

±24

±32

TABLE 14: SCRATCHPAD SWAP SELECTION

1

0

1

0

1

0

1

±40

±44

±48

±52

FCTR[6] EMSR[1] EMSR[0] Scratchpad is

0

1

X

0

1

X

0

1

0

1

Scratchpad

RX FIFO Counter Mode

TX FIFO Counter Mode

RX FIFO Counter Mode

1

0

1

0

1

0

1

±12

±20

±28

±36

Alternate RX/TX FIFO

Counter Mode

During Alternate RX/TX FIFO Counter Mode, the first EMSR[7:6]: Reserved

value read after EMSR bits 1-0 have been asserted

4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY

will always be the RX FIFO Counter. The second val-

ue read will correspond with the TX FIFO Counter.

The next value will be the RX FIFO Counter again,

then the TX FIFO Counter and so on and so forth.

The FIFO Level Register replaces the Scratchpad

Register (during a Read) when FCTR[6] = 1. Note

that this is not identical to the FIFO Data Count Reg-

ister which can be accessed when LCR = 0xBF.

EMSR[3:2]: Reserved

FLVL[7:0]: FIFO Level Register

This register provides the FIFO counter level for the

RX FIFO or the TX FIFO or both depending on EM-

SR[1:0]. See Table 14 for details.

4.13 BAUD RATE GENERATOR REGISTERS (DLL AND

DLM) - READ/WRITE

The concatenation of the contents of DLM and DLL

gives the 16-bit divisor value which is used to calcu-

late the baud rate:

• Baud Rate = (Clock Frequency / 16) / Divisor

See MCR bit-7 and the baud rate table also.

4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ

ONLY

This register contains the device ID (0x14 for

XR16C854). Prior to reading this register, DLL and

DLM should be set to 0x00.

4.15 DEVICE REVISION REGISTER (DREV) - READ

ONLY

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This register contains the device revision information. FCTR[5:4]: Transmit/Receive Trigger Table Select

For example, 0x01 means revision A. Prior to reading

this register, DLL and DLM should be set to 0x00.

See Table 11 for more details.

TABLE 16: TRIGGER TABLE SELECT

4.16 TRIGGER LEVEL (TRG) - WRITE-ONLY

User Programmable Transmit/Receive Trigger Level

Register.

FCTR

BIT-5

FCTR

BIT-4

TABLE

TRG[7:0]: Trigger Level Register

0

1

0

1

0

1

Table-A (TX/RX)

These bits are used to program desired trigger levels

when trigger Table-D is selected. FCTR bit-7 selects

between programming the RX Trigger Level (a logic

0) and the TX Trigger Level (a logic 1).

Table-B (TX/RX)

Table-C (TX/RX)

Table-D (TX/RX)

4.17 FIFO DATA COUNT REGISTER (FC) - READ-ONLY

This register is accessible when LCR = 0xBF. Note

that this register is not identical to the FIFO Level

Register which is located in the general register set

when FCTR bit-6 = 1.

FCTR[6]: Scratchpad Swap

• Logic 0 = Scratch Pad register is selected as gen-

eral read and write register. ST16C550 compatible

mode.

FC[7:0]: FIFO Data Count Register

• Logic 1 = FIFO Count register (Read-Only),

Enhanced Mode Select Register (Write-Only).

Number of characters in transmit or receive holding

register can be read via scratch pad register when

this bit is set. Enhanced Mode Select Register is

selected when it is written into.

Transmit/Receive FIFO Count. Number of characters

in Transmit (FCTR[7] = 1) or Receive FIFO (FCTR[7]

= 0) can be read via this register.

4.18 FEATURE CONTROL REGISTER (FCTR) - READ/

WRITE

FCTR[7]: Programmable Trigger Register Select

This register controls the XR16C854 new functions

that are not available in ST16C554 or ST16C654.

• Logic 0 = Receive programmable trigger level regis-

ter is selected.

FCTR[1:0]: RTS Hysteresis

• Logic 1 = Transmitter programmable trigger level

register is selected.

User selectable RTS# hysteresis levels for hardware

flow control application. After reset, these bits are set

to “0” to select the next trigger level for hardware flow

control. See Table 15 for more details.

4.19 ENHANCED FEATURE REGISTER (EFR) - READ/

WRITE

Enhanced features are enabled or disabled using this

register. Bit 0-3 provide single or dual consecutive

character software flow control selection (see

Table 17). When the Xon1 and Xon2 and Xoff1 and

Xoff2 modes are selected, the double 8-bit words are

concatenated into two sequential characters. Cau-

tion: note that whenever changing the TX or RX flow

control bits, always reset all bits back to logic 0 (dis-

able) before programming a new setting.

FCTR[2]: IrDa RX Inversion

• Logic 0 = Select RX input as encoded IrDa data

(Idle state will be logic 0).

• Logic 1 = Select RX input as inverted encoded IrDa

data (Idle state will be logic 1).

FCTR[3]: Auto RS-485 Direction Control

The Auto RS-485 Direction Control is not available in

the XR16C854. See XR16C864. However, this bit

changes the TX Ready Interrupt behavior. See

Table 3.

EFR[3:0]: Software Flow Control Select

Single character and dual sequential characters soft-

ware flow control is supported. Combinations of soft-

ware flow control can be selected by programming

these bits.

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TABLE 17: SOFTWARE FLOW CONTROL FUNCTIONS

EFR BIT-3

CONT-3

EFR BIT-2

CONT-2

EFR BIT-1

CONT-1

EFR BIT-0

CONT-0

TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL

0

1

0

1

X

1

0

1

X

0

X

0

X

0

1

No TX and RX flow control (default and reset)

No transmit flow control

Transmit Xon1, Xoff1

Transmit Xon2, Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2

No receive flow control

1

Receiver compares Xon1, Xoff1

Receiver compares Xon2, Xoff2

0

1

Transmit Xon1, Xoff1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

0

1

0

1

0

1

Transmit Xon2, Xoff2

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

No transmit flow control,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

EFR[4]: Enhanced Function Bits Enable

4 will be set to indicate detection of the special

character. Bit-0 corresponds with the LSB bit of the

receive character. If flow control is set for compar-

ing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control

and special character work normally. However, if

flow control is set for comparing Xon2, Xoff2

(EFR[1:0]= ‘01’) then flow control works normally,

but Xoff2 will not go to the FIFO, and will generate

an Xoff interrupt and a special character interrupt, if

enabled via IER bit-5.

Enhanced function control bit. This bit enables IER

bits 4-7, ISR bits 4-5, FCR bits 4-5, and MCR bits 5-7

to be modified. After modifying any enhanced bits,

EFR bit-4 can be set to a logic 0 to latch the new val-

ues. This feature prevents legacy software from alter-

ing or overwriting the enhanced functions once set.

Normally, it is recommended to leave it enabled, logic

1.

• Logic 0 = modification disable/latch enhanced fea-

tures. IER bits 4-7, ISR bits 4-5, FCR bits 4-5, and

MCR bits 5-7 are saved to retain the user settings.

After a reset, the IER bits 4-7, ISR bits 4-5, FCR

bits 4-5, and MCR bits 5-7are set to a logic 0 to be

compatible with ST16C550 mode (default).

EFR[6]: Auto RTS Flow Control Enable

RTS# output may be used for hardware flow control

by setting EFR bit-6 to logic 1. When Auto RTS is se-

lected, an interrupt will be generated when the re-

ceive FIFO is filled to the programmed trigger level

and RTS de-asserts to a logic 1 at the next upper trig-

ger level/hysteresis level. RTS# will return to a logic 0

when FIFO data falls below the next lower trigger lev-

el/hysteresis level. The RTS# output must be assert-

ed (logic 0) before the auto RTS can take effect.

RTS# pin will function as a general purpose output

when hardware flow control is disabled.

• Logic 1 = Enables the above-mentioned register

bits to be modified by the user.

EFR[5]: Special Character Detect Enable

• Logic 0 = Special Character Detect Disabled

(default).

• Logic 1 = Special Character Detect Enabled. The

UART compares each incoming receive character

with data in Xoff-2 register. If a match exists, the

receive data will be transferred to FIFO and ISR bit-

• Logic 0 = Automatic RTS flow control is disabled

(default).

• Logic 1 = Enable Automatic RTS flow control.

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EFR[7]: Auto CTS Flow Control Enable

TABLE 18: UART RESET CONDITIONS FOR

CHANNELS A-D

Automatic CTS Flow Control.

• Logic 0 = Automatic CTS flow control is disabled

REGISTERS

DLL

RESET STATE

Bits 7-0 = 0xXX

(default).

• Logic 1 = Enable Automatic CTS flow control. Data

transmission stops when CTS# input de-asserts to

logic 1. Data transmission resumes when CTS#

returns to a logic 0.

DLM

RHR

THR

Bits 7-0 = 0xXX

Bits 7-0 = 0x00

Bits 7-0 = 0x01

Bits 7-0 = 0x00

Bits 7-0 = 0x60

4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1,

XOFF2, XON1, XON2) - READ/WRITE

IER

FCR

These registers are used as the programmable soft-

ware flow control characters xoff1, xoff2, xon1, and

xon2. For more details, see Table 7 .

ISR

LCR

MCR

LSR

4.21 FIFO STATUS REGISTER (FSTAT) - READ/WRITE

This register is applicable only to the 100 pin QFP

XR16C854. The FIFO Status Register provides a

status indication for each of the transmit and receive

FIFO. These status bits contain the inverted logic

states of the TXRDY# A-D outputs and the (un-invert-

ed) logic states of the RXRDY# A-D outputs. The con-

tents of the FSTAT register are placed on the data bus

when the FSRS# pin (pin 76) is a logic 0. Also see

FSRS# pin description.

MSR

Bits 3-0 = Logic 0

Bits 7-4 = Logic levels of the inputs

inverted

SPR

EMSR

FLVL

Bits 7-0 = 0xFF

Bits 7-0 = 0x00

Bits 7-0 = 0xFF

RESET STATE

Logic 1

TRG

FC

FSTAT[3:0]: TXRDY# A-D Status Bits

FCTR

EFR

Please see Table 5 for the interpretation of the

TXRDY# signals.

XON1

XON2

XOFF1

XOFF2

FSTAT

I/O SIGNALS

TX

FSTAT[7:4]: RXRDY# A-D Status Bits

Please see Table 5 for the interpretation of the

RXRDY# signals.

IRTX

Logic 0

RTS#

Logic 1

DTR#

RXRDY#

TXRDY#

INT

Logic 1

Logic 0

XR16C854 = Three-State Condition

XR16C854D = Logic 0

IRQ#

Logic 1 (68 mode, INTSEL = 0)

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ABSOLUTE MAXIMUM RATINGS

Power Supply Range

Voltage at Any Pin

7 Volts

GND-0.3 V to 7 V

-40^oto +85^oC

Operating Temperature

-65^oto +150^oC

500 mW

Storage Temperature

Package Dissipation

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)

theta-ja = 49^oC/W, theta-jc = 10^oC/W

Thermal Resistance (64-TQFP)

theta-ja = 39^oC/W, theta-jc = 17^oC/W

Thermal Resistance (68-PLCC)

theta-ja = 45^oC/W, theta-jc = 12^oC/W

Thermal Resistance (100-QFP)

ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS

UNLESS OTHERWISE NOTED: TA=0^OTO 70^OC (-40^OTO +85^OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 3.3V,

5.0V ±10%

LIMITS

3.3V

LIMITS

5.0V

SYMBOL

PARAMETER

UNITS

CONDITIONS

MIN

MAX

MIN

MAX

V_ILCK

V_IHCK

V_IL

Clock Input Low Level

Clock Input High Level

Input Low Voltage

-0.3

0.6

VCC

0.8

-0.5

0.6

VCC

0.8

V

2.4

-0.3

2.0

3.0

-0.5

2.2

V

V_IH

Input High Voltage

VCC

0.4

V

V_OL

V_OH

I_IL

Output Low Voltage

Output High Voltage

Input Low Leakage Current

Input High Leakage Current

Input Pin Capacitance

Power Supply Current

Sleep Current

V

I_OL= 6 mA

I_OL= 4 mA

I_OH= -6 mA

I_OH= -1 mA

0.4

V

2.4

V

2.0

V

±10

5

±10

5

uA

pF

mA

uA

I_IH

C_IN

I_CC

3

6

I_SLEEP

100

200

See Test 1

Test 1: The following inputs remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0-D7, IOR#, IOW#,

CSA#, CSB#, CSC#, and CSD#. Also, RXA, RXB, RXC, and RXD inputs idle at logic 1 state while asleep.

35

XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

áç

REV. 2.0

AC ELECTRICAL CHARACTERISTICS

TA=0^OTO 70^OC (-40^OTO +85^OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 3.3- 5.0V ±10%

LIMITS

3.3

LIMITS

5.0

SYMBOL

PARAMETER

UNIT

CONDITIONS

MIN

MAX MIN

MAX

CLK

OSC

T_AS

Clock Pulse Duration

20

15

ns

MHz

ns

Oscillator Frequency

8

24

32

External Clock Frequency

Address Setup Time (16 Mode)

24

10

66

35

40

5

Address Hold Time (16 Mode)

Chip Select Width (16 Mode)

IOR# Strobe Width (16 Mode)

Read Cycle Delay (16 Mode)

Data Access Time (16 Mode)

Data Disable Time (16 Mode)

IOW# Strobe Width (16 Mode)

Write Cycle Delay (16 Mode)

Data Setup Time (16 Mode)

Data Hold Time (16 Mode)

5

ns

T_AH

T_CS

T_RD

T_DY

50

25

30

T_RDV

T_DD

T_WR

T_DY

35

25

15

0

25

30

5

35

40

10

T_DS

T_DH

T_ADS

T_ADH

T_RWS

T_RDA

T_RDH

T_WDS

T_WDH

T_RWH

T_CSL

T_CSD

5

Address Setup (68 Mode)

10

15

10

15

ns

Address Hold (68 Mode)

R/W# Setup to CS# (68 Mode)

Read Data Access (68 mode)

Read Data Hold (68 mode)

10

15

5

15

Write Data Setup (68 mode)

Write Data Hold (68 Mode)

20

10

15

10

CS# De-asserted to R/W# De-asserted (68 Mode)

CS# Strobe Width (68 Mode)

CS# Cycle Delay (68 Mode)

Delay From IOW# To Output

10

40

10

40

70

T_WDO

T_MOD

T_RSI

50

40

1

40

35

1

ns 100 pF load

Bclk

Delay To Set Interrupt From MODEM Input

Delay To Reset Interrupt From IOR#

Delay From Stop To Set Interrupt

T_SSI

36

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

AC ELECTRICAL CHARACTERISTICS

TA=0^OTO 70^OC (-40^OTO +85^OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 3.3- 5.0V ±10%

LIMITS

3.3

LIMITS

5.0

SYMBOL

PARAMETER

UNIT

CONDITIONS

MIN

MAX MIN

MAX

T_RRI

T_SI

Delay From IOR# To Reset Interrupt

Delay From Stop To Interrupt

Delay From Initial INT Reset To Transmit Start

Delay From IOW# To Reset Interrupt

Delay From Stop To Set RXRDY#

Delay From IOR# To Reset RXRDY#

Delay From IOW# To Set TXRDY#

Delay From Center of Start To Reset TXRDY#

Reset Pulse Width

40

ns 100 pF load

45

40

24

40

1

ns

Bclk

ns

T_INT

T_WRI

T_SSR

T_RR

T_WT

T_SRT

T_RST

N

8

24

45

1

8

Bclk

ns

45

8

40

8

ns

Bclk

ns

40

1

40

1

Baud Rate Divisor

-

2

¹⁶-1

2¹⁶-1

Bclk

Baud Clock

16X of data rate

bps

FIGURE 14. CLOCK TIMING

CLK

EXTERNAL

CLOCK

OSC

37

XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

áç

REV. 2.0

FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D

IO W #

IO W

A c tiv e

T _W

D O

R T S #

D T R #

C h a n g e o f s ta te

C D #

C T S #

D S R #

C h a n g e o f s ta te

T _{M O D}

IN T

A c tiv e

T _{R S I}

IO R #

A c tiv e

T _{M O D}

C h a n g e o f s ta te

R I#

FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D

A0-A7

CS#

Valid Address

T_CS

Valid Address

T_CS

T_AS

T_AH

T_DY

T_RD

IOR#

D0-D7

T_DD

T_RDV

Valid Data

RDTm

38

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D

A0-A7

CS#

Valid Address

T_CS

Valid Address

T_CS

T_AS

T_AH

T_DY

T_WR

IOW#

D0-D7

T_DH

T_DS

Valid Data

T_DS

Valid Data

16Write

FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D

A0-A7

CS#

Valid Address

TCSL

Valid Address

TADS

TADH

TCSD

TRWS

TRWH

R/W#

D0-D7

TRDH

TRDA

Valid Data

68Read

39

XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

áç

REV. 2.0

FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D

A0-A7

CS#

Valid Address

TCSL

Valid Address

TADS

TADH

TCSD

TRWS

TRWH

R/W#

D0-D7

T

WDH

TWDS

Valid Data

68Write

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D

RX

Stop

Bit

Start

Bit

D0:D7

T_SSR

1 Byte

in RHR

INT

T_SSR

Active

Data

Active

Data

Active

Data

RXRDY#

Ready

T_RR

IOR#

(Reading data

out of RHR)

RXNFM

40

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D

TX

(Unloading)

Stop

Bit

Start

Bit

D0:D7

IER[1]

enabled

ISR is read

INT*

T_WRI

T_SRT

TXRDY#

T_WT

IOW#

(Loading data

into THR)

*INT is cleared when the ISR is read or when data is loaded into the THR.

TXNonFIFO

FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D

Start

Bit

RX

S

T

D0:D7

S

T

S

D0:D7

T

D0:D7

T_SSI

D0:D7

T

D0:D7

Stop

Bit

RX FIFO drops

below RX

Trigger Level

INT

T_SSR

FIFO

Empties

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

RXRDY#

First Byte is

Received in

RX FIFO

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXINTDMA#

41

XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

áç

REV. 2.0

FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D

Start

Bit

Stop

Bit

RX

S

T

D0:D7

T

S

T

S

T

D0:D7

T_SSI

D0:D7

RX FIFO drops

below RX

Trigger Level

INT

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

T_SSR

FIFO

Empties

RXRDY#

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXFIFODMA

FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX FIFO

Empty

TX

(Unloading)

T

S

T

D0:D7

T

S

D0:D7

T

D0:D7

T

D0:D7

T

D0:D7

S

D0:D7

T

ISR is read

T_SI

IER[1]

enabled

ISR is read

T_SRT

INT*

TX FIFO

Empty

TX FIFO fills up

to trigger level

TX FIFO drops

below trigger level

T_WRI

Data in

TX FIFO

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT is cleared when the ISR is read or when TX FIFO fills up to the trigger level.

TXDMA#

42

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX

(Unloading)

S

D0:D7

S

D0:D7

S

D0:D7

T

D0:D7

S

D0:D7

T

S D0:D7

T

IER[1]

enabled

ISR Read

T_SI

T_SRT

INT*

TX FIFO fills up

to trigger level

TX FIFO drops

below trigger level

T_WRI

At least 1

empty location

in FIFO

TX FIFO

Full

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT cleared when the ISR is read or when TX FIFO fills up to trigger level.

TXDMA

43

XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

áç

REV. 2.0

PACKAGE DIMENSIONS

64 LEAD THIN QUAD FLAT PACK (10 x 10 x 1.4 mm TQFP)

D

D₁

48

33

49

32

D₁

D

64

17

1

16

B

A₂

e

C

A

α

Seating Plane

A₁

L

Note: The control dimension is the millimeter column

INCHES

MAX

MILLIMETERS

SYMBOL

MIN

MAX

1.60

0.15

1.45

0.27

0.20

12.20

10.10

A

A1

A2

B

0.055

0.002

0.053

0.007

0.004

0.465

0.390

0.063

0.006

0.057

0.011

0.008

0.480

0.398

1.40

0.05

1.35

0.17

0.09

11.80

9.90

C

D

D1

e

0.020 BSC

0.50 BSC

L

0.018

0.030

0.45

0.75

α

0°

7°

0°

7°

44

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

68 LEAD PLASTIC LEADED CHIP CARRIER (PLCC)

D

C

Seating Plane

D₁

°

45 x H₁

A₂

45° x H₂

2

1

68

B₁

B

D₃

D₂

D

D₁

e

R

D₃

A₁

A

Note: The control dimension is the inch column

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

0.200

0.130

MIN

MAX

5.08

3.30

A

0.165

0.090

4.19

2.29

A

1

A

0.020

0.013

0.026

0.008

0.985

0.950

---.

0.51

0.33

---

2

B

0.021

0.032

0.013

0.995

0.958

0.53

0.81

0.32

25.27

24.33

B

0.66

1

C

D

0.19

25.02

24.13

D

1

D

0.890

0.930

22.61

23.62

2

D

0.800 typ.

0.050 BSC

0.042

20.32 typ.

1.27 BSC

3

e

H

0.056

0.048

0.045

1.07

0.64

1.42

1.22

1.14

1

H

0.042

0.025

2

R

45

XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

áç

REV. 2.0

100 LEAD PLASTIC QUAD FLAT PACK (14 mm x 20 mm QFP, 1.95 mm Form)

D

D₁

80

51

81

50

E₁

E

100

31

p

1

30

B

A₂

e

C

A

α

Seating Plane

A₁

L

Note: The control dimension is the millimeter column

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

0.134

0.014

MIN

MAX

3.40

0.35

A

0.102

0.002

2.60

0.05

A

1

A

0.100

0.009

0.004

0.931

0.783

0.695

0.547

0.120

0.015

0.009

0.951

0.791

0.715

0.555

2.55

0.22

3.05

0.38

0.23

2

B

C

D

0.11

23.65

19.90

17.65

13.90

24.15

20.10

18.15

14.10

D

1

E

1

e

L

α

0.0256 BSC

0.65 BSC

0.029

0°

0.040

0.73

1.03

7°

0°

7°

46

áç

XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

REVISION HISTORY

Date

November 1999 Rev 1.0

April 2002 Rev 2.0

Revision

Description

Removed Preliminary designation.

Changed to standard style format. Text descriptions were clarified and

simplified (eg. DMA operation, FIFO mode vs. Non-FIFO mode opera-

tions etc). Corrected RTS Hysteresis character values in Table 15 . Clar-

ified timing diagrams. Renamed Rclk (Receive Clock) to Bclk (Baud

Clock) and timing symbols. Added T_CS, T_RWSand T_RST

.

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order

to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of

any circuits described herein, conveys no license under any patent or other right, and makes no represen-

tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for

illustration purposes and may vary depending upon a user’s specific application. While the information in

this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where

the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys-

tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-

tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury

or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-

ration is adequately protected under the circumstances.

Datasheet April 2002.

Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

47

XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

áç

REV. 2.0

TABLE OF CONTENTS

GENERAL DESCRIPTION .................................................................................................1

FEATURES...................................................................................................................................................1

APPLICATIONS .............................................................................................................................................1

FIGURE 1. XR16C854 BLOCK DIAGRAM .................................................................................................................................................. 1

FIGURE 2. PIN OUT ASSIGNMENT FOR 100-PIN QFP PACKAGES IN 16 AND 68 MODE ............................................................................... 2

FIGURE 3. PIN OUT ASSIGNMENT FOR PLCC PACKAGES IN 16 AND 68 MODE AND TQFP PACKAGES....................................................... 3

ORDERING INFORMATION ..............................................................................................................................4

PIN DESCRIPTIONS .........................................................................................................5

1.0 Product DESCRIPTION ........................................................................................................... 9

2.0 FUNCTIONAL DESCRIPTIONS .............................................................................................. 9

2.1 CPU INTERFACE ................................................................................................................................. 9

FIGURE 4. XR16C854/854D TYPICAL INTEL/MOTOROLA DATA BUS INTERCONNECTIONS ........................................................................ 10

2.2 DEVICE RESET .................................................................................................................................. 11

2.3 DEVICE IDENTIFICATION AND REVISION ............................................................................................... 11

2.4 CHANNEL SELECTION ......................................................................................................................... 11

TABLE 1: CHANNEL A-D SELECT IN 16 MODE......................................................................................................................................... 11

2.5 CHANNELS A-D INTERNAL REGISTERS ................................................................................................ 11

2.6 INT OUPUTS FOR CHANNELS A-D ...................................................................................................... 11

TABLE 2: CHANNEL A-D SELECT IN 68 MODE......................................................................................................................................... 11

TABLE 3: INT PINS OPERATION FOR TRANSMITTER FOR CHANNELS A-D................................................................................................. 12

TABLE 4: INT PIN OPERATION FOR RECEIVER FOR CHANNELS A-D ........................................................................................................ 12

2.7 DMA MODE ...................................................................................................................................... 12

TABLE 5: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE FOR CHANNELS A-D................................................................... 12

2.8 CRYSTAL OSCILLATOR OR EXT. CLOCK INPUT .................................................................................... 12

FIGURE 5. TYPICAL OSCILLATOR CONNECTIONS ...................................................................................................................................... 13

2.9 PROGRAMMABLE BAUD RATE GENERATOR ......................................................................................... 13

FIGURE 6. BAUD RATE GENERATOR AND PRESCALER............................................................................................................................. 13

TABLE 6: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK.............................................................................. 14

2.10 TRANSMITTER .................................................................................................................................. 14

2.10.1 Transmit Holding Register (THR) - Write Only ....................................................................................... 14

2.10.2 Transmitter Operation in non-FIFO Mode .............................................................................................. 14

FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE...................................................................................................................... 14

2.10.3 Transmitter Operation in FIFO Mode...................................................................................................... 14

FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE............................................................................................. 15

2.11 RECEIVER ....................................................................................................................................... 15

2.11.1 Receive Holding Register (RHR) - Read-Only ....................................................................................... 15

FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE ........................................................................................................................... 16

FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE............................................................................... 16

2.12 AUTO RTS HARDWARE FLOW CONTROL .......................................................................................... 16

2.13 AUTO RTS HYSTERESIS ................................................................................................................. 16

2.14 AUTO CTS FLOW CONTROL ............................................................................................................ 17

FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION .............................................................................................................. 18

2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................ 18

TABLE 7: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL....................................................................................................................... 19

2.16 SPECIAL CHARACTER DETECT ........................................................................................................ 19

2.17 INFRARED MODE ............................................................................................................................. 19

FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING ................................................................................. 20

2.18 SLEEP MODE WITH AUTO WAKE-UP ................................................................................................ 20

2.19 INTERNAL LOOPBACK ...................................................................................................................... 21

FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B........................................................................................................................ 21

3.0 UART INTERNAL REGISTERS ............................................................................................. 22

TABLE 8: UART CHANNEL A AND B UART INTERNAL REGISTERS............................................................................................. 22

TABLE 9: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1 ................................................ 23

4.0 INTERNAL Register descriptions ........................................................................................ 24

4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ........................................................................... 24

4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ......................................................................... 24

I

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XR16C854/XR16C854D

3.3V AND 5V QUAD UART WITH 128-BYTE FIFO

REV.2.0

4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE .......................................................................... 24

4.3.1 IER versus Receive FIFO Interrupt Mode Operation ............................................................................... 24

4.3.2 IER versus Receive/Transmit FIFO Polled Mode Operation.................................................................... 25

4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................ 25

4.4.1 Interrupt Generation: ................................................................................................................................ 25

4.4.2 Interrupt Clearing: .................................................................................................................................... 26

TABLE 10: INTERRUPT SOURCE AND PRIORITY LEVEL............................................................................................................................. 26

4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ............................................................................... 26

TABLE 11: TRANSMIT AND RECEIVE FIFO TRIGGER LEVEL SELECTION ................................................................................................... 27

4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ................................................................................ 28

4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE ....... 28

TABLE 12: PARITY SELECTION................................................................................................................................................................ 28

TABLE 13: INT OUTPUT MODES ............................................................................................................................................................ 29

4.8 LINE STATUS REGISTER (LSR) - READ ONLY ..................................................................................... 29

4.9 MODEM STATUS REGISTER (MSR) - READ ONLY ............................................................................... 30

4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE ............................................................................... 30

4.11 ENHANCED MODE SELECT REGISTER (EMSR) ................................................................................. 31

TABLE 14: SCRATCHPAD SWAP SELECTION............................................................................................................................................ 31

4.12 FIFO LEVEL REGISTER (FLVL) - READ-ONLY .................................................................................. 31

4.13 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 31

4.14 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY ................................................................. 31

4.15 DEVICE REVISION REGISTER (DREV) - READ ONLY ......................................................................... 31

TABLE 15: AUTO RTS HYSTERESIS ....................................................................................................................................................... 31

4.16 TRIGGER LEVEL (TRG) - WRITE-ONLY ............................................................................................ 32

4.17 FIFO DATA COUNT REGISTER (FC) - READ-ONLY ........................................................................... 32

4.18 FEATURE CONTROL REGISTER (FCTR) - READ/WRITE .................................................................... 32

4.19 ENHANCED FEATURE REGISTER (EFR) - READ/WRITE ..................................................................... 32

TABLE 16: TRIGGER TABLE SELECT....................................................................................................................................................... 32

TABLE 17: SOFTWARE FLOW CONTROL FUNCTIONS ............................................................................................................................... 33

4.20 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ............... 34

4.21 FIFO STATUS REGISTER (FSTAT) - READ/WRITE ........................................................................... 34

TABLE 18: UART RESET CONDITIONS FOR CHANNELS A-D......................................................................................................... 34

ABSOLUTE MAXIMUM RATINGS .................................................................................. 35

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)35

ELECTRICAL CHARACTERISTICS................................................................................ 35

DC ELECTRICAL CHARACTERISTICS ........................................................................................................... 35

AC ELECTRICAL CHARACTERISTICS ........................................................................................................... 36

TA=0O TO 70OC (-40O TO +85OC FOR INDUSTRIAL GRADE PACKAGE), VCC IS 3.3- 5.0V ±10%................. 36

FIGURE 14. CLOCK TIMING .................................................................................................................................................................... 37

FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A-D............................................................................................................ 38

FIGURE 16. 16 MODE (INTEL) DATA BUS READ TIMING FOR CHANNELS A-D........................................................................................... 38

FIGURE 17. 16 MODE (INTEL) DATA BUS WRITE TIMING FOR CHANNELS A-D ......................................................................................... 39

FIGURE 18. 68 MODE (MOTOROLA) DATA BUS READ TIMING FOR CHANNELS A-D .................................................................................. 39

FIGURE 19. 68 MODE (MOTOROLA) DATA BUS WRITE TIMING FOR CHANNELS A-D................................................................................. 40

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D.................................................................... 40

FIGURE 21. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A-D.................................................................. 41

FIGURE 22. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A-D .................................................. 41

FIGURE 23. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A-D................................................... 42

FIGURE 24. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A-D...................................... 42

FIGURE 25. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A-D....................................... 43

PACKAGE DIMENSIONS.............................................................................................................................. 44

REVISION HISTORY.................................................................................................................................... 47

TABLE OF CONTENTS ................................................................................................................................. I

II


型号：	XR16C850IP
厂家：	ETC
描述：	UART\|CMOS\|DIP\|40PIN\|PLASTIC 外围集成电路光电二极管数据传输通信时钟
文件：	总49页 (文件大小：651K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XR16C850IP [ETC]

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