ZIOL2212_技术文档

Data Sheet

Rev. 2.2.1 / January 2012

ZIOL2xxx IC Family

IO-Link compliant HV Line Driver IC Family

Data Sheet

January 31, 2012

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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ZIOL2xxx – IC Family

IO-Link compliant HV Line Driver IC Family

Contents

1 The ZIOL2xxx IC Family Overview .......................................................................................6

2 Electrical Characteristics ......................................................................................................7

2.1. Absolute Maximum Ratings ............................................................................................7

2.2. Operating Conditions ......................................................................................................8

2.3. Electrical Parameters......................................................................................................9

3 Detailed Description............................................................................................................15

3.1. Block schematic ............................................................................................................15

3.2. Dual Channel Transceiver.............................................................................................16

3.2.1. IC Data Path Configuration......................................................................................16

3.2.2. Transmitter ..............................................................................................................20

3.2.3. Receiver ..................................................................................................................22

3.3. System Control .............................................................................................................24

3.3.1. General....................................................................................................................24

3.3.2. IO-Link Master and Device Mode ............................................................................25

3.3.3. Internal Exceptions ..................................................................................................25

3.3.4. IO-Link specific Wake-Up (WURQ)..........................................................................25

3.3.5. IC Self-Protection – Lock Mode ...............................................................................27

3.3.6. Channel Locking in Master/Device Mode ................................................................29

3.3.7. Memory Unit ............................................................................................................29

3.3.8. Serial Peripheral Interface (SPI) ..............................................................................31

3.3.9. Register Table / Registers for IC Configuration and Monitoring...............................36

3.3.10.Interrupt and IC Lock Mode Control.........................................................................46

3.3.11.Die Temperature Measurement...............................................................................54

3.4. Smart Power Supply .....................................................................................................54

3.5. The Power Fail Detector ...............................................................................................56

3.5.1. Overview..................................................................................................................56

3.5.2. Line-Fault Detector ..................................................................................................56

3.5.3. Under-voltage Detector............................................................................................57

3.5.4. Channel Locking and Interrupt Generation..............................................................57

3.5.5. Downward Compatibility ..........................................................................................57

Data Sheet

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3.6. DC/DC Converter..........................................................................................................57

3.6.1. Principle of Operation ..............................................................................................57

3.6.2. Principle of Operation ..............................................................................................58

3.6.3. Dimensioning of external Devices............................................................................59

3.6.4. PCB Layout considerations .....................................................................................61

4 Application Information .......................................................................................................63

5 Pin Configuration, Latch-Up and ESD Protection ...............................................................68

5.1. Pin Configuration and Latch-up Conditions...................................................................68

5.2. ESD-Protection .............................................................................................................69

6 Package..............................................................................................................................70

6.1. Pin Hardware Configurations ........................................................................................70

6.2. Pin Diagram ..................................................................................................................70

6.3. Optimal PCB Layout......................................................................................................71

6.4. Package Outline............................................................................................................72

6.5. Device Marking .............................................................................................................73

7 Ordering Information...........................................................................................................74

8 Related Documents............................................................................................................75

9 Glossary .............................................................................................................................76

9.1. Terms and Abbreviations ..............................................................................................76

9.2. Symbols used in this Datasheet....................................................................................76

10 Document Revision History ................................................................................................78

Appendix A

ZIOL2xxx Diagnostic Techniques .....................................................................80

A.1. General Remarks..........................................................................................................80

A.2. Overload Counter Behavior and Peak Register Access................................................80

A.3. Overload Counter and Lock Reset Methods .................................................................84

Appendix B

ZIOL2xxx Configuration Techniques.................................................................87

Appendix C ZIOL2xxx Line Fail Detector .............................................................................89

Data Sheet

January 31, 2012

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List of Figures

Figure 2.1 Max. Total Power Dissipation ................................................................................................................7

Figure 2.2 Efficiency of the DC/DC converter for VOUT=5V, C=10µF and L=10µH............................................14

Figure 3.1 Functional Block Diagram of the ZIOL2xxx .........................................................................................15

Figure 3.2 ZIOL24xx Transceiver Data Path in Principle......................................................................................16

Figure 3.3 ZIOL22xx Transceiver Data Path in Principle......................................................................................17

Figure 3.4 ZIOL21xx Transceiver Data Path in Principle......................................................................................18

Figure 3.5 ZIOL24xx in Device and Master Mode Application..............................................................................21

Figure 3.6 Typical IO-Link Device Configuration with HS driver only ...................................................................24

Figure 3.7 Wake-Up Signal Recognition...............................................................................................................26

Figure 3.8 The Basic Scheme of the IC Self Protection .......................................................................................28

Figure 3.9 Memory Unit.........................................................................................................................................30

Figure 3.10 General timing of a byte transfer .........................................................................................................32

Figure 3.11 Structure of SPI accesses ...................................................................................................................33

Figure 3.12 SPI Command Structure......................................................................................................................34

Figure 3.13 SPI Timing ...........................................................................................................................................36

Figure 3.14 Interrupt (INT_L pin) and Wake-up (WURQ_L pin) Signaling .............................................................47

Figure 3.15 COM Channel Lock Control.................................................................................................................49

Figure 3.16 AUX Channel Lock Control..................................................................................................................50

Figure 3.17 Over-Temperature Lock Control..........................................................................................................51

Figure 3.18 Internal IC Sensors and related Overload and Over-Temperature Detection Circuits........................53

Figure 3.19 Low Voltage Supply Concept...............................................................................................................55

Figure 3.20 PFD Working Principle.........................................................................................................................56

Figure 3.21 DC/DC Converter in Principle..............................................................................................................58

Figure 3.22 DC/DC Converter Output Voltage as Function of R1 (R2 = 10kOhms) ..............................................60

Figure 3.23 High frequency critical loops of DC/DC converter for PCB layout.......................................................61

Figure 3.24 PCB layout of Evaluation board as an example ..................................................................................62

Figure 4.1 Simplified Application Circuit with the ZIOL2xxx in Device Mode .......................................................63

Figure 4.2 Simplified Application Circuit with the ZIOL2xxx in Master Mode .......................................................64

Figure 4.3 Power Line Fail Detection....................................................................................................................65

Figure 4.4 PCB Layout Recommendations...........................................................................................................66

Figure 6.1 Pin Diagram of the ZIOL2xxx...............................................................................................................71

Figure 6.2 Package Dimensions...........................................................................................................................72

Figure 6.3 Top Marking of the ZIOL2xxx ..............................................................................................................73

Figure 9.1 Register Representation in Principle (Example)..................................................................................77

Figure 10.1 Peak Register Access Scenarios.........................................................................................................81

Figure 10.2 Overload Counter Behavior in permanent Over-Current Situations....................................................82

Figure 10.3 Overload Counter Behavior in permanent Over-Temperature Situations ...........................................83

Figure 10.4 Overload Counter Behavior in typical Over-Temperature Situations ..................................................84

Figure 10.5 Partial Reset of Overload Counter or the entire Lock circuit ...............................................................85

Data Sheet

January 31, 2012

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Figure 10.6 Configuration Checker Report of the ZIOL2xxx Application Kit (Example) .........................................87

List of Tables

Table 1.1

Table 2.1

Table 2.2

Table 2.3

Table 3.1

Table 3.2

Table 3.3

Table 3.4

Table 3.5

Table 3.6

Table 3.7

Table 3.8

Table 3.9

Table 4.1

Table 5.1

Table 6.1

Table 6.2

ZIOL2xxx Product Matrix and Product Naming Convention..................................................................6

Absolute Maximum Ratings...................................................................................................................7

Operating Conditions.............................................................................................................................8

Electrical Characteristics .......................................................................................................................9

Master-Device-Mode Function Table...................................................................................................19

Driver configurations............................................................................................................................22

Receiver configurations .......................................................................................................................23

Sink Mode Configuration in Detail .......................................................................................................24

Example for building the SHIFT Byte...................................................................................................34

Valid Address and Length Combinations ............................................................................................34

Register Table......................................................................................................................................37

Temperature Sensor Levels ................................................................................................................54

Examples for the resistors R1 and R2 using E96 resistor series ........................................................59

Recommended External Components.................................................................................................67

Pin Configuration and Latch-Up Conditions ........................................................................................68

Availability of Pin Interconnections ......................................................................................................70

Package Dimensions in mm ................................................................................................................72

Table 10.1 Abnormal Power Supply Situations .....................................................................................................89

Data Sheet

January 31, 2012

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ZIOL2xxx – IC Family

IO-Link compliant HV Line Driver IC Family

1 The ZIOL2xxx IC Family Overview

ZMDI provides a universal and IO-Link compatible cable driver IC by issuing the ZIOL2401 integrated circuit. The

ZIOL2401 is highly configurable and suitable for a wide range of applications in process and factory automation.

In order to fulfill the requirements of specific applications stripped down versions of the IC were required. The

ZIOL2xxx IC family is derived from the ZIOL2401 by modification (elimination or disabling) of certain functional

building blocks. In this combination the following building blocks or functions are affected:



The transceiver channels COM and AUX

The availability of the integrated DC/DC converter

The activation of a read-only data access via the SPI interface

This datasheet describes the entire IC family ZIOL2xxx. Respective notes or footnotes describe the availability the

above mentioned building blocks or functionality with respect to certain IC family members. Table 1.1 shows an

overview concerning the ZIOL2xxx IC family and the used naming convention.

Table 1.1 ZIOL2xxx Product Matrix and Product Naming Convention

ZIOL2xxx

Member

Transceiver

Channel

COM + AUX

DC/DC

Converter

yes

SPI

Access

r/w

Remarks

Base type - released

ZIOL2401

ZIOL2201

ZIOL2101

ZIOL2411

ZIOL2211

ZIOL2111

ZIOL2402

ZIOL2202

ZIOL2102

ZIOL2412

ZIOL2212

ZIOL2112

COM

AUX

yes

no

r/w

r

released

1)

COM + AUX

COM

released

no

released

1)

AUX

no

1)

COM + AUX

COM

yes

no

r

AUX

r

COM + AUX

COM

r

no

r

AUX

no

r

1)

For future product releases, please contact ZMDI's sales representative

Data Sheet

January 31, 2012

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changes without notice.

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2 Electrical Characteristics

2.1.

Absolute Maximum Ratings

Parameters apply in operation temperature range and without time limitations.

Table 2.1 Absolute Maximum Ratings

Symbol

V_{DD_HV}

V_HV

Parameter

Min

Max

Unit

Conditions

Supply voltage

-0.3

40

V

Voltage at HV pins

-0.3

60

V

_{DD_HV}+0.3

V

2)

Voltage at LV pins

V

_{DD_LV}+0.3

V_LV

Impulse voltage withstand

Abs. ESD test voltage

V

V_imp

V_ESD

T_s

according to IEC 60947-5-2

2k

V

according to HBM

1)

125

150

2.6

°C

W

Junction temperature

-50

T_a

Storage temperature

P_tot

Average total power dissipation

integration period < 10ms ³⁾

1)

2)

Average die-temperature.

Exceptions are the digital input pins (µC

interface) which tolerate 5V logic signals (refer

to Table 5.1).

Figure 2.1 Max. Total Power Dissipation

3)

3

2,5

2

The allowed total power dissipation depends

on the in the PCB design achieved thermal

resistance R_th(package/ambient) and the

ambient operation temperature as shown in

Figure 2.1. In order to obtain optimal heat

distribution (R_th< 35K/W) certain PCB layout

rules shall be applied. Those rules are

described in the application note for the used

QFN package (refer to chapter 8, [4]).

Rth = 35K/W

1,5

Rth = 45K/W

1

0,5

0

-40

-20

0

20

40

60

80

T_amb/°C

Data Sheet

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2.2.

Operating Conditions

Table 2.2 Operating Conditions

Symbol

Parameter

Min Typ¹⁾Max

Unit

Conditions

V_{DD_HV}

V_in

Supply voltage

8.0

24

36

V

Linear regulator input voltage

4.75

LR_IN can be connected to V_{DD_HV}or

DC/DC output voltage.

V_{DD_LV}

I_out

Linear regulator output voltage

Linear regulator output current

3.0

3.3

3.6

10

V

Voltage LR_OUT  GND pin

mA

LR_OUT provides supply current for

external applications. ²⁾

t_startup

Startup timing @ V_{DD_HV}= 8V

5

ms

Time for system start up including

loading of configuration registers

from EEPROM

T_amb

f_osc

Operating ambient temperature

Internal oscillator frequency

-40

4.5

+85

5.5

°C

MHz

Internal clock is not available

externally. All digital circuit timing

parameters of the IC are derived

from the internal clock.

1)

2)

The mentioned typical values of IC properties are provided for information only.

While start-up (until the voltage at LR_OUT has reached 1V) the output current may be limited to 5mA.

Data Sheet

January 31, 2012

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2.3.

Electrical Parameters

All parameter values are valid under operating conditions specified in chapter 2.2 if no other conditions are

mentioned.

Table 2.3 Electrical Characteristics

Symbol

Parameter

Min Typ¹⁾Max

Unit

Conditions

Transmitter Output Stages (COM¹/AUX²)

I_{DAL_0}

I_{DAL_1}

I_{DAL_2}

I_{DAL_3}

I_{MAL_0}

I_{MAL_1}

I_{MAL_2}

I_{MAL_3}

I_{Dout_0}

I_{Dout_1}

I_{Dout_2}

I_{Dout_3}

I_{Mout_0}

I_{Mout_1}

I_{Mout_2}

I_{Mout_3}

Alarm level threshold

50

I_{Dout_0}

I_{Dout_1}

I_{Dout_2}

I_{Dout_3}

I_{Mout_0}

I_{Mout_1}

I_{Mout_2}

I_{Mout_3}

95

mA

Dual mode

corresponding to configurable

output current limitation ²⁾

100

200

250

100

200

400

500

The active setting is defined in

the configuration registers

Dual Driver Mode

Alarm level threshold

Tandem mode

corresponding to configurable

output current limitation ²⁾

The active setting is defined in

the configuration registers.

Tandem Driver Mode

Configurable output current limit²⁾56

Dual mode

112

180

Dual Driver Mode

The active setting is defined in

the configuration registers.

224

280

330

410

Configurable output current limit²⁾112

180

Tandem mode

224

360

Tandem Driver Mode

The active setting is defined in

the configuration registers.

448

560

660

820

14⁵⁾

80⁵⁾

V/µs

referring to IO-Link Spec.:

38,4kBaud (COM2),

SR₃₈

6

10

60

Slew rate ³⁾

SR₂₃₀

40

referring to IO-Link Spec.:

230.4kBaud (COM3)

Time from LV L-H edge till HV

edge begins to rise (COM3 baud

rate)

t_TLHdelayCOM3

Propagation delay L-H edge

Propagation delay H-L edge

250

ns

Time from LV H-L edge till HV

edge begins to fall (COM3 baud

rate)

t_THLdelayCOM3

¹The COM transmitter is only available inside the products ZIOL24xx/22xx

²The AUX transmitter is only available inside the products ZIOL24xx/21xx

Data Sheet

January 31, 2012

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Symbol

Parameter

Min Typ¹⁾Max

Unit

Conditions

Time from LV L-H edge till HV

edge begins to rise (COM2 baud

rate)

t_TLHdelayCOM2

Propagation delay L-H edge

700

ns

Time from LV H-L edge till HV

edge begins to fall (COM2 baud

rate)

t_THLdelayCOM2

Propagation delay H-L edge

700

ns

Receiver Input Channels (COM³/AUX⁴)

V_ih1

V_il1

IO-Link specific threshold, High

IO-Link specific threshold, Low

10.75

8.75

1.5

12.75

10.75

2.5

V

V_ihyst1

IO-Link specific thresholds,

Hysteresis

V_ih2

V_il2

Ratiometric threshold, High

52

43

7

57

%V_{DD_HV}

Ratiometric threshold, Low

47.7

11.6

V_ihyst2

Ratiometric thresholds,

Hysteresis

R_in

C_in

Input resistance

150

kOhms

pF

Input capacitance

20

No filter within signal path.

Input edge with:

>30V/µs (COM3)

>5V/µs (COM2)

>0.75V/µs (COM1)

t_Rdelay

Propagation delay without

filtering

80

100

200

ns

t_FRdelay

Propagation delay with analog

filtering

750

850

950

ns

@V_{DD_HV}= 24V, Input edge

with:

>30V/µs (COM3)

t_Rpulse

t_FRpulse

t_DIGdelay

f_cut

Minimal propagated pulse width

without filtering

25

ns

µs

Minimal propagated pulse width

with analog filtering

1.1

Additional propagation delay with 180

digital filtering

440

250

ns

Input filter – cut off frequency

(-3dB) COM and AUX channel

100

kHz

filter characteristic: 1^storder

Line input voltage >5V

I_sink1

I_sink2

Sink strength 1

2

5

2.5

6

3

7

mA

Sink strength 2

According to IO-Link

Specification

R_pull

Configurable pull-up/pull-down

resistor @ COM_O/AUX_O

100k

250k

Ohms

³The COM receiver is only available inside the products ZIOL24xx/22xx

⁴The AUX receiver is only available inside the products ZIOL24xx/21xx

Data Sheet

January 31, 2012

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Symbol

Parameter

Min Typ¹⁾Max

Unit

Conditions

WURQ Detection

t_wurqL

Lower pulse width limit of signal

evaluated as IO-Link wake-up

60

85

68

94

75

µs

Refer to chapter 3.3.4

t_wurqU

Upper pulse width limit of signal

evaluated as IO-Link wake-up

109

5

DC/DC converter

V_OUT

Output voltage Range⁶⁾

3

15

50

V

mA

MHz

V

@ V_{DD_HV}> V_out+ 2V

(step down function only)

I_LOAD

I_PK

Output load current

5⁴⁾

Current that flows to the

application and the R-Divider

Over current limit for output

transistor

240

Averaged current over complete

short at DCDC converter output

f_osc

Operating frequency

2.25

2.75

V_ref

Reference/feedback Voltage

DC Output Line Regulation

DC Output Load Regulation

1.225

8

at FB pin in steady state

ΔV_{OUT_Line}

ΔV_{OUT_Load}

mV/V

@V_out=5V, I_LOAD= 5mA

Filter: C=10µF, L=10µH

mV/mA Filter: C=10µF, L=10µH

_OUT= 5V

V

@Vout=3.3V 0.7

@Vout=15V 3.3

1.4

6.9

V_ripple

Ripple of Output Voltage

@ VDD_HV >= 24V

@ VDD_HV < 24V

Settling time after POR is

mV_PP

Filter: C=10µF, L=10µH

_OUT= 5V

65⁷⁾

25⁷⁾

1

V

t_strt

t_DLY

η

ms

%

For C=10µF, L=10µH

Higher C may result in higher t_strt

released

digital delay for DC_RDY signal

45

50

55

If enabled in configuration

8)

Efficiency

Filter: C=10µF, L=10µH

⁵The DC/DC converter is only available inside the products ZIOL2401/2402/2201/2202/2101/2102

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

Data Sheet

January 31, 2012

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Symbol

Parameter

Min Typ¹⁾Max

Unit

Conditions

Microcontroller Interface ⁹⁾

V_LIH

V_LIL

Voltage range for input ”high”

level

2.5

5.5

0.9

1

V

@ V_{DD_LV}= 3.6V, otherwise

V_LIH-min= 0.7  V_{DD_LV}

Voltage range for input ”low” level -0.3

V

@ V_{DD_LV}= 3.0V, otherwise

V_LIL-max= 0.3  V_{DD_LV}

I_LIH

Logic “high”

@ pins without

-1

µA

@ V_LIH= V_{DD_LV}

input current pull-up/pull-down

resistors:

INT_L, WURQ_L

I_LIL

Logic “low”

input current

1

@ V_LIL= 0V

I_{LIH_PD}

I_{LIL_PD}

Logic “high”

@ pins with pull- -300

-150

1

@ V_LIH= V_{DD_LV-max}= 3.6V

@ V_LIH= 5.5V, V_{DD_LV-max}= 3.6V

input current down resistors:

TX_EN/SPI_CLK,

TX/MOSI,

AUX_EN,

AUX_TX,

DC_RDY

Logic “low”

input current

-1

@ V_LIL= 0V, V_{DD_LV-max}= 3.6V

@ V_LIL= 0V, V_{DD_LV-max}= 3.0V

I_{LIH_PU}

I_{LIL_PU}

V_LOL

Logic “high”

input current up resistors:

@ pins with pull-

-1

-150

0

1

µA

@ V_LIH-min= V_{DD_LV-max}= 3.0V

@ V_LIH-max= V_{DD_LV-max}= 3.6V

RST_L,

SPI_EN_L

Logic “low”

input current

250

5

µA

@ V_LIL= 0V, V_{DD_LV-max}= 3.6V

@ V_LIL= -0.3V, V_{DD_LV-max}= 3.6V

Logic “high”

output voltage RX/MISO,

@ output pins:

@ I_LIL= 1mA

%V_{DD_LV}

AUX_RX

V_LOH

Logic “high”

output voltage

95

100

@ I_LIH= -1mA

Internal Current Consumption ¹⁰⁾

SPI_EN=3.3V

I_VDD

Current into VDD

Current into LR_IN

1.7

2.2

2.5

3.4

mA

I_{LR_IN}

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Symbol

Parameter

Min Typ¹⁾Max

Unit

Conditions

1)

2)

The mentioned typical values of IC properties are provided for information only and shall not be considered as statistical

guaranteed mean values. Typical values are not subject for measurement while the electrical test of each IC – they are correct by

design.

If the output current exceeds the configured current limit, the IC will raise an overload signal which causes up-counting of the

overload counter (if configured) and which definitely limits the output current. However, the current limit will be performed after a

certain settling time in order to ensure the configured slope of the output signal.

3)

4)

Absolute edge rise and fall times are proportional to V_{DD_HV}

A minimum of the output current must be provided by the application circuit. Otherwise the DC/DC converter shall be unused by

interconnecting the FB pin with the LR_OUT pin. The required voltage divider (refer to Figure 3.21) may provide this current partly

or in full.

Slew-rate measured after settlement time of the output signal

Configurable with an external voltage divider (refer to chapter 3.5)

The ripple on the output voltage depends significantly on both the external components and the PCB layout. Reference PCB

layouts are available from ZMDI. The layouts used in the application kits are shown in Figure 4.4; detailed layout data of the

application kits are available from ZMDI upon request.

5)

6)

7)

8)

The efficiency of the DC/DC converter is depending on the external components and the used PCB layout. Moreover, there is an

influence from several operational conditions which is illustrated in the diagram of Figure 2.2

Microcontroller interface pins are : RST_L, SPI_EN_L, INT_L, WURQ_L, TX_EN/SPI_CLK, TX/MOSI, RX/MISO, AUX_EN,

AUX_TX, AUX_RX, DC_RDY

Current consumption is measured by applying the maximum supply voltage at the supply pins VDD and LR_IN (V_{VDD_HV}=36V,

V_in=36V) and using a decoupling cap of 10µF between LR_OUT and ground. Both VDD and both VSS pins are interconnected,

respectively. Pins TX_EN/SPI_CLK, AUX_TX, TX_EN, AUX_EN, PFD, COM_I, AUX_I are connected to ground.

9)

10)

Data Sheet

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Figure 2.2 Efficiency of the DC/DC⁶converter for VOUT=5V, C=10µF and L=10µH

⁶The DC/DC converter is only available inside the products ZIOL2401/2402/2201/2202/2101/2102

Data Sheet

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3

Detailed Description

3.1.

Block schematic

Figure 3.1 Functional Block Diagram of the ZIOL2xxx

LV

Interface

HV

Interface

LR_OUT LR_IN

DC_RDY SW

FB

System control

SPI

DC / DC

Converter

RST_L

internal

supply

VDD

PFD

INT_L

WURQ_L

SPI_EN_L

status

register

config

EEPROM

config

register

OSC

Under-voltage and

line-fail detector

Dual channel

transceiver

COM

TX_EN/

SPI_CLK

COM_O

TX/

MOSI

analog

filter

COM_I

digital

RX/

filter

en

MISO

en

AUX

AUX_EN

AUX_TX

AUX_RX

AUX_O

AUX_I

analog

filter

digital

filter

en

VSS

Analog Block

Digital Block

en

= Function (building block) can be enabled/disabled by the configuration settings.

= Function (building block) can be configured/parameterized by the configuration settings.

= Building block functionality/availability depends on the ZIOL2xxx product definition,

please refer to the ZIOL2xxx product matrix.

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3.2.

Dual Channel Transceiver

3.2.1. IC Data Path Configuration

The ZIOL2xxx ICs contains one (ZIOL22xx/21xx) or two (ZIOL24xx) transceiver channels. The channels inside

the product versions with two channels can work independently in the “Dual Mode” or coordinated in “Tandem

Mode”. The data path of the ZIOL24xx Ics is illustrated in Figure 3.2. Both channels, which are designed

identically, are widely configurable. Due to configuration and the range of supported supply voltages the Ics can

be used in a broad field of applications. Example applications can be level shifter for standard sensor applications

or driver for resistive, capacitive or inductive loads.

Figure 3.2 ZIOL24xx Transceiver Data Path in Principle

Maximum driver capability of minimum 500mA can be achieved by combining both drivers. In this case the drivers

work in parallel (Tandem Mode).

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In order to gain optimal EMC behavior the slew rate of the output signals of both drivers can be adjusted. The

input threshold levels of the receiver can be set to ratiometric or to IO-Link conform levels, which enables the IC to

be used in applications having a wide supply voltage range.

The configuration of the transceiver can be changed during operation. After power-on this configuration is

automatically loaded from the on-chip EEPROM.

Driver and receiver are kept totally separated, so full duplex mode in data communication systems is supported.

The ability to enable/disable the drivers output also enables applications in half duplex mode, where output and

input are connected. Having the I/O-pins separated also enables additional external input filtering.

The COM channel send and receive signals (TX_EN, TX, RX) are multiplexed with the signals of the SPI

functional unit of the IC (SPI_CLK, MOSI, MISO) as shown in Figure 3.2. The SPI unit is used for IC configuration

and diagnostic purposes (refer to chapter 3.3.8). As long the SPI unit is active (SPI_EN_L = low), the send status

of the COM channel is kept (for information refer to chapter 3.3.8 and Figure 3.10).

Figure 3.3 ZIOL22xx Transceiver Data Path in Principle

ZIOL22xx Data Path

SPI_EN_L

SPI

Conf.Reg[7][7:5]

CLK

MOSI

TX_EN/

SPI_CLK

MISO

A

B

C

S3

L

EN

TX

COM

TX/

MOSI

OUT

A

B

S2

Device

I1

COM_O

COM_I

RX/

MISO

RX

IN

DF

I2

AF

CS

B

A

n.c.

AUX_EN

AUX_TX

S1

B

A

AUX_O

AUX_I

n.c.

Device

I1

S0

n.c.

DF

I2

AUX_RX

RST_L

INT_L

Single channel

transceiver

Control

WURQ_L

Legend:

AF:

Analog Block

Digital Block

Analog Filter (on/off configurable)

CS:

DF:

Current Sink (on/off/strength configurable)

Digital Filter (on/off configurable)

I1, I2:

L:

SPI:

Transmit/Receive Data Inverter (on/off configurable)

Data Latch, stores channel transmit status

Serial Peripheral Interface

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The (stripped down) IC versions ZIOL22xx/21xx contain only one channel. Figure 3.3 and Figure 3.4 show the

data path of the ZIOL22xx versions and ZIOL21xx versions, respectively. The following chapters regarding details

of the transmitter and receiver apply to IC versions with two channels (ZIOL24xx). The in the following described

functionality applies to IC versions with one channel (ZIOL22xx/21xx) correspondingly. With the implicit

understanding that one channel IC versions cannot perform tandem (master) mode operations or coordinated

transceiver operations no explicit statement in the following chapters will reflect this.

Figure 3.4 ZIOL21xx Transceiver Data Path in Principle

The master mode configuration flags MASTER_MODE, EN_FOLLOW_PRIM_CH and PRIMARY_MASTER_CH

located in the MASTER_SENS_CTRL configuration register (refer to Table 3.7) control the switches S0, S1, S2

and S3 (Figure 3.2, Figure 3.3 and Figure 3.4) thus they control the actually used data path. In principle, the

ZIOL2xxx IC family supports five data path types which are mentioned in Table 3.1. In case the MASTER_MODE

flag is cleared (=0), the IC operates in device mode. For more information about the operation in device/master

mode, please refer to chapter 3.2.2.1.

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Table 3.1 Master-Device-Mode Function Table

Data Path

Switch

Position

Data Path Configuration

MASTER_SENS

Receiver

available

1)

RX/

MISO

_CTRL[7:5]

REMARKS

T

y

p

State

control

[7] = MASTER_MODE

[6] = EN_FOLLOW_PRIM_CH

[5] = PRIMARY_MASTER_CH

S

0

S

1

S

2

S

3

Global IC Function

e

COM²⁾

AUX

Equivalent to

IC Rev A

Device Mode

0

1

Device Mode

0 X X

1 0 0

A

B

A

push/ pull

Master Mode,

COM²⁾

AUX

Equivalent to

IC Rev A

Master Mode

COM = prim channel,

AUX enable not following

prim-ch

Master Mode,

Saves one

interconnection

wire (AUX_EN)

to µC

COM²⁾

AUX

COM = prim channel,

AUX enable is following

prim-ch ¹⁾

2

1 1 0

B

A

push/ pull

Master Mode,

Process (IO-

Link) and

Service (SPI)

data separation

– SPI pin bus

wiring!

AUX = prim channel,

COM enable is following

prim-ch ³⁾

3

4

1 1 1

1 0 1

A

B

C

high-Z if

SPI_EN_L

= high

AUX

Master Mode,

AUX = prim channel,

COM is disabled ⁴⁾

1)

If AUX_EN is permanently wired to GND, the total driver strength can be controlled by toggling the MASTER_SENS_CTRL[6] bit (0:

AUX disabled using just COM/ 1: AUX enabled if COM is enabled = double strength).  Switching between type 1 and 2 via SPI

access.

The logic value of the COM receiver output (RX) is available if the SPI communication is disabled (SPI_EN_L = 1).

Driver strength is “double” – “WAKE_UP_MODE”. The total driver strength can be decreased by switching to type 4 (single strength).

Driver strength is “single”. The total driver strength can be increased by switching to type 3 (double strength)

2)

3)

4)

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3.2.2. Transmitter

3.2.2.1. General functionality

The IC versions ZIOL24xx consists of two⁷independent driver stages. Each driver (COM/AUX) is configurable as

regards the parameter

 Output current limitation

 Output slew rate

 Driver function (push, pull, pull ups/downs)

Several Modes of operation are supported – as independent or as combined driver outputs.

3.2.2.2. Modes of operation (IO-Link specific Operation)

Operating both on-chip drivers independently or in parallel ensures the IC utilization in a wide range of

applications. An example can be the different requirements of driver capability in master or device mode regarding

the IO-Link specification (refer also to chapter 3.3.2). Both modes are supported by the ZIOL2xxx Ics. The active

mode is defined in the configuration register [7] bit 7. The chosen mode influences the IC’s driver behavior as well

as the handling of overload exceptions. Both input channels do not depend on the operational mode.

In master mode⁸the data inputs (TX) of both drivers are connected internally. As regards their functionality both

drivers work in parallel. Therefore, the driver outputs have to be interconnected externally in master mode.

In device mode both drivers are working independently. A respective current overload signal will be generated if

at one or at both drivers the output current exceeds the set current limit for longer than the configured amount of

time.

Figure 3.5 shows a simplified application circuit including ZIOL24xx Ics in device and in master mode,

respectively. Although both drivers are controlled by the same “TX” signal in master mode, the driver strength can

be influenced with the COM_EN and AUX_EN signal thus the resulting driver strength can be reduced in this

mode.

Starting with Rev B of the IC the MASTER_MODE flag (configuration register MASTER_SENS_CTRL[7] replaces

the formerly used control via an input pin. Summarizing the above, the MASTER_MODE flag controls:

 The Data path; it controls whether both channels use an individual or common TX signal

 The current sinks at the receiver’s inputs in the IO-Link sink mode (refer to Table 3.4)

For more information about the data path configuration of the IC in device and in mode master, please refer to

chapter 3.2.1.

⁷Note: The IC versions ZIOL22xx/21xx have just one channel. With respect to those IC versions the statements concerning the existence of

two channels shall be ignored or interpreted analogously.

⁸Not applicable for the IC versions ZIOL22xx/21xx

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Figure 3.5 ZIOL24xx in Device and Master Mode Application

Device

Master

ZIOL24xx

COM_EN

TX

L+

bidirectional

communication

TX

COM

RX

AUX_EN

(WURQ)

AUX

AUX_EN

AUX_TX

AUX_RX

AUX

direct signalling

L-

The illustration in Figure 3.5 shows the principal way of using the ZIOL2xxx integrated circuit in master and

device mode. Figure 3.5 does not include all required electronic components of the application circuit which are

mentioned in chapter 4 (Figure 4.1 and Figure 4.2).

3.2.2.3. Configuration

The COM and AUX drivers are built identically. Their features can be configured in a wide range. The behavior of

the output stages can be set to push, pull or push/pull. Current limitation and the overload timing can be set

individually. In order to improve the EMC system behavior the slew rate of the output signal is controlled and can

be set according to the needs of the application. The following table gives an overview of the possible

configurations for the COM and AUX driver in master and device mode, respectively.

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Table 3.2 Driver configurations

Parameter

Config.-Register

Reg.- Bit-

Ranges & Coding

Unit Remarks¹⁾

Addr. Field

COM and AUX driver

output current limitation AUX_PARAM

COM_PARAM,

2

4

4:2 0b000: 50

mA IC in Device mode: both

mA drivers work independently

0b010: 100

0b100: 200

mA

0b110: 250

0bxx1: limitation off²⁾

Combined driver output COM_PARAM,

2

4

4:2 0b000: 100

mA IC in Master mode: both

mA drivers work in parallel

mA Both drivers shall be set to

mA identical driver capability.

current limitation

Slew Rate Control

AUX_PARAM

0b010: 200

0b100: 400

0b110: 500

0bxx1: limitation off²⁾

COM_CTRL,

AUX_CTRL

1

3

4:3 0b00: 10

V/µs Limitation of maximal edge

V/µs steepness.

0b10: 60

0b01: slow

Limitation turned off!

control off

0b11: fast

control off

Limitation turned off!

Output characteristic

COM_CTRL,

AUX_CTRL

1

3

1:0 0b00: off

0b01: pull

0b10: push

0b11: push+pull

Overload time base –

COM, AUX

COM_MON_CTRL,

AUX_MON_CTRL

11

13

6:5 0b00: 0.2

0b01: 1000

0b10: 8000

0b11: 16000

µs Defines the clock

frequency for COM/AUX

overload counters

Overload counter

compare value – COM, AUX_ASSERT_TIME

AUX

COM_ASSERT_TIME,

10

12

7:0

Byte

If overload counter value

equals compare value an

overload will be asserted

Pull up/down enable – COM_PARAM,

2

4

6:5 Bit 6:

Bit 5:

pull-up

pull-down

Enables resistor of typical

150kOhms

COM, AUX

1)

AUX_PARAM

For a summary of all configuration registers, please refer to Table 3.7.

Not recommended due to chance of overheating

2)

3.2.3. Receiver

3.2.3.1. General Functionality

In principle, the ZIOL2xxx IC family has two⁹identical input channels with a configurable feature set. The input

threshold levels can be set ratiometric or absolute. The absolute values are compatible with definition of Type 1

digital inputs in IEC61131-2 and conform to the IO-Link specification. The ratiometric levels¹⁰are proportional to

the HV power supply voltage. The ratiometric level configuration allows the input channels to function down to a

⁹Note: The IC versions ZIOL22xx/21xx have only one receiver.

¹⁰Note: Ripple on the supply voltage may have influence to the trip-point of the input stage. Another influence to be considered is that an

enabled analog input filter is reducing the ripple on the on the received signal.

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supply voltage of 8V. For each input channel an analog and a digital filter are implemented, which can separately

be enabled.

3.2.3.2. Configuration

The following table gives an overview of the possible configurations for the COM and AUX input channels.

Table 3.3 Receiver configurations

Parameter

Config.-

Register

Reg.- Bit-

Addr. Field

Setting / Range

Unit Remarks¹⁾

Threshold level for

COM and AUX

COM_CTRL,

AUX_CTRL

1

3

5

2

7

0b0:

0b1:

absolute

ratiometric

Absolute = IO-Link

compliant thresholds

Analogue filter

COM_CTRL,

AUX_CTRL

1

3

0b0:

0b1:

disabled

enabled

Digital filter

COM_CTRL,

AUX_CTRL

1

3

0b0:

0b1:

disabled

enabled

I_sink, sink strength

Sink mode

COM_PARAM,

AUX_PARAM

2

4

0b0:

0b1:

2 – 3

5 – 7

mA

COM_PARAM,

AUX_PARAM

2

4

1:0 0b00: off

0b01: IO-Link

Following driver:

if driver is enabled

then sink = off

if driver is disabled

then sink = on

0b10: follow

driver

0b11: on

1)

For a summary of all configuration registers, please refer to Table 3.7.

3.2.3.3. Sink Modes

The IO-Link standard defines a possible configuration option, in which the device drives the signal line only with a

high side driver thus the logic low level will be generated with a current sink on the master side (Figure 3.6). The

ZIOL2xxx supports the current sinks in different modes on master side (for details refer to Table 3.4).

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Figure 3.6 Typical IO-Link Device Configuration with HS driver only

Table 3.4 Sink Mode Configuration in Detail

Register[2][1:0]

Register[4][1:0]

00

Mode

n.a.

Sink enabling

Remark

OFF

Sink steady disabled

01

10

Device

Typical application mode for the

IO-Link channel:

device: no sink

master: sink enabled contrary to

the corresponding driver enable

signal

Enabling contrary to the driver

enable signal;

Mode ¹⁾

Master

Sink enabled if:

Mode ²⁾



TX_EN/SPI_CLK = low (COM)

AUX_EN = low (AUX)

n.a.

Sink enabled if:



TX_EN/SPI_CLK = low (COM)

AUX_EN = low (AUX)

sink is only enabled while the driver

is disabled. (helps to reduce the

system’s power dissipation)

11

n.a.

steady enabled

ON

1)

MASTER_MODE flag (configuration register MASTER_SENS_CTRL[7] is cleared (=0).

MASTER_MODE flag (configuration register MASTER_SENS_CTRL[7] is set (=1).

2)

3.3.

System Control

3.3.1. General

The system control provides device configuration, status signaling and SPI data transfer functionality.

Implemented are several register areas which contain configuration data and which provide status information. In

order to gain read/write access to these register areas, the standard serial peripheral interface (SPI) is

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implemented. Since the pin count of the package is limited to 24 pins, the SPI specific pins (CLK, MOSI, and

MISO) are multiplexed with IO-pins of the COM driver. A dedicated pin SPI_EN_L is used to switch between SPI

(logic low) and COM transceiver functionality (logic high). The low voltage (LV) interface works with 3.3V supply

voltage (refer to Figure 3.1). The LV outputs drive 3.3V as high level, the inputs are 5V tolerant.

If the SPI communication channel of the ZIOL2xxx Ics is active (SPI_EN_L = low), the status of the COM channel

drivers is kept. This means while SPI_EN_L = low the output driver status (driving low, driving high, or high-z) is

the same as defined by the pins TX_EN/SPI_CLK and TX/MOSI at the point of time of the SPI_EN_L high-low

transition. The AUX channel is not affected by the activity of the SPI communication. For more information, please

refer to chapter 3.3.8 and Figure 3.10.

3.3.2. IO-Link Master¹¹and Device Mode

The IC architecture is suitable for both IO-Link application cases, the physical layer transceiver at an IO-Link

master port and at an IO-Link device port. In the first case the IC shall operate in its “master mode” which is the

case if configuration register [7] bit 7 is set (=1). If the IC shall operate in “device mode”, configuration register [7]

bit 7 shall be cleared (=0). Details regarding the control of both driver channels are described in chapter 3.2.1,

3.2.2.2 and 3.2.3.3.

The IO-Link specific WURQ detection (detection of an IO-Link master’s wake-up request, refer to IO-Link

Communication Specification – chapter 8, [2]) works only in device mode.

3.3.3. Internal Exceptions

Depending on the IC configuration the ZIOL2xxx can detect several critical situations and rise internal exceptions

accordingly. Also depending on the IC configuration an occurred internal exception can be indicated externally by

changing the logic level of the INT-L pin to “low”. The situations that cause an internal exception are channel locks

(channel driver protection), detected IO-Link specific Wake-Up pulses and several issues concerning the internal

EEPROM as described in chapter 3.3.10.

3.3.4. IO-Link specific Wake-Up (WURQ)

In device mode the IC can detect the IO-Link specific wake-up request (WURQ) of the IO-Link master and can

therefore help to save resources in the microcontroller of IO-Link device. As regards the IO-Link specific “Wake-

Up (WURQ)” specification, please refer to the IO-Link Communication Specification issued by the IO-Link

consortium (refer to chapter 8, [2]).

The WURQ can be detected on the COM or on the AUX channel. The chosen channel is defined in a

configuration register (IRQ_WURQ_CTRL, refer to chapter 3.3.9).

In order to establish an IO-Link specific communication, the master will generate the WURQ event. In this case

the master overdrives the devices output level for a determined period. The ZIOL2xxx can detect that event which

physically occurs in two ways:

 A current overload in the drivers output for a certain period

 A contradiction of the TX and RX lines of the device for a certain period

¹¹Not applicable for the IC versions ZIOL22xx/21xx.

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The IC configuration register (IRQ_WURQ_CTRL, refer to chapter 3.3.9) defines if the “overload” or the

“contradiction” or both events shall be chosen for the WURQ detection. Both ways of detection can be enabled

independently. If at least one of both events appears for a specific time, the incident will be regarded as WURQ

request from master side and the IC will generate an internal exception (issue an interrupt) in order to signal this

to the interconnected µC. Besides the configurable signaling on the INT_L pin (refer to chapter 3.3.10.1) this

special exception will be displayed on the therefore dedicated WURQ_L pin. Details of the signaling via the

WURQ_L and/or the INT_L pin and the pin driver configuration of the WURQ_L pin can be defined in the

configuration registers which are described in detail in chapter 3.3.9.

The logic level of the WURQ_L pin (a wake-up causes logic low) or the stored WURQ event will be reset as soon

as the drivers direction is set to input (TX_EN=0), which equals the WURQ acknowledge from the IO-Link device

side.

The on logic level based WURQ detection works only for level-changes which are driven by the master. That

means a WURQ will not be detected if a level change has been initiated by the device itself, even if the signal

timing is equivalent to a WURQ event. This prevents the in SIO mode operating IO-Link device to misinterpret the

situation caused for instance by capacitive loads.

If the ZIOL2xxx operates in master mode (physical interface for IO-Link master port) and a Wake-Up pulse

(WURQ) shall be issued, the µC has to control the required driver strength by activating both channels (via

COM_EN and AUX_EN, refer to Figure 3.5) and has to provide the correct timing.

Figure 3.7 Wake-Up Signal Recognition

MAX: Wake-Up pulse width

MIN: Wake-Up pulse width

0

60

68

75

80

85

94

110

µs

t_wurqL

t_wurqU

Tolerance range due

tolerant OSC frequency

- 6 / + 25 clocks

+10%

-10%

Accepted Wake-Up

pulse width range (device)

Accepted Wake-Up pulse width range if

OSC runs at lowest possible frequency

Overdriven Output

Overdriven

Output

Accepted pulse width range if

OSC runs at highest possible frequency

The WURQ pulse recognition of the ZIOL2xxx in device mode is – in contrast to that – based on a time base

derived from the internal oscillator (OSC). Therefore the as WURQ recognized pulse width range of an received

Wake-Up signal is dependent on the frequency tolerance of the internal oscillator as illustrated in Figure 3.7. A

Wake-Up signal (pulse width according to the IO-Link Communication Specification, refer to chapter 8, [2]) shall

have a pulse width between 75µs and 85µs (variation 10µs). The ZIOL2xxx Wake-Up signal detection will always

recognize such a signal securely considering a frequency tolerance of the internal oscillator of ±10% (refer to

parameter f_oscin Table 2.3).

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3.3.5. IC Self-Protection – Lock Mode

In order to prevent serious IC damage due to overloaded or overheated driver transistors, the IC has a build-in

protection mechanism. If a critical situation occurs for a certain configurable time, the IC can protect itself in

transferring its control in a special mode, called lock mode, in which the driver of the related channel is turned-off

in case of over-current, or in case of over-temperature the drivers of both channels are turned-off, respectively.

Figure 3.8 shows the basic scheme of the IC self protection. In principle, this scheme is five times implemented in

order to tread:

 Over-current situations separately at the high side and at the low side switch of the COM channel as

described in Figure 3.15

 Over-current situations separately at the high side and at the low side switch of the AUX channel as

described in Figure 3.16

 Over-temperature situations of the silicon die as described in Figure 3.17

In case of an over-current or over-temperature situation occurs (in the following called overload) the related over-

current/over-temperature counter (overload counter) will count up. Since the overload counter counts down to

zero in case of no overload is existent, the circuit performs an integrator function. This integrator function makes

sure that overloads which temporarily occur are not accumulated thus will not lead to an unwanted driver locks.

If the overload counter has reached the (in the related configuration register) defined maximum value, the IC will

generate an internal exception. This exception will lock the associated channel or both channels in case of an

over-temperature situation. The “assert Time” (refer to Figure 3.8) which is the elapsed time in until reaching the

configured maximum of the overload counter depends on the used clock period for the overload counter. This

clock period can be defined separately for the lock control circuit of each channel (Figure 3.15, Figure 3.16) and

the temperature lock control circuit (Figure 3.17) in the associated configuration register.

To each overload counter is a peak register associated. The value of the overload counters can not be retrieved

via the SPI port. However, the value of the overload counter will be copied in the related peak register if the value

of the overload counter is greater than the value of the peak register. The peak registers can be read via the SPI

port. The content of the peak register will be cleared after each read access. However, within the next cycle of the

IC control circuit the peak register will be set to the overload counter value again if this value is greater than zero.

The above described peak register update is only performed if an overload situation is present. In case of

overload situation the peak register is an important instrument to perform an IC diagnostic. For more information

about techniques to operate the peak, please refer to Appendix A.

A due to an overload raised internal exception will cause in case of over-current a lock of the related channel or a

lock of both channels in case of a over-temperature situation. There are three signals (displayed in status

register[20] which indicate the lock activator. The other five bits of this status register indicate what IC sensor has

detected an over-current or if the configured maximum of the die temperature has been exceeded.

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Figure 3.8 The Basic Scheme of the IC Self Protection

Any internal exception will be stored in status register[18]. This status register will be cleared by reading the

register but the appropriated bit will be set again (within the next cycle of the IC control circuit) if an exception is

still present.

A lock can be reset by using the build-in and configurable lock counter (defined in the associated configuration

registers). As shown in Figure 3.8 the lock reset will be performed when the lock time has been elapsed. The lock

counter is using the same clock as the associated overload counter(s). Alternatively a lock can be reset by

performing an write access to status register[16] (for more details refer to Appendix A).

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Depending on the IC configuration the any exception or stored exception can cause the INT_L pin to logic low. As

shown in Figure 3.8 INT_L can follow the state signals (internal exceptions) or the stored exception which is also

depending on the IC configuration.

3.3.6. Channel Locking in Master/Device Mode

There are three independent lock mechanisms implemented. For each channel (COM and AUX) a separate lock

can be generated if an over-current at the high side or low side switch has occurred. Therefore it is implied that for

the considered switch a current limit had been configured. The third lock mechanism which is affecting both

channels is related to over-temperature situations.

As regards the IC operation as IO-Link master or device PHY (master/device mode, refer to chapter 3.3.2) the

lock mechanisms of both channels are really separated or coordinated as following described:

Master¹²mode (COM and AUX driver work in parallel – Tandem Mode):

 Assumed that both channels (COM and AUX) are enabled and the configuration flag

BOTH_CHANNEL_LOCK (register[14]) is set (=1), both HS or both LS driver of both channels need to be

overloaded simultaneously for longer as a configured time in order to generate an IC-internal overload

exception which is indicated at the INT_L pin (logic low).

 In the case the IC works in tandem mode and the configuration flag BOTH_CHANNEL_LOCK (register 14)

is set (=1), but only one of the channels (COM or AUX) is enabled, the protection of the enabled channel is

performed analogous to the device mode.

 If single HS or a single LS driver is disabled, then its overload signal is not needed to create a general

overload signal, in that case just the other (enabled) HS or LS driver can generate the overload exception.

 If the die temperature exceeds the configured limit thus a temperature overload exception is detected, the

IC locks both channels and signals and according to the IC’s configuration an interrupt can be signaled at

the INT_L pin.

Device mode:

 Any single overloaded HS or LS driver of the COM or AUX channel leads to a lock and an interrupt

signaling (INT_L pin) according to the configuration of the IC.

 If the die temperature exceeds the configured limit thus a temperature overload exception is detected, the

IC locks both driver channels and signals and according to the IC’s configuration an interrupt is signaled at

the INT_L pin.

 If both drivers are configured parallel, the interrupt behavior equals the master mode

The lock mode is associated with IC-internal exceptions that are signaled to the interconnected µC as an interrupt.

The details for building and clearing an exception are described in the chapter 3.3.10 which deals with the

interrupt handling and lock mode operation.

3.3.7. Memory Unit

The memory unit of the IC provides several IC configuration options. Those configuration options define the

properties of the Ics driver channels and define the IC monitoring and protection functions with respect to the

over-current and over-temperature handling.

¹²Not applicable for the IC versions ZIOL22xx/21xx

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The currently applied configuration data of the IC is stored in the configuration-register area which is implemented

as a register file. The configuration-register area can be uploaded via SPI command into an on-chip EEPROM for

non-volatile storage. While power-on-reset or also via SPI command the EEPROM content will be downloaded to

the configuration-register area.

Besides data for IC configuration the IC has certain status registers that can be used to monitor the internal status

of the IC. The status registers reflect the IC status as regards the occurrence of different driver channel overload

situations and their duration. Moreover, four alert phases (green, yellow, orange and red) indicate the die

temperature of the IC and in this combination the die temperature margin prior a thermal shut down of certain IC

building blocks. In principle, status registers are read-only registers. Some status registers are reset by reading

the register’s value. Furthermore, a write access to some status registers will cause certain control actions (for

more information refer to Table 3.7).

The read/write access to the Ics memory unit is provided by an SPI interface (refer to chapter 3.3.8). In order to

access a certain register or range of consecutive registers (block access) an 8-bit-address has to be applied

which consists of segment address (2bits) and register address (6 bits) as illustrated in Figure 3.9.

Figure 3.9 Memory Unit

Memory block boundaries

which cannot be exceeded

while bock accesses

Register File

31

26

Memory control

Status

Register

EEPROM

16

15

Non-volatile

configuration

data

Config-

Register

EE

Upload

Download

Valid-flag

0

Segment 0

Segment 1

Address

Segment 2 and 3 must not be used

reserved

In case of a collapsing supply voltage while writing data into the EEPROM, the EEPROM data shall be suspected

to be corrupt. There is an additional build-in security feature to indicate this situation and to avoid that corrupt

EEPROM data is used for the IC configuration. In this combination a non-volatile flag (one bit EEPROM) is used

to indicate possibly not valid (corrupt) EEPROM data. This flag which is called valid-flag is set if the data are valid

or is cleared if the data are suspected to be corrupt. As shown in Figure 3.14 corrupt EEPROM data or any other

EEPROM problems can cause an internal exception.

The above mentioned feature is using the following procedure while performing an EEPROM write access:

1. Clearing the valid-flag.

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2. Write access to the EEPROM. This is the critical step which can lead to corrupt data if interrupted at certain

points in time. Since the valid-flag is cleared the IC can detect this and make sure that no corrupt data are

going to be used unintentionally.

3. Set the valid-flag. From now on the data are declared as valid.

If the power supply of the IC collapses while writing to the EEPROM or the write access is interrupted by any

other reason, the IC can detect this while power-up due to the cleared valid-flag and can and block the EEPROM

data against further use. Just in case the IC has detected possibly corrupt EEPROM data the configuration

registers will be load with default values which are equal to the initial state (reset values) mentioned in Table 3.7.

3.3.7.1. EEPROM Error Correction Features

The physical memory array of the EEPROM contains 16 words of 13 bits. In addition to the eight “real” data bits

there are five parity bits which are used as error correction code (ECC). In case one of the data bits changes its

information an automatic single-error correction will be done. Thus the data word (read by the IC system control)

is still correct if this one-bit-error occurs. In order to signal this incident the exception “Eeprom-error” is generated

(stored in bit 4 of the status register[18]).

If a two-bit-error occurs (two bits of the data word are wrong) the ECC cannot correct the memory failure. This

means the in such a situation read data is corrupt. In order to signal this non-recoverable memory failure the

exception “Eeprom_2_error” is generated (stored in bit 3 of the status register[18]).

In summary the ECC features of the EEPROM allow to recognize problems (single bit errors) of the EEPROM

(Eeprom_error exception) without jeopardizing the entire system application. Only for the case that there are

multiple-bit-errors, which are signaled with the “Eeprom_2_error” exception, it is recommended to stop the

application and maintain the application circuit.

3.3.8. Serial Peripheral Interface (SPI)

3.3.8.1. SPI Features

The purpose of the SPI interface is to provide access to the memory unit of the IC. Within communication pauses

of the transceiver channels the SPI can be used to retrieve diagnostic data from the IC and/or to reconfigure the

IC, respectively. An active SPI communication causes that the COM communication channel, which shares its

control pins with the SPI interface, cannot change its output value and output status and cannot forward received

signals for exactly the period SPI_EN_L is low (refer to Figure 3.10).

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Figure 3.10 General timing of a byte transfer

SPI feature summary:

 The interface works in SPI-slave mode only

 The timing follows the scheme in Figure 3.10 which defines

▬ Clock Polarity CPOL = 1 (clock is idle high)

▬ Clock Phase CPHA = 1 (data captured with 2^ndclock edge after SPI_EN_L went low; data are read on

clock’s rising edge and data are changed on a falling edge)

 Maximum clock frequency of the SPI_CLK shall not exceed 4 MHz for accessing the on-chip EEPROM and

10 MHz for other SPI accesses

 SPI clock duty cycle: 40…60%

 MSB will be transmitted first

 If access exceeds last byte, a wrap will NOT happen – the last byte will be written correctly, rest will be

disregarded

 Block write (access to more than one address location) is only supported for the configuration-register area

but not for the EEPROM area.

 Block read is supported for both the EEPROM and configuration-register area.

 During enabling the SPI (SPI_EN_L = low ) the input lines of the COM driver are latched, so the COM

driver does not change its output state while SPI is enabled.

The SPI telegram structure can be divided into three types of SPI accesses:



READ: read access to register file or EEPROM, block access possible

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

WRITE¹³: write access to register file (if applicable) or EEPROM, block access only supported with the

access to register file

COMMAND: Commands to achieve an IC (soft-)reset or up- or download of configuration data

Figure 3.11 illustrates the structure of supported SPI accesses. The in this figure illustrated write access works

only with the IC versions ZIOL2xx1

Figure 3.11 Structure of SPI accesses

3.3.8.2. SPI access details

The timing of the three SPI access types is illustrated in Figure 3.13. As shown in this figure the 1^stbyte, which is

called destination byte, is composed out of the segment address (bit 7:6) and the register address (bit 5:0). A

command is always using the address 0xFF which is a not physically implemented memory location within the IC

memory unit.

¹³Note: IC versions ZIOL2xx2 do not allow any write access.

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The READ and WRITE¹⁴access is defined in the value of bit 7 (0=write; 1=read) of the 2^ndbyte which is called

the SHIFT byte. Bit 6:0 represent the repeat count. This value defines the number of additional consecutive bytes

to be accessed. In case of a write access the SHIFT byte following bytes are the actual data to be written into the

memory location(s). Table 3.5 illustrates the building of the SHIFT byte in using an example.

Table 3.5 Example for building the SHIFT Byte

Number of

bytes to be

accessed

SHIFT byte value SHIFT byte value

In case of a read

access

In case of a write

access

1

2

0000 0000

0000 0001

0000 0010

…

1000 0000

1000 0001

1000 0010

…

3

…

16

0000 1111

1000 1111

If the transferred data stream of one telegram exceeds the border line of the chosen memory block, all following

accesses will be disregarded. No wrap will happen! For more details refer to Table 3.6.

Table 3.6 Valid Address and Length Combinations

Segment

00

Address

Length = SHIFT[6:0]

Comment

00 0000

…

000 0000…000 1111

…

Configuration-register block

00 1111

000 0000…000 0000

01 0000

…

01 1001

01 1111

000 0000…000 1111

…

000 0000…000 0101

000 0000…000 0000

Status register block

Although status registers can be accessed up to

address 31 the useful range is only up to address 25

01

00 0000

…

000 0000

…

EEPROM is directly accessible via SPI but there is

no block operation allowed

00 1110

000 0000

Figure 3.12 SPI Command Structure

¹⁴Note: IC versions ZIOL2xx2 do not allow any write access.

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The structure of an SPI command is shown in Figure 3.12. There are three commands implemented which are:



MEM_DOWNLOAD

Code: 0x01

Description: If the EEPROM data is valid (valid-flag = 1  data is not corrupt) the MEM_DOWNLOAD

copies the EEPROM data into the configuration registers. If the data are suspected to be corrupt (valid-flag

= 0), the EEPROM data are not downloaded and an interrupt (INT_L pin) will be asserted.

MEM_UPLOAD

Code: 0x02

Description: The command copies the entire configuration register data into the EEPROM memory. The

command execution starts with clearing the valid-flag and then with reading the configuration registers and

writing the data into the EEPROM. At the end of cycle the valid-flag is set to 1.

SOFT_RESET

Code: 0x07

Description: The command execution generates a reset for the entire IC. This reset occurs

asynchronously with reference to the system clock but is released synchronously. When this SPI command

is being executed, the system is hold in the reset state for about 2µs. The system reset state is indicated

with active low on the INT_L pin.

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Figure 3.13 SPI Timing¹⁵

3.3.9. Register Table / Registers for IC Configuration and Monitoring

The following Table 3.7 shows a summary of the configuration- and status registers of the ZIOL2xxx. The

address space from address 0 to 15 is implemented in both the register file area and the EEPROM area.

Registers with addresses greater than 15 (status registers) are implemented in the register file area only.

¹⁵Note: IC versions ZIOL2xx2 do not allow any write access.

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As regards the access type to a particular register the following four types have been implemented:

1.

2.

3.

4.

r/w

normal read/write¹⁶

r

read only

r/rst

w/pulse

read only, clear by read

writing to such type of registers causes a partial reset of certain IC functions which

correspond to the assigned bit of the write accessed register; reading is possible but will

return no useful information

In order to illustrate for instance the w/pulse type a write access to status register MON_RST_LOCK_WURQ shall

be explained. The bits of this register are assigned to

 the power fail event (bit 4) and

 the IO-Link specific wake-up request event (bit 3) and

 the COM/AUX driver over-current event (bit 2 and 1) and

 the over-temperature event (bit 0).

Writing the value 0x08 (MON_RST_WURQ = 1) to the register would cause a reset of the previously detected and

stored wake-up request. In doing so the to the IC interconnected µC acknowledges the occurred wake-up request

thus the IC is ready to detect the next wake-up request.

Table 3.7 Register Table

Reg.-Name

Addr.

Bit-Field

Bit Reset- r/w

Value

Comment

Reference

CONFIGURATION REGISTER

IRQ_ENABLE

0

7:0 255

r/w

Figure 3.14

Power fail interrupt

enable

Added in

Rev B

IRQ_EN_POWER_FAIL

IRQ_EN_WURQ

7

6

5

4

3

1

WURQ interrupt

enable

Valid-flag error

interrupt enable

IRQ_EN_VALID_FLAG_ERR

IRQ_EN_EEPROM_ERR

IRQ_EN_EEPROM2_ERR

Single bit error

interrupt enable

Multiple bit error

interrupt enable

¹⁶Note: IC versions ZIOL2xx2 do not allow any write access.

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Reg.-Name

Addr.

Bit-Field

Bit Reset- r/w

Value

Comment

Reference

interrupt enable for

0

IRQ_EN_LOCK_AUX

IRQ_EN_LOCK_COM

2

1

r/w over-load lock of

AUX line driver

interrupt enable for

r/w over-load lock of

COM line driver

interrupt enable for

over-temperature

r/w lock of both, AUX

and COM, line

0

IRQ_EN_LOCK_OVT

0

1

drivers

IOLINK-control-

register

COM_CTRL

1

7:0

7

0

r/w

Enable digital RX-

Filter

COM_DIG_FILTER

COM_INV_SEND

r/w

invert receive and

r/w send (implemented in

digital part)

6

Disables the receiver

r/w IO-Link levels and

enables ratiometric

1

COM_RATIO

COM_COM3

5

4

0

COM3-Mode (slope-

control),

0: COM2

r/w

1: COM3

Disables Edge

control

1

2

COM_NOEDGE

COM_FILTER

COM_LS_ON

COM_HS_ON

3

2

0

r/w

Filter-enable

r/w

0=off / 1 = on

LowSide-Driver

r/w

1

0=off / 1=on

HighSide-Driver

r/w

0

0=off / 1=on

IOLINK-Control-

r/w

COM_PARAM

7:0

7

Parameters

COM_SINK_STRENGTH

COM_PULLUP_EN

r/w Sink_strength

Pull-Up Enable for

r/w

6

COM-Channel

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Reg.-Name

Addr.

Bit-Field

Bit Reset- r/w

Value

Comment

Reference

Pull-Down Enable for

COM-Channel

2

3

COM_PULLDOWN_EN

COM_CULI

5

4:3

2

0

r/w

r/w Current Limit

Current-Limiting

disabled

COM_NOCULI

r/w

COM_SINK_MODE

1:0

7:0

7

r/w Sink-Mode

IOLINK-control-

register

AUX_CTRL

r/w

AUX_DIG_FILTER

AUX_INV_SEND

r/w digital RX-Filter

invert receive and

r/w send ( implemented

in digital part)

3

6

5

0

Disables the receiver

r/w IO-Link levels and

enables ratiometric

AUX_RATIO

COM3-Mode (slope-

control)

3

4

AUX_COM3

4

3

0

r/w

Disables Edge

control

AUX_NOEDGE

AUX_FILTER

AUX_LS_ON

AUX_HS_ON

r/w

Filter-enable

r/w

2

0=off / 1 = on

LowSide-Driver

r/w

1

0=off / 1=on

HighSide-Driver

r/w

0

0=off / 1=on

IOLINK-Control-

r/w

AUX_PARAM

7:0

7

Parameters

AUX_SINK_STRENGTH

AUX_PULLUP_EN

r/w Sink strength

Pull-Up Enable for

r/w

6

AUX-Channel

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Reg.-Name

Addr.

Bit-Field

Bit Reset- r/w

Value

Comment

Reference

Pull-Down Enable for

AUX-Channel

4

AUX_PULLDOWN_EN

AUX_CULI

5

0

r/w

4:3

2

r/w Current Limit

Current-Limiting

disabled

AUX_NOCULI

r/w

AUX_SINK_MODE

1:0

r/w Sink-Mode

Over-temperature:

r/w time until lock is

released

OVT_LOCK_TIME

5

7:0 200

7:0 100

Figure 3.17

Overload: time until Figure 3.15

Lock is released

COM_LOCK_TIME

6

7

r/w

Figure 3.16

MASTER_SENS_CTRL

7:0

7

1

0

r/w Over-temperature

Figure 3.18

Master mode

enabled, influences

r/w the data path and the

receiver’s current

Added in

Rev B

7

MASTER_MODE

sinks in IO-Link mode

The secondary

channel:

0 = uses a separate

enable signal

1 = uses the enable

of the prim. ch.

Added in

Rev B

7

EN_FOLLOW_PRIM_CH

PRIMARY_MASTER_CH

6

5

0

r/w

Defines the primary

channel:

0 = COM

Added in

Rev B

r/w

1 = AUX

7

RESERVED

OVT_RED

4

3

2

1

0

r/w RESERVED

OVT level set to

“Red”

r/w

OVT level set to

“Orange”

OVT_ORANGE

OVT_YELLOW

r/w

OVT level set to

“Yellow”

r/w

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Reg.-Name

Addr.

Bit-Field

Bit Reset- r/w

Value

Comment

Reference

OVT level set to

“Green”

7

8

9

OVT_GREEN

0

1

r/w

Over-temperature:

r/w time until lock is

asserted

OVT_ASSERT_TIME

OVT_PFD_CTRL

7:0 100

6:0 15

Figure 3.17

OVT and Power-Fail

control

r/w

Enables Line-fault

r/w

Added in

Rev B

LINE_FAULT_EN

UNDER_VOLTAGE_EN

OVT_TBASE

6

5

0

1

(LF) detection

Enables Under-

r/w Voltage (UV)

detection

Added in

Rev B

Over-temperature:

time base

4:3

2

r/w

Over-temperature:

r/w reset lock (also) time

based

OVT_LOCK_TIME_RST

OVT_LOCK_EN

Over-temperature:

enable lock

1

r/w

Over-temperature:

enable OVT-

measurement and

9

OVT_EN

0

1

r/w

control

COM-Overload: time

r/w

COM_ASSERT_TIME

COM_MON_CTRL

10

11

7:0 50

6:0 63

Figure 3.15

until lock is asserted

r/w

COM-Overload: time

base

11 COM_OVL_TBASE

6:5

4

1

r/w

COM-Overload: reset

r/w lock (also) time

based

11 COM_LOCK_TIME_RST

COM-Overload:

r/w

11 COM_HS_LOCK_EN

11 COM_LS_LOCK_EN

3

2

1

enable HighSide-lock

COM-Overload:

r/w

enable LowSide-lock

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Reg.-Name

Addr.

Bit-Field

Bit Reset- r/w

Value

Comment

Reference

COM-Overload:

enable HighSide-

control, to be set if

wake-up shell be

detected via over-

current activity

11 COM_OVL_HS_EN

11 COM_OVL_LS_EN

1

0

1

r/w

COM-Overload:

enable LowSide-

control, to be set if

wake-up shell be

detected via over-

current activity

AUX-Overload: time

until lock is asserted

AUX_ASSERT_TIME

AUX_MON_CTRL

12

7:0 50

6:0 63

r/w

Figure 3.17

13

AUX-Overload: time

base

13 AUX_OVL_TBASE

13 AUX_LOCK_TIME_RST

6:5

4

1

AUX-Overload: reset

r/w lock (also) time

based

AUX-Overload:

r/w

13 AUX_HS_LOCK_EN

13 AUX_LS_LOCK_EN

3

2

1

enable HighSide-lock

AUX-Overload:

enable LowSide-lock

r/w

AUX-Overload:

enable HighSide-

control, to be set if

wake-up shell be

detected via over-

current activity

13 AUX_OVL_HS_EN

13 AUX_OVL_LS_EN

1

0

1

AUX-Overload:

enable LowSide-

control, to be set if

wake-up shell be

detected via over-

current activity

r/w

IRQ_WURQ_CTRL

14

7:0 35

Figure 3.14

IRQ_PAD_MODE:

14 IRQ_PAD_MODE

7

0

r/w 0 = open-drain /

1 = push-pull

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Reg.-Name

Addr.

Bit-Field

Bit Reset- r/w

Value

Comment

Reference

WURQ_PAD_MODE:

14 WURQ_PAD_MODE

6

5

0

1

r/w 0 = open-drain /

1 = push-pull

DCDC-Ready-delay-

r/w enable / 0 = No delay

/ 1 = delay 50 ms

14 DCDC_READY_DELAY

lock only, when both

channel are in OVL-

alarm

Recommended to be

set (=1) in tandem

mode

14 BOTH_CHANNEL_LOCK

14 IRQ_NOREG

4

3

0

r/w

0 = IRQ-Port follows

r/w state-reg / 1 = IRQ

follows state-signals

Source for WURQ-

r/w detection 0 = COM /

1 = AUX

14 WURQSOURCE

2

1

0

1

WURQ detection on

r/w

14 WURQDETECT_CURRENT

current (overload)

WURQ detection on

levels (can be

combined with

current)

14 WURQDETECT_LVL

15

0

1

r/w

Overload: time until

r/w

Added in

Rev B

AUX_LOCK_TIME

7:0 100

Lock is released

STATUS REGISTER

MON_RST_LOCK_WURQ 16

4:0

4

0

w/pulse

Figure 3.14

Reset for power fail

w/pulse due to line-fault or

under-voltage

Added in

Rev B

16 MON_RST_POWER_FAIL

Reset for Wake Up

w/pulse

16 MON_RST_WURQ

3

2

1

0

Request

Reset for Channel 2

16 MON_RST_AUX_LOCK

16 MON_RST_COM_LOCK

w/pulse

Lock

Reset for Channel 1

w/pulse

Lock

Data Sheet

January 31, 2012

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Reg.-Name

Addr.

Bit-Field

Bit Reset- r/w

Value

Comment

Reference

Reset for

Temperature Lock

16 MON_RST_OVT_LOCK

17

0

w/pulse

MON_RST_COUNTER

Reset Channel2

OVL-HS-Counter

17 MON_RST_AUX_HS

17 MON_RST_AUX_LS

17 MON_RST_COM_HS

17 MON_RST_COM_LS

17 MON_RST_OVT

18

4

3

w/pulse

Reset Channel2

OVL-LS-Counter

Reset Channel1

OVL-HS-Counter

2

Reset Channel1

OVL-LS-Counter

1

0

w/pulse Reset OVT Counter

r/rst Interrupt-Status

IRQ_STATUS

7:0

7

Figure 3.14

POWER_FAIL

r/rst

Added in

Rev B

18 IRQ_POWER_FAIL

18 IRQ_WURQ

interrupt request

6

r/rst wake-up request

Valid-flag error

occurred

18 IRQ_VALID_FLAG_ERR

18 IRQ_EEPROM_ERR

18 IRQ_EEPROM2_ERR

18 IRQ_LOCK_AUX

18 IRQ_LOCK_COM

5

r/rst

Single error has been

corrected

4

r/rst

Multiple bit error

occurred

3

r/rst

over-load lock of

r/rst

2

AUX line driver

over-load lock of

r/rst

1

COM line driver

over-temperature

LOCK of both line

drivers, AUX and

18 IRQ_LOCK_OVT

0

r/rst

COM

Data Sheet

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Reg.-Name

Addr.

Bit-Field

Bit Reset- r/w

Value

Comment

Reference

MON_DEVICE_TEMP

MON_STAT

19

20

3:0

7:0

7

0

r

Device Temperature

Lock on AUX due to

AUX-Overload

20 MON_AUX_LOCK

20 MON_COM_LOCK

Lock on COM due to

COM-Overload

6

Lock on COM + AUX

due to Over-

20 MON_OVT_LOCK

5

0

r

temperature

20 MON_STAT_AUX_HS_OVL

4

3

0

r

AUX-HighSide-OVL

AUX-LowSide-OVL

COM-HighSide-OVL

COM-LowSide-OVL

Over-temperature

20 MON_STAT_AUX_LS_OVL

20 MON_STAT_COM_HS_OVL

2

r

20 MON_STAT_COM_LS_OVL

1

r

20 MON_STAT_OVT

0

r

Longest COM-LS-

Overload

MON_COM_LS_PEAK

MON_COM_HS_PEAK

MON_AUX_LS_PEAK

MON_AUX_HS_PEAK

MON_OVT_PEAK

21

22

23

24

25

26

7:0

1:0

r/rst

Longest COM-HS-

Overload

Longest AUX-LS-

Overload

Longest AUX-HS-

Overload

Longest over-

temperature duration

Added in

Rev B

MON_POW_DETECT

r/rst Power Monitor

Data Sheet

January 31, 2012

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Reg.-Name

Addr.

Bit-Field

Bit Reset- r/w

Value

Comment

Reference

26 RESERVED

7:2

0

r/rst RESERVED

26 MON_LINE_FAULT

r/rst Line fault occurred

Under voltage

r/rst

26 MON_UNDER_VOLTAGE

occurred

Manufacture Use Only

PRODUCT_ID

27:30

7:0

r

Read returns 0

Allows to retrieve

product and revision

information

Added in

Rev B

31

7:0 ID

3.3.10. Interrupt and IC Lock Mode Control

3.3.10.1. Interrupt Handling

The INT_L pin provides indication functionality for a set of IC-internal exceptions. Once an exception had

occurred, expressed as logic low of the INT_L signal, the actual cause can be evaluated by reading the IC’s

status register via the SPI interface. Depending on the condition – a reset of the exception by reading the

corresponding status register can be performed.

The following exceptions are combined in the INT indication functionality:

 Lock caused by power fail detector (refer to chapter 3.5)

 Lock caused by COM-Overload (refer to chapter 3.3.10)

 Lock caused by AUX-Overload (refer to chapter 3.3.10)

 Lock caused by over-temperature (refer to chapter 3.3.10)

 EEPROM-single-bit-error (refer to chapter 3.3.7)

 EEPROM-2bit-error (refer to chapter 3.3.7)

 Valid-flag-cleared due to possibly corrupt EEPROM (refer to chapter 3.3.7)

 WURQ detected (refer to chapter 3.3.4)

Figure 3.14 illustrates the handling of the above mentioned exceptions and their monitoring. It also shows how to

configure the interrupt (INT_L pin) and wake-up (WURQ_L pin) signal generation. Besides several exceptions

concerning channel overload, die over-temperature and IO-Link specific wake-up situations the IC can also signal

problems as regards the EEPROM.

Since the configuration registers get their content initially from the EEPROM, the data should be correct. The

following described features make sure that no corrupt EEPROM data can cause unwanted IC configurations.

Data Sheet

January 31, 2012

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An EEPROM single bit error indicates a one bit problem in the content of the EEPROM. Since the EEPROM

includes a self correction, one bit errors will be detected and corrected automatically. However, the indication shall

trigger a rewrite¹⁷of the entire EEPROM content.

The EEPROM 2-bit error indicates a two bit problem in the content of the EEPROM. That error is not

automatically corrected, so the content of the EEPROM can not be considered as correct. Thus a reprogramming

is absolutely required.

The valid-flag is used to indicate that the last write access to the EEPROM was successful. If the valid-flag

indicates a problem, then the chip configuration has to be regarded as faulty – no save IC function can be

guaranteed. Rewriting of the entire EEPROM content is necessary. In case of a regular write process to the

EEPROM is not completed, for instance by an interruption of the IC supply power within the ongoing write

process, the valid-flag will indicate this as a problem because of the EEPROM content might be corrupt.

Besides the signalization of IC-internal exceptions the IN_L pin signals also the system reset state. The system

reset state is indicated with active low on the INT_L pin.

Figure 3.14 Interrupt (INT_L pin) and Wake-up (WURQ_L pin) Signaling¹⁸

Memory

Control

DC/DC converter

reset

bit

7

0

1

IRQ_PAD_MODE

WURQ_PAD_MODE

DCDC_READY_DELAY

INL_L pin config

6

WURQ_L pin config

WURQ

5

0

BOTH_CHANNEL_LOCK

4

0

3

IRQ_NOREG

WURQSOURCE

WURQDETECT_CURRENT

0

2

INT_L pin

(low active)

0

1

0

WURQDETECT_LVL

r / w

set

WURQ Detection

Power Fail Detection

AUX_LOCK Circuit

COM_LOCK Circuit

OVT_LOCK Circuit

clear

reset

bit

7

reset

bit

0

1

IRQ_EN_POWER_FAIL

IRQ_EN_WURQ

7

6

5

4

3

2

1

0

IRQ_POWER_FAIL

IRQ_WURQ

set

6

Internal IC

Sensors for

Overload and

Over-

temperature

dectection

clear

0

IRQ_VALID_FLAG_ERR

IRQ_EEPROM_ERR

IRQ_EEPROM2_ERR

IRQ_LOCK_AUX

5

1

IRQ_EN_VALID_FLAG_ERR

IRQ_EN_EEPROM_ERR

IRQ_EN_EEPROM2_ERR

IRQ_EN_LOCK_AUX

IRQ_EN_LOCK_COM

IRQ_EN_LOCK_OVT

8

4

8

AND

(8x)

set

INT_L pin

(low active)

3

NOR

IRQ

clear

2

1

IRQ_LOCK_COM

IRQ_LOCK_OVT

set

0

clear

r / rst

r / w

set

8

State Signals

clear

lock circuit reset (influences also reg[18])

reset OVL/OVT counter only

COM OFF if IRQ_LOCK_COM == 1

AUX OFF if IRQ_LOCK_AUX == 1

Both OFF if IRQ_LOCK_OVT == 1

Driver

Protection

Circuit

4

reset

bit

7

reset

bit

7

Driver OFF

or

0

reserved

(COM and

AUX)

IRQ_POWER_FAIL == 1

6

reserved

5

reserved

5

MON_RST_POWER_FAIL

MON_RST_WURQ

MON_RST_LOCK_AUX

4

MON_RST_AUX_HS

MON_RST_AUX_LS

MON_RST_COM_HS

MON_RST_COM_LS

MON_RST_OVT

3

A write access to the MON_RST_LOCK_WURQ/MON_RST_COUNT

register leads to a reset of the circuit that is associated with the for this

partial functionality assigned register bit if the write-data contain a 1 at to

this bit corresponding bit position.

2

0

MON_RST_LOCK_COM

MON_RST_LOCK_OVT

1

0

w / pulse

For example, writing 0x08 to MON_RST_LOCK_WURQ will reset a

detected WURQ exception but not a possibly performed lock with respect to

the COM-channel, AUX-channel, and the over-temp detection circuit.

SPI

eset via

Partial R

¹⁷Note: IC versions ZIOL2xx2 do not allow any write access.

¹⁸The in this an in the following figures used symbols for the IC registers are explained in Figure 9.1.

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

Data Sheet

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The WURQ indication is a dedicated IO-Link functionality. A WURQ event is indicated if an over current situation

with a determined timing – regarding to IO-Link Communication Specification happened on one of the output

driver stages (refer to chapter 3.3.4, 3.3.10.1 and 8). A WURQ event will be created if there is either a timely

limited (typical 80µs) different logical value between the logical output value of the driver and the received logical

value from the line or an also timely limited (typical 80µs) over-current at the considered channel. It can be

configured whether the first or the last or both conditions lead to a WURQ event.

3.3.10.2. IC Lock Mode Configuration and Monitoring

If the current through the output driver exceeds the configured limit, an exception will be generated. In addition to

that and depending on the Ics configuration, the lock mode operation which corresponds to the overloaded

channel can be performed (refer to Figure 3.15 and Figure 3.16). The above mentioned lock mode operation is

activated if either one driver stage (HS or LS) or both drivers stages (HS and LS stage) are overloaded, means

the output current exceeds the configured limit.

If the event occurs, the corresponding driver stage will be set to a save state, meaning it will be disabled.

The Lock mode configuration as shown in the following figures (Figure 3.15, Figure 3.16, Figure 3.17) is based on

configurable current limits and time periods.

Data Sheet

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Figure 3.15 COM Channel Lock Control¹⁹

COM_HS_OVL

AND count

High side

stage

reset

bit

7

From COM_HS overload

detector

0

:

if input signal

==1

== 0

6

:

- no overrun

5

rst

1

8

- no underrun

Counter reset with

- write access to

4

[6:5]

MOM_COM_HS_PEAK

SPI

0

3

1

0b00: 200 ns

0b01:

0b10:

Peak values

0

2

COM_HS

(8bit)

1 ms

8 ms

MON_RST_COUNTER [17]

Data = 0bxxxxx1xx

- 0à1 transition of

0

1

0

0b11: 16 ms

r / rst

COM_OVL_HS_EN

Counter reset with

- write access to

2

8

2

MON_RST_COUNTER [17]

Data = 0bxxxxxx1x

- 0à1 transition of

COM_OVL_LS_EN

Comparator

Counter == Assert_time

Enables time based lock reset

reset

bit

7

0

reseved

6

COM_OVL_TBASE

AND

0

5

Driver OFF

set

0

4

COM_LOCK_TIME_RST

COM_HS_LOCK_EN

COM_LS_LOCK_EN

COM_OVL_HS_EN

COM_OVL_LS_EN

OR

0

3

0

2

0

1

To register IRQ_STATUS

0

r / w

8

reset

bit

7

1

AND

clear

Lock counter

6

Comparator

8

5

Counter == Assert_time

4

COM_ASSERT_TIME

8

1

3

0

2

1

0

r / w

Low side

stage

reset

bit

7

reset

bit

0

1

7

6

5

4

3

2

1

0

6

0

5

1

8

0

4

1

MOM_COM_LS_PEAK

COM_LOCK_TIME

0

3

1

Peak values

rst

2

0

2

0

COM_LS

(8bit)

SPI

0

1

From COM_LS overload

detector

0

r / rst

r / w

AND count

COM_LS_OVL

AUX-Channel

¹⁹The COM transmitter is only available inside the products ZIOL24xx/22xx

Data Sheet

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Figure 3.16 AUX Channel Lock Control²⁰

AUX_HS_OVL

AND count

High side

stage

reset

bit

7

From AUX_HS overload

detector

0

:

if input signal

==1

== 0

6

:

- no overrun

5

rst

1

8

- no underrun

Counter reset with

- write access to

4

[6:5]

MOM_AUX_HS_PEAK

SPI

0

3

1

0b00: 200 ns

0b01:

0b10:

Peak values

0

2

AUX_HS

(8bit)

1 ms

8 ms

MON_RST_COUNTER [17]

Data = 0bxxx1xxxx

- 0à1 transition of

0

1

0

0b11: 16 ms

r / rst

AUX_OVL_HS_EN

Counter reset with

- write access to

2

8

2

MON_RST_COUNTER [17]

Data = 0bxxxx1xxx

- 0à1 transition of

AUX_OVL_LS_EN

Comparator

Counter == Assert_time

Enables time based lock reset

reset

bit

7

0

reseved

6

AUX_OVL_TBASE

AND

0

5

Driver OFF

set

0

4

AUX_LOCK_TIME_RST

AUX_HS_LOCK_EN

AUX_LS_LOCK_EN

AUX_OVL_HS_EN

AUX_OVL_LS_EN

OR

0

3

0

2

0

1

To register IRQ_STATUS

0

r / w

8

reset

bit

7

1

AND

clear

Lock counter

6

Comparator

8

1

5

Counter == Assert_time

1

4

AUX_ASSERT_TIME

8

1

3

0

2

1

0

r / w

Low side

stage

reset

bit

7

reset

bit

0

1

7

6

5

4

3

2

1

0

6

0

5

1

8

0

4

1

MOM_AUX_LS_PEAK

AUX_LOCK_TIME

0

3

1

Peak values

rst

2

0

2

0

AUX_LS

(8bit)

SPI

0

1

From AUX_LS overload

detector

0

r / rst

r / w

AND count

AUX_LS_OVL

COM-Channel

²⁰The AUX transmitter is only available inside the products ZIOL24xx/21xx

Data Sheet

January 31, 2012

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Figure 3.17 Over-Temperature Lock Control

MON_OVT_PEAK [25]

>S<

Over-Temperature Counter

OVT

AND count

reset

bit

7

From Over-Temperature

detector

0

Count-up:

if input signal count ==1

if input signal count == 0

Over-

Temperature

Counter

0

6

Count-down:

- no overrun

- no underrun

0

5

OVT_TIME_BASE

[6:5]

rst

1

8

0

4

MON_OVT_PEAK

SPI

0

3

Counter reset with

- write access to

1

0b00: 200 ns

Peak values

0

2

0b01:

0b10:

1 ms

8 ms

(8bit)

8

0

1

MON_RST_COUNTER [17]

Data = 0bxxxxxxx1

- 0 1 transition of OVT_EN

0

0b11: 16 ms

r / rst

2

Power

Fail

Detector

2

OVT_PFD_CTRL [09]

Comparator

Counter == Assert_time

>C<

reset

bit

7

AND

set

0

reseved

LINE_FAULT_EN

To register IRQ_STATUS

6

5

UNDER_VOLTAGE_EN

4

OVT_TBASE

3

Enables time based lock reset

0

2

OVT_LOCK_TIME_RST

OVT_LOCK_EN

OVT_EN

AND

clear

Lock counter

0

1

0

r / w

8

OVT_ASSERT_TIME [08]

>C<

OVT_LOCK_TIME [05]

>C<

8

reset

bit

7

reset

bit

7

1

6

1

5

1

5

1

4

1

4

OVT_ASSERT_TIME

OVT_LOCK_TIME

1

3

1

3

0

2

0

2

1

0

r / w

The Lock caused by an over-temperature displays that the die temperature has reached a critical level. That

forces a self protecting save state, it causes disabling the COM and the AUX channel by turning off all the HV

driver output stages (Figure 3.17).

The IC configuration allows disabling the lock mode operation for overload exceptions from both channels

(COM/AUX) and the exception from the die over-temperature detector. Since the lock mode operation prevents

the IC to be destroyed due to physical stress situation, the disabling is not recommended or shall be done with

particular caution only.

Disabled lock mode operations for the above mentioned building blocks will prevent generating the related

contribution to the interrupt signal at the INT_L pin. However, those exceptions can be retrieved by reading the

status register MON_STAT[20] (refer to chapter 3.3.9 and/or Figure 3.18).

Not depending on the lock mode operation the IC allows retrieving diagnostic information about the duration of an

exception (peak values). The corresponding IC configuration that is required for retrieving such diagnostic data is

illustrated above figures (Figure 3.15, Figure 3.16, and Figure 3.17).

Data Sheet

January 31, 2012

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3.3.10.3. Overload and Over-Temperature Configuration and Monitoring

The ZIOL2xxx is dedicated to work in harsh industrial environments. Several situations can cause serious stress

to the IC which may lead to partly or complete damage of the IC. In order to minimize the impact of physical stress

the IC generates exceptions if the HV drivers exceed the configured current limits or if finally the die temperature

exceeds a certain configured value (for more details refer to chapter 3.3.11). The status register MON_STAT[20]

reflects all currently occurred exceptions. Status register MON_DEVICE_TEMP[19] allows reading of the current

die temperature.

Data Sheet

January 31, 2012

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Figure 3.18 Internal IC Sensors and related Overload and Over-Temperature Detection Circuits²¹

High side current limit exceeded

V_DD

AUX_HS_OVL

A

s

r

AUX_LOCK Circuit

A

V_SS

Low side current limit exceeded

AUX_LS_OVL

COM_HS_OVL

High side current limit exceeded

V_DD

reset

bit

7

A

0

MON_AUX_LOCK

MON_COM_LOCK

MON_OVT_LOCK

6

5

set

0

4

MON_STAT_AUX_HS_OVL

MON_STAT_AUX_LS_OVL

MON_STAT_COM_HS_OVL

MON_STAT_COM_LS_OVL

MON_STAT_OVT

3

s

r

COM_LOCK Circuit

2

1

0

r

A

V_SS

Low side current limit exceeded

COM_LS_OVL

Over-Temperature (OVT)

Master Mode Control

(data path switches)

Die

Temperature

[3:0]

red

reset

bit

reset

0

bit

0b0000: blue

0b0001: green

0b0011: yellow

0b0111: orange

0b1111: red

0

7

MASTER_MODE

reserved

orange

yellow

green

6

0

6

5

4

3

2

1

0

EN_FOLLOW_PRIM_CH

PRIMARY_MASTER_CH

reserved

5

0

4

0

3

2

0

s

r

0

OVT_LOCK Circuit

DIE_TEMP

OVER_TEMP

1

0

1

r

r / w

²¹The COM transmitter is only available inside the products ZIOL24xx/22xx and the AUX transmitter is only available inside the products

ZIOL24xx/22xx, respectively

Data Sheet

January 31, 2012

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3.3.11. Die Temperature Measurement

Figure 3.18 illustrates the die temperature measurement of the ZIOL2xxx IC. The die temperature is measured

with an on-chip sensor right in the center of the silicon die. Since there is one temperature sensor which has a

certain distance to all the different locations that produce heat (due to dissipated electrical power), the sensor can

only indicate a rough average value of the die temperature. This shall be considered in defining the alarm values

for the over-temperature counter and in defining the over-temperature lock mode duration.

In combination with four comparators the temperature sensor circuit provides five temperature levels that

correspond to certain temperatures as described in Table 3.8. The current die temperature (level) can be retrieved

in reading the status register MON_DEVICE_TEMP[19].

Table 3.8 Temperature Sensor Levels

Temperature Typical Trigger

Min.

Max. Unit MON_DEVICE_TEMP[19] Remarks / OVER_TEMP

Level

Temperature

Trig.

value

value for over-

temperature exception

2)

Value¹⁾

Blue

< 95

°C

0b0000

No comparator level

reached

Green

Yellow

Orange

Red

> 100

> 110

> 120

> 130

n.a.

95

105

115

125

135

n.a.

°C

0b0001

0b0011

0b0111

0b1111

0bxxxx

0b0001

0b0010

0b0100

0b1000

0b0000 ⁴⁾

105

115

125

n.a.

°C

Software-Test

1)

n.a.

The mentioned typical values of IC properties shall not be considered as statistical guaranteed mean values.

The tolerance (deviation from the typical trigger value) is ±5°C. The deviation is for all trigger values the same. This means for

example that in extreme situations all trigger levels equal the min. temperature or the max. temperature trigger value.

Setting configuration register[7][3:0] = 0b1111 will cause an over-temperature exception immediately. This setting is supposed to

be used while software development and not supposed to be used in regular operation.

2)

3)

4)

There is a deviating code 0b1111for the software test which valid for Rev A only.

The configuration-register OVT_TEMPERATURE defines what temperature level causes an over-temperature

exception (Figure 3.18/Table 3.8). This configuration feature ensures a flexibility of the IC in various application

cases.

Depending on the IC configuration an over-temperature can cause disabled HV drivers in order to prevent the IC

against damage. Besides the DC/DC converter all other IC building feature will still function, also if a over-

temperature exception has been detected²². Thus all control and diagnostic functions are still available if the IC is

being overheated.

3.4.

Smart Power Supply

The internal low voltage supply of the chip is 3.3V and generated by an on chip linear regulator. In order to

decouple this voltage a capacitor needs to be connected externally. Since the regulator supports more load

current than the IC requires itself, a certain current can be drawn by the external application (Table 2.2).

²²This security shutdown of the DC/DC converter is not implemented in the IC revision A but prearranged for later easy implementation.

Data Sheet

January 31, 2012

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In order to reduce power dissipation, caused by the voltage drop above the regulating transistor, the regulator can

be powered with an input voltage less than V_{DD_HV}. If for example the on-chip DC/DC converter is in use and its

output voltage is set to at least 5V, then the linear regulator can be powered with this output voltage.

The electrical characteristics are shown in the chapter “operating conditions” (chapter 1).

The following block schematic (Figure 3.19) shows the principle of the low voltage generation in conjunction with a

possible usage of the on chip DC/DC converter. For more information about required external components refer to

chapter 4.

Figure 3.19 Low Voltage Supply Concept

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3.5.

The Power Fail Detector

3.5.1. Overview

The Power-Fail detector function is split into two tasks. The first task is the “Line-Fault” (LF) detection which shall

recognize a situation in which the ZIOL2xxx is not powered regularly. This situation can happen if for instance the

wiring between device and host port is not performed in the right way (interchanged wires, broken wires).

The second task is the “Under-Voltage” (UV) detector which monitors the supply voltage at the VDD pin of the

ZIOL2xxx. The purpose of this detector is ensure a proper working of the HV drivers COM and AUX which is not

guaranteed if the supply voltage at VDD drops below the allowed minimum value.

Figure 3.20 illustrated the working principle of both the LF and the UV detector in combination with the further

processing to the detected events (LINE_FAULT and UNDER_VOLTAGE). Based on the IC configuration

(LF_ENABLE, UV_ENABLE flags) each event (or both events) may activate the lock for both channels exactly for

the period the respective event is present. The new status register [26] allows diagnosing what event is present or

was present in the past.

Figure 3.20 PFD Working Principle

3.5.2. Line-Fault Detector

The Line-Fault (LF) detection feature assumes the utilization of both channels in device mode. In the case one

channel is used only, the number of detectable failures be reduced accordingly. For more information about

detectable failures, please refer to the Appendix C.

The optional (configurable) detection of the situation of an abnormal power supply of the IC will be achieved by a

ratiometric working voltage sensor. As sensor input works the PFD pin (formerly M_EN) in combination with two

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“sense” resistors which are interconnected to the L+ and L- pin of the sensor/actuator device. Those resistors

provide a voltage divider. The so downscaled supply voltage (voltage at the pin PFD) is compared with the output

voltage of an IC-internal voltage divider. In case of abnormal power supply of the IC (refer to Figure 3.20) a

window comparator will detect this situation as LINE_FAULT event. The further processing of the LINE_FAULT

event depends on the LF_ENABLE configuration flag (Figure 3.20). A Power-Fail Lock (LOCK_PF) will be

generated only if the duration of the so detected abnormal power supply (or break of power supply) is longer than

10ms (Figure 3.20).

3.5.3. Under-voltage Detector

The IC has a Power-on-reset circuit which puts the IC in RESET state while power-on, or if the internal (core)

supply voltage of 3.3V (voltage at LR_OUT) drops below a critical value. For example with VDD = 5V the internal

3.3V power supply may not be jeopardized thus the IC control will work as usual. In this situation the under-

voltage detection shall protect the HV driver which may not work correctly with VDD < 8V and which might have a

chance to get damaged in this situation. If configured the Under-Voltage detector will avoid this situation by

locking both driver channels.

3.5.4. Channel Locking and Interrupt Generation

As mentioned in chapter 3.5.1 both channels can be locked if one or both of the events LINE_FAULT and

UNDER_VOLTAGE occur. In this case the resulting signal LOCK_PF (refer to Figure 3.20) will be stored in the

IRQ_STATUS status register [18][7] (refer to Table 3.7). Depending on the IRQ_ENABLE configuration register

[0][7] or on IRQ_NOREG (configuration register [14][3]) and interrupt (pin INT_L ) can be issued.

3.5.5. Downward Compatibility

The introduction of the PFD in IC Rev B goes in parallel with the conversion of the formerly master enable (M_EN)

pin to a voltage sense pin (PFD pin). Therefore the master enable /disable function must be defined by using a

configuration flag. Since old PCB designs are using the M_EN interconnection either to VDD/LR_OUT or VSS

(enabling/disabling the master functionality), the LF feature cannot be used.

3.6.

DC/DC Converter²³

3.6.1. Principle of Operation

The on chip DC/DC converter is a constant frequency (2.5MHz) buck converter with an adjustable output voltage.

The wide input voltage range of 8V to 36V, a minimized output ripple (< 25mVpp), and the maximum output

current of 50mA make the converter suitable for standard sensor/actuator applications. The output voltage can be

adjusted with an external voltage divider.

The electrical characteristics are shown in the chapter “operating conditions” (chapter 1).

The DC/DC converter can be disabled if the application does not require this functionality. In order to do this the

FB pin shall be connected to the 3.3V LV power supply output (pin LR_OUT).

²³Only available with IC versions ZIOL240x/220x/210x

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The converter runs independently from the two driver channels (COM/AUX) and their digital control state

machine. A reset has no influence on the DC/DC converter.

3.6.2. Principle of Operation

Figure 3.21 shows the working principle of the DC/DC converter. Required external components are described in

chapter 3.6.3.

Figure 3.21 DC/DC Converter in Principle

The DC/DC converter senses the output voltage divided by the resistors R1 and R2 at pin FB. The difference

between this signal and the reference voltage is amplified and then transformed into a PWM signal by comparing

it with a triangular waveform. The PWM signal now enables and disables the output transistor. This results in a

pulse length modulated signal with an amplitude of V_{DD_HV}and –V_D(the Schottky diode forward drop) which is

then been filter via a second order LC filter to generate the output voltage V_OUT

.

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The capability of the output driver of the DC/DC converter is limited to 200mA (refer to parameter I_PKin Table 2.3).

Operating at this limit must be limited in time. Since the DC/DC is not shut down when the die-temperature

exceeds the configured limit, the application circuit hardware and software design must make sure that no IC

damage can occur.

In the start-up phase of the IC (power-on-reset) the DC/DC converter control moves to a soft-start regime which

limits the current that charges the capacitor at the V_OUTvoltage. This is done by increasing the reference voltage

and thus the output voltage follows that reference in a controlled manner.

The DC_RDY pin provides information on the state of the output voltage. If the DC/DC converter is overloaded

(V_OUTdrops below 85% of the nominal value), DC_RDY is low. In addition to that DC_RDY is kept on logic low

level if the IC is in power-on-reset. In this power-on-reset case and only in this case the converter is restarted.

The rising edge of DC_RDY signal can be delayed by 50ms (+/- 5%). This delay function is configurable with bit 5

of the configuration-register IRQ_WURQ_CTRL[14] (refer to Figure 3.14). The IC manufacturer default value for

this bit is ‘1’ thus the delay function is enabled by default. If DC_RDY is low during re-configuration of the IC and

the delay is not yet finished, it stays low. The falling edge of the DC_RDY signal will not be delayed thus is not

affected by bit 5 of the configuration-register IRQ_WURQ_CTRL[14].

3.6.3. Dimensioning of external Devices

The output capacitor C1 acts as filter capacitor. It has to have low equal series resistance (ESR) thus a ceramic

capacitor with a 10µF capacitance has to be chosen. The ESR has influence on the output ripple. The higher the

ESR the higher is the output ripple. The self-resonant frequency of the capacitor shall be as high as possible. It is

possible to have a 100nF block capacitor (C2) in parallel to C1 to increase its frequency behaviour.

The Schottky diode acts as freewheeling diode. Therefore, it shall have a low voltage drop to increase efficiency.

A low parasitic capacity or a fast reverse recovery time increase the efficiency by preventing a large shoot-through

current through the output transistor and the diode when switching on the transistor.

The voltage divider provides the feedback voltage for the DC/DC converter. R2 shall be ~10kΩ. R1 can be

calculated by

V





OUT ,set

R₁ R₂

1 _.





1,225V





The tolerance of the resistors affect the tolerance of the output voltage thus resistors with 1% tolerance are

preferred. Figure 3.22 illustrates the DC/DC converter output voltage (including its tolerance range) as function of

R1 for R2 = 10kOhms.

Table 3.9 Examples for the resistors R1 and R2 using E96 resistor series

V_OUT,set

3.3V

5V

R1

R2

18.2kΩ

38.3 kΩ

10.5 kΩ

12.4 kΩ

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Figure 3.22 DC/DC Converter Output Voltage as Function of R1 (R2 = 10kOhms)

15,00

14,00

Max

13,00

12,00

11,00

10,00

Min

9,00

8,00

7,00

6,00

5,00

4,00

3,00

10

20

30

40

50

60

70

80

90 100 110 120 130

R1 /kOhms

The inductor stores energy when the output transistor is conducting and releases the energy if the transistor is

switched off. For most applications a 10µH inductor is sufficient. To reduce the electromagnetic interference or to

reduce the ripple voltage of the output voltage, the required inductance is calculated by

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



V_{OUT ,set}







L_min 1

,





V_{DD _ HV ,max}2 f_Sw I_{OUT ,min}





where I_OUT,minis the lowest output current, V_{DD_HV,max}is the highest input voltage and f_Swis the switching frequency

of the DC/DC converter.

3.6.4. PCB Layout considerations

To achieve optimal parameters for the DC/DC converter (e.g. efficiency or ripple voltage), attention has to be

given to the PCB layout. Figure 3.23 shows the DC/DC converter, its external elements and two high frequency

loops. The length of each loop has to be as short as possible. Furthermore, the distance between SW and FB has

to be as large as possible to decrease the interference. It is recommended to have ground planes in between

each signal line.

Figure 3.23 High frequency critical loops of DC/DC converter for PCB layout

VDD

V_{DD_HV}

Loop 1

C5

L1

V_OUT

SW

FB

R1

R2

C1

C2

D1

Loop 2

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Figure 3.24 PCB layout of Evaluation board as an example

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4

Application Information

ZIOL2xxx application circuits contain usually external components, which are required for overvoltage and

reverse polarity protection. Table 4.1 provides a summary about requires components. The in the following figures

used external components, in particular the special component type and it parameters are mentioned in this

table.. The following schematics show standard application circuits in principle with the focus to the interface part

of the physical level transceiver performed by the ZIOL2xxx Ics..

Figure 4.1 Simplified Application Circuit with the ZIOL2xxx in Device Mode

In principle an IO-Link device cable interface (or the interface for a standard sensor/actuator) requires four (one

channel) or six (Two channels) protection diodes. The diodes D4 … D7 are fast clipping schottky diodes. Those

highly recommended diodes damp signal overshoots and make sure that in IO-Link device applications the device

can detect supply power failures as illustrated in Figure 4.3. D2 and D3 provide the reverse polarity protection for

the device unit as shown in Figure 4.1.

Since there is normally no chance in IO-Link master applications to apply the supply voltage in reverse manner,

the reverse polarity protection diodes D2 and D3 can be omitted in master applications (Figure 4.2). With respect

to Figure 4.1 and Figure 4.2 the PFD pin (prior IC Rev B called M_EN pin) is connected to power or ground as it

was required in using Rev A. Using this way of interconnections of the PFD pin requires disabling of the line-fail

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feature (refer to chapter 3.5). In case the line fail feature is intended to be use the PFD shall be connected to a

voltage divider as described in chapter 3.5 or illustrated in Figure 4.3.

Figure 4.2 Simplified Application Circuit with the ZIOL2xxx in Master Mode

In case of (IO-Link) device applications the IC might be powered not correctly via the L+/L- line. The circuit in

Figure 4.3 illustrates how to detect this power fail situation by using a voltage divider as “sensor”. Since the

voltage at the PFD pin is compared with an internal voltage divider resistors with low tolerace range (<= 1%) shall

be used.

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Figure 4.3 Power Line Fail Detection

Vout

L1

R3 and R4 which perform

the line voltage sensor

shall connected directly to

the cable (L+/L-).

R1

C2

C1

D1

C3 C4

R2

Standard

Cable

SW

FB

LR_IN

LR_OUT

VDD

D2

DC_RDY

L+

C5

RST_L

INT_L

D6

R3

D4

D5

TX_EN

TX

COM_O

COM_I

C/Q

ZIOL2401

RX

WURQ

AUX_O

AUX_I

AUX_TX

R4

D7

AUX_EN

AUX_RX

VSS

L-

PFD

D3

Device (Sensor)

The PCB layout design requires considering several recommendations. In particular the placement of decoupling

capacitors and the placement external components that perform the DC/DC converter circuits shall be done

carefully. Recommendations are:



Low resistive and low inductive ground interconnections due to metal ground areas surrounding the IC

or/and using a special “Ground” PCB layer.



The wiring of the channel driver output shall consider that the wires are designed for currents up to

500mA (depending on the IC configuration) and in combination with that wiring for VDD and VSS shall

designed for currents up to 1A.



Decoupling capacitors related to the IC pins VDD and LR_OUT (and LR_IN if applicable) shall placed

as close as possible to the IC pin.

The DC/DC converter requires an external Schottky-diode as free-wheel diode. Its anode shall be

interconnected to the SW pin. It is important that its cathode has good (short) ground connection. With

respect to all to the SW pin interconnected devices (free-wheel diode and inductor L1) all wires have to

be kept as short as possible. Moreover, the PCB design shall make sure that the parasitic coupling

between the node belonging to the SW pin and the node belonging to the FB pin of the IC is

minimized.

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

The voltage divider R1/R2 shall interconnected to the FB (feedback pin) in that way that the

electromagnetic coupling to the wire interconnected to the SW pin is low as possible.

In order to achieve an optimal heat distribution form the IC to the environment it is strongly

recommended to place via’s underneath the QFN package. An example as regards this PCB design

detail is illustrated in Figure 4.4 (2-layer PCB example). Please refer to applications notes of the

package manufacturer AMKOR for more details how to place cooling via’s underneath the IC package

(please visit the link mentioned in chapter 8, [4]).

Figure 4.4 PCB Layout Recommendations

D1

L1

Schottky Diode

10µH

38.3KW

12.4KW

10µF / 10V (low ESR)

100nF

10µF / 10V (low ESR)

100nF

10µF / 50V (low ESR)

100nF

TMMBAT42

C3

(close to pin 21 of ZIOL2401)

( DC/DC converter output

voltage Vout = 5V )

R1

R2

C1

C2

C3

C4

C5

C6

C5

C4

D1

C6

2-layer PCB

4-layer PCB

Application

Example

C1

L1

Vout = 5V

L1

R1

C2

C1

D1

C3 C4

R2

C6

C5

SW

FB

LR_IN

LR_OUT

VDD

DC_RDY

C5

C6

RST_L

INT_L

C3

TX_EN

TX

COM_O

COM_I

ZIOL2401

RX

ZIOL

2401

WURQ

AUX_O

AUX_I

AUX_TX

C2

C1

AUX_EN

AUX_RX

VSS

L1

D1

M_EN

R2/R1

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Figure 4.4 shows two layout variants as regards the component placement in the case the DC/DC converter is

used in the application circuit. The in this figure shown PCBs are the PCBs of the ZIOL2xxx application kits

(ZIOL2xxx LabKit: 2-layer-PCB/ ZIOL2xxx USB-Stick: 4-layer-PCB). The complete PCB documentation of the

applications kit is available at ZMDI upon request and is part of the documentation package of the application kits.

Another more optimized PCB layout recommendation for utilizing the on-chip DC/DC-converter shows Figure 3.24

in chapter 3.6.4. An appropriated explanation about the considerations behind this recommendation is give in this

chapter as well and illustrated in Figure 3.23.

Table 4.1 Recommended External Components

Symbol

Parameter

Min

Typ

Max

Unit

Notes

R1

R

14 ¹⁾

112 ²⁾

kΩ

Value depends on desired output

voltage.

R2

R3

R4

L1

R

L

10

kΩ

µH

-1%

10

49.9

210

+1%

50

Low tolerance range resistor (1% class)

Optimal value depends on application

requirements.

C1

C2

C3

C4

C5

D1

C

10

50

µF

nF

µF

nF

µF

Low ESR recommended

Low ESR required

C

100

10

C

Low ESR recommended

Low ESR required

C

100

10

C

Low ESR recommended

Schottky Diode

Recommended: small signal low cap

schottky diode, e.g.

V_RRM

I_F

40

V

A

TMMBAT48 (SGS-THOMSON) or

similar device

0.2

D2, D3

Schottky Diode

Only in device applications

Recommended:

10BQ040PBF (Vishay) or similar device

V_RRM

40

1.0 ³⁾

V

A

I_F

D4 – D7

Schottky Diode

Recommended:

BAT64-04W (ٛ nfineon) or similar

device,

V_RRM

I_F

40

V

A

0.1

The BAT64-04W has a SOT323

package with two diodes in series. Thus

there only one component for one

channel (one dual diode for D4/D5 and

one dual diode for D6/D7).

Q1

Optocoupler

ACPL-217 (Avago Technologies)

1)

R2 = 10kΩ, please refer to minimum output voltage V_outin Table 2.3

R2 = 10kΩ, please refer to maximum output voltage V_outin Table 2.3

Two channels in operation, each channel drives max. current

IMPORTANT: The ratio R4/R3 shall be 4.2084 +/- 2%

2)

3)

4)

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5

Pin Configuration, Latch-Up and ESD Protection

5.1.

Pin Configuration and Latch-up Conditions

Table 5.1 Pin Configuration and Latch-Up Conditions

Name¹⁾

Description

Remarks

Usage¹⁾/

Application Circuit Restrictions

and/or Remarks

Connection ³⁾

11, 20

VDD (x2)

Positive external supply Supply IN

voltage pins (HV⁴⁾)

Required/-

Both pins must be interconnected

using a low impedance wiring

14, 17

n.a.

VSS (x2)

VSS

Negative external supply Ground

voltage pins

Required/-

Both pins and the exposed die

paddle must be interconnected

using a low impedance wiring

Exposed die paddle

Ground

Required

Requirements:

- to be connected to VSS

- cooling via’s underneath the die

paddle (refer to application note

from Amkor (refer to [4] in chapter

8)

24

15

RST_L

PFD

Reset Input

Digital IN

L-active

Required or

open/-

Pin tolerates 5V logic signals

Power Fail Detector

(sense input of the line-

fail detector)

Analog IN

Required/

HV analog input pin, avoid long

VDD, LR_OUT or wires in order to optimize the

VSS (Rev A

EMC behavior

compatibility) or

Voltage divider

7

8

9

4

5

6

SPI_EN_L

INT_L

SPI enable

Digital IN

L-active

Required/-

Pin tolerates 5V logic signals

Overload indication

Wake up detect signal

Digital OUT Required or

open/-

L-active

Digital OUT Required or

WURQ_L

open/-

L-active

TX_EN/SPI_CLK COM driver enable

Digital IN

H-active

Required/-

Pin tolerates 5V logic signals

TX/MOSI

RX/MISO

TX: Data input

MOSI: SPI IN

Digital IN

Required or

open/-

RX: Data output

MISO: SPI OUT

Digital OUT Required or

open/-

12

13

1

COM_I

COM_O

AUX_EN

COM driver IN

HV⁴⁾IN

Required or

open/-

COM driver OUT

AUX driver enable

HV⁴⁾OUT

Required or

open/-

Digital IN

H-active

Required/-

Pin tolerates 5V logic signals

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2

Name¹⁾

AUX _TX

AUX _RX

AUX_O

AUX _I

DC_RDY

SW

Description

TX: Data input

Remarks

Usage¹⁾/

Application Circuit Restrictions

and/or Remarks

Connection ³⁾

Digital IN

Required or

open/-

Pin tolerates 5V logic signals

3

RX: Data output

AUX driver OUT

AUX driver IN

Digital OUT Required or

open/-

18

19

23

21

22

HV⁴⁾OUT

Required or

open/-

HV⁴⁾IN

Required or

open/-

DC/DC ready signal

DC/DC switch OUT

DC/DC feed back

Digital OUT Required or

open/-

HV OUT

Required or

open/-

FB

Analog IN

Required / either In operation mode of the DC/DC

interconnected converter the voltage divider shall

voltage divider or provide 1.225V at the FB pin.

to LR_OUT

Interconnecting FB to LR_OUT

will disable the DC/DC converter.

16

10

LR_IN

Linear regulator Input

Voltage (HV⁴⁾)

Supply IN

HV

Required/-

LR_OUT

Linear regulator Output

Supply

OUT LV

Required/ Block

Cap to VSS

Voltage (LV ⁵⁾

)

1)

2)

3)

4)

5)

Names of low active digital I/O pins end with “_L”

Usage: If “Required” is specified, an electrical connection is necessary – refer to the application circuits

Connection: To be connected to this potential, if not used or no application/configuration related constraints are given

HV: High voltage – The primary supply voltage of the IC or the voltage swing of the cable signal, typically 24V (>8V, <36V)

LV: Low voltage – The supply voltage for the internal building blocks of the IC or control signals of the IC, typically 3.3V

5.2.

ESD-Protection

All pins have an ESD protection of >2000 V.

ESD protection referred to the Human Body Model (HBM) is tested with devices in QFN24 packages during

product qualification. The ESD test follows the Human Body Model with 1.5 kꢀ/100 pF, based on MIL 883,

Method 3015.7.

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6

Package

6.1.

Pin Hardware Configurations

In contrast to the integrated circuit product ZIOL2401 which is base IC for the ZIOL2401 IC family, not all derived

Ics provide all electrical pin interconnections as provided with the ZIOL2401. Table 6.1 shows what pins are not

connected (n.c.).

Table 6.1 Availability of Pin Interconnections

ZIOL

PCB Design

Recommendations for

not connected (n.c.)

Pins

240x

1) 2)

241x

1) 2)

220x

1) 2)

221x

1) 2)

210x

1) 2)

211x

1) 2)

Number

Name

+

n.c.

+

n.c.

+

Connect to VSS

Do not connect

12

13

19

18

21

22

COM_I

COM_O

AUX_I

AUX_O

SW

+

n.c.

+

n.c.

+

n.c.

+

n.c.

+

FB

1)

2)

“+”:

Pin is in connected, regular use as mentioned in this datasheet

“n.c.”: Pin is not connected, the PC design recommendations shall be considered

6.2. Pin Diagram

The standard package of the ZIOL2xxx is a “sawn type” 24 pin MicroLeadFrame package (Amkor, QFN24): It is a

green package having a 4mm body width and a lead pitch of 0.5 mm (refer to [3] in chapter 8).

Wit respect to the different pin hardware configurations of certain Ics of the product family ZIOL2xxx not all pins

are interconnected with the silicon die (for more information refer to Table 6.1). the pin diagram shown in Figure

6.1 does not reflect this or can be considered as the pin diagram of the ZIOL2401.

Data Sheet

January 31, 2012

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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Figure 6.1 Pin Diagram of the ZIOL2xxx

6.3. Optimal PCB Layout

In order to obtain optimal heat distribution (minimized thermal resistance between package and board) certain

PCB layout rules shall be applied. Those rules are described in the application note for the used QFN package

(refer to chapter 8, [4]). Crucial for optimal heat distribution is the correct number, diameter and placement of via’s

underneath the exposed die paddle as described in the above mentioned application note.

Data Sheet

January 31, 2012

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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6.4. Package Outline

The IC is packaged in a 24 pin QFN package (Figure 6.2, based on JEDEC MO-220) having dimensions as

shown in Table 6.2.

Figure 6.2 Package Dimensions

Table 6.2 Package Dimensions in mm

Dimensions min

max

A

0.80

0.00

0.18

0.90

A₁

b

0.05

0.30

e

0,5nom

H_D

H_E

L

3.90

0.35

4.10

0.45

Data Sheet

January 31, 2012

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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6.5. Device Marking

Figure 6.3 illustrates the device top marking which reflects:



First line:

The product type (ZIOL2xxx, xxx: refer to Table 1.1)

and

product revision identification (last letter, e.g. “B” for Rev B)



Second line: The date code (“YYWW” = Year / Workweek),

“E” stands for “engineering sample” if applicable

Third line: IC manufacture’s traceability code (XXXXX)

Figure 6.3 Top Marking of the ZIOL2xxx

The ZIOL2xxx has no bottom marking.

Data Sheet

January 31, 2012

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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7

Ordering Information

Product Sales Code¹Description

Package

1)

ZIOL2xxx#R

ZIOL2xxx#W

ZIOL2xxx, ZIOL2xx - IO-Link compliant HV Line Driver IC Family,

QFN24, 4x4

packing: 13’’ reel

1)

ZIOL2xxx, ZIOL2xx - IO-Link compliant HV Line Driver IC Family,

packing: 7’’ reel

QFN24, 4x4

ZIOL2401-Lab Kit

ZIOL2401 LabKit for detailed lab evaluation ^{(suitable for}ZIOL2xxx)

(configurable IC-/Communication/Controller PCB, software, USB-cable)

ZIOL2401-Starter Kit ZIOL2401 Introduction tool (USB stick, extension board, software) ^{(suitable for}

ZIOL2xxx)

1)

# stands for the device revision

xxx stands for the device derivate (refer to chapter 1)

Data Sheet

January 31, 2012

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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8


型号：	ZIOL2212
厂家：	ETC
描述：	IO-Link compliant HV Line Driver IC Family
文件：	总91页 (文件大小：3543K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ZIOL2212 [ETC]

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ZIOL2411BI1W

ZIOL2412

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ZIP-18

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ZIP-28