MC74VHC1GT02DFT2 [ETL]
2-Input NOR Gate / CMOS Logic Level Shifter; 2输入或非门/ CMOS逻辑电平转换器型号: | MC74VHC1GT02DFT2 |
厂家: | E-TECH ELECTRONICS LTD |
描述: | 2-Input NOR Gate / CMOS Logic Level Shifter |
文件: | 总4页 (文件大小:558K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
2-Input NOR Gate / CMOS Logic Level Shifter
with LSTTL–Compatible Inputs
MC74VHC1GT02
The MC74VHC1GT02 is a single gate 2–input NOR fabricated with silicon gate CMOS technology. It achieves high speed operation
similar to equivalent Bipolar Schottky TTL while maintaining CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer output which provides high noise immunity and stable output.
The device input is compatible with TTL–type input thresholds and the output has a full 5.0 V CMOS level output swing. The input
protection circuitry on this device allows overvoltage tolerance on the input, allowing the device to be used as a logic–level translator from
3.0 V CMOS logic to 5.0 V CMOS Logic or from 1.8 V CMOS logic to 3.0 V CMOS Logic while operating at the high–voltage power
supply.
The MC74VHC1GT02 input structure provides protection when voltages up to 7 V are applied, regardless of the supply voltage. This
allows the MC74VHC1GT02 to be used to interface 5 V circuits to 3 V circuits. The output structures also provide protection when
V CC = 0 V. These input and output structures help prevent device destruction caused by supply voltage – input/output voltage mismatch,
battery backup, hot insertion, etc.
• High Speed: tPD = 4.7 ns (Typ) at VCC = 5 V
• Low Power Dissipation: ICC = 2 mA (Max) at TA = 25°C
• TTL–Compatible Inputs: VIL = 0.8 V; VIH = 2.0 V
• CMOS–Compatible Outputs: VOH > 0.8 VCC ; VOL < 0.
1 VCC @Load
• Balanced Propagation Delays
• Pin and Function Compatible with Other Standard Logic Families
• Chip Complexity: FETs = 65; Equivalent Gates = 14
• Power Down Protection Provided on Inputs and Outputs
MARKING DIAGRAMS
5
4
1
2
3
VJd
SC–88A / SOT–353/SC–70
DF SUFFIX
CASE 419A
Y
Pin 1
d = Date Code
5
Figure 1. Pinout (Top View)
4
VJd
1
2
3
Figure 2. Logic Symbol
TSOP–5/SOT–23/SC–59
DT SUFFIX
CASE 483
Pin 1
d = Date Code
FUNCTION TABLE
PIN ASSIGNMENT
Inputs
Output
1
2
3
4
5
IN B
IN A
A
L
B
L
Y
H
L
GND
OUT Y
V CC
L
H
L
H
H
L
H
L
ORDERING INFORMATION
See detailed ordering and shipping information in the
package dimensions section on page 4 of this data sheet.
VHT2–1/4
MC74VHC1GT02
MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
V
V CC
V IN
DC Supply Voltage
– 0.5 to + 7.0
– 0.5 to 7.0
– 0.5 to 7.0
–0.5 to V cc + 0.5
–20
DC Input Voltage
V
V OUT
DC Output Voltage
V CC=0
V
High or Low State
I IK
Input Diode Current
Output Diode Current
mA
mA
mA
mA
mW
°C/W
°C
I OK
I OUT
I CC
P D
θ JA
T L
V OUT < GND; V OUT > V CC
+20
DC Output Current, per Pin
DC Supply Current, V CC and GND
Power dissipation in still air
Thermal resistance
+ 25
+50
SC–88A, TSOP–5
SC–88A, TSOP–5
200
333
Lead Temperature, 1 mm from Case for 10 s
Junction Temperature Under Bias
Storage temperature
260
T J
+ 150
°C
T stg
V ESD
–65 to +150
>2000
°C
ESD Withstand Voltage
Human Body Model (Note 2)
Machine Model (Note 3)
V
> 200
Charged Device Model (Note 4)
N/A
I LATCH–UP
Latch–Up Performance Above V CC and Below GND at 125°C (Note 5)
± 500
mA
1. Maximum Ratings are those values beyond which damage to the device may occur. Exposure to these conditions or conditions
beyond those indicated may adversely affect device reliability. Functional operation under absolute–maximum–rated conditions is
not implied. Functional operation should be restricted to the Recommended Operating Conditions.
2. Tested to EIA/JESD22–A114–A
3. Tested to EIA/JESD22–A115–A
4. Tested to JESD22–C101–A
5. Tested to EIA/JESD78
RECOMMENDED OPERATING CONDITIONS
Symbol
V CC
Parameter
Min
3.0
0.0
0.0
0.0
– 55
0
Max
5.5
Unit
V
DC Supply Voltage
DC Input Voltage
DC Output Voltage
V IN
5.5
V
V OUT
V CC = 0
5.5
V
High or Low State
V CC
+ 125
100
20
T A
Operating Temperature Range
Input Rise and Fall Time
°C
t r ,t f
V CC = 3.3 ± 0.3 V
V CC = 5.0 ± 0.5 V
ns/V
0
DEVICE JUNCTION TEMPERATURE VERSUS
TIME TO 0.1% BOND FAILURES
Junction
Time,
Hours
Time,
Years
117.8
47.9
20.4
9.4
Temperature °C
80
90
1,032,200
419,300
178,700
79,600
37,000
17,800
8,900
100
110
120
130
140
4.2
1
2.0
1.0
1
10
100
1000
TIME, YEARS
Figure 3. Failure Rate vs. Time
Junction Temperature
VHT2–2/4
MC74VHC1GT02
DC ELECTRICAL CHARACTERISTICS
V CC
T A = 25°C
T A <85°C –55°C<TA<125°C
Symbol
Parameter
Test Conditions
(V) Min Typ Max Min Max Min Max Unit
V IH
Minimum High–Level
Input Voltage
V
3.0 1.4
4.5 2.0
5.5 2.0
1.4
2.0
2.0
1.4
2.0
2.0
V IL
Maximum Low–Level
Input Voltage
V
V
3.0
4.5
5.5
0.53
0.8
0.53
0.8
0.53
0.8
0.8
0.8
0.8
V OH
Minimum High–Level
Output Voltage
V IN = V IH or V IL
I OH = – 50 µA
3.0 2.9 3.0
4.5 4.4 4.0
2.9
4.4
2.9
4.4
V
IN = V IH or V IL
V IN = V IH or V IL
I OH = –4 mA
I OH = –8 mA
V IN = V IH or V IL
I OL = 50 µA
3.0 2.58
4.5 3.94
2.48
3.80
2.34
3.66
V OL
Maximum Low–Level
Output Voltage
V
3.0
4.5
0.0
0.0
0.1
0.1
0.1
0.1
0.1
0.1
V
IN = V IH or V IL
V IN = V IH or V IL
I OL = 4 mA
3.0
4.5
0.36
0.36
±0.1
0.44
0.44
±1.0
0.52
0.52
±1.0
I OL = 8 mA
I IN
Maximum Input
Leakage Current
Maximum Quiescent
Supply Current
Quiescent Supply
Current
V IN = 5.5 V or GND
0 to5.5
µA
µA
I CC
I CCT
I OPD
V IN = V CC or GND
Input: V IN = 3.4 V
V OUT = 5.5 V
5.5
5.5
0.0
2.0
1.35
0.5
20
1.50
5.0
40
1.65 mA
10 µA
Output Leakage
Current
AC ELECTRICAL CHARACTERISTICS C load = 50 pF, Input t r = t f = 3.0 ns
T A = 25°C
Min Typ Max Min Max Min Max Unit
T A
<85°C –55°C<TA <125°C
Symbol Parameter
Test Conditions
t PLH
t PHL
,
Maximum
V CC = 3.3± 0.3 V C L = 15 pF
C L = 50 pF
4.0
5.8
10.0
13.5
11.0
15.0
13.0 ns
17.5
Propagation Delay,
Input A or B to Y
V CC = 5.0± 0.5 V C L = 15 pF
C L = 50 pF
3.0
3.8
5.5
6.7
7.7
10
7.5
8.5
10
8.5
9.5
C IN
Maximum Input
Capacitance
10
pF
Typical @ 25°C, V CC = 5.0 V
C PD
Power Dissipation Capacitance (Note 6)
11
pF
6. C PD is defined as the value of the internal equivalent capacitance which is calculated from the operating current consumption without
load. Average operating current can be obtained by the equation: I CC(OPR) = C PD • V CC • f in + I CC C PD is used to determine the no–
load dynamic power consumption; P D = C PD • V CC 2 • f in + I CC • V CC
.
.
VHT2–3/4
MC74VHC1GT02
3.0V
V OH
V OL
Y
Figure 4. Switching Waveforms
*Includes all probe and jig capacitance
Figure 5. Test Circuit
DEVICE ORDERING INFORMATION
Device Nomenclature
Package Type
Device
Temp
Tape and
Reel Size
Tape &
Reel
(Name/SOT#/
Circuit
Order Number
Device
Package
Suffix
Range
Common Name)
Technology
Indicator
Function
Identifier
Suffix
MC74VHC1GT02DFT1 MC
MC74VHC1GT02DFT2 MC
MC74VHC1GT02DFT4 MC
MC74VHC1GT02DTT1 MC
MC74VHC1GT02DTT3 MC
74
74
74
74
74
VHC1G
VHC1G
VHC1G
VHC1G
VHC1G
T02
T02
T02
T02
T02
DF
DF
DF
DT
DT
T1
T2
T4
T1
T3
SC–70/SC–88A/
SOT–353
178 mm (7 in)
3000 Unit
SC–70/SC–88A/
SOT–353
178 mm (7 in)
3000 Unit
SC–70/SC–88A/
SOT–353
330 mm (13 in)
10,000 Unit
178 mm (7 in)
3000 Unit
SOT–23/TSOPS/
SC–59
SOT–23/TSOPS/
SC–59
330 mm (13 in)
10,000 Unit
VHT2–4/4
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