MR0A16ACYS35_技术文档

MR0A16A

64K x 16 MRAM Memory

FEATURES

• 3.3 Volt power supply

• Fast 35ns read/write cycle

• SRAM compatible timing

• Unlimited read & write endurance

• Commercial, Industrial, and Extended Temperatures

• Data non-volatile for >20 years at temperature

• RoHS-compliant TSOP2 and BGA packages available

• All products meet MSL-3 moisture sensitivity level

• Automotive AEC-Q100 Grade 1 option available

44-pin TSOP2

BENEFITS

• One memory replaces FLASH, SRAM, EEPROM and BBSRAM

in system for simpler, more eﬃcient designs

48-ball BGA

• Improves reliability by replacing battery-backed SRAM

• Automatic data protection on power loss

RoHS

INTRODUCTION

The MR0A16A is a 1,048,576-bit magnetoresistive random access memory (MRAM) device organized as

65,536 words of 16 bits. The MR0A16A oﬀers SRAM compatible 35 ns read/write timing with unlimited en-

durance. Data is always non-volatile for greater than 20 years. Data is automatically protected on power loss

by low-voltage inhibit circuitry to prevent writes with voltage out of speciﬁcation.

MR0A16A is the ideal memory solution for applications that must permanently store and retrieve critical

data and programs quickly.

The MR0A16B is available in a small footprint 48-pin ball grid array (BGA) package and a 44-pin thin small

outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM products and

other nonvolatile RAM products.

The MR0A16A provides highly reliable data storage over a wide range of temperatures. The product is avail-

able with commercial temperature (0 to +70 °C), industrial temperature (-40 to +85 °C), extended tempera-

ture (-40 to +105 °C), and Automotive AEC-Q100 Grade 1 (-40 to +125°) temperature range options.

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MR0A16A Rev. 8.3 3/2018

MR0A16A

TABLE OF CONTENTS

FEATURES .............................................................................................................................................1

BENEFITS...............................................................................................................................................1

INTRODUCTION ...................................................................................................................................1

BLOCK DIAGRAM AND PIN ASSIGNMENTS.......................................................................................4

Figure 1 – Block Diagram........................................................................................................................................... 4

Table 1 – Pin Functions............................................................................................................................................... 4

Figure 2 – MR0A16A Package Pinouts .................................................................................................................. 5

OPERATING MODES.............................................................................................................................5

Table 2 – Operating Modes....................................................................................................................................... 5

ABSOLUTE MAXIMUM RATINGS.........................................................................................................6

Table 3 – Absolute Maximum Ratings................................................................................................................... 6

OPERATING CONDITIONS ...................................................................................................................7

Table 4 – Operating Conditions............................................................................................................................... 7

Power Up and Power Down Sequencing .......................................................................................8

Figure 3 – Power Up and Power Down Timing ................................................................................................. 8

DC CHARACTERISTICS.........................................................................................................................9

Table 5 – DC Characteristics...................................................................................................................................... 9

Table 6 – Power Supply Characteristics................................................................................................................ 9

TIMING SPECIFICATIONS ................................................................................................................. 10

Table 7 – Capacitance ...............................................................................................................................................10

Table 8 – AC Measurement Conditions ..............................................................................................................10

Figure 4 – Output Load Test Low and High.......................................................................................................10

Figure 5 – Output Load Test All Others...............................................................................................................10

Table 9 – Read Cycle Timing ...................................................................................................................................11

Figure 6 – Read Cycle 1.............................................................................................................................................12

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MR0A16A Rev. 8.3 3/2018

MR0A16A

TABLE OF CONTENTS - continued

Figure 7 – Read Cycle 2.............................................................................................................................................12

Table 10 – Write Cycle Timing 1 (W Controlled) ..............................................................................................13

Figure 8 – Write Cycle Timing 1 (W Controlled)...............................................................................................14

Table 11 – Write Cycle Timing 2 (E Controlled)................................................................................................15

Figure 9 – Write Cycle Timing 2 (E Controlled)................................................................................................15

Table 12 – Write Cycle Timing 3 (LB/UB Controlled).....................................................................................16

Figure 10 – Write Cycle Timing 3 (UB/LB Controlled)...................................................................................16

ORDERING INFORMATION ............................................................................................................... 17

Table 13 – Part Numbering System......................................................................................................................17

Table 14 – MR0A16A Ordering Part Numbers..................................................................................................18

PACKAGE OUTLINE DRAWINGS....................................................................................................... 19

Figure 11 – 44-pin TSOP2.........................................................................................................................................19

Figure 12 – 48-ball FBGA..........................................................................................................................................20

REVISION HISTORY ........................................................................................................................... 21

HOW TO CONTACT US....................................................................................................................... 22

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MR0A16A Rev. 8.3 3/2018

MR0A16A

BLOCK DIAGRAM AND PIN ASSIGNMENTS

Figure 1 – Block Diagram

OUTPUT

ENABLE

BUFFER

UPPER BYTE OUTPUT ENABLE

LOWER BYTE OUTPUT ENABLE

G

8

UPPER

BYTE

OUTPUT

BUFFER

A[15:0] ADDRESS

8

ROW

DECODER

8

BUFFER

COLUMN

DECODER

16

8

SENSE

AMPS

CHIP

ENABLE

BUFFER

E

LOWER

BYTE

OUTPUT

BUFFER

8

16

64K x 16

BIT

MEMORY

ARRAY

UPPER

BYTE

WRITE

8

WRITE

ENABLE

BUFFER

DQU[15:8]

DQL[7:0]

W

8

DRIVER

FINAL

WRITE

DRIVERS

16

LOWER

BYTE

WRITE

DRIVER

UB

LB

UB

UPPER BYTE WRITE ENABLE

LOWER BYTE WRITE ENABLE

BYTE

ENABLE

BUFFER

LB

Table 1 – Pin Functions

Function

Signal Name

Address Input

Chip Enable

Write Enable

Output Enable

A

E

W

G

Upper Byte Enable

Lower Byte Enable

Data I/O

UB

LB

DQ

Power Supply

V_DD

V_SS

Ground

Do Not Connect

No Connection

DC

NC

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MR0A16A Rev. 8.3 3/2018

MR0A16A

Figure 2 – MR0A16A Package Pinouts

1

2

3

4

5

6

1

2

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

A

LB

G

A0

A1

A2

NC

A

B

C

D

E

3

4

G

UB

A

E

5

DQU8

DQU9

DQL0

DQL2

UB

A3

A5

A4

A6

E

6

LB

7

DQU15

DQU14

DQU13

DQU12

DQL0

DQL1

DQL2

DQL3

8

DQU10

DQU11

DQU12

DQU13

DQL1

DQL3

9

10

11

12

13

14

15

16

17

18

19

20

21

22

VSS

VDD

V_SS

A15

NC

VDD

VSS

V

DD

DQU11

DQU10

DQU9

DQU8

DC

DQL4

DQL5

DQL6

DQL7

VDD

A14

A13

A11

A9

DQL4

DQL5

VSS

F

DQU14

DQU15

NC

DQL6

DQL7

A12

A10

A8

W

A

V

DD

G

H

VSS

NC

A7

W

A

V_DD

DC

44-Pin TSOP Type 2

48-Pin BGA

OPERATING MODES

Table 2 – Operating Modes

Mode

V_DDCurrent

I_SB1, I_SB2

I_DDR

DQL[7:0] ²

Hi-Z

D_Out

Hi-Z

D_Out

D_in

DQU[15:8] ²

Hi-Z

E ¹

H

G ¹

X

W ¹

X

LB ¹

X

UB ¹

X

Not selected

L

H

X

L

H

X

H

L

X

H

L

X

H

L

Output disabled

Lower Byte Read

Upper Byte Read

Word Read

Hi-Z

I_DDR

Hi-Z

I_DDR

Hi-Z

L

H

L

I_DDR

D_Out

Hi-Z

L

I_DDR

X

L

H

L

Lower Byte Write

Upper Byte Write

Word Write

I_DDW

L

H

L

I_DDW

Hi-Z

D_in

L

I_DDW

D_in

Notes:

1. H = high, L = low, X = don’t care

2. Hi-Z = high impedance

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MR0A16A Rev. 8.3 3/2018

MR0A16A

ABSOLUTE MAXIMUM RATINGS

This device contains circuitry to protect the inputs against damage caused by high static voltages or electric ﬁelds; however,

normal precautions should be taken to avoid application of any voltage greater than maximum rated voltages to these high-

impedance (Hi-Z) circuits.

The device also contains protection against external magnetic ﬁelds. Precautions should be taken to avoid application of any

magnetic ﬁeld more intense than the maximum ﬁeld intensity speciﬁed in the maximum ratings.

Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to

recommended operating conditions. Exposure to excessive voltages or magnetic ﬁelds could aﬀect device reliability. ¹

Table 3 – Absolute Maximum Ratings

Symbol Parameter

Temp Range

Package

Value

Unit

V_DD

V_IN

Supply voltage ²

-

-0.5 to 4.0

V

Voltage on any pin ²

Output current per pin

Package power dissipation ³

-

-0.5 to V_DD+ 0.5

V

mA

W

-

I_OUT

P_D

-

20

Note 3

0.600

Commercial

Industrial

-

-10 to 85

-45 to 95

-45 to 110

-45 to 130

T_BIAS

Temperature under bias

°C

Extended

AEC Q-100 Grade 1

T_stg

Storage Temperature

-

-55 to 150

260

°C

Lead temperature during solder (3

minute max)

T_Lead

-

Commercial

TSOP2, BGA

BGA

2,000

10,000

2,000

8,000

10,000

8,000

Maximum magnetic ﬁeld during

write

Industrial, Ex-

tended

H_{max_write}

A/m

TSOP2

AEC-Q100 Grade 1

Commercial

TSOP2

TSOP2, BGA

BGA

Maximum magnetic ﬁeld during

read or standby

Industrial, Ex-

tended

H_{max_read}

TSOP2

AEC-Q100 Grade 1

TSOP2

Notes appear on the next page.

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MR0A16A Rev. 8.3 3/2018

MR0A16A

Notes: for MR0A16A Absolute Maximum Ratings:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted

to recommended operating conditions. Exposure to excessive voltages or magnetic ﬁelds could aﬀect device reliability.

2. All voltages are referenced to V_SS.

3. Power dissipation capability depends on package characteristics and use environment.

OPERATING CONDITIONS

Table 4 – Operating Conditions

Symbol

Parameter

Temp Range

Min

Typical

Max

Unit

V_DD

Power supply voltage ¹

All

3.0

3.3

3.6

V

V_WI

V_IH

V_IL

Write inhibit voltage

Input high voltage

Input low voltage

All

2.5

2.2

2.7

3.0 ¹

V_DD+ 0.3 ²

0.8

V

-

-0.5 ³

Commercial

Industrial

0

70

85

-40

T_A

Ambient Temperature under bias

°C

Extended

105

125

4

AEC Q-100 Grade 1

Notes:

1. There is a 2 ms startup time once V_DDexceeds V_DD,(min). See Power Up and Power Down Sequencing below.

2. V_IH(max) = V_DD+ 0.3 V_DC; V_IH(max) = V_DD+ 2.0 V_AC(pulse width ≤ 10 ns) for I ≤ 20.0 mA.

3. V_IL(min) = -0.5 V_DC; V_IL(min) = -2.0 V_AC(pulse width ≤ 10 ns) for I ≤ 20.0 mA.

4. AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2 years out of 20 years life.)

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MR0A16A Rev. 8.3 3/2018

MR0A16A

Power Up and Power Down Sequencing

The MRAM is protected from write operations whenever V_DDis less than V_WI. As soon as V_DDexceeds

V_DD(min), there is a startup time of 2 ms before read or write operations can start. This time allows memory

power supplies to stabilize.

The E and W control signals should track V_DDon power up to V_DD- 0.2 V or V_IH(whichever is lower) and

remain high for the startup time. In most systems, this means that these signals should be pulled up with a

resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and

W should hold the signals high with a power-on reset signal for longer than the startup time.

During power loss or brownout where V_DDgoes below V_WI, writes are protected and a startup time must be

observed when power returns above V_DD(min)

.

Figure 3 – Power Up and Power Down Timing

VDD

V

WI

BROWNOUT or POWER LOSS

2 ms

STARTUP

RECOVER

NORMAL

OPERATION

NORMAL

OPERATION

READ/WRITE

INHIBITED

READ/WRITE

INHIBITED

VIH

E

W

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MR0A16A Rev. 8.3 3/2018

MR0A16A

DC CHARACTERISTICS

Table 5 – DC Characteristics

Symbol

Parameter

Condition

Min

Max

Unit

I_lkg(I)

Input leakage current

All

-

1

μA

I_lkg(O)

Output leakage current

Output low voltage

All

-

1

μA

V

I_OL= +4 mA

I_OL= +100 μA

I_OH= -4 mA

0.4

V_SS+ 0.2

-

V_OL

2.4

V_OH

Output high voltage

V

I_OH= -100 μA

V_DD- 0.2

Table 6 – Power Supply Characteristics

Symbol

Parameter

Condition

Temp Range Typical

Max

Unit

AC active supply current

- read modes ¹

I_DDR

I_OUT= 0 mA, V_DD= max

All

55

80

mA

Commercial

Industrial

Extended

105

155

165

AC active supply current

- write modes¹

I_DDW

V_DD= max

mA

AEC-Q100

Grade 1

V_DD= max, E = V_IH

I_SB1

AC standby current

All

18

9

28

12

mA

No other restrictions on other

inputs

E ≥ V_DD- 0.2 V and V_In≤ V_SS

0.2 V or ≥ V_DD- 0.2 V

+

I_SB2

CMOS standby current

V_DD= max, f = 0 MHz

Notes:

1. All active current measurements are measured with one address transition per cycle and at minimum cycle time.

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MR0A16A Rev. 8.3 3/2018

MR0A16A

TIMING SPECIFICATIONS

Table 7 – Capacitance

Symbol Parameter ¹

Typical

Max

Unit

C_In

Address input capacitance

-

6

pF

C_In

Control input capacitance

Input/Output capacitance

-

6

8

pF

C_I/O

Notes:

1. f = 1.0 MHz, dV = 3.0 V, T_A= 25 °C, periodically sampled rather than 100% tested.

Table 8 – AC Measurement Conditions

Parameter

Value

Unit

Logic input timing measurement reference level

Logic output timing measurement reference level

Logic input pulse levels

1.5

V

1.5

0 or 3.0

2

V

Input rise/fall time

ns

Output load for low and high impedance parameters

Output load for all other timing parameters

See Figure 4

See Figure 5

Figure 4 – Output Load Test Low and High

Z_D= 50 Ω

Output

R_L= 50 Ω

V_L= 1.5 V

Figure 5 – Output Load Test All Others

3.3 V

590 Ω

Output

5 pF

435 Ω

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MR0A16A Rev. 8.3 3/2018

MR0A16A

Table 9 – Read Cycle Timing

Symbol

^tAVAV

Parameter ¹

Min

Max

-

Unit

ns

Read cycle time

35

-

^tAVQV

^tELQV

Address access time

Enable access time ²

35

15

-

ns

-

ns

^tGLQV

^tBLQV

^tAXQX

^tELQX

Output enable access time

-

ns

Byte enable access time

-

ns

Output hold from address change

Enable low to output active ³

Output enable low to output active ³

Byte enable low to output active ³

Enable high to output Hi-Z ³

Output enable high to output Hi-Z³

Byte high to output Hi-Z³

3

0

ns

-

ns

^tGLQX

^tBLQX

^tEHQZ

^tGHQZ

^tBHQZ

-

ns

-

ns

15

10

ns

Notes:

1. W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be

minimized or eliminated during read or write cycles.

2. Addresses valid before or at the same time E goes low.

3. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage.

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MR0A16A Rev. 8.3 3/2018

MR0A16A

Figure 6 – Read Cycle 1

t_AVAV

A (ADDRESS)

Q (DATA OUT)

t_AXQX

Previous Data Valid

Data Valid

t_AVQV

Note: Device is continuously selected (E≤V_IL, G≤V_IL).

Figure 7 – Read Cycle 2

t_AVAV

A (ADDRESS)

E (CHIP ENABLE)

t_AVQV

t_ELQV

t_EHQZ

t_ELQX

G (OUTPUT ENABLE)

LB, UB (BYTE ENABLE)

t_GHQZ

t_GLQV

t_GLQX

t_BHQZ

t_BLQV

t_BLQX

Data Valid

Q (DATA OUT)

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MR0A16A Rev. 8.3 3/2018

MR0A16A

Table 10 – Write Cycle Timing 1 (W Controlled)

Symbol

^tAVAV

Parameter ¹

Min

35

Max

Unit

ns

Write cycle time ²

-

^tAVWL

Address set-up time

0

ns

^tAVWH

Address valid to end of write (G high)

Address valid to end of write (G low)

18

ns

20

ns

^tWLWH

^tWLEH

Write pulse width (G high)

Write pulse width (G low)

15

-

ns

^tWLWH

^tWLEH

^tDVWH

^tWHDX

^tWLQZ

^tWHQX

^tWHAX

Data valid to end of write

Data hold time

10

0

-

ns

Write low to data Hi-Z ³

Write high to output active ³

Write recovery time

0

12

-

3

12

-

Notes:

1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in

steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted

low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

2. All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

3. This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given

voltage or temperate, t_WLQZ(max) < t_WHQX(min)

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MR0A16A Rev. 8.3 3/2018

MR0A16A

Figure 8 – Write Cycle Timing 1 (W Controlled)

t_AVAV

A (ADDRESS)

t_AVWH

t_WHAX

E (CHIP ENABLE)

t_WLEH

t_WLWH

W (WRITE ENABLE)

t_AVWL

UB, LB (BYTE ENABLED)

D (DATA IN)

t_DVWH

t_WHDX

DATA VALID

t_WLQZ

Hi -Z

Q (DATA OUT)

t_WHQX

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MR0A16A Rev. 8.3 3/2018

MR0A16A

Table 11 – Write Cycle Timing 2 (E Controlled)

Symbol

Parameter ¹

Min

Max

Unit

^tAVAV

Write cycle time ²

35

-

ns

^tAVEL

^tAVEH

Address set-up time

0

-

ns

Address valid to end of write (G high)

Address valid to end of write (G low)

18

20

^tELEH

^tELWH

^tELEH

^tELWH

Enable to end of write (G high)

Enable to end of write (G low) ³

15

-

ns

^tDVEH

^tEHDX

^tEHAX

Data valid to end of write

Data hold time

10

0

-

ns

Write recovery time

12

Notes:

1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in

steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted

low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

2. All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

3. If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the

same time or before W goes high, the output will remain in a high-impedance state.

Figure 9 – Write Cycle Timing 2 (E Controlled)

t_AVAV

A (ADDRESS)

t_EHAX

t_AVEH

t_ELEH

E (CHIP ENABLE)

t_AVEL

t_ELWH

W (WRITE ENABLE)

UB, LB (BYTE ENABLE)

D (DATA IN)

t_EHDX

t_DVEH

Data Valid

Hi-Z

Q (DATA OUT)

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MR0A16A Rev. 8.3 3/2018

MR0A16A

Table 12 – Write Cycle Timing 3 (LB/UB Controlled)

Symbol

Parameter ¹

Min

Max

Unit

^tAVAV

Write cycle time ²

35

-

ns

^tAVBL

Address set-up time

0

-

ns

Address valid to end of write (G high)

Address valid to end of write (G low)

18

20

^tAVBH

^tBLEH

^tBLWH

^tBLEH

^tBLWH

Write pulse width (G high)

Write pulse width (G low)

15

-

ns

^tDVBH

^tBHDX

^tBHAX

Data valid to end of write

Data hold time

10

0

-

ns

Write recovery time

12

Notes:

1. All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

Wgoes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must

remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals must have no

more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in

a subsequent cycle is the same as the minimum cycle time allowed for the device.

2. All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

Figure 10 – Write Cycle Timing 3 (UB/LB Controlled)

t_AVAV

A (ADDRESS)

t_AVEH

t_BHAX

E (CHIP ENABLE)

W (WRITE ENABLE)

t_AVBL

t_BLEH

t_BLWH

UB, LB (BYTE ENABLED)

D (DATA IN)

t_DVBH

Data Valid

t_BHDX

Hi -Z

Q (DATA OUT)

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MR0A16A Rev. 8.3 3/2018

MR0A16A

ORDERING INFORMATION

Table 13 – Part Numbering System

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MR0A16A Rev. 8.3 3/2018

MR0A16A

Table 14 – MR0A16A Ordering Part Numbers

Temp Grade

Temp

Package

Shipping

Tray

Ordering Part Number

MR0A16AYS35

44-TSOP2

Tape and Reel

Tray

MR0A16AYS35R

MR0A16AMA35

MR0A16AMA35R

MR0A16ACYS35

MR0A16ACYS35R

MR0A16ACMA35

MR0A16ACMA35R

MR0A16AVYS35

MR0A16AVYS35R

MR0A16AVMA35

MR0A16AVMA35R

MR0A16AMYS35

MR0A16AMYS35R

Commercial

0 to +70 °C

48-BGA

Tape and Reel

Tray

44-TSOP2

Tape and Reel

Tray

Industrial

-40 to +85 °C

48-BGA

44-TSOP2

48-BGA

Tape and Reel

Tray

Tape and Reel

Tray

Extended

-40 to +105 °C

-40 to 125 °C

Tape and Reel

Tray

AEC-Q100 Grade 1

44-TSOP2

Tape and Reel

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MR0A16A Rev. 8.3 3/2018

MR0A16A

PACKAGE OUTLINE DRAWINGS

Figure 11 – 44-pin TSOP2

Notes:

1. Dimensions and tolerances per ASME

Y14.5M - 1994.

2. Dimensions in Millimeters.

3. Dimensions do not include mold protru-

sion.

4. Dimension does not include DAM bar

protrusions.

5. DAM Bar protrusion shall not cause the

lead width to exceed 0.58.

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MR0A16A Rev. 8.3 3/2018

MR0A16A

Figure 12 – 48-ball BGA Package Outline

Notes:

1.

2.

Dimensions in Millimeters.

Dimensions and tolerances per ASME Y14.5M

- 1994.

3.

4.

5.

Maximum solder ball diameter measured paral-

lel to DATUM A

DATUM A, the seating plane is determined by

the spherical crowns of the solder balls.

Parallelism measurement shall exclude any ef-

fect of mark on top surface of package.

20

MR0A16A Rev. 8.3 3/2018

MR0A16A

REVISION HISTORY

Description of Change

Date

Revision

0

1

2

Jun 18, 2007

Sept 21, 2007

Nov 12, 2007

Initial Advanced Information Release

Table 6, Applied Values to TBD’s in IDD Speciﬁcations

Table 2, Changed IDDA to IDDR or IDDW

Reformat Datasheet for EverSpin, Add BGA Packaging Information, Add Tape & Reel Part

Numbers, Add Power Sequencing Info, Correct IOH spec of VOH to -100 uA, Correct ac Test

Conditions.

3

Sep 12, 2008

4

5

Feb 28, 2011

Dec 9, 2011

Add TSOPII Lead Cross-Section, Add Production Note. Converted to new document format.

Figure 2.1 cosmetic update. Figure 5.2 BGA package outline drawing revised for ball size.

Updated logo and contact information.

Revised Table 1 and Figure 1 to be correct for x16 device. Revised magnetic immunity

ratings for TSOP2 Industrial Grade. Revised ﬁgure 3. Complete document reformat and

restructure.

6

7

8

August 6, 2012

October 14,

2013

Added AEC-Q100 Grade 1 product option.

February 19,

2015

Revised package outline for BGA. Ball size to 0.25 / 0.35 mm.

8.1

8.2

8.3

May 19, 2015

June 11, 2015

Revised contact information on Contact Us page.

Correction to Japan Sales Oﬃce telephone number.

March 23, 2018 Revised contact information on Contact Us page.

21

MR0A16A Rev. 8.3 3/2018

MR0A16A

HOW TO CONTACT US

Everspin Technologies, Inc.

How to Reach Us:

Home Page:

Information in this document is provided solely to enable system and

software implementers to use Everspin Technologies products. There are

no express or implied licenses granted hereunder to design or fabricate any

integrated circuit or circuits based on the information in this document.

Everspin Technologies reserves the right to make changes without further

notice to any products herein. Everspin makes no warranty, representa-

tion or guarantee regarding the suitability of its products for any particular

purpose, nor does Everspin Technologies assume any liability arising out of

the application or use of any product or circuit, and speciﬁcally disclaims

any and all liability, including without limitation consequential or inci-

dental damages. “Typical”parameters, which may be provided in Everspin

Technologies data sheets and/or speciﬁcations can and do vary in diﬀer-

ent applications and actual performance may vary over time. All operating

parameters including “Typicals”must be validated for each customer ap-

plication by customer’s technical experts. Everspin Technologies does not

convey any license under its patent rights nor the rights of others. Everspin

Technologies products are not designed, intended, or authorized for use

as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other ap-

plication in which the failure of the Everspin Technologies product could

create a situation where personal injury or death may occur. Should Buyer

purchase or use Everspin Technologies products for any such unintended

or unauthorized application, Buyer shall indemnify and hold Everspin Tech-

nologies and its oﬃcers, employees, subsidiaries, aﬃliates, and distributors

harmless against all claims, costs, damages, and expenses, and reasonable

attorney fees arising out of, directly or indirectly, any claim of personal

injury or death associated with such unintended or unauthorized use, even

if such claim alleges that Everspin Technologies was negligent regarding

the design or manufacture of the part. Everspin™ and the Everspin logo are

trademarks of Everspin Technologies, Inc.

www.everspin.com

World Wide Information Request

WW Headquarters - Chandler, AZ

5670 W. Chandler Blvd., Suite 100

Chandler, Arizona 85226

Tel: +1-877-480-MRAM (6726)

Local Tel: +1-480-347-1111

Fax: +1-480-347-1175

support@everspin.com

orders@everspin.com

sales@everspin.com

Europe, Middle East and Africa

Everspin Europe Support

support.europe@everspin.com

Japan

Everspin Japan Support

support.japan@everspin.com

Asia Paciﬁc

Everspin Asia Support

support.asia@everspin.com

All other product or service names are the property of their respective owners.

Filename:

EST00354_MR0A16A_Datasheet_Rev8.3032318

22

MR0A16A Rev. 8.3 3/2018


型号：	MR0A16ACYS35
厂家：	Everspin Technologies
描述：	64K x 16 MRAM Memory 静态存储器光电二极管内存集成电路
文件：	总22页 (文件大小：930K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MR0A16ACYS35 [EVERSPIN]

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