MR0DL08B [EVERSPIN]

Dual Supply 128K x 8 MRAM;


型号：	MR0DL08B
厂家：	Everspin Technologies
描述：	Dual Supply 128K x 8 MRAM
文件：	总16页 (文件大小：786K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MR0DL08B

Dual Supply 128K x 8 MRAM

FEATURES

• 3.3 Volt V_DDpower supply with a range of 2.7V to 3.6V

• I/O Voltage range supports wide +1.65 to +3.6 Volt interfaces

• Fast 45 ns read/write cycle

• SRAM compatible timing

• Unlimited read & write endurance

• Data always non-volatile for >20-years at temperature

• All products meet MSL-3 moisture sensitivity level

• RoHS-compliant small footprint BGA package

BENEFITS

• One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems

for simpler, more eﬃcient designs

RoHS

• Improves reliability by replacing battery-backed SRAM

INTRODUCTION

The MR0DL08B is a dual power supply 1,048,576-bit magnetoresistive random access memory (MRAM)

device organized as 131,072 words of 8 bits. It supports I/O voltages from +1.65 to +3.6 volts. The

MR0DL08B oﬀers SRAM compatible 45ns read/write timing with unlimited endurance. Data is always

non-volatile for greater than 20-years. Data is automatically protected on power loss by low-voltage inhibit

circuitry to prevent writes with voltage out of speciﬁcation. The MR0DL08B is the ideal memory solution

for applications that must permanently store and retrieve critical data and programs quickly.

The MR0DL08B is available in small footprint 8 mm x 8 mm, 48-pin ball grid array (BGA) package with 0.75

mm ball centers.

The MR0DL08B provides highly reliable data storage over a wide range of temperatures. The product is

oﬀered with commercial temperature (0 to +70 °C).

CONTENTS

1. DEVICE PIN ASSIGNMENT......................................................................... 2

2. ELECTRICAL SPECIFICATIONS................................................................. 4

3. TIMING SPECIFICATIONS.......................................................................... 8

4. ORDERING INFORMATION....................................................................... 13

5. MECHANICAL DRAWING.......................................................................... 14

6. REVISION HISTORY...................................................................................... 15

How to Reach Us.......................................................................................... 15

MR0DL08B Rev. 1.3, 3/2018

MR0DL08B

1. DEVICE PIN ASSIGNMENT

Figure 1.1 Block Diagram

OUTPUT

ENABLE

ꢀ

OUTPUT ENABLE

BUFFER

ꢂ

ꢄꢅ1ꢆꢇ0ꢈ ADDRESS

ROW

DECODER

BUFFER

COLUMN

DECODER

1ꢂ

CHIP

ENABLE

BUFFER

ꢁ

OUTPUT

BUFFER

SENSE

AMPS

128Kx 8

BIT

MEMORY

ARRAY

WRITE

ENABLE

BUFFER

ꢃ

FINAL

WRITE

DRIVERS

WRITE

DRIVER

Dꢉꢅꢂꢇ0ꢈ

WRITE ENABLE

Table 1.1 Pin Functions

Signal Name

Function

Address Input

Chip Enable

Write Enable

Output Enable

Data I/O

V_DD

Power Supply

V_DDQ

V_SS

I/O Power Supply

Ground

Do Not Connect

No Connection, Ball D3, H1, H6, G2 Reserved for Future Expansion

MR0DL08B Rev. 1.2, 3/2018

DEVICE PIN ASSIGNMENT

MR0DL08B

Figure 1.2 Pin Diagrams for Available Packages (Top View)

ꢀ

ꢁ

ꢂ

ꢃ

ꢄ

ꢈ_DD

ꢄ

ꢇ

ꢅ

Dꢇ

ꢄ

ꢋꢇ

Dꢆ

Dꢇ

ꢈ_DD

Dꢆ

ꢅ

Dꢇ

Dꢆ

ꢋꢇ

Dꢆ

ꢈꢉꢉ

ꢈDDꢆ

ꢋꢇ

Dꢇ

Dꢆ

ꢈDDꢆ

ꢈꢉꢉ

ꢊ

Dꢆ_ꢀ

ꢋꢇ

ꢄ

Dꢆ

ꢋꢇ

ꢌ

ꢄ

ꢃ

ꢍ

ꢄ

ꢋꢇ

48 Pin FBGA

Table 1.2 Operating Modes

E¹

G¹

W¹

Mode

Not selected

Output disabled

Byte Read

V_DDCurrent

DQ[7:0]²

Hi-Z

I_SB1, I_SB2

I_DDR

Hi-Z

I_DDR

D_Out

Byte Write

I_DDW

D_in

H = high, L = low, X = don’t care

Hi-Z = high impedance

MR0DL08B Rev. 1.3, 3/2018

MR0DL08B

2. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

This device contains circuitry to protect the inputs against damage caused by high static voltages or

electric ﬁelds; however, it is advised that normal precautions be taken to avoid application of any

voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic ﬁelds. Precautions should be taken

to avoid application of any magnetic ﬁeld more intense than the maximum ﬁeld intensity speciﬁed

in the maximum ratings.

Table 2.1 Absolute Maximum Ratings¹

Parameter

Core Supply voltage²

I/O Power Supply voltage²

Symbol

Value

-0.5 to 4.0

-0.5 to +4.0 or

V_DDQ+ 0.5

whichever is less

Unit

V_DD

V_DDQ

V_IN

Voltage on any pin²

I_OUT

P_D

Output current per pin

Package power dissipation ³

0.600

T_BIAS

Temperature under bias

-10 to 85

-55 to 150

260

°C

T_stg

Storage Temperature

°C

T_Lead

Lead temperature during solder (3 minute max)

Maximum magnetic ﬁeld during write

Maximum magnetic ﬁeld during read or standby

°C

H_{max_write}

H_{max_read}

2000

A/m

8000

Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera-

tion should be restricted to recommended operating conditions. Exposure to excessive voltages or

magnetic ﬁelds could aﬀect device reliability.

All voltages are referenced to V_SS.

Power dissipation capability depends on package characteristics and use environment.

MR0DL08B Rev. 1.2, 3/2018

Electrical Speciﬁcations

MR0DL08B

Table 2.2 Operating Conditions

Parameter

Symbol

Min

Typical

Max

Unit

2.7 ¹

3.3

3.6

Core Power supply voltage

V_DD

1.65 ¹

2.3

3.6

I/O Power supply voltage

Write inhibit voltage V_DD

Write inhibit voltage V_DDQ

V_DDQ

V_WIDD

V_WIDDQ

2.5

2.7 ¹

1.2

1.4

1.65 ¹

V_DDQ+ 0.2²

0.4

Input high voltage (V_DDQ=1.65-2.2V)

Input high voltage (V_DDQ=2.2-2.7V)

Input high voltage (V_DDQ=2.7-3.6V)

Input low voltage (V_DDQ=1.65-2.2V)

Input low voltage (V_DDQ=2.2-2.7V)

Input low voltage (V_DDQ=2.7-3.6V)

Access Time

V_IH

V_IL

T_A

1.8

2.2

-0.2 ³

0.6

0.8

°C

Notes:

1. V_DDQ≤V_DD. Write inhibit occurs when either V_DDor V_DDQdrops below its write inhibit voltage. There is a 2 ms startup time once

V_DDexceeds V_DD(min). See Power Up and Power Down Sequencing.

2. V_IH(max) = V_DDQ+ 0.2 V DC ; V_IH(max) = V_DDQ+ 0.5 V AC (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

3. V_IL(min) = -0.2 V DC ; V_IL(min) = -2.0 V AC (pulse width ≤ 20 ns) for I ≤ 20.0 mA.

MR0DL08B Rev. 1.3, 3/2018

Electrical Speciﬁcations

MR0DL08B

Power Up and Power Down Sequencing

Initial Power Up

The MRAM is protected from write operations whenever V_DDis less than V_WIDD. Upon power up V_DDmust go

above 3.0V, and a 2 ms startup time must be observed before read or write operations can start. This time

allows memory power supplies to stabilize.

Power Loss or Brownout

During power loss or brownout where V_DDgoes below V_WIDDwrites are inhibited. To return to normal opera-

tion and exit Write Inhibit, V_DDmust go above 3.0V, and a 2 ms startup time must be observed. Once pow-

ered up, V_DDminimum can go as low as 2.7V.

Chip Enable and Write Enable

The E and W control signals should track V_DDon power up to V_DD- 0.2 V or V_IH(whichever is lower) and remain

high for the startup time. In most systems, this means that these signals should be pulled up with a resis-

tor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W

should hold the signals high with a power-on reset signal for longer than the startup time.

Figure 2.1 Power Up and Power Down Sequencing

VDD / VDDQ

WIDD

WIDDQ

2 ms

BROWNOUT or POWER LOSS

STARTUP

RECOVER

NORMAL

OPERATION

NORMAL

OPERATION

READ/WRITE

INHIBITED

READ/WRITE

INHIBITED

VIH

MR0DL08B Rev. 1.2, 3/2018

Electrical Speciﬁcations

MRD08B

Table 2.3 DC Characteristics

Parameter

Symbol

Min Typical Max

Unit

I_lkg(I)

Input leakage current

μA

I_lkg(O)

Output leakage current

μA

V_OL

V_OH

Output low voltage (V_DDQ=1.65-2.2V@ 0.1mA)

Output low voltage (V_DDQ=2.2-2.7V@ 0.1mA)

Output low voltage (V_DDQ=2.7-3.6V@ 2.1 mA)

Output high voltage (V_DDQ=1.65-2.2V@ - 0.1 mA)

Output high voltage (V_DDQ=2.2-2.7V@ -0.1 mA)

Output high voltage (V_DDQ=2.7-3.6V@ -1.0 mA)

0.2

0.4

1.4

2.4

Table 2.4 Power Supply Characteristics

Parameter

Symbol

Typical

Max

Unit

AC active supply current - read modes¹

(I_OUT= 0 mA, V_DD= max)

I_DDR

AC active supply current - write modes¹

(V_DD= max)

I_DDW

AC active operating current

(V_DDQ= V_IH= 3.6V, V_IL= 0V)

I_DDQ

0.50

input transitions <2ns, no output load

AC standby current

(V_DD= max, E = V_IH)

I_SB1

no other restrictions on other inputs

CMOS standby current

(E ≥ V_DD- 0.2 V and V_In≤V_SS+ 0.2 V or ≥ V_DDQ- 0.2 V)

(V_DD= max, f = 0 MHz)

I_SB2

All active current measurements are measured with one address transition per cycle and at minimum cycle time.

MR0DL08B Rev. 1.3, 3/2018

MR0DL08B

3. TIMING SPECIFICATIONS

Table 3.1 Capacitance¹

Symbol

Parameter

Typical

Max

Unit

Address input capacitance

Control input capacitance

C_In

Input/Output capacitance

C_I/O

f = 1.0 MHz, VDDQ=VDDQ(typ), T_A= 25 °C, periodically sampled rather than 100% tested.

Table 3.2 AC Measurement Conditions

Parameter

V_DDQ=1.8

0.8

V_DDQ=2.5

0.8

V_DDQ=3.3

0.8

Unit

Logic input timing measurement reference level

Logic output timing measurement reference level

Logic input pulse levels

0.8

0 or 1.8

0 or 2.5

0 or 3.3

Output load voltage (VL) for low & high impedance

parameters (Figure 3.1)

0.8

1.2

1.75

Output load resistor (R1) for all other timing

Output load resistor (R2) for all other timing

13,500

10,800

16,600

15,400

1,103

1,554

Figure 3.1 Output Load Test Low and High

Z_D= 50 Ω

Output

R_L= 50 Ω

V_L

Figure 3.2 Output Load Test All Others

V^DDQ

Output

30 pF

MR0DL08B Rev. 1.2, 3/2018

Timing Speciﬁcations

MR0DL08B

Read Mode

Table 3.3 Read Cycle Timing¹

Parameter

Symbol

Min

Max

Unit

t_AVAV

Read cycle time

t_AVQV

t_ELQV

Address access time

Enable access time²

t_GLQV

t_AXQX

t_ELQX

Output enable access time

Output hold from address change

Enable low to output active³

Output enable low to output active³

Enable high to output Hi-Z³

t_GLQX

t_EHQZ

t_GHQZ

Output enable high to output Hi-Z³

W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be

minimized or eliminated during read or write cycles.

Addresses valid before or at the same time E goes low.

This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage.

Figure 3.3A Read Cycle 1

t_AVAV

A (ADDRESS)

t_AXQX

Previous Data Valid

Data Valid

Q (DATA OUT)

t_AVQV

NOTE: Device is continuously selected (E ≤ V_IL, G ≤ V_IL)

Figure 3.3B Read Cycle 2

t_AVAV

A (ADDRESS)

t_AVQV

t_ELQV

E (CHIP ENABLE)

t_EHQZ

t_ELQX

G (OUTPUT ENABLE)

Q (DATA OUT)

t_GHQZ

t_GLQV

t_GLQX

Data Valid

MR0DL08B Rev. 1.3, 3/2018

Timing Speciﬁcations

MR0DL08B

Table 3.4 Write Cycle Timing 1 (W Controlled)¹

Parameter

Write cycle time²

Symbol

Min

Max

Unit

t_AVAV

t_AVWL

Address set-up time

t_AVWH

Address valid to end of write (G high)

Address valid to end of write (G low)

t_AVWH

t_WLWH

t_WLEH

t_WLWH

t_WLEH

t_DVWH

Write pulse width (G high)

Write pulse width (G low)

Data valid to end of write

Data hold time

Write low to data Hi-Z³

Write high to output active³

t_WHDX

t_WLQZ

t_WHQX

t_WHAX

Write recovery time

All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in

steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted

low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given

voltage or temperature, t_WLQZ(max) < t_WHQX(min)

Figure 3.4 Write Cycle Timing 1 (W Controlled)

t_AVAV

A (ADDRESS)

t_WHAX

t_AVWH

E (CHIP ENABLE)

t_WLEH

t_WLWH

W (WRITE ENABLE)

t_AVWL

t_DVWH

t_WHDX

D (DATA IN)

Data Valid

t_WLQZ

Hi-Z

Q (DATA OUT)

t_WHQX

MR0DL08B Rev. 1.2, 3/2018

Timing Speciﬁcations

MR0DL08B

Table 3.5 Write Cycle Timing 2 (E Controlled)¹

Parameter

Symbol

Min

Max

Unit

Write cycle time²

t_AVAV

t_AVEL

t_AVEH

Address set-up time

Address valid to end of write (G high)

Address valid to end of write (G low)

t_AVEH

t_ELEH

t_ELWH

t_ELEH

t_ELWH

t_DVEH

Enable to end of write (G high)

Enable to end of write (G low)³

Data valid to end of write

Data hold time

t_EHDX

t_EHAX

Write recovery time

All writes occur during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in

steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted

low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the

same time or before W goes high, the output will remain in a high-impedance state.

Figure 3.5 Write Cycle Timing 2 (E Controlled)

t_AVAV

A (ADDRESS)

t_EHAX

t_AVEH

t_ELEH

E (CHIP ENABLE)

t_AVEL

t_ELWH

W (WRITE ENABLE)

D (DATA IN)

t_EHDX

t_DVEH

Data Valid

MR0DL08B Rev. 1.3, 3/2018

Timing Speciﬁcations

MR0DL08B

Table 3.6 Write Cycle Timing 3 (Shortened t_WHAX, W and E Controlled)¹

Parameter

Symbol

Min

Max

Unit

Write cycle time²

t_AVAV

t_AVWL

t_AVWH

Address set-up time

Address valid to end of write (G high)

Address valid to end of write (G low)

t_WLWH

t_WLEH

t_DVWH

Write pulse width

Data valid to end of write

Data hold time

t_WHDX

t_EHAX

t_WHAX

t_WHEL

Enable recovery time

-2

Write recovery time³

Write to enable recovery time³