MR10Q010CSCR [EVERSPIN]
1 Mb High Speed Quad SPI MRAM;型号: | MR10Q010CSCR |
厂家: | Everspin Technologies |
描述: | 1 Mb High Speed Quad SPI MRAM |
文件: | 总72页 (文件大小:2808K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MR10Q010
1 Mb High Speed Quad SPI MRAM
FEATURES
•
High bandwidth – Read and Write at 52MB/sec
Quad I/O with the use of dual purpose pins to maintain a low pin count
•
RoHS
•
Operates in both standard, single SPI mode and high speed quad SPI mode
Fast quad Read and Write with quad address input and quad I/O
•
•
Intended for next generation RAID controllers, server system logs, storage device
buffers, and embedded system data and program memory
•
•
•
•
•
•
Data is non-volatile with retention greater than 20 years
Automatic data protection on power loss
Unlimited write endurance
16-SOIC
Low-current sleep mode
Dual 3.3v V / 1.8v V
power supply
DD
DDQ
Tamper Detect function will detect possible data modification from outside mag-
netic fields.
•
•
Quad Peripheral Interface (QPI) mode is supported to enhance system performance
for Execute in Place (XIP) operation.
24-BGA
MSL Level 3.
DESCRIPTION
The MR10Q010 is the ideal memory solution for applications that must store and retrieve data and programs quickly
using a small number of pins, low power, and choice of a 24-ball BGA or a 16-pin SOIC package. The four I/O’s in Quad
SPI mode allow very fast reads and writes, making it an attractive alternative to conventional parallel data bus inter-
faces in next generation RAID controllers, server system logs, storage device buffers, and embedded system data and
program memory.
Using Everspin’s patented MRAM technology, both reads and writes can occur randomly in memory with no delay
between writes.
Standard Serial Peripheral Interface (SPI), Quad SPI and Quad Peripheral Interface (QPI) modes are supported at a clock
rate up to 104MHz. XIP operation is supported for Read commands in all three modes.
The MR10Q010 Quad SPI MRAM is organized as 131,072 words of 8 bits.
Operational Overview
Mode
Command Set
Utility Commands
XIP Command Operation
Write Enable/Disable, Sleep Mode, Read/Write
Status Register, Tamper Detect, Read Device ID, Fast Read
Enable QPI Mode
Read 40MHz. Write, Fast Read
104MHz
SPI Mode
Quad I/O mode Read/Write data,
or both address and data
Fast Read Quad Output, Fast Read
Quad Address and Data
Quad SPI Mode
QPI Mode
None.
Enables command instruction
entry in quad I/O mode. (2 clocks)
Fast Read, Fast Read Quad Output,
Fast Read Quad Address and Data
Disable QPI Mode.
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
TABLE OF CONTENTS
Operational Overview....................................................................................................................1
OVERVIEW ............................................................................................................................................7
Table 1 – Operational Parameters Summary...................................................................................................... 7
Operation in 3.3v Data Bus Systems - Evaluation Board Available .............................................7
Figure 1 – MR10Q010 Block Diagram.................................................................................................................... 8
Figure 2 – System Configuration............................................................................................................................. 9
Figure 3 – 16-SOIC Package Pin Assignments..................................................................................................10
Table 2 – 16-SOIC Pin Functions............................................................................................................................10
Figure 4 – 24-BGA Package Ball Assignments..................................................................................................12
Table 3 – 24-BGA Ball Functions............................................................................................................................12
STATUS REGISTER ............................................................................................................................. 14
Table 4 – Status Register Bit Definitions.............................................................................................................14
Memory Protection Modes.......................................................................................................... 15
Table 5 – Memory Protection Modes ..................................................................................................................15
Block Protection Modes............................................................................................................... 15
Table 6 – Block Memory Write Protection..........................................................................................................15
SPI COMMUNICATIONS PROTOCOL................................................................................................ 16
SPI MODE COMMANDS .................................................................................................................... 16
Table 7 – SPI Mode Commands Overview.........................................................................................................17
SPI Mode Commands Overview .................................................................................................. 17
Read Status Register (RDSR)........................................................................................................ 18
Figure 5 – Read Status Register (RDSR) Command Operation ..................................................................18
Write Enable (WREN).................................................................................................................... 19
Figure 6 – Write Enable (WREN) Command Operation ................................................................................19
Write Disable (WRDI).................................................................................................................... 20
Figure 7 – Write Disable (WRDI) Command Operation ................................................................................20
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Table of Contents (Cont’d)
Write Status Register (WRSR) ...................................................................................................... 21
Figure 8 – Write Status Register (WRSR) Command Operation ................................................................21
Read Data Bytes (READ) ............................................................................................................... 22
Figure 9 – Read Data Bytes (READ) Command Operation...........................................................................22
Fast Read Data Bytes (FREAD) ..................................................................................................... 23
Figure 10 – Fast Read Data Bytes (FREAD) Command Operation .............................................................23
Write Data Bytes (WRITE)............................................................................................................. 24
Figure 11 – Write Data Bytes (WRITE) Command Operation ......................................................................24
Enter Sleep Mode (SLEEP)............................................................................................................ 25
Figure 12 – Enter Sleep Mode (SLEEP) Command Operation.....................................................................25
Exit Sleep Mode (WAKE)............................................................................................................... 26
Figure 13 – Exit Sleep Mode (WAKE) Command Operation........................................................................26
Tamper Detect (TDET).................................................................................................................. 27
Figure 14 – Tamper Detect (TDET) Command Operation............................................................................27
Tamper Detect Exit (TDETX) ........................................................................................................ 28
Figure 15 – Tamper Detect Exit (TDETX) Command Operation.................................................................28
Read ID (RDID) .............................................................................................................................. 29
Figure 16 – Read ID (RDID) Command Operation...........................................................................................29
Table 8 – Device ID for MR10Q010 .......................................................................................... 30
QUAD SPI MODE COMMANDS......................................................................................................... 31
Quad SPI Mode Commands Overview ........................................................................................ 31
Table 9 – Quad SPI Mode Commands Overview.............................................................................................31
Fast Read Quad Output (FRQO) .................................................................................................. 32
Figure 17 – Fast Read Quad Output (FRQO) Command Operation..........................................................33
Fast Read Quad Address and Data (FRQAD).............................................................................. 34
Figure 18 – Fast Read Quad Address and Data (FRQAD) Command Operation ..................................35
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Table of Contents (Cont’d)
Fast Write Quad Data (FWQD)...................................................................................................... 36
Figure 19 – Fast Write Quad Data (FWQD) Command Operation.............................................................36
Fast Write Quad Address and Data (FWQAD) ............................................................................. 37
Figure 20 – Fast Write Quad Address and Data (FWQAD) Command Operation ................................37
QPI MODE .......................................................................................................................................... 38
Table 10 – SPI Mode Command Structures in QPI Mode .............................................................................38
Table 11 – Quad SPI Mode Command Structures in QPI Mode .................................................................39
Enable QPI (EQPI) Command ....................................................................................................... 40
Figure 21 – Enable QPI Mode (EQPI) Command Operation .......................................................................40
Disable QPI (DQPI) Command ..................................................................................................... 41
Figure 22 – Disable QPI Mode (DQPI) Command Timing ............................................................................41
EXECUTE IN PLACE ꢀXIPꢁ MODE....................................................................................................... 42
Table 12 – Mode Byte Definitions to Set/Reset XIP Mode ...........................................................................42
Table 13 – XIP Mode with FREAD Command....................................................................................................43
Figure 23 – FREAD Command- Set XIP Mode - Initial Access .....................................................................44
Figure 24 – FREAD Command - XIP Mode Set - Next Access .....................................................................45
Figure 25 – FREAD Command - XIP Mode Exit.................................................................................................46
Table 14 – XIP Operation with FRQO Command.............................................................................................47
Figure 26 – FRQO Command - Set XIP Mode - Initial Access ....................................................................48
Figure 27 – FRQO Command - XIP Mode Set - Next Access.......................................................................49
Figure 28 – FRQO Command - XIP Mode Exit...................................................................................................50
Table 15 – XIP Operation with FRQAD Command..........................................................................................51
Figure 29 – FRQAD Command - Set XIP Mode - Initial Access ..................................................................52
Figure 30 – FRQAD Command - XIP Mode Set - Next Access ....................................................................53
Figure 31 – FRQAD Command - XIP Mode Exit................................................................................................54
ELECTRICAL SPECIFICATIONS ......................................................................................................... 55
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Table of Contents (Cont’d)
Table 16 – Absolute Maximum Ratings ...........................................................................................................55
Table 17 – Operating Conditions..........................................................................................................................56
Table 18 – DC Characteristics .................................................................................................................................56
Table 19 – Power Supply Characteristics............................................................................................................57
Table 20 – Capacitance.............................................................................................................................................57
TIMING SPECIFICATIONS ................................................................................................................. 58
AC Measurement Conditions....................................................................................................... 58
Table 21 – AC Measurement Conditions............................................................................................................58
Figure 32 – Output Load for Impedance Parameter Measurements .......................................................58
Figure 33 – Output Load for all Other Parameter Measurements.............................................................58
Power Up Timing .......................................................................................................................... 59
Table 22 – Power-Up Delay Minimum Voltages and Timing.......................................................................59
Figure 34 – Power-Up Timing................................................................................................................................60
AC Timing Parameters.................................................................................................................. 61
Table 23 – AC Timing Parameters .........................................................................................................................61
Figure 35 – Synchronous Data Timing (READ) .................................................................................................63
Figure 36 – Synchronous Data Timing Fast Read (FREAD)...........................................................................63
Figure 37 – Synchronous Data Timing (WRITE) ...............................................................................................64
Figure 38 – Synchronous Data Timing Fast Write Quad Data and Fast Write Quad Address and
Data (FWQD and FWQAD)..............................................................................................................................64
Figure 39 – HOLD Timing.......................................................................................................................................65
PART NUMBERS AND ORDERING .................................................................................................... 66
Table 24 – Part Numbering System......................................................................................................................66
Table 25 – Ordering Part Numbers.......................................................................................................................66
PACKAGE CHARACTERISTICS .......................................................................................................... 67
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Table of Contents (Cont’d)
Table 26 – Thermal Resistance 16-pin SOIC .....................................................................................................67
Figure 40 – 16-SOIC Package Outline.................................................................................................................68
Figure 41 – 24 Ball BGA Package Outline..........................................................................................................70
HOW TO REACH US ........................................................................................................................... 72
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Copyright © 2018 Everspin Technologies, Inc.
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MR10Q010
OVERVIEW
The Serial Peripheral Interface, SPI, is becoming increasingly popular in system design due to the reduced
pin count of the serial interface and increasing data bandwidth offered when compared against x8 or x16
parallel interface architectures. The SPI interface has evolved from a single data line to a four data line, or
quad architecture. This interface provides a data bandwidth in excess of 50Mbytes/sec.
SPI is currently well-established in microcontroller/microprocessor based systems. The Everspin family of
single I/O SPI MRAM is popular in smart meter applications and a variety of other embedded systems. How-
ever, the 40MHz limitation with a single data I/O may be too slow for higher performance applications such
as the next generation RAID controllers, server system logs, and storage device buffers .
Operating at 52MB/second for both Read and Write the Everspin 1Mb Quad I/O SPI MRAM will meet the
needs of these applications. And as a non-volatile memory with over 20 years of data retention, this SPI
memory family is equally suited for embedded system data and program memory.
The Quad Peripheral Interface, QPI, mode provides a lower overhead to load commands, which will improve
system throughput when operating in an Execute in Place, XIP, environment. This added feature will make
the device attractive in embedded applications that store program code in an external memory. QPI effec-
tively increases the effective clock rate and, when combined with Quad SPI instructions, Quad SPI memory
performance will outstrip asynchronous parallel memories.
Table 1 – Operational Parameters Summary
Standby
Current Current Package
(mA)
Sleep
Voltage
(V)
Read/
Write
Active Current
R/W (mA)
Density
Interface
(μA)
3.3v V
DD
1 Mb
104MHz Quad SPI
52MB/sec
60/100
8.0
100
16-SOIC
1.8v V
DDQ
Operation in 3.3v Data Bus Systems - Evaluation Board Available
The Everspin MR10Q010 Quad SPI Serial MRAM requires a 3.3v V power supply and is designed to operate
DD
on a 1.8v I/O bus. Adapting the MR10Q010 to operate on a 3.3v data bus can be done by interfacing it to the
bus through a level translator.
An evaluation board is available to test this adaptation of the MR10Q010 in an existing system. It can be
2
connected to the bus at the board position currently occupied by a SPI or Quad SPI E PROM and operate
with the MR10Q010 I/O levels translated for operation on a 3.3v bus.
Contact Everspin for more information about the MR10Q010 3.3v evaluation board and adapting your 3.3v
bus system to operate with MR10Q010 MRAM.
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 1 – MR10Q010 Block Diagram
Address Register
Counter
SCK
CS
17
Instrucꢀon Decode
Control Logic
Write Protect
Clock Generator
SI or I/O
0
1 Mb
SPI MRAM
Array
Serial I/O
Interface
SO or I/O
WP or I/O
1
2
3
8
4
Data I/O
Register
NonvolaꢀleStatus
Register
HOLD or I/O
8
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 2 – System Configuration
SCK
MOSI or I/O
(Master Out - Slave In)
0
MISO or I/O
(Master In - Slave Out)
1
SO
I/O
SI
I/O
SCK
SO
I/O
SI
I/O
SCK
1
0
1
0
SPI
Micro Controller
WP HOLD
I/O I/O
WP HOLD
I/O I/O
CS
CS
2
3
2
3
CS (1)
WP or I/O (1)
2
HOLD or I/O (1)
3
CS (2)
WP or I/O (2)
2
HOLD or I/O (2)
3
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 3 – 16-SOIC Package Pin Assignments
HOLD (I/O 3)
SCK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDDQ
VDD
NC
SI (I/O 0)
VSS
NC
16-SOIC
16-SOIC
TOP VIEW
NC
NC
VSS
VDD
CS
VSSQ
SO (I/O 1)
WP (I/O 2)
Table 2 – 16-SOIC Pin Functions
Signal
Name
Quad SPI
Mode
Pin
SPI Mode
Description
1
An active low chip select for the serial MRAM. When chip select is
high, the memory is powered down to minimize standby power,
inputs are ignored and the serial output pin is Hi-Z. Multiple serial
memories can share a common set of data pins by using a unique
chip select for each memory.
CS
7
8
Chip Select
Chip Select
SPI Mode: The data output pin is driven during a read operation and
remains Hi-Z at all other times. SO is Hi-Z when HOLD is low. Data
transitions on the data output occur on the falling edge of SCK.
SO (I/O )
Serial Output
Quad SPI Mode: Bidirectional I/O to serially write instructions, ad-
dresses or data to the device on the rising edge of SCK or read data
output from the device on the falling edge of SCK.
I/O
1
1
Table continues on next page.
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Copyright © 2018 Everspin Technologies, Inc.
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MR10Q010
16-SOIC Pin Functions - Continued
Signal
Name
Quad SPI
Mode
Pin
SPI Mode
Description
1
SPI Mode: A low on the write protect input prevents write opera-
tions to the Status Register.
WP (I/O )
9
Write Protect
I/O
2
Quad SPI Mode: Bidirectional I/O to serially write instructions, ad-
dresses or data to the device on the rising edge of SCK or read data
output from the device on the falling edge of SCK.
2
V
11, 14
10
Ground
Ground
Ground
Ground
Power supply ground pin.
I/O Voltage ground pin.
SS
V
SSQ
SPI Mode: All data is input to the device through this pin. This pin
is sampled on the rising edge of SCK and ignored at other times. SI
can be tied to SO to create a single bidirectional data bus if desired.
SI (I/O )
15
16
Serial Input
I/O
0
0
Quad SPI Mode: Bidirectional I/O to serially write instructions, ad-
dresses or data to the device on the rising edge of SCK or read data
output from the device on the falling edge of SCK.
Synchronizes the operation of the MRAM. The clock can operate up
to 104 MHz to shift commands, address, and data into the memory.
Inputs are captured on the rising edge of clock. Data outputs from
the MRAM occur on the falling edge of clock. The serial MRAM sup-
ports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1,
CPHA=1). In Mode 0, the clock is normally low. In Mode 3, the clock
is normally high. Memory operation is static so the clock can be
stopped at any time.
SCK
Clock
Clock
SPI Mode: A low on the HOLD pin interrupts a memory operation
for another task. When HOLD is low, the current operation is sus-
pended. The device will ignore transitions on the CS and SCK when
HOLD is low. All transitions of HOLD must occur while CS is low.
HOLD
1
HOLD
I/O
3
(I/O )
3
Quad SPI Mode: Bidirectional I/O to serially write instructions, ad-
dresses or data to the device on the rising edge of SCK or read data
output from the device on the falling edge of SCK.
V
3, 6
2
Power Supply
Power Supply Power supply voltage from +3.0 to +3.6 volts.
DD
I/O Bus Power
Supply
I/O Bus Power
V
I/O Bus supply voltage from +1.7 volts to +1.9 volts.
Supply
DDQ
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 4 – 24-BGA Package Ball Assignments
1
ꢀ
ꢁ
ꢂ
ꢃ
NC NC NC NC
•
•
•
•
•
24-ball BGA package.
VSS
NC
NC SCK
VDD NC
8mm x 6mm package outline.
Serial NOR Flash pinout compatible.
WP
NC
IOꢀ
V
on ball E4 to support 1.8v I/O.
ball.
NC
NC
CS
DDQ
No V
SSQ
SO
SO
HOLD
NC
IOꢁ
IOꢂ
IOꢃ
VDDQ
NC NC NC
NC
Table 3 – 24-BGA Ball Functions
Signal
Name
Quad SPI
Mode
Ball
SPI Mode
Description
1
An active low chip select for the serial MRAM. When chip select is
high, the memory is powered down to minimize standby power,
inputs are ignored and the serial output pin is Hi-Z. Multiple serial
memories can share a common set of data pins by using a unique
chip select for each memory.
CS
C2
Chip Select
Chip Select
SPI Mode: The data output pin is driven during a read operation and
remains Hi-Z at all other times. SO is Hi-Z when HOLD is low. Data
transitions on the data output occur on the falling edge of SCK.
SO (I/O )
D2
Serial Output
Quad SPI Mode: Bidirectional I/O to serially write instructions, ad-
dresses or data to the device on the rising edge of SCK or read data
output from the device on the falling edge of SCK.
I/O
1
1
Table continues on next page.
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Copyright © 2018 Everspin Technologies, Inc.
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MR10Q010
24-BGA Ball Functions - Continued
Signal
Name
Quad SPI
Mode
Ball
SPI Mode
Description
1
SPI Mode: A low on the write protect input prevents write opera-
tions to the Status Register.
WP (I/O )
C4
Write Protect
I/O
2
Quad SPI Mode: Bidirectional I/O to serially write instructions, ad-
dresses or data to the device on the rising edge of SCK or read data
output from the device on the falling edge of SCK.
2
V
B3
Ground
Ground
Power supply ground pin.
SS
SPI Mode: All data is input to the device through this pin. This pin
is sampled on the rising edge of SCK and ignored at other times. SI
can be tied to SO to create a single bidirectional data bus if desired.
Quad SPI Mode: Bidirectional I/O to serially write instructions, ad-
dresses or data to the device on the rising edge of SCK or read data
output from the device on the falling edge of SCK.
SI (I/O )
D3
Serial Input
I/O
0
0
Synchronizes the operation of the MRAM. The clock can operate up
to 104 MHz to shift commands, address, and data into the memory.
Inputs are captured on the rising edge of clock. Data outputs from
the MRAM occur on the falling edge of clock. The serial MRAM sup-
ports both SPI Mode 0 (CPOL=0, CPHA=0) and Mode 3 (CPOL=1,
CPHA=1). In Mode 0, the clock is normally low. In Mode 3, the clock
is normally high. Memory operation is static so the clock can be
stopped at any time.
SCK
B2
Clock
Clock
SPI Mode: A low on the HOLD pin interrupts a memory operation
for another task. When HOLD is low, the current operation is sus-
pended. The device will ignore transitions on the CS and SCK when
HOLD is low. All transitions of HOLD must occur while CS is low.
HOLD
D4
HOLD
I/O
3
(I/O )
3
Quad SPI Mode: Bidirectional I/O to serially write instructions, ad-
dresses or data to the device on the rising edge of SCK or read data
output from the device on the falling edge of SCK.
V
B4
E4
Power Supply
Power Supply Power supply voltage from +3.0 to +3.6 volts.
DD
I/O Bus Power
Supply
I/O Bus Power
V
I/O Bus supply voltage from +1.7 volts to +1.9 volts.
Supply
DDQ
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
STATUS REGISTER
The status register consists of the 8 bits shown in Table 3 below.
The Status Register Write Disable bit (SRWD, Bit 7) is used in conjunction with the Write Enable Latch (WEL,
bit 1) and the Write Protection pin (WP) to provide hardware memory block protection. Their usage for
memory block protection is defined in “Table 5 – Memory Protection Modes”. The Status Register Write Dis-
able bit is non-volatile and will remain set whenever power is removed from the memory. The WEL bit (Bit 7)
is volatile and set by the Write Enable command. It is set to “0”at power up and reset to “0”when recovering
from a loss of power.
The status of memory block protection is indicated by the states of bits BP0 and BP1 (Bits 2 and 3) and are
also defined in “Table 5 – Memory Protection Modes”on page 15. BP0 and BP1 are non-volatile and re-
main set if power is removed from the memory.
The QPI Mode bit (Bit 6) indicates whether the memory is in QPI mode or not. Its value is set when the En-
able QPI (EQPI) or Disable QPI (DQPI) commands are invoked. Logic “1”indicates QPI mode is enabled. The
QPI Mode Bit is volatile and set to “0”at power up and reset to “0”when recovering from a loss of power.
The fast writing speed of the MR10Q010 does not require write status bit information (Normally Bit 0). The
state of reserved bits 4, 5, and 0 can be modified by the user but do not affect memory operation.
All bits in the status register are pre-set at the factory to the “0”state.
Non-reserved Status Register bits are non-volatile with the exception of the WEL and QPI Mode which are
reset to 0 upon power cycling.
Table 4 – Status Register Bit Definitions
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
QPI Mode
(Volatile)
SRWD
(Non volatile)
BP1
BP0
WEL
(Volatile)
R2
R1
R0
(Non-Volatile) (Non-Volatile)
Bit Definitions:
7 - SRWD - Status Register Write Disable
6 - QPI Mode bit. Logic 1 = The device is in QPI Mode. Set by the Enable QPI (page 40) and Disable QPI Commands (page
41). Cannot be modified by the Write Status Register Command (page 21). Reset to “0”upon any power cycling.
5 - R2 - Reserved bit 2
4 - R1 - Reserved bit 1
3 - BP1 - Block Protect bit 1
2 - BP0 - Block Protect bit 0
1 - WEL - Write Enable Latch bit. Set by the Write Enable (page 19) Command. Reset to “0”upon any power cycling.
0 - R0 - Reserved bit 0. This is the “Write in Progress”bit for many memory devices. For MR10Q010, the “Write in progress”bit (bit
0) is not written by the memory because there is no write delay with MRAM.
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MR10Q010
Memory Protection Modes
When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1, BP0
and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1, status
register bits BP0 and BP1 can be modified. Once SRWD is set to 1, WP must be high to modify SRWD, BP0 and
BP1.
Table 5 – Memory Protection Modes
Status
WEL
SRWD
WP
Protected Blocks
Unprotected Blocks
Register
Protected
Writable
0
1
1
1
X
0
1
1
X
X
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Low
High
Protected
Writable
Block Protection Modes
The memory enters hardware block protection when the WP input is low and the Status Register Write Dis-
able (SRWD) Bit is set to 1. The memory leaves hardware block protection only when the WP pin goes high.
While WP is low, the write protection blocks for the memory are determined by the status register bits BP0
and BP1 and cannot be modified without taking the WP signal high again.
If the WP signal is high (independent of the status of SRWD Bit), the memory is in software protection mode.
This means that block write protection is controlled solely by the status register BP0 and BP1 block write pro-
tect bits and this information can be modified using the WRSR command.
Table 6 – Block Memory Write Protection
Status Register
Memory Contents
BP1
BP0
Protected Area
Unprotected Area
0
0
None
All Memory
0
1
Upper Quarter
Lower Three-Quarters
1
1
0
1
Upper Half
All
Lower Half
None
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
SPI COMMUNICATIONS PROTOCOL
The MR10Q010 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1).
For both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling
edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high.
The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when
CS falls.
All memory transactions start when CS is brought low to the memory. The first byte is a command code.
Depending upon the command, subsequent bytes of address are input. Data is either input or output.
There is only one command performed per CS active period. CS must go inactive before another command
can be accepted. To ensure proper part operation according to specifications, it is necessary to terminate
each access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping to avoid partial
or aborted accesses.
SPI MODE COMMANDS
All memory transactions start when CS is brought low, selecting the memory. The first byte is an 8-bit com-
mand code in hexadecimal. The subsequent 24 bits entered are address input. Following the address input
(except for the FREAD command) the device will read/write data beginning at the address entered.
For the FREAD command the Mode Byte must be entered following the address. The Mode Byte will either
set or reset the XIP mode. See ”Execute in Place (XIP) Mode”on page 42.
There is only one command performed per CS active period. CS must go inactive before another command
can be accepted. Note: To avoid partial or aborted accesses, memory access must remain active (CS low) for
a multiple of 8 clocks from CS going low (the end of a byte.)
At power up, the default operational mode is SPI mode.
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MR10Q010
Table 7 – SPI Mode Commands Overview
SPI Mode Commands Overview
Code
Description
Name
Operation
RDSR
Read Status Register
05h
Returns the contents of the 8 Status Register bits.
Sets the Write Enable Latch (WEL) bit in the status register to 1.
Sets the Write Enable Latch (WEL) bit in the status register to 0.
Writes new values to the entire Status Register.
Continuously reads data bytes starting at an initial address specified.
High-speed READ with XIP operation option.
WREN
WRDI
WRSR
READ
Write Enable
Write Disable
06h
04h
01h
03h
0Bh
02h
B9h
ABh
17h
4Bh
Write Status Register
Read Data Bytes
Fast Read Data Bytes
Write Data Bytes
Enter Sleep Mode
Exit Sleep Mode
Tamper Detect
Read ID
1
FREAD
WRITE
SLEEP
WAKE
TDET
Continuously writes data bytes starting at an address specified.
Initiates Sleep Mode.
Terminates Sleep Mode.
Returns 4 data bytes indicating corrupted or uncorrupted memory.
Returns the Everspin device ID assigned by JEDEC.
RDID
Notes:
1. FREAD has the option of using XIP operational mode. See “Execute in Place (XIP) Mode”on page 42 for details of XIP mode
with the FREAD command.
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MR10Q010
Read Status Register (RDSR)
The Status Register can be read at any time to check the status of the Write Enable Latch Bit, status register
Write Protect Bit, QPI mode, and the block write protect bits. The RDSR command is entered by driving CS
low, sending the command code, and then driving CS high.
See “Table 3 – Status Register Bit Definitions”on page 11 for Status Register Bit definitions.
Figure 5 – Read Status Register (RDSR) Command Operation
2
Clock Number
1
0 - 7
8 - 15
16 - 23
-
24 - 31
-
32 - 39
-
40 - n
Name
Operation
3
RDSR
Read Status Register
05h
S7-S0
-
Notes:
1. Clocks 0 - 7 are the command byte.
2. See “AC Timing Parameters”on page 61 for timing requirements.
3. See “Table 3 – Status Register Bit Definitions”on page 11 for status register bit definitions.
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCK
Instruction (05h)
0
0
0
0
0
1
0
1
SI
Status Register Bits
High Impedance
High Z
SO
7
6
5
4
3
2
1
0
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MR10Q010
Write Enable (WREN)
The Write Enable (WREN) command sets the Write Enable Latch Bit (WEL) in the status register (Bit 1). The
Write Enable Latch must be set prior to writing in the status register or the memory. The WREN command is
entered by driving CS low, sending the command code, and then driving CS high.
See “Table 3 – Status Register Bit Definitions”on page 11 for Status Register Bit definitions.
Figure 6 – Write Enable (WREN) Command Operation
1
Clock Number
2
0 - 7
8 - 15
-
16 - 23
-
24 - 31
-
32 - 39
-
40 - n
Name
Operation
WREN
Write Enable
06h
-
Notes:
1. See “AC Timing Parameters”on page 61 for timing requirements.
2. Clocks 0 - 7 are the command byte.
CS
Mode 3
Mode 0
Mode 3
0
1
2
3
4
5
6
7
SCK
Mode 0
Instruction (06h)
SI
0
0
0
0
0
1
1
0
High Impedance
SO
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MR10Q010 Revision 5.6, 6/2018
MR10Q010
Write Disable (WRDI)
The Write Disable (WRDI) command resets the Write Enable Latch (WEL) bit in the status register (bit 1) to 0.
This prevents writes to status register or memory. The WRDI command is entered by driving CS low, sending
the command code, and then driving CS high.
The Write Enable Latch (WEL) is reset to 0 on power-up or when the WRDI command is completed.
See “Table 3 – Status Register Bit Definitions”on page 11 for Status Register bit definitions.
Figure 7 – Write Disable (WRDI) Command Operation
1
Clock Number
2
0 - 7
04h
8 - 15
-
16 - 23
-
24 - 31
-
32 - 39
-
40 - n
Name
Operation
WRDI
Write Disable
-
Notes:
1. See “AC Timing Parameters”on page 61 for timing requirements.
2. Clocks 0 - 7 are the command byte.
CS
Mode 3
Mode 0
Mode 3
0
1
2
3
4
5
6
7
Mode 0
SCK
Instruction (04h)
0
0
0
0
0
1
0
0
SI
High Impedance
SO
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MR10Q010 Revision 5.6, 6/2018
MR10Q010
Write Status Register (WRSR)
The Write Status Register (WRSR) command allows new values for certain bits to be written to the Status
Register. The WRSR command cannot be executed unless the Write Enable Latch (WEL) has been set to 1 by
executing a WREN command while pin WP the SRWD Bit correspond to values that make the status register
writable as seen in Table 5 on page 15.
QPI Mode Bit, Bit 6, and the WEL Bit, Bit 0, are set by other commands and cannot be changed by this com-
mand.
The WRSR command is entered by driving CS low, sending the command code and status register write data
byte, and then driving CS high.
Figure 8 – Write Status Register (WRSR) Command Operation
Clock Number
1
2
0 - 7
8 - 15
16 - 23
-
24 - 31
-
32 - 39
-
40 - n
Name
Operation
WRSR
Write Status Register
01h
S7-S0
-
Notes:
1. Clocks 0 - 7 are the command byte.
2. Neither the QPI Mode Bit, Bit 6, or the WEL Bit, bit 0, can be changed by this command.
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
Mode 0
SCK
SI
1
Instruction (01h)
Status Register In
6 (DC)
0 (DC)
0
0
0
0
0
0
0
1
7
5
4
3
2
1
MSB
High Impedance
SO
Notes:
1. Neither the QPI Mode Bit, Bit 6, or the WEL Bit, bit 0, can be changed by this command. Treat as Don’t Care.
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MR10Q010
Read Data Bytes (READ)
The Read Data Bytes (READ) command allows data bytes to be continuously read starting at an initial ad-
dress specified by the 24-bit address entry. The data bytes are read out sequentially from memory until the
read operation is terminated by bringing CS high. The entire memory can be read in a single command.
The address counter will roll over to 0000H when the address reaches the top of memory.
The READ command is entered by driving CS low and sending the command code. The memory drives the
read data bytes on the SO pin. Reads continue as long as the memory is clocked. (Maximum READ clock
frequency 40MHz.) The command is terminated by bringing CS high.
Figure 9 – Read Data Bytes (READ) Command Operation
Clock Number
1
0 - 7
8 - 15
16 - 23
24 - 31
A7-A0
32 - 39
40 - n
Name
Operation
READ
Read Data Bytes
03h
A23-A16
A15-A8
D7-D0, until CS high
Notes:
1. Clocks 0 - 7 are the command byte.
2. For timing details, see “Figure 35 – Synchronous Data Timing (READ)”on page 63.
CS
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
Mode 3
Mode 0
SCK
Instruction (03h)
24-Bit Address
3
0
0
0
0
0
0
1
1
23
MSB
High Impedance
22
21
2
1
0
SI
Data Out 1
Data Out 2
7
6
5
4
3
2
1
0
7
SO
Data Clocked Out Continuously until CS high.
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MR10Q010
Fast Read Data Bytes (FREAD)
The Fast Read Data Bytes FREAD command is similar to the READ command except that the device can be
f
operated at the highest frequency ( SCK = 104MHz ) and the command has an XIP operation option. For
more detail on the XIP option, see “Table 13 – XIP Mode with FREAD Command”on page 43.
The FREAD command is entered by driving CS low and sending the command code. The memory drives the
read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi-
nated by bringing CS high.
Figure 10 – Fast Read Data Bytes (FREAD) Command Operation
Clock Number
1
0 - 7
8 - 15
16 - 23
24 - 31
32 - 39
40 - n
Name
Operation
2
D7-D0, until
CS high
Mode bits
(7-0)
FREAD
Fast Read Data Bytes
0Bh
A23-A16
A15-A8
A7-A0
Notes:
1. Clocks 0 - 7 are the command byte.
2. Mode Byte to Set/Reset XIP operation. Set/Continue XIP Mode = EFh. Reset XIP Mode FFh (exit XIP). See “Execute in Place
(XIP) Mode”on page 42 for more detailed information on XIP operation with FREAD.
3. For timing details, see “Figure 36 – Synchronous Data Timing Fast Read (FREAD)”on page 63.
CS
0
1
2
3
4
5
6
7
8
9
10
28
29
2
30
1
31
Mode 3
SCK Mode 0
Instruction (0Bh)
24-Bit Address
3
0
0
0
0
1
0
1
1
23
MSB
High Impedance
22
21
0
SI
LSB
SO
CS
31
32
33
34
35
36
37
38
39 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
SCK
Mode Bits Set /Reset XIP Mode
M7 M6 M5 M4 M3 M2
0
M1 M0
SI
Data Out 1
Data Out 2
High Impedance
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
SO
Data Clocked Out Continuously until CS high.
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MR10Q010
Write Data Bytes (WRITE)
The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by
the 24-bit address. The data bytes are written sequentially in memory until the write operation is terminat-
ed by bringing CS high. The entire memory can be written in a single command. The address counter will
roll over to 0000h when the address reaches the top of memory.
MRAM is a random access memory rather than a page, sector, or block organized memory so it is ideal for
both program and data storage. Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously
at its maximum rated clock speed without write delays or data polling. Back to back WRITE commands to
any random location in memory can be executed without write delay.
The WRITE command is entered by driving CS low, sending the command code, and then sequential write
data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS
high.
Figure 11 – Write Data Bytes (WRITE) Command Operation
Clock Number
1
0 - 7
8 - 15
16 - 23
24 - 31
A7-A0
32 - 39
40 - n
Name
Operation
WRITE
Write Data Bytes
02h
A23-A16
A15-A8
D7-D0, until CS high
Notes:
1. Clocks 0 - 7 are the command byte.
2. For timing details see “Figure 37 – Synchronous Data Timing (WRITE)”on page 64.
CS
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
Mode 3
Mode 0
SCK
SI
Instruction (02h)
24-Bit Address
3
Data Byte 1
0
0
0
0
0
0
1
0
23
MSB
High Impedance
22
21
2
1
0
7
6
5
4
3
2
1
0
MSB
SO
CS
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
SCK
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SI
MSB
MSB
High Impedance
SO
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MR10Q010 Revision 5.6, 6/2018
MR10Q010
Enter Sleep Mode (SLEEP)
The Enter Sleep Mode (SLEEP) command turns off all MRAM power regulators in order to reduce the overall
chip standby power to 15 μA typical. The SLEEP command is entered by driving CS low, sending the com-
t
mand code, and then driving CS high. The standby current is achieved after time, DP. See “Table 23 – AC
t
Timing Parameters”on page 61 for the DP value.
If power is removed when the part is in sleep mode, upon power restoration, the part enters normal standby.
The only valid command following SLEEP mode entry is a WAKE command.
Figure 12 – Enter Sleep Mode (SLEEP) Command Operation
Clock Number
1
0 - 7
8 - 15
-
16 - 23
-
24 - 31
-
32 - 39
-
40 - n
Name
Operation
SLEEP
Enter Sleep Mode
B9h
-
Notes:
1. Clocks 0 - 7 are the command byte.
CS
t DP
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
Instruction (B9h)
1
0
1
1
1
0
0
1
SI
Active Current
Standby Current
Sleep Mode Current
SO
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MR10Q010
Exit Sleep Mode (WAKE)
The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation.
The WAKE command is entered by driving CS low, sending the command code, and then driving CS high.
t
The memory returns to standby mode after RDP. See “Table 23 – AC Timing Parameters”on page 61 for
t
the RPD value.
t
The CS pin must remain high until the RDP period is over. WAKE must be executed after sleep mode entry
and prior to any other command when the device is in Sleep mode.
Figure 13 – Exit Sleep Mode (WAKE) Command Operation
Clock Number
1
0 - 7
8 - 15
-
16 - 23
-
24 - 31
-
32 - 39
-
40 - n
Name
Operation
WAKE
Exit Sleep Mode
ABh
-
Notes:
1. Clocks 0 - 7 are the command byte.
CS
t RDP
0
1
2
3
4
5
6
7
Mode 3
Mode 0
SCK
Instruction (ABh)
1
0
1
0
1
0
1
1
SI
Sleep Mode Current
Standby Current
SO
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MR10Q010
Tamper Detect (TDET)
The Tamper Detect command is used to check whether the memory contents have been corrupted by ex-
posure to external magnetic fields. The command is invoked by entering the command code followed by
the 8-bit Mode Byte. The device reads dedicated pre-programmed memory bits located around the memory
physical array. The contents of these bits are compared to reference bits that are hard programmed into the
device via a metal mask. The result of the comparison is returned in 32 status bits of data on SO beginning
after the last Mode Byte clock.
All 0’s in the 32 TDET status bits indicates that the tamper check bits are correct against the reference bits
and the memory has not been corrupted. Presence of any 1’s in the 32-bit string indicates that at least one
of the check bits does not match its reference bit and the memory contents have likely been corrupted.
Following CS high, any new command can be entered on the next access, except another TDET command.
If it is necessary to immediately enter another TDET command, a Tamper Detect Exit (TDETX) command must
be issued first to reset the device for another Tamper Detect sequence.
Figure 14 – Tamper Detect (TDET) Command Operation
Clock Number
1
0 - 7
8 - 15
16 - 47
48 - n
Name
Operation
Mode Byte
bits 7 - 0 3
2
TDET
Tamper Detect
17h
T31 - T0
CS high
Notes:
1. Clocks 0 - 7 are the command byte.
2. 32 Tamper Detect indication bits. Any 1’s present in the 32-bit string indicate probable corruption of the memory contents.
3. In the TDET command operation, the Mode Byte is used as a time delay to read the check and reference bits. The Mode Byte
must be set to FFh.
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
44 45
46
47
SCK
SI
Mode Bits 1
Instruction (4Bh)
Don’t Care
Don’t Care
M7
1
M6
1
M5
1
M4
1
M3
M2
M1
M0
0
1
0
0
1
0
1
1
1
1
1
1
High Impedance
High-Z
T29
T1
T0
T2
T31
T30
T3
SO
Notes:
1. In the TDET command operation, the Mode Byte must be set to FFh.
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MR10Q010
Tamper Detect Exit (TDETX)
After running a TDET command, any other command can be run as the next command, except another TDET
command. If another TDET command is to be run, then the Tamper Detect Exit (TDETX) command must
be run first to reset the device. This is necessary only if immediately running another TDET command. See
“Tamper Detect (TDET)”on page 27.
Figure 15 – Tamper Detect Exit (TDETX) Command Operation
Clock Number
1
2
0 - 7
8 - n
Name
Operation
TDETX
Tamper Detect Exit
07h
CS high. Any command can be entered on next access.
Notes:
1. Clocks 0 - 7 are the command byte.
2. After CS goes high any other command can be given on the next access.
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MR10Q010
Read ID (RDID)
The Read Device ID command (RDID) returns 40 bits of information that identify the Everspin device. The
command is invoked with CS low, and sending command code 4Bh on the Serial Input (SI) pin. See “Fig-
ure 16 – Read ID (RDID) Command Operation”below. After 8 clocks for the Mode Byte, 40 bits of data
uniquely identifying the Everspin device are returned on the Serial Out (SO) pin. See “Table 8 – Device ID for
MR10Q010”. If CS remains low after reading the 40 ID bits, additional clocks with CS low will return zeros on
SO until CS goes high.
Figure 16 – Read ID (RDID) Command Operation
Clock Number
1
0 - 7
8 - 15
16 - 23
24 - 31
32 - 39
40 - n
Name
Operation
Mode Byte 2
Bits 7 - 0
3
RDID
Read ID
4Bh
Device ID Clocks 16 - 55
Notes:
1. Clocks 0 - 7 are the command byte.
2. In the RDID command operation, the Mode Byte is used as a time delay to read the device ID bits. The Mode Byte must be
set to FFh.
3. For the Everspin device ID codes, see “Table 8 – Device ID for MR10Q010”on page 30.
CS
0
0
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
50 51
52
53
54 55
Mode 3
Mode 0
SCK
Mode Bits 1
Instruction (4Bh)
M7
1
M6
1
M5
1
M4
1
M3
M2
M1
M0
Don’t Care
0
0
1
0
1
1
1
1
1
1
SI
High Impedance
High-Z
Bit 39
Bit 38
Bit 37
Bit 36
Bit 35
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SO
Device ID Data Bits
Notes:
1. In the RDID command operation, the Mode Byte must be set to FFh.
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MR10Q010
Table 8 – Device ID for MR10Q010
RDID Device ID for MR10Q010
Bit #
39 - 24
23 - 20
19 - 16
15 - 12
Speed
11 - 8
7 - 4
3 - 0
Manufacturer’s ID
(JEP 106AH)
Meaning
Technology
Interface
Density
Voltage
Die Rev
Toggle
MRAM
3.3v V
1.8v V
/
DD
MR10Q010
Binary
6Bh, eighth bank
Quad IO SPI
0001
104MHz
0001
1 Mb
0001
A
DDQ
0000_0111_0110_1011
0001
0001
0001
Complete Hexadecimal and Binary Device ID for MR10Q010
Hexadecimal
Binary
076B111111
0000_0111_0110_1011_0001_0001_0001_0001_0001_0001
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MR10Q010
QUAD SPI MODE COMMANDS
Quad SPI commands allow data to be transferred to or from the device at least four times the rate of conven-
tional SPI mode. When using Quad SPI commands the DI and DO pins become bidirectional IO and IO , and
0
1
the WP and HOLD pins become IO and IO respectively. Address and data information can be input to the
2
3
device on four IO’s and data output can be read from four IO’s, offering a significant improvement in continu-
ous and random access transfers. XIP mode operation is available for FRQO and FRQAD commands.
Quad SPI Mode Commands Overview
Table 9 – Quad SPI Mode Commands Overview
Name
Operation
Code Description
Initial address entry on IO , returns data continuously in Quad SPI
Mode on all four I/O. Has XIP operation option.
1
0
FRQO
Fast Read Quad Output
6Bh
32h
EBh
12h
Initial address entry on IO , writes data continuously in Quad SPI
0
FWQD
Fast Write Quad Data
Mode on all four I/O.
Fast Read Quad Address
and Data
Initial address entry on all four IO’s, returns data continuously in
quad mode on all four I/O’s. Has XIP operation option.
1
FRQAD
Fast Write Quad Address
and Data
Initial address entry on all four IO’s, writes data continuously in quad
mode on all four I/O’s.
FWQAD
Notes:
1. XIP mode option. See “Execute in Place (XIP) Mode”on page 42 for details of how to use FRQD and FRQAD in XIP mode.
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Fast Read Quad Output (FRQO)
The Fast Read Quad Output (6Bh) command is similar to the Fast Read Output except that a data byte is
output on the four I/O pins, requiring only two clocks. An XIP mode is available for this command. See
“Table 14 – XIP Operation with FRQO Command”on page 47 for more information about XIP mode op-
eration. The I/O pins should be high impedance prior to the falling edge of the first Mode clock. The FRQO
command is entered by driving CS low and sending the command code. The memory drives the read data
bytes on the IO pins. Reads continue as long as the memory is clocked. The command is terminated by
bringing CS high.
Commmand Operation and Timing next page.
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MR10Q010
Figure 17 – Fast Read Quad Output (FRQO) Command Operation
Clock Number
24 - 31
1
0 - 7
8 - 15
16 - 23
32 - 33
34 - 35
36 - n
Name
Title
2
3
FRQO
Fast Read Quad Output
6Bh
A23-A16 A15 - A8
A7- A0 M7- M0
D7 - D0, until CS high
Notes:
1. Clocks 0 - 7 are the command byte. All commands and address bits on I/O .
0
2. Mode Byte. See “Execute in Place (XIP) Mode”on page 42 for more information on XIP operation with FRQO.
t
3. Quad Mode data output. I/O switches from Input to Output. I/O active outputs until CS returns high. CSH must be ob-
0
1-3
served for valid output when bringing CS high.
CS
0
1
2
3
4
5
6
7
8
9
10
28
29
2
30
1
31
Mode 3
SCK Mode 0
Instruction (6Bh)
24-Bit Address
3
IO0
0
1
1
0
1
0
1
1
23
22
21
0
MSB
LSB
High Impedance
IO1
IO2
IO3
High
High
(Low)
CS
31 32
33
1
34
35
36
37
38
39
40
1
41
SCK
Mode Bits
Set / Reset XIP
IO switches from Input to Output
LSB
0
IO0
IO1
IO2
IO3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
M4 M0
M5 M1
M6 M2
M7 M3
Byte 1
Byte 2
Byte 3
Byte 4
Data Clocked Out Continuously until CS high.
Note:
1. The I/O pins should be high impedance prior to the falling edge of the second mode clock.
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Fast Read Quad Address and Data (FRQAD)
The Fast Read Quad Address and Data (FRQAD) command is similar to the FRQO command except that the
address bits are loaded into the four I/O’s, requiring six clocks instead of 24. The data bytes also are read
from the four I/O’s as shown in Figure 18 below. An XIP operating mode is available for this command. See
“Table 15 – XIP Operation with FRQAD Command”on page 51 for more information on the XIP operating
mode for this command. The FRQAD command is entered by driving CS low and sending the command
code. The memory drives the read data bytes on the IO pins. Reads continue as long as the memory is
clocked. The command is terminated by bringing CS high.
Commmand Operation and Timing next page.
34
Copyright © 2018 Everspin Technologies, Inc.
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MR10Q010
Figure 18 – Fast Read Quad Address and Data (FRQAD) Command Operation
Clock Number
16 - 17
1
4
2
0 - 7
8 - 13
14- 15
18 - n
Name
Description
Fast Read Quad Address
and Data
2
3
FRQAD
EBh
A23 - A0 M7 - M0
D7 - D0 every two clocks until CS high
Notes:
1. Clocks 0 - 7 are the command byte. All commands and address bits on I/O .
0
2. Mode Byte. See “Execute in Place (XIP) Mode”on page 42 for more information on XIP operation with FRQAD.
t
3. Quad Mode data output. I/O switches from Input to Output. I/O active outputs until CS returns high. CSH must be ob-
0
1-3
served for valid output when bringing CS high.
4. For timing details, see “Figure 38 – Synchronous Data Timing Fast Write Quad Data and Fast Write Quad Address and Data
(FWQD and FWQAD)”on page 64.
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Mode 3
SCK Mode 0
24-Bit Address
A15 - 8
Instruction (EBh)
A23 - 16
A7 - 0
Mode Bits
IO0
1
1
1
0
1
0
1
1
12
20
16
8
4
0
High Impedance
IO1
IO2
IO3
21 17
22 18
23 19
13
14
15
9
5
6
7
1
2
3
High
High
10
11
(Low)
CS
13 14
15
16
17
18
19
20
21
22
23
SCK
1
Mode
Bits
IO switches from Input to Output
IO0
IO1
IO2
IO3
M4 M0
M5 M1
M6 M2
M7 M3
4
5
6
7
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
2
3
1
2
3
Byte 1
Byte 2
Byte 3
Byte 4
Data Clocked Out Continuously until CS high.
Note:
1. The I/O pins should be high impedance prior to the falling edge of the second mode clock.
35
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Fast Write Quad Data (FWQD)
The Fast Write Quad Data FWQD command provides a high speed write capability to the memory using four
f
I/O’s for data input. The FWQD command can operate at the highest frequency, SCK = 104MHz.
The FWQD command is entered by driving CS low and sending the command code (32h). Data is input on
all four I/O’s and Writes continue as long as the memory is clocked. The command is terminated by bringing
CS high.
Figure 19 – Fast Write Quad Data (FWQD) Command Operation
Clock Number
1
0 - 7
8 - 15
16 - 23
24 - 31
A7- A0
32 - 33
34 - 35
36 - n
Name
Title
D7 - D0 every two clocks until CS
FWQD
Fast Write Quad Data
32h
A23-A16 A15 - A8
2
high
Notes:
1. Clocks 0 - 7 are the command byte. All commands and address bits on I/O .
0
2. Quad Mode address input. I/O remains input. I/O active inputs until CS returns high.
0
1-3
3. For timing details, see “Figure 38 – Synchronous Data Timing Fast Write Quad Data and Fast Write Quad Address and Data
(FWQD and FWQAD)”on page 64.
CS
0
1
2
3
4
5
0
6
1
7
0
8
9
10
29
30
1
31
0
Mode 3
SCK Mode 0
Instruction (32h)
24-Bit Address
2
21
IO0
23
22
0
0
1
1
0
IO1
IO2
IO3
High Impedance
High
High
(Low)
CS
31 32
33
34
35
36
37
38
39
SCK
Data Bytes
IO0
4
0
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
IO1
IO2
IO3
5
6
7
1
2
3
Byte 1
Byte 2
Byte 3
Byte 4
Byte n
Data Writes Continuously until CS high.
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MR10Q010 Revision 5.6, 6/2018
MR10Q010
Fast Write Quad Address and Data (FWQAD)
The Fast Write Quad Address and Data Command (FWQAD) provides a very fast write at both the highest
frequency and fewest clock cycles. The 24-bit address is input on all four I/O’s, reducing the number of clock
cycles. The data bytes to be written are also input on all four I/O’s following the address bits. The FWQAD
f
command can operate at the highest frequency, SCK = 104MHz.
The FWQAD command is entered by driving CS low and sending the command code (12h). Data are input
on all four I/O’s and Writes continue as long as the memory is clocked. The command is terminated by bring-
ing CS high.
Figure 20 – Fast Write Quad Address and Data (FWQAD) Command Operation
Clock Number
1
4
2
0 - 7
8 - 13
14 - 15
16 - n
Name
Description
Fast Write Quad Address
and Data
2
FWQAD
12h
A23 - A0
D7 - D0 every two clocks until CS high
Notes:
1. Clocks 0 - 7 are the command byte. All commands and address bits on I/O .
0
2. Quad Mode address input. I/O remains input. I/O active inputs until CS returns high.
0
1-3
CS
0
0
1
2
3
4
5
0
6
1
7
0
8
9
10
11
12
13
Mode 3
SCK Mode 0
24-Bit Address
A15 - 8
Instruction (12h)
A23 - 16
20 16
A7 - 0
0
IO0
0
0
1
0
12
8
4
IO1
IO2
IO3
21 17
22 18
23 19
13
14
15
9
5
6
7
1
2
3
High Impedance
High
10
11
High
(Low)
CS
13 14
15
16
17
18
19
20
21
SCK
Data Bytes
IO0
IO1
IO2
IO3
4
5
6
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
4
0
1
2
3
5
6
7
1
2
7
3
Byte 1
Byte 2
Byte 3
Byte 4
Byte n
Data Writes Continuously until CS high.
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
QPI MODE
QPI Mode is designed to reduce command entry overhead in an XIP environment. QPI mode allows the
instruction code to be entered on all four I/O’s, which reduces the number of clock cycles required for com-
mand entry to two from eight. Otherwise, all SPI or Quad SPI commands operate normally.
In SPI or Quad SPI mode device operation is determined by which command is entered. To operate in QPI
Mode, the device must be specifically placed into QPI Mode by invoking the Enable QPI Command. When
in QPI Mode, the Status Register Bit 6 is set to 1 and will reset to 0 when either power is removed from the
device or the QPI Mode is exited with an DQPI command.
At power up, QPI mode is disabled.
Table 10 – SPI Mode Command Structures in QPI Mode
Clock Number
1
0 - 1
2 - 9
10 - 17
-
18 - 25
-
26 - 33
-
34 - n
Name
Description
RDSR
Read Status Register
05h
S7-S0
-
WREN
WRDI
WRSR
READ
Write Enable
Write Disable
06h
04h
01h
03h
-
-
-
-
-
-
-
-
-
-
-
-
-
Write Status Register
Read Data Bytes
S7-S0
A23-A16
-
A15-A8
A7-A0
D7-D0 until CS high
D7-D0 until
CS high
2
FREAD
WRITE
Fast Read Data Bytes
Write Data Bytes
08h
02h
A23-A16
A23-A16
A15-A8
A15-A8
A7-A0
A7-A0
M7 - M0
D7-D0 until CS high
SLEEP
WAKE
TDET
RDID
DQPI
Enter Sleep Mode
Exit Sleep Mode
Tamper Detect
Read ID
B9h
ABh
17h
4Bh
FFh
-
-
-
-
-
-
-
-
-
-
3
M7 - M0
M7 - M0
-
T7 - T0
3
Device ID 40 bits
Disable QPI
-
-
-
-
Notes:
1. Clocks 0 - 1 are the command bits while in QPI mode.
2. M7 - M0 is the Mode Byte to Set/Reset XIP Mode. Set XIP Mode = EFh; Reset XIP Mode = FFh.
3. Mode Byte must be FFh for TDET and RDID.
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Table 11 – Quad SPI Mode Command Structures in QPI Mode
Clock Number
1
0 - 1
FFh
2 - 9
-
10 - 17
18 - 25
-
26 - 27
-
28 - n
Name
Description
DQPI
Disable QPI
-
-
D7-D0 until
CS high
Fast Read Quad
Output
2
FRQO
6Bh
32h
A23-A16
A23-A16
A15-A8
A7-A0
A7-A0
M7 - M0
FWQD
Fast Write Quad Data
A15-A8
D7-D0 until CS high
Clock Number
1
0 - 1
2 - 3
4 - 5
6 - 7
8 - 9
10 - n
Name
Description
D7-D0 until
CS high
Fast Read Quad Ad-
dress and Data
2
FRQAD
EBh
A23-A16
A15-A8
A7-A0
M7 - M0
Fast Write Quad Ad-
dress and Data
FWQAD
12h
A23-A16
A15-A8
A7-A0
D7-D0 until CS high
Notes:
1. Clocks 0 - 1 are the command bits while in QPI mode.
2. Mode Byte. Set/Reset XIP operating mode. See “Execute in Place (XIP) Mode”on page 42.
39
Copyright © 2018 Everspin Technologies, Inc.
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MR10Q010
Enable QPI (EQPI) Command
The Enable QPI command is used to enter the device into QPI mode. The command code, 38h, is entered
on the DI pin. The command is entered by driving CS low and sending the command code. The command is
terminated by driving CS high. When in QPI Mode, the Status Register Bit 6 is set to “1”and the device stays
in QPI mode until a power-on reset or the Disable QPI command is entered.
Figure 21 – Enable QPI Mode (EQPI) Command Operation
Clock Number
1
0 - 7
8
9 - n
Name
Description
EQPI
Enable QPI Mode
38h
CS high
In QPI Mode
Notes:
1. Clocks 0 - 7 are the command byte.
CS
0
0
1
0
2
3
4
5
0
6
0
7
0
Mode 3
SCK Mode 0
Instruction (38h)
SI
1
1
1
High Impedance
SO
40
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Disable QPI (DQPI) Command
The Disable QPI command is used to exit QPI mode and return to the standard SPI/Quad SPI mode and set
the Status Register Bit 6 to “0”.
The command code FFh is entered on all four IO’s in just two clock cycles as shown below. The command is
entered by driving CS low and sending the command code. The command is terminated by driving CS high.
Figure 22 – Disable QPI Mode (DQPI) Command Timing
Clock Number
1
0 - 1
FFh
2
9 - n
Name
Description
DQPI
Disable QPI Mode
CS high
Now in SPI / Quad SPI Mode
Notes:
1. Clocks 0 - 1 are the command byte on all four I/O.
CS
0
1
Mode 3
SCK
Mode 0
Instruction (FFh)
IO0
IO1
IO2
IO3
1
1
1
1
1
1
1
1
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
EXECUTE IN PLACE ꢀXIPꢁ MODE
Execute in Place (XIP) mode provides faster read operations by not requiring a command code for each
new starting address during consecutive reads. This improves random access time and eliminates the need
to shadow code onto RAM for fast execution. The read commands supported in XIP mode are FREAD (SPI
Mode), FRQO, and FRQAD (both Quad SPI Mode commands).
XIP may be run when in QPI mode. Entering or exiting XIP mode will not affect other aspects of QPI mode
operation. The device will stay in QPI mode until QPI is disabled with the DQPI command.
XIP mode for these commands is Set or Reset by entering the Mode Byte as shown in “Table 12 – Mode Byte
Definitions to Set/Reset XIP Mode”on page 42 below.
In XIP Mode it is possible to perform a series of reads beginning at different addresses without having to
load the command code for every new starting address / CS cycle. XIP can be entered or exited during
these commands at any time and in any sequence. If it is necessary to perform another operation, not
supported by XIP, such as a write, then XIP must be exited before the new command code is entered for the
desired operation.
Table 12 – Mode Byte Definitions to Set/Reset XIP Mode
XIP Operation
Hex
M7
M6
M5
M4
M3
M2
M1
M0
1
1
0
1
1
Set/Continue
EF
1
1
1
1
1
1
1
1
Reset/Stop (Default)
FF
1
1
1
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Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Table 13 – XIP Mode with FREAD Command
Initial Command
SPI Mode
Clock Number
1
0 - 7
0 - 1
8 - 31
3 - 26
32 - 39
27 - 34
40 - 47
35 - 42
48 - n
43 - n
1
QPI Mode
2
FREAD
Fast Read Data Bytes
0Bh
A23-A0
M7 - M0
Set XIP
D7 - D0
Read Next Byte
Read Data
Byte
24-bit Address
Repeat until CS goes high.
3
Mode
Notes:
1. Command code eight bits.
2. Mode Byte will Set/Reset the XIP mode. See “Table 12 – Mode Byte Definitions to Set/Reset XIP Mode”on page 42 above
for the Set/Reset XIP mode bit definitions.
3. If the XIP mode is not Set on the initial command, the command operates in normal SPI Mode until CS high. And, on the next
new address, the FREAD the command must be reentered. If XIP Mode has been Set during this initial command entry, the
command still operates normally until CS goes high. But on the next CS low, the device remains in FREAD Command mode.
No command is entered and the initial read address is entered on the first clock. See the table below.
If XIP Set - Next CS Low
Clock Number
32 - 39
1
Either SPI or QPI Mode
0 - 23
24 - 31
40 - n
FREAD
Fast Read Data Bytes
A23-A0
M7 - M0
D7 - D0
Read Next Byte
If XIP Mode is Set, the Command need
not be reentered. Initial 24-bit ad-
dress entry begins on the first clock.
Set/Reset XIP
Mode
Read Data
Byte
24-bit Address
Repeat until CS goes high.
Notes:
1. In XIP mode, the last command code sent remains in effect. The starting address is entered beginning on the first clock after
CS low.
2. If XIP Mode is Reset, the device is out of XIP mode and any command may be entered on the next access.
43
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 23 – FREAD Command- Set XIP Mode - Initial Access
CS
0
1
2
3
4
5
6
7
8
9
10
28
29
2
30
1
31
Mode 3
SCK Mode 0
Instruction (0Bh)
24-Bit Address
3
0
0
0
0
1
0
1
1
23
MSB
High Impedance
22
21
0
SI
LSB
SO
CS
31
32
33
34
35
36
37
38
39 40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
SCK
SI
1
1
EFh Set XIP Mode
0
1
1
1
0
1
1
1
LSB
Read Data Byte
Read Next Byte
High Impedance
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Data Clocked Out Continuously until CS high.
Note:
1. Initial FREAD access, XIP mode set for next access.
Copyright © 2018 Everspin Technologies, Inc.
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MR10Q010
Figure 24 – FREAD Command - XIP Mode Set - Next Access
CS
0
1
2
20
21
2
22
1
23
Mode 3
SCK Mode 0
24-Bit Address
3
23
MSB
22
21
0
SI
LSB
High Impedance
SO
CS
23
24
25
26
27
28
29
30
31 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
SCK
SI
1
EFh Continue XIP Mode
0
1
1
1
0
1
1
1
1
LSB
Read Data Byte
Read Next Byte
High Impedance
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Data Clocked Out Continuously until CS high.
Note:
1. Continue FREAD in XIP Mode after this access.
45
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 25 – FREAD Command - XIP Mode Exit
CS
0
1
2
20
21
2
22
1
23
Mode 3
SCK Mode 0
24-Bit Address
3
23
MSB
22
21
0
SI
LSB
High Impedance
SO
CS
23
24
25
26
27
28
29
30
31 32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
SCK
SI
1
FFh Exit XIP Mode
0
1
1
1
1
1
1
1
1
LSB
Read Data Byte
Read Next Byte
High Impedance
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SO
Data Clocked Out Continuously until CS high.
Note:
1. XIP Mode code FFh: Reset XIP Mode. After this access a comnmand must be entered on the next access. Any new command may be en-
tered, including the original command.
46
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Table 14 – XIP Operation with FRQO Command
Initial Command
Quad SPI Mode
QPI Mode
Clock Number
1
0 - 7
0 - 1
8 - 31
2 - 25
32 - 33
26 - 27
34 - 35
28 - 29
36 - n
30 - n
1
Fast Read Quad
Output
2
FRQO
6Bh
A23-A0
M7 - M0
Set XIP
D7 - D0
Read Next Byte
Read Data
Byte
24-bit Address
Repeat until CS goes high.
3
Mode
Notes:
1. Command code eight bits.
2. Mode Byte entered Set/Reset the XIP mode. See “Table 12 – Mode Byte Definitions to Set/Reset XIP Mode”on page 42
above for the Set/Reset XIP mode bit definitions.
3. If the XIP mode is not set on the initial command, the command operates in normal SPI Mode until CS high. And, on the next
FRQO the command must be reentered. If XIP has been set during this initial command entry, the command still operates
normally until CS goes high. But on the next CS low, the device remains in FRQO Command mode, and the initial read ad-
dress is entered on the first clock. See the table below.
If XIP Set - Next CS Low
Either Quad SPI or QPI Mode
0 - 23
24 - 25
26 - 27
D7 - D0
28 - n
Fast Read Quad
FRQO Set
Output
A23-A0
M7 - M0
Read Next Byte
If XIP Mode is Set, the Command
need not be reentered. Initial 24-bit
address entry begins on the first
clock.
Set/Reset XIP
Mode
24-bit Address
Read Data Byte
Repeat until CS goes high.
Notes:
1. In XIP operating mode, the last command code sent remains in effect and no command entry is required on the next access.
47
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 26 – FRQO Command - Set XIP Mode - Initial Access
CS
0
1
2
3
4
5
6
7
8
9
10
28
29
2
30
1
31
Mode 3
SCK Mode 0
Instruction (6Bh)
24-Bit Address
3
IO0
0
1
1
0
1
0
1
1
23
MSB
22
21
0
LSB
High Impedance
IO1
IO2
IO3
High
High
(Low)
CS
31 32
33
34
35
36
37
38
39
40
41
SCK
1,2
EFh
Set XIP
Mode
IO switches from Input to Output 2
LSB
IO0
IO1
IO2
IO3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
1
1
1
0
1
1
1
Byte 1
Byte 2
Byte 3
Byte 4
Data Clocked Out Continuously until CS high.
Notes:
1. Initial access, XIP Mode Byte set for next access.
2. The I/O pins should be high impedance prior to the falling edge of the second mode clock.
48
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 27 – FRQO Command - XIP Mode Set - Next Access
CS
0
1
2
20
21
2
22
1
23
Mode 3
SCK Mode 0
24-Bit Address
3
IO0
23
MSB
22
21
0
LSB
High Impedance
IO1
IO2
IO3
High
High
(Low)
CS
23 24
25
26
27
28
29
30
31
32
33
SCK
1,2
EFh
Set (Continue)
XIP
2
IO switches from Input to Output
Mode
LSB
IO0
IO1
IO2
IO3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
0
1
1
1
1
1
1
1
0
5
6
7
Byte 1
Byte 2
Byte 3
Byte 4
Data Clocked Out Continuously until CS high.
Notes:
1. Next access, set to continue XIP Mode.
2. The I/O pins should be high impedance prior to the falling edge of the second mode clock.
49
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 28 – FRQO Command - XIP Mode Exit
CS
0
1
2
20
21
2
22
1
23
Mode 3
SCK Mode 0
24-Bit Address
3
IO0
23
MSB
22
21
0
LSB
High Impedance
IO1
IO2
IO3
High
High
(Low)
CS
23 24
25
26
27
28
29
30
31
32
33
SCK
1,2
FFh
Reset
XIP
Mode
2
IO switches from Input to Output
LSB
IO0
IO1
IO2
IO3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
1
1
0
1
1
1
1
1
1
Byte 1
Byte 2
Byte 3
Byte 4
Data Clocked Out Continuously until CS high.
Notes:
1. XIP Mode Byte FFh. Exit XIP Mode.
2. The I/O pins should be high impedance prior to the falling edge of the second mode clock.
3. After this access a command must be entered on the next access. Any new command may be entered, including the original
command.
50
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Table 15 – XIP Operation with FRQAD Command
Initial Command
Quad SPI Mode
QPI Mode
Clock Number
1
0 - 7
0 - 1
8 - 13
2 - 7
14 - 15
8 - 9
16 - 17
10 - 11
18 - n
12 - n
1
Fast Read Quad Ad-
dress and Data
2
FRQAD
EBh
A23-A0
M7 - M0
Set XIP
D7 - D0
Read Next Byte
Read Data
Byte
24-bit Address
Repeat until CS goes high.
3
Mode
Notes:
1. Command code eight bits.
2. Mode Byte entered Set/Reset the XIP mode. See “Table 12 – Mode Byte Definitions to Set/Reset XIP Mode”on page 42
above for the Set/Reset XIP mode bit definitions.
3. If the XIP mode is not set on the initial command, the command operates in normal SPI Mode until CS high. And, on the next
FRQAD the command must be reentered. If XIP has been set during this initial command entry, the command still operates
normally until CS goes high. But on the next CS low, the device remains in FREAD Command mode, and the initial read ad-
dress is entered on the first clock. See the table below.
If XIP Set - Next CS Low
Either Quad SPI or QPI Mode
0 - 5
6 - 7
8 - 9
10 - n
Fast Read Quad Ad-
dress and Data
FRQAD Set
A23-A0
M7 - M0
D7 - D0
Read Next Byte
If XIP Mode is Set, the Command
need not be reentered. Initial 24-bit
address entry begins on the first
clock.
Set/Reset XIP
Mode
24-bit Address
Read Data Byte
Repeat until CS goes high.
Notes:
1. In XIP operating mode, the last command code sent remains in effect and no command entry is required on the next access.
51
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 29 – FRQAD Command - Set XIP Mode - Initial Access
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
Mode 3
SCK Mode 0
24-Bit Address
A15 - 8
Instruction (EBh)
A23 - 16
A7 - 0
IO0
1
1
1
0
1
0
1
1
12
20
16
8
4
0
High Impedance
IO1
IO2
IO3
21 17
22 18
23 19
13
14
15
9
5
6
7
1
2
3
High
High
10
11
(Low)
CS
13 14
15
16
17
18
19
20
21
22
23
SCK
1
EFh
IO switches from Input to Output2
Set XIP
Mode
IO0
IO1
IO2
IO3
0
1
1
1
1
4
5
6
7
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
0
1
2
3
1
1
1
1
2
3
Byte 1
Byte 2
Byte 3
Byte 4
Data Clocked Out Continuously until CS high.
Notes:
1. Initial access, XIP Mode Byte set for next access.
2. The I/O pins should be high impedance prior to the falling edge of the second mode clock.
52
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 30 – FRQAD Command - XIP Mode Set - Next Access
CS
0
1
2
3
4
5
Mode 3
SCK Mode 0
24-Bit Address
A15 - 8
A23 - 16
A7 - 0
0
IO0
12
20
16
8
4
IO1
IO2
IO3
21 17
22 18
23 19
13
14
15
9
5
6
7
1
2
3
10
11
(Low)
CS
5
6
7
8
9
10
11
12
13
14
15
SCK
1
EFh
IO switches from Input to Output2
Set (Continue)
XIP Mode
IO0
0
1
1
1
1
1
1
1
4
5
6
7
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
0
IO1
1
IO2
2
IO3
3
Byte 1
Byte 2
Byte 3
Byte 4
Data Clocked Out Continuously until CS high.
Notes:
1. Next access, set to continue XIP Mode.
2. The I/O pins should be high impedance prior to the falling edge of the second mode clock.
53
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 31 – FRQAD Command - XIP Mode Exit
CS
0
1
2
3
4
5
Mode 3
SCK Mode 0
24-Bit Address
A15 - 8
A23 - 16
A7 - 0
0
IO0
12
20
16
8
4
IO1
IO2
IO3
21 17
22 18
23 19
13
14
15
9
5
6
7
1
2
3
10
11
(Low)
CS
5
6
7
8
9
10
11
12
13
14
15
SCK
1
FFh
IO switches from Input to Output2
Reset (Exit)
XIP Mode
IO0
1
1
1
1
1
1
1
1
4
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
0
1
2
3
0
IO1
5
6
7
1
IO2
2
IO3
3
Byte 1
Byte 2
Byte 3
Byte 4
Data Clocked Out Continuously until CS high.
Notes:
1. XIP Mode Byte FFh. Exit XIP Mode.
2. The I/O pins should be high impedance prior to the falling edge of the second mode clock.
3. After this access a command must be entered on the next access. Any new command may be entered, including the original
command.
54
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
ELECTRICAL SPECIFICATIONS
This device contains circuitry to protect the inputs against damage caused by high static voltages or electric
fields. However, it is advised that normal precautions be taken to avoid application of any voltage greater
than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to avoid
application of any magnetic field more intense than the maximum field intensity specified in the maximum
ratings.
Table 16 – Absolute Maximum Ratings
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted to
recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability.
Symbol Parameter
Conditions
Value
Unit
1
V
Supply voltage
-0.5 to 4.0
V
DD
1
V
I/O Bus Supply voltage
-0.5 to 2.4
V
V
DDQ
1
V
Voltage on any pin
-0.5 to V
+ 0.5
DDQ
IN
I
Output current per pin
20
mA
°C
OUT
T
Temperature under bias
Storage Temperature
Commercial Grade
-45 to 95
BIAS
T
stg
-55 to 150
260
°C
°C
T
Lead temperature during solder (3 minute max)
Lead
H
Maximum magnetic field during write
Write
12,000
12,000
A/m
A/m
max_write
Maximum magnetic field during read or
standby
H
Read or Standby
max_read
Notes:
1. All voltages are referenced to V . The DC value of V must not exceed actual applied V by more than 0.5V. The AC value of
SS
IN
DD
V
must not exceed applied V by more than 2V for 10ns with I limited to less than 20mA.
DD IN
IN
55
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Table 17 – Operating Conditions
Symbol
Parameter
Conditions
Min
Typical
Max
Unit
V
Power supply voltage
3.0
3.3
3.6
V
DD
V
I/O Bus Power supply voltage
Input high voltage
1.7
1.4
1.8
2.0
V
V
DDQ
V
V
+ 0.2
DDQ
IH
V
Input low voltage
-0.2
0
0.4
70
V
IL
Commercial Grade
°C
°C
°C
Ambient temperature
under bias
T
Industrial Grade
Extended Grade
-40
-40
85
A
105
Table 18 – DC Characteristics
Symbol
Parameter
Conditions
Min
Max
Unit
I
Input leakage current
-
-
-
2
μA
μA
V
IL
I
Output leakage current
Output low voltage
Output high voltage
2
0.4
-
OL
V
I
I
= 4mA
OL
OL
V
= -100μA
1.4
V
OH
OH
56
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Table 19 – Power Supply Characteristics
Symbol Parameter
Conditions
Typical
Max
Unit
SPI @ 1 MHz
5.0
11
mA
SPI @ 40 MHz
12
-
17
60
mA
mA
I
Active Read Current
DDR
Quad SPI @
104MHz
@ 1 MHz
9.0
28
25
42
mA
mA
@ 40 MHz
I
Active Write Current
DDW
Quad SPI @
104MHz
-
-
100
3
mA
mA
I
Active V
Current
Note 1
DDQ
DDQ
AC Standby Current (CS High = V . No other
restrictions on other inputs.)
IH
I
f ≤104MHz
-
8
mA
SB1
AC Standby Current on V
supply (CS High =
DDQ
I
f ≤104MHz
f = 0 MHz
-
-
-
-
1
3
mA
mA
μA
SB1Q
V . No other restrictions on other inputs.)
IH
I
CMOS Standby Current (CS High)
SB2
CMOS Standby Current on V
High)
Supply (CS
DDQ
I
f = 0 MHz
10
100
SB2Q
I
Standby Sleep Mode Current (CS High)
Sleep Mode
μA
ZZ
Note
1.
I
Conditions: Quad SPI at 104MHz, V
= 2.0v, V = 1.8v, V = 0v.
DDQ IH IL
DDQ
Table 20 – Capacitance
Symbol Parameter
Typical
Max
Unit
1
1
C
Control input capacitance
-
6
pF
In
C
Input/Output capacitance
-
8
pF
I/O
Notes:
1. ƒ = 1.0 MHz, dV = 3.0 V, T = 25 °C, periodically sampled rather than 100% tested.
A
57
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
TIMING SPECIFICATIONS
AC Measurement Conditions
Table 21 – AC Measurement Conditions
Parameter
Value
Unit
Logic input timing measurement reference level
Logic output timing measurement reference level
Logic input pulse levels
0.9
V
0.9
0 to 1.6
2
V
V
ns
Input rise/fall time
Output load for low and high impedance parameters
Output load for all other timing parameters
See Figure 32
See Figure 33
Figure 32 – Output Load for Impedance Parameter Measurements
Output
RL = 50Ω
VL = VDCQ /2
Figure 33 – Output Load for all Other Parameter Measurements
1.8ꢄ
R1
ꢀꢁꢂꢃꢁꢂ
ꢅ0 ꢃꢆ
R2
58
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Power Up Timing
To provide protection for data during initial power up, power loss or brownout, whenever V falls below
DD
V
or V
falls below V
the device cannot be selected (CS is restricted from going low) and the
WIDD
DDQ
WIDDQ
device is inhibited from Read or Write operations. See “Table 22 – Power-Up Delay Minimum Voltages and
Timing”below.
Power Up Delay Time
t
During initial power up or when recovering from brownout or power loss, a power up delay time ( PU)
must be added to the time required for voltages to rise to their specified minimum voltages (V
and
DD(min)
V
) before normal operations may commence. This time is required to insure that the device internal
DDQ(min)
voltages have stabilized. See “Table 22 – Power-Up Delay Minimum Voltages and Timing”below.
t
PU is measured from the time that both V and V
have reached their specified minimum voltages. See
DD
DDQ
“Figure 34 – Power-Up Timing”for an illustration of the timing.
During initial startup or power loss recovery the CS pin should always track V
(up to V
+ 0.2 V) or
DDQ
DDQ
t
V , whichever is lower, and remain high for the total startup time, PU. In most systems, this means that CS
IH
should be pulled up to V
with a resistor. Any logic that drives other inputs or IOs should hold the signals
DDQ
at V
until normal operation can commence.
DDQ
Table 22 – Power-Up Delay Minimum Voltages and Timing
Symbol
Parameter
Min
Unit
V
Write Inhibit Voltage
2.2
V
WIDD
V
I/O Write Inhibit Voltage
Power Up Delay Time
1.2
V
WIDDQ
t
PU
400
μs
59
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 34 – Power-Up Timing
BROWNOUT or
POWER LOSS
INITIAL
POWER ON
t
t
PU
PU
RECOVER
TIME
STARTUP
TIME
READ/WRITE operations
inhibited
READ/WRITE operations
inhibited
NORMAL
OPERATION
NORMAL
OPERATION
VDD
VDD min
VWIDD
VDDQ
VDDQ min
VWIQQ
Note: CS may not be enabled until tPU startup or recovery time is met.
60
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
AC Timing Parameters
Table 23 – AC Timing Parameters
Symbol Parameter
Min
Typical
Max
Unit
SCK Clock Frequency for all instructions except READ
-
-
104
MHz
f
SCK
SCK Clock freq for READ
-
-
-
-
-
-
-
-
40
50
50
-
MHz
ns
t
RI
Input Rise Time
-
t
RF
Input Fall Time
-
ns
t
WH
SCK High Time except READ
SCK High Time READ
SCK Low Time except READ
SCK Low Time READ
4
ns
t
WHR
11
4
-
ns
t
WL
-
ns
t
WLR
12
-
ns
Synchronous Data Timing see Figures 35, 36, 37, 38
t
CSS
CS Setup Time
5
5
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
t
CSH
CS Hold Time
t
SU
Data In Setup Time
2
-
t
H
Data In Hold Time
5
-
t
V
Output Valid
-
7
-
t
HO
Output Hold Time
1.5
10
50
t
CS
CS High Time at end of all Cycles except Writes
CS High Time at end of Write Cycles
-
t
CSW
-
61
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
AC Timing Parameters - Continued
Symbol Parameter
Min
Typical
Max
Unit
HOLD Timing see Figure 39
t
HD
HOLD Setup Time
HOLD Hold Time
2
2
-
-
-
-
-
-
ns
ns
ns
ns
t
CD
t
LZ
HOLD to Output Low Impedance
HOLD to Output High Impedance
-
-
12
7
t
HZ
Other Timing Specifications
t
WPS
WP Setup To CS Low
WP Hold From CS High
Sleep Mode Entry Time
Sleep Mode Exit Time
Output Disable Time
5
5
-
-
-
-
-
-
-
-
ns
ns
μs
μs
ns
t
WPH
t
DP
3
t
RDP
-
400
7
t
DIS
-
62
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 35 – Synchronous Data Timing (READ)
Figure 36 – Synchronous Data Timing Fast Read (FREAD)
63
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 37 – Synchronous Data Timing (WRITE)
t
CSW
CS
t
t
CSS
CSH
t
t
SCK
WH
WL
t
t
SU
H
SI
Figure 38 – Synchronous Data Timing Fast Write Quad Data and
Fast Write Quad Address and Data (FWQD and FWQAD)
t
CSW
CS
t
t
CSS
CSH
t
t
SCK
WH
WL
t
t
SU
H
I/O
64
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 39 – HOLD Timing
CS
t
t
CD
CD
SCK
t
t
HD
HD
HOLD
SO
t
t
HZ
LZ
65
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
PART NUMBERS AND ORDERING
Table 24 – Part Numbering System
Mꢀꢁꢂꢃꢄ
ꢘꢙꢉꢁꢐꢚꢀ ꢛꢃꢗꢀꢃꢍꢆꢓ ꢑꢉꢃꢇ ꢜꢝꢁꢞꢀꢃ MR
ꢅꢆꢇꢀꢃꢈꢉꢊꢀ ꢋꢀꢆꢌꢍꢇꢄ Rꢀꢎꢍꢌꢍꢂꢆ ꢏꢀꢁꢐ ꢑꢉꢊꢒꢉꢓꢀ
10Q 010 ꢁꢀ
ꢔꢕꢍꢐ
R
ꢖꢃꢉꢗꢀ
ꢀ
MRꢂM ꢃꢄoꢅꢅꢆeꢇ
10ꢈMꢉꢊ Qꢋꢌꢍ ꢁꢎꢏ ꢐꢌꢑiꢆꢒ
1 Mꢓ
ꢈ Mꢓ
16Mꢓ
ꢔo Revision
Revision ꢂ
Revision ꢕ
MR
10Q
010
0ꢈ0
160
ꢕꢆꢌnꢖ
ꢂ
ꢕ
ꢀoꢑꢑeꢗꢘiꢌꢆ
ꢏnꢍꢋsꢙꢗiꢌꢆ
ꢟꢠꢙenꢍeꢍ
0 ꢙo ꢚ0ꢛꢀ
ꢜꢈ0 ꢙo 85ꢛꢀ
ꢜꢈ0 ꢙo 105ꢛꢀ
ꢕꢆꢌnꢖ
ꢀ
ꢡ
16ꢜꢝin ꢁꢞꢏꢀ
2ꢈꢜꢓꢌꢆꢆ ꢕꢢꢂ
ꢁꢀ
Mꢕ
ꢄꢗꢌꢒ
ꢕꢆꢌnꢖ
R
ꢀꢁ
ꢄꢌꢝe ꢌnꢍ Reeꢆ
ꢀꢋsꢙoꢑeꢗ ꢁꢌꢑꢝꢆes
Mꢌss ꢎꢗoꢍꢋꢘꢙion
ꢕꢆꢌnꢖ
Table 25 – Ordering Part Numbers
Temp Grade Temperature
Package
Shipping Container
Order Part Number
Trays
MR10Q010SC
16-SOIC
Tape and Reel
Trays
MR10Q010SCR
MR10Q010MB
MR10Q010MBR
MR10Q010CSC
MR10Q010CSCR
MR10Q010CMB
MR10Q010CMBR
MR10Q010VSC
MR10Q010VSCR
MR10Q010VMB
MR10Q010VMBR
Commercial
0 to 70°C
24-BGA
16-SOIC
Tape and Reel
Trays
Tape and Reel
Trays
Industrial
Extended
-40 to 85°C
24-BGA
16-SOIC
24-BGA
Tape and Reel
Trays
Tape and Reel
Trays
-40 to 105°C
Tape and Reel
66
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
PACKAGE CHARACTERISTICS
Table 26 – Thermal Resistance 16-pin SOIC
All thermal resistance values are estimated by simulation.
1
2
3
4
5
6
Θ
Velocity
T
P
T Max
Θ
Θ
JB
A
D
J
JA
JC
m/s
0
°C
W
°C
°C/W
71.0
58.1
49.9
47.7
46.4
1
2
3
64.5
62.8
61.8
25
0.792
30.6
31.6
Notes:
1. T - Ambient temperature.
A
2. P - Power dissipation at maximum V and I .
DDW
D
DD
3. T Max - Maximum junction temperature reached at maximum power dissipation.
J
4.
5.
Θ
Θ
- Junction to ambient.
- Junction to board.
JA
JB
6.
Θ
- Junction to package case.
JC
67
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 40 – 16-SOIC Package Outline
ꢁ
ꢀ
e
ꢀ1
ꢂ
ꢅ
ꢃ2
ꢃ
ꢄ
ꢃ1
ꢄ1
ꢄꢂ
Dimensions next page.
68
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
16-SOIC Package Outline - Dimensions
Symbol
JEDEC MS - 013 (AA)
Everspin POD 16L SOIC PKG OUTLINE
DWG. 300 MIL (mm)
issue (mm)
Ref
A
MIN
-
NOM
MAX
2.65
0.30
-
MIN
2.46
NOM
2.56
MAX
2.64
0.29
2.39
0.51
0.32
10.46
10.63
7.59
1.02
-
A1
A2
b
0.10
2.05
0.31
0.20
-
0.127
2.29
0.22
-
2.34
-
0.51
0.33
0.35
0.41
c
-
0.23
0.25
D
10.30 BSC
10.30 BSC
7.50 BSC
-
10.21
10.16
7.44
10.34
10.31
7.52
E
E1
L
0.40
0°
1.27
8°
0.61
0.81
L1
e
1.40 REF
1.27 BSC
-
N/A
1.27 BSC
5°
Θ
0°
8°
69
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
Figure 41 – 24 Ball BGA Package Outline
Copyright © 2018 Everspin Technologies, Inc.
70
MR10Q010 Revision 5.6, 6/2018
MR10Q010
REVISION HISTORY
Revision
Description of Change
Date
1.7
February 26, 2013 Initial Release Preliminary.
1.8
1.9
March 7, 2013
May 14, 2013
Revision to Table 5. Revision to HOLD timing Table 15. Corrected package illustration.
Added QPI Commands.
Removed QPI Commands, TDET and reference to XIP. These features will be released in a
future product revision.
2.0
October 24, 2013
Major revision. Complete restructure of command section. Added QPI Mode, TDET,
TDETX commands and XIP operating mode commands, instructions and timing diagrams.
Removed Preliminary watermark from all pages. Removed Max and Typical values for
3.0
April 17, 2014
V
and V
.
WIDD
WIDDQ
Added I
, I , I
, I
values. Revisions to Command Descriptions for FRQO and
SB1Q SB2 SB2Q DDQ
December 17,
2014
4.0
FRQAD. Revisions to Note 3 for Command Timing Diagrams for FRQO and FRQAD. Added
package thermal resistance table. I values in Table 8 have been updated.
DD
t
t
t
4.1
4.2
4.3
5.0
March 20, 2015
May 19, 2015
June 11, 2015
Revised Table 23: CS updated. V (min) now unspecified. HO (min) revised to 1.5ns.
Revised Everspin contact information.
Corrected Japan Sales Office telephone number.
August 12, 2015 Added 6x8mm 24-ball BGA package outline and dimensions.
t
t
Table 23: Revised WHR = 11ns; WLR = 12ns. 16-SOIC package options released to MP.
24-BGA now qualified.
5.1
January 26, 2017
t
t
5.2
5.3
5.4
5.5
5.6
February 1, 2017 Figures 35 and 36 - Synchronous Data Timing. Added timing detail for V and HO.
December 4, 2017 Figure 40 updated with new dimensions
January 26, 2018 Added extended temperature range to the data sheet.
March 15, 2018
June 1, 2018
Added extended range to Table 17
Updated table 24
71
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
MR10Q010
HOW TO REACH US
Information in this document is provided solely to enable system and soft-
ware implementers to use Everspin Technologies products. There are no
express or implied licenses granted hereunder to design or fabricate any
integrated circuit or circuits based on the information in this document.
Everspin Technologies reserves the right to make changes without further
notice to any products herein. Everspin makes no warranty, representa-
tion or guarantee regarding the suitability of its products for any particu-
lar purpose, nor does Everspin Technologies assume any liability arising
out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential
or incidental damages. “Typical” parameters, which may be provided in
Everspin Technologies data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All
operating parameters including “Typicals” must be validated for each cus-
tomer application by customer’s technical experts. Everspin Technologies
does not convey any license under its patent rights nor the rights of oth-
ers. Everspin Technologies products are not designed, intended, or au-
thorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or
for any other application in which the failure of the Everspin Technologies
product could create a situation where personal injury or death may oc-
cur. Should Buyer purchase or use Everspin Technologies products for any
such unintended or unauthorized application, Buyer shall indemnify and
hold Everspin Technologies and its officers, employees, subsidiaries, affili-
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penses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Everspin Technologies
was negligent regarding the design or manufacture of the part. Everspin™
and the Everspin logo are trademarks of Everspin Technologies, Inc. All
other product or service names are the property of their respective owners.
Contact Information:
How to Reach Us:
Home Page:
www.everspin.com
World Wide Information Request
WW Headquarters - Chandler, AZ
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Tel: +1-877-480-MRAM (6726)
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Asia Pacific
Copyright © 2018 Everspin Technologies, Inc.
Everspin Asia Support
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72
Copyright © 2018 Everspin Technologies, Inc.
MR10Q010 Revision 5.6, 6/2018
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