MR25H10MDF [EVERSPIN]
1Mb Serial SPI MRAM;型号: | MR25H10MDF |
厂家: | Everspin Technologies |
描述: | 1Mb Serial SPI MRAM |
文件: | 总20页 (文件大小:1874K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MR25H10
1Mb Serial SPI MRAM
FEATURES
• No write delays
• Unlimited write endurance
• Data retention greater than 20 years
• Automatic data protection on power loss
• Block write protection
• Fast, simple SPI interface with up to 40 MHz clock rate
• 2.7 to 3.6 Volt power supply range
• Low current sleep mode
DFN
• Industrial temperatures
• Available in 8-pin DFN or 8-pin DFN Small Flag RoHS-compliant
packages
• Direct replacement for serial EEPROM, Flash, FeRAM
• AEC-Q100 Grade 1 Option
Small Flag DFN
INTRODUCTION
The MR25H10 is a 1,048,576-bit magnetoresistive random access memory
(MRAM) device organized as 131,072 words of 8 bits. The MR25H10 offers serial
EEPROM and serial Flash compatible read/write timing with no write delays and
unlimited read/write endurance.
RoHS
Unlike other serial memories, both reads and writes can occur randomly in memory with no delay between
writes. The MR25H10 is the ideal memory solution for applications that must store and retrieve data and
programs quickly using a small number of I/O pins.
The MR25H10 is available in either a 5 mm x 6 mm 8-pin DFN package or a 5 mm x 6 mm 8-pin DFN Small
Flag package. Both are compatible with serial EEPROM, Flash, and FeRAM products.
The MR25H10 provides highly reliable data storage over a wide range of temperatures. The product is
offered with Industrial (-40° to +85 °C) and AEC-Q100 Grade 1 (-40°C to +125 °C) operating temperature
range options.
CONTENTS
1. DEVICE PIN ASSIGNMENT......................................................................... 2
2. SPI COMMUNICATIONS PROTOCOL...................................................... 4
3. ELECTRICAL SPECIFICATIONS................................................................. 10
4. TIMING SPECIFICATIONS.......................................................................... 12
5. ORDERING INFORMATION....................................................................... 12
6. MECHANICAL DRAWING.......................................................................... 13
7. REVISION HISTORY...................................................................................... 15
How to Reach Us.......................................................................................... 15
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
1
MR25H10
1. DEVICE PIN ASSIGNMENT
Overview
The MR25H10 is a serial MRAM with memory array logically organized as 128Kx8 using the four pin in-
terface of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial peripheral
interface (SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM and
Flash components allowing MRAM to replace these components in the same socket and interoperate on
a shared SPI bus. Serial MRAM offers superior write speed, unlimited endurance, low standby & operating
power, and more reliable data retention compared to available serial memory alternatives.
Figure 1.1 Block Diagram
Instruction Decode
Clock Generator
Control Logic
WP
CS
HOLD
SCK
Write Protect
128KB
MRAM ARRAY
Instruction Register
17
8
Address Register
Counter
SO
Data I/O Register
SI
4
Nonvolatile Status
Register
System Configuration
Single or multiple devices can be connected to the bus as shown in Figure 1.2. Pins SCK, SO and SI are
common among devices. Each device requires CS and HOLD pins to be driven separately.
Figure 1.2 System Configuration
SCK
MOSI
MISO
SO
SI
SCK
SO
SI
SCK
SPI
EVERSPIN SPI MRAM 1
EVERSPIN SPI MRAM 2
Micro Controller
CS
HOLD
CS
HOLD
CS1
HOLD1
CS2
HOLD2
MOSI = Master Out Slave In
MISO = Master In Slave Out
MR25H10 Rev. 9.5 3/2018
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MR25H10
DEVICE PIN ASSIGNMENT
Figure 1.3 Pin Diagrams (Top View)
1
8
CS
V
DD
2
3
4
7
6
5
HOLD
SCK
SI
SO
WP
V
SS
8-Pin DFN or 8-Pin DFN Small Flag Package
Table 1.1 Pin Functions
Signal Name Pin
I/O
Function
Description
An active low chip select for the serial MRAM. When chip select is high, the
memory is powered down to minimize standby power, inputs are ignored
and the serial output pin is Hi-Z. Multiple serial memories can share a com-
mon set of data pins by using a unique chip select for each memory.
CS
1
2
Input
Chip Select
The data output pin is driven during a read operation and remains Hi-Z at
all other times. SO is Hi-Z when HOLD is low. Data transitions on the data
output occur on the falling edge of SCK.
SO
Output
Serial Output
A low on the write protect input prevents write operations to the Status
Register.
WP
VSS
3
4
Input
Hold
Power supply ground pin.
Supply
Ground
All data is input to the device through this pin. This pin is sampled on the
rising edge of SCK and ignored at other times. SI can be tied to SO to create
a single bidirectional data bus if desired.
SI
5
Input
Input
Serial Input
Serial Clock
Synchronizes the operation of the MRAM. The clock can operate up to 40
MHz to shift commands, address, and data into the memory. Inputs are
captured on the rising edge of clock. Data outputs from the MRAM occur
on the falling edge of clock. The serial MRAM supports both SPI Mode 0
(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is
normally low. In Mode 3, the clock is normally high. Memory operation is
static so the clock can be stopped at any time.
SCK
6
A low on the Hold pin interrupts a memory operation for another task.
When HOLD is low, the current operation is suspended. The device will
ignore transitions on the CS and SCK when HOLD is low. All transitions of
HOLD must occur while CS is low.
HOLD
VDD
7
8
Input
Hold
Power supply voltage from +2.7 to +3.6 volts.
Supply
Power Supply
MR25H10 Rev. 9.5 3/2018
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MR25H10
2. SPI COMMUNICATIONS PROTOCOL
MR25H10 can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1, CPHA=1). For
both modes, inputs are captured on the rising edge of the clock and data outputs occur on the falling
edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK is high. The
memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the SCK when CS
falls.
All memory transactions start when CS is brought low to the memory. The first byte is a command code. De-
pending upon the command, subsequent bytes of address are input. Data is either input or output. There
is only one command performed per CS active period. CS must go inactive before another command can
be accepted. To ensure proper part operation according to specifications, it is necessary to terminate each
access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or
aborted accesses.
Table 2.1 Command Codes
Instruction
WREN
WRDI
Description
Write Enable
Binary Code
0000 0110
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
1011 1001
1010 1011
Hex Code
06h
Address Bytes
Data Bytes
0
0
0
0
3
3
0
0
0
Write Disable
04h
0
RDSR
Read Status Register
Write Status Register
Read Data Bytes
Write Data Bytes
Enter Sleep Mode
Exit Sleep Mode
05h
1
WRSR
01h
1
1 to ∞
1 to ∞
0
READ
03h
WRITE
SLEEP
WAKE
02h
B9h
ABh
0
Status Register and Block Write Protection
The status register consists of the 8 bits listed in table 2.2. Status register bits BP0 and BP1 define the mem-
ory block arrays that are protected as described in table 2.3. The Status Register Write Disable bit (SRWD)
is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) as shown in table 2.4 to enable
writes to status register bits. The fast writing speed of MR25H10 does not require write status bits. The
state of bits 6,5,4, and 0 can be user modified and do not affect memory operation. All bits in the status
register are pre-set from the factory to the “0”state.
Table 2.2 Status Register Bit Assignments
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
Don’t Care Don’t Care Don’t Care
BP1
BP0
WEL
Don’t Care
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
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MR25H10
SPI COMMUNICATIONS PROTOCOL
Table 2.3 Block Memory Write Protection
Status Register
BP1 BP0
Memory Contents
Protected Area
None
Upper Quarter
Upper Half
All
Unprotected Area
0
0
All Memory
Lower Three-Quarters
Lower Half
0
1
1
1
0
1
None
Table 2.4 Memory Protection Modes
Status
Register
WEL
SRWD
WP
Protected Blocks
Unprotected Blocks
0
1
1
1
X
0
1
1
X
X
Low
High
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
Protected
Writable
Protected
Writable
When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1,
BP0 and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1,
status register bits BP0 and BP1 can be modified. Once SRWD is set to 1, WP must be high to modify SRWD,
BP0 and BP1.
Read Status Register (RDSR)
The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can
be read at any time to check the status of write enable latch bit, status register write protect bit, and block
write protect bits. For MR25H10, the write in progress bit (bit 0) is not written by the memory because
there is no write delay. The RDSR command is entered by driving CS low, sending the command code, and
then driving CS high.
Figure 2.1 RDSR
CS
Mode 3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Mode 0
SCK
0
0
0
0
0
1
0
1
SI
MSB
Status Register Out
High Impedance
High Z
SO
7
6
5
4
3
2
1
0
MSB
MR25H10 Rev. 9.5 3/2018
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MR25H10
SPI COMMUNICATIONS PROTOCOL
Write Enable (WREN)
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register to 1. The
WEL bit must be set prior to writing in the status register or the memory. The WREN command is entered
by driving CS low, sending the command code, and then driving CS high.
Figure 2.2 WREN
CS
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (06h)
0
0
0
0
0
1
1
0
SI
High Impedance
SO
Write Disable (WRDI)
The Write Disable (WRDI) command resets the WEL bit in the status register to 0. This prevents writes to
status register or memory. The WRDI command is entered by driving CS low, sending the command code,
and then driving CS high.
The WEL bit is reset to 0 on power-up or completion of WRDI.
Figure 2.3 WRDI
CS
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (04h)
0
0
0
0
0
1
0
0
SI
High Impedance
SO
Write Status Register (WRSR)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. The
WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 1 by executing a
WREN command while pin WP and bit SRWD correspond to values that make the status register writable
as seen in table 2.4. Status Register bits are non-volatile with the exception of the WEL which is reset to 0
upon power cycling.
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
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MR25H10
SPI COMMUNICATIONS PROTOCOL
The WRSR command is entered by driving CS low, sending the command code and status register write
data byte, and then driving CS high.The WRSR command is entered by driving CS low, sending the com-
mand code and status register write data byte, and then driving CS high.
Figure 2.4 WRSR
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction (01h)
Status Register In
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
SI
MSB
High Impedance
SO
Read Data Bytes (READ)
The Read Data Bytes (READ) command allows data bytes to be read starting at an address specified by the
24-bit address. Only address bits 0-16 are decoded by the memory. The data bytes are read out sequen-
tially from memory until the read operation is terminated by bringing CS high The entire memory can be
read in a single command. The address counter will roll over to 0000h when the address reaches the top of
memory.
The READ command is entered by driving CS low and sending the command code. The memory drives the
read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is termi-
nated by bring CS high.
Figure 2.5 READ
CS
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
SCK
Instruction (03h)
24-Bit Address
3
0
0
0
0
0
0
1
1
X
X
X
2
1
0
SI
MSB
High Impedance
Data Out 1
Data Out 2
7
6
5
4
3
2
1
0
7
SO
MSB
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
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MR25H10
SPI COMMUNICATIONS PROTOCOL
Write Data Bytes (WRITE)
The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by
the 24-bit address. Only address bits 0-16 are decoded by the memory. The data bytes are written sequen-
tially in memory until the write operation is terminated by bringing CS high. The entire memory can be
written in a single command. The address counter will roll over to 0000h when the address reaches the top
of memory.
Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock
speed without write delays or data polling. Back to back WRITE commands to any random location in mem-
ory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or
block organized memory so it is ideal for both program and data storage.
The WRITE command is entered by driving CS low, sending the command code, and then sequential write
data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS
high.
Figure 2.6 WRITE
CS
0
1
2
3
4
5
6
7
8
9
10
28
29
30
31
32
33
34
35
36
37
38
39
SCK
Instruction (02h)
24-Bit Address
3
0
0
0
0
0
0
1
0
X
X
X
2
1
0
7
6
5
4
3
2
1
0
SI
MSB
High Impedance
MSB
SO
CS
Mode 3
Mode 0
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
SCK
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SI
MSB
MSB
High Impedance
SO
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
8
MR25H10
SPI COMMUNICATIONS PROTOCOL
Enter Sleep Mode (SLEEP)
The Enter Sleep Mode (SLEEP) command turns off all MRAM power regulators in order to reduce the overall
chip standby power to 3 μA typical. The SLEEP command is entered by driving CS low, sending the com-
mand code, and then driving CS high. The standby current is achieved after time, tDP.
Figure 2.7 SLEEP
CS
t DP
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (B9h)
1
0
1
1
1
0
0
1
SI
Active Current
Standby Current
Sleep Mode Current
SO
Exit Sleep Mode (WAKE)
The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation.
The WAKE command is entered by driving CS low, sending the command code, and then driving CS high.
The memory returns to standby mode after tRDP. The CS pin must remain high until the tRDP period is over.
Figure 2.8 WAKE
CS
t RDP
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (ABh)
1
0
1
0
1
0
1
1
SI
Sleep Mode Current
Standby Current
SO
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
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MR25H10
3. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or
electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage
greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to avoid
application of any magnetic field more intense than the field intensity specified in the maximum ratings.
Table 3.1 Absolute Maximum Ratings1
Symbol Parameter
Conditions
Limit
Unit
VDD
Supply voltage2
-0.5 to 4.0
V
VIN
IOUT
PD
Voltage on any pin2
-0.5 to VDD + 0.5
V
mA
W
Output current per pin
Package power dissipation 3
20
0.600
Industrial
-45 to 95
°C
°C
TBIAS
Temperature under bias
AEC-Q100 Grade 1
-45 to 130
Tstg
Storage Temperature
-55 to 150
260
°C
°C
TLead
Lead temperature
3 minutes max
Write
Hmax_write
Hmax_read
Maximum magnetic field exposure
Maximum magnetic field exposure
12,000
A/m
Read or Standby
1
2
3
Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation
should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic
fields could affect device reliability.
All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more than
0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited to less than
20mA.
Power dissipation capability depends on package characteristics and use environment.
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
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MR25H10
ELECTRICAL SPECIFICATIONS
Table 3.2 Operating Conditions
Symbol Parameter
Grade
Min
2.7
Max
Unit
V
Industrial
3.6
3.6
VDD
Power supply voltage
AEC-Q100 Grade1
3.0
V
VIH
VIL
Input high voltage
Input low voltage
All
2.2
VDD + 0.3
V
All
-0.5
-40
-40
0.8
85
V
Industrial
°C
°C
TA
Temperature under bias
AEC-Q100 Grade1 1
125
1 AEC-Q100 Grade 1 temperature profile assumes 10 percent duty cycle at maximum temperature (2 years
out of 20-year life.)
Table 3.3 DC Characteristics
Symbol Parameter
Conditions
Min
Typical
Max
Unit
ILI
Input leakage current
-
-
1
μA
ILO
Output leakage current
Output low voltage
-
-
1
μA
IOL = +4 mA
-
-
-
-
0.4
V
V
VOL
IOL = +100 μA
VSS + 0.2v
(IOH = -4 mA)
2.4
-
-
-
-
V
V
VOH
Output high voltage
(IOH = -100 μA)
VDD - 0.2
Table 3.4 Power Supply Characteristics
Symbol Parameter
Conditions
1 MHz
Typical
Max
3
Unit
mA
mA
mA
mA
2.5
6
IDDR
Active Read Current
40 MHz
1 MHz
10
13
27
8
IDDW
Active Write Current
Standby Current
40 MHz
23
ISB
Izz
CS high and SPI bus inactive
90
7
115
30
μA
μA
Standby Sleep Mode Current CS high and SPI bus inactive
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
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MR25H10
4. TIMING SPECIFICATIONS
Table 4.1 Capacitance1
Symbol
Parameter
Typical
Max
Unit
pF
CIn
Control input capacitance
Input/Output capacitance
-
-
6
8
CI/O
pF
1
ƒ = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.
Table 4.2 AC Measurement Conditions
Parameter
Value
1.5
Unit
Logic input timing measurement reference level
Logic output timing measurement reference level
Logic input pulse levels
V
V
1.5
0 or 3.0
2
V
Input rise/fall time
ns
Output load for low and high impedance parameters
Output load for all other timing parameters
See Figure 4.1
See Figure 4.2
Figure 4.1 Output Load for Impedance Parameter Measurements
ZD= 50 Ω
Output
RL = 50 Ω
VL = 1.5 V
Figure 4.2 Output Load for all Other Parameter Measurements
3.3 V
590 Ω
Output
30 pF
435 Ω
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
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MR25H10
TIMING SPECIFICATIONS
Power-Up Timing
The MR25H10 is not accessible for a start-up time, tPU= 400 μs after power up. Users must wait this time
from the time when VDD (min) is reached until the first CS low to allow internal voltage references to become
stable. The CS signal should be pulled up to VDD so that the signal tracks the power supply during power-up
sequence.
Table 4.3 Power-Up
Symbol
Parameter
Min
Typical
Max
Unit
VWI
Write Inhibit Voltage
2.2
-
2.7
V
tPU
Startup Time
400
-
-
μs
Figure 4.3 Power-Up Timing
VDD
DD(max)
V
Chip Selection not allowed
DD(min)
V
Reset state
of the
Normal Operation
t PU
device
VWI
Time
MR25H10 Rev. 9.5 3/2018
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MR25H10
TIMING SPECIFICATIONS
Synchronous Data Timing
Symbol Parameter
Table 4.4 AC Timing Parameters1
Conditions
Min
Max
Unit
fSCK
SCK Clock Frequency
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
0
40
MHz
tRI
-
50
50
-
ns
ns
ns
ns
tRF
-
tWH
tWL
11
11
-
Synchronous Data Timing (See figure 4.4)
tCS
tCSS
tCSH
tSU
tH
CS High Time
40
10
10
5
-
-
-
-
-
ns
ns
ns
ns
ns
CS Setup Time
CS Hold Time
Data In Setup Time
Data In Hold Time
5
VDD = 2.7 to
3.6v.
Output Valid Industrial Grade
Output Valid Industrial Grade
0
0
10
9
ns
ns
VDD = 3.0 to
3.6v.
tV
VDD = 3.0 to
3.6v.
Output Valid AEC-Q100 Grade 1
Output Hold Time
0
0
10
-
ns
ns
tHO
HOLD Timing (See figure 4.5)
tHD
HOLD Setup Time
10
10
-
-
ns
ns
ns
ns
tCD
HOLD Hold Time
-
tLZ
HOLD to Output Low Impedance
HOLD to Output High Impedance
20
20
tHZ
-
Other Timing Specifications
tWPS
tWPH
tDP
WP Setup To CS Low
WP Hold From CS High
Sleep Mode Entry Time
Sleep Mode Exit Time
Output Disable Time
5
5
-
-
-
-
-
ns
ns
μs
μs
ns
3
tRDP
tDIS
400
12
1 Over the Operating Temperature Range and CL= 30 pF
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
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MR25H10
Figure 4.4 Synchronous Data Timing
Figure 4.5 HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
SO
tHZ
tLZ
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
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MR25H10
5. ORDERING INFORMATION
Figure 5.1 Part Numbering System
MR 25H 10
C
DC
Package Options
DC 8 Pin DFN on Tray
DCR 8 Pin DFN on Tape and Reel
DF 8 pin DFN Small Flag on Tray
DFR 8 pin DFN Small Flag on Tape and Reel
Temperature Range
C -40 to +85 °C ambient (Industrial)
-40 to +125 °C ambient (AEC-Q100 Grade 1)
M
Memory Density
10 1 Mb
Interface
25H High Speed Serial SPI Family
Product Type
MR Magnetoresistive RAM
Table 5.1 Available Parts
Temperature
Grade
Range
Package
Shipping Container
Order Part Number
1
Tray
MR25H10CDC
1
8-DFN
1
Tape and Reel
MR25H10CDCR
Industrial
-40 to +85 C
Tray
Tape and Reel
MR25H10CDF
MR25H10CDFR
Small Flag 8-DFN
1
Tray
MR25H10MDC
1
8-DFN
1
Tape and Reel
MR25H10MDCR
MR25H10MDF
MR25H10MDFR
AEC-Q100 Grade 1
Note:
-40 to +125 C
Tray
Small Flag 8-DFN
Tape and Reel
1. The DC pckage option (8-DFN) is not recommended for new designs. Please select the DF (small flag
8-DFN) option for new designs.
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
16
MR25H10
6. MECHANICAL DRAWINGS
Dimension
A
B
C
D
E
F
G
H
I
J
K
L
M
N
Max.
Min.
5.10
4.90
6.10
5.90
1.00 1.27
0.90 BSC
0.45
0.35
0.05 0.35
0.00 Ref.
0.70
0.50
4.20
4.00
4.20
4.00
0.261
0.195
0.05
0.00
C0.35 R0.20
NOTE:
1. All dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be
within 0.08 mm.
3. Warpage shall not exceed 0.10 mm.
4. Refer to JEDEC MO-229
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
17
MR25H10
6. MECHANICAL DRAWINGS
Figure 6.2 Small Flag DFN Package
Exposed metal Pad. Do not con-
nect anything except VSS
A
2X 0.10 C
5
8
2X 0.10 C
J
B
I
L
G
H
M
4
1
Pin 1 Index
C
Detail A
F
K
N
D
E
Detail A
Dimension
A
B
C
D
E
F
G
H
I
J
K
L
M
N
Max
Min
5.10
4.90
6.10
5.90
0.90
0.80
1.27
BSC
0.45
0.35
0.05 1.60
0.00 1.20
0.70
0.50
2.10
1.90
2.10 .210
1.90 .196
0.05
0.00
C0.45 R0.20
NOTE:
1. All dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be
within 0.08 mm.
3. Warpage shall not exceed 0.10 mm.
4. Refer to JEDEC MO-229
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
18
MR25H10
7. REVISION HISTORY
Revision
Date
Description of Change
0
Sep 12, 2008
Initial Advance Information Release
Change ac load resistance, tPU to 400 us, tRDP to 400 us, Change # of Address Bytes in Table
2 to 3, New Package Drawing, Make Preliminary
1
Jul 10, 2009
2
3
4
5
Jul 16, 2009
Jan 5, 2010
Feb 5, 2010
May 17, 2010
Increase Absolute Max Magnetic Field during write, read, and standby to 12,000 A/m
Described block protect in detail with power sequencing.
Added section system configuration.
Removed commercial specifications. All parts meet industrial specifications.
Corrected various typos. Clarified block and status register protection description. Revised
Table 3.4 Power Supply specifications. Added AEC-Q100 Grade 1 ordering option. Revised
Table 3.1, Table 3.2, Table 4.4 revised and Note 2 deleted, revised Figure 5.1 and Table 5.1.
6
Sep 14, 2011
Corrected VOL in Table 3.3 to read VOL Max = VSS + 0.2v. Operating Conditions Power Supply
Voltage for AEC-Q100 Grade1revised to 3.0-3.6v. Table 4.4: Output Valid tV specifications
revised to include VDD ranges for Industrial and AEC-Q100 Grade 1 options. Corrected SI
waveform in Figure 2.8. Output Valid, tv for AEC-Q100 Grade revised from 9ns max to 10ns
max in Table 4.4. New Small Flag DFN package option added to Page 1 Features and avail-
able parts Table 5.1. DFN Small Flag drawing and dimensions table added as Figure 6.2.
Figure 6.1, DFN Package, cleaned up with better quality drawing and dimension table. No
specifications were changed in Figure 6.1.
November 18,
2011
7
Reformatted tables for Section 3 Electrical Characteristics and timing parameters, Table
4.4. Revised Ordering Part Numbers Table 5.1. Removed MDF and MDFR options. MDC
and MDCR options are now qualified. Added Small Flag DFN illustrations. Revised 8-DFN
package drawing to show correct proportion for flag and package. Corrected errors in DFN
package outline drawings. Corrected VDD range for AEC-Q100 tV specification.
October 19,
2012
8
9
April 17, 2013
May 19, 2015
June 11, 2015
Added Automotive Grade AEC-Q100 Grade 1 for Small Flag DFN package.
Revised Everspin contact information.
9.1
9.2
Corrected Japan Sales Office telephone number.
Changed all large flag DFN optoins to “The DC pckage option (8-DFN) is not recom-
mended for new designs. Please select the DF (small flag 8-DFN) option for new
designs.”
December 13,
2016
9.3
t
t
9.4
9.5
February 2, 2017
March 23, 2018
Added HO and V relationship to Synchronous Data Timing
Updated the Contact Us table
MR25H10 Rev. 9.5 3/2018
Copyright © Everspin Technologies 2018
19
MR25H10
Everspin Technologies, Inc.
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Home Page:
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MR25H10 Rev. 9.5 3/2018
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