MR25H256MDCR [EVERSPIN]
256Kb Serial SPI MRAM;
| 型号： | MR25H256MDCR |
| 厂家： | 
Everspin Technologies |
| 描述： | 256Kb Serial SPI MRAM 静态存储器 光电二极管 内存集成电路 |
| 文件： | 总24页 (文件大小：1470K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
MR25H256 / MR25H256A
256Kb Serial SPI MRAM
FEATURES
• No write delays
• Unlimited write endurance
• Data retention greater than 20 years
• Automatic data protection on power loss
• Block write protection
8-DFN
• Fast, simple SPI interface with up to 40 MHz clock rate
• 2.7 to 3.6 Volt power supply range
• Low current sleep mode
• Industrial and Automotive Grade 1 and Grade 3 tempera-
tures
• Available in 8-DFN or 8-DFN Small Flag RoHS-compliant
package.
Small Flag 8-DFN
• Direct replacement for serial EEPROM, Flash, FeRAM
• Industrial Grade and AEC-Q100 Grade 1 and Grade 3 options
• Moisture Sensitivity MSL-3
RoHS
Product Versions and Options
MR25H256A has been released for mass production and is recommended for all new designs.
MR25H256 remains in mass production but will be subject to eventual phase out and end of life
and is not recommended for new designs.Both versions have the same specifications.
MR25H256A Product Options
Grade
Temperature Package
Industrial
-40 to +85 C
-40 to +85 C
8-DFN Small Flag
8-DFN Small Flag
Automotive AEC-Q100 Grade 3
Automotive AEC-Q100 Grade 1
-40 to +125 C 8-DFN Small Flag
MR25H256 Product Options (Not recommended for new designs)
Grade
Temperature Package
8-DFN Small Flag
8-DFN
Industrial
-40 to +85 C
8-DFN Small Flag
8-DFN
Automotive AEC-Q100 Grade 1
-40 to +125 C
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
1
MR25H256 / MR25H256A
TABLE OF CONTENTS
OVERVIEW ............................................................................................................................................4
Figure 1 – Block Diagram........................................................................................................................................... 4
System Configuration .....................................................................................................................4
Figure 2 – System Configuration............................................................................................................................. 4
DEVICE PIN ASSIGNMENT...................................................................................................................5
Figure 3 – Pin Diagram All 8-DFN Packages........................................................................................................ 5
Table 1 – Pin Functions All 8-DFN Packages ....................................................................................................... 5
SPI COMMUNICATIONS PROTOCOL...................................................................................................6
Table 2 – Command Codes ....................................................................................................................................... 6
Status Register and Block Write Protection ..................................................................................6
Table 3 – Status Register Bit Assignments........................................................................................................... 6
Table 4 – Block Memory Write Protection............................................................................................................ 7
Table 5 – Memory Protection Modes .................................................................................................................... 7
Read Status Register (RDSR)...........................................................................................................7
Figure 4 – RDSR ............................................................................................................................................................. 7
Write Enable (WREN).......................................................................................................................8
Figure 5 – WREN............................................................................................................................................................ 8
Write Disable (WRDI).......................................................................................................................8
Figure 6 – WRDI ............................................................................................................................................................. 8
Write Status Register (WRSR) .........................................................................................................9
Figure 7 – WRSR............................................................................................................................................................. 9
Read Data Bytes (READ) ............................................................................................................... 10
Figure 8 – READ...........................................................................................................................................................10
Write Data Bytes (WRITE)............................................................................................................. 11
Figure 9 – WRITE..........................................................................................................................................................11
Enter Sleep Mode (SLEEP)............................................................................................................ 12
Figure 10 – SLEEP........................................................................................................................................................12
MR25H256 / MR25H256A Rev. 1.5 3/2018
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MR25H256 / MR25H256A
Table of Contents - Continued
Exit Sleep Mode (WAKE)............................................................................................................... 12
Figure 11 – WAKE........................................................................................................................................................12
ELECTRICAL SPECIFICATIONS ......................................................................................................... 13
Absolute Maximum Ratings ........................................................................................................ 13
Table 6 – Absolute Maximum Ratings.................................................................................................................13
Table 7 – Operating Conditions.............................................................................................................................14
Table 8 – DC Characteristics....................................................................................................................................14
Table 9 – Power Supply Characteristics..............................................................................................................14
TIMING SPECIFICATIONS ................................................................................................................. 15
Table 10 – Capacitance.............................................................................................................................................15
Table 11 – AC Measurement Conditions............................................................................................................15
Figure 12 – Output Load for Impedance Parameter Measurements .......................................................15
Figure 13 – Output Load for All Other Parameter Measurements............................................................15
Power-Up Timing.......................................................................................................................... 16
Table 12 – Power-Up..................................................................................................................................................16
Figure 14 – Power-Up Timing................................................................................................................................16
Synchronous Data Timing............................................................................................................ 17
Table 13 – AC Timing Parameters .........................................................................................................................17
Figure 15 – Synchronous Data Timing................................................................................................................19
Figure 16 – HOLD Timing........................................................................................................................................19
ORDERING INFORMATION ............................................................................................................... 20
Table 14 – Ordering Part Number Decoder Table...........................................................................................20
Table 15 – Ordering Part Numbers.......................................................................................................................20
PACKAGE OUTLINE DRAWINGS....................................................................................................... 21
Figure 17 – 8-DFN Small Flag Package................................................................................................................21
Figure 18 – 8-DFN Package.....................................................................................................................................22
REVISION HISTORY ........................................................................................................................... 23
HOW TO REACH US ........................................................................................................................... 24
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
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MR25H256 / MR25H256A
OVERVIEW
The MR25H256/MR25H256A is a serial MRAM with memory array logically organized as 32Kx8 using the four
pin interface of chip select (CS), serial input (SI), serial output (SO) and serial clock (SCK) of the serial periph-
eral interface (SPI) bus. Serial MRAM implements a subset of commands common to today’s SPI EEPROM
and Flash components allowing MRAM to replace these components in the same socket and interoperate
on a shared SPI bus. Serial MRAM offers superior write speed, unlimited endurance, low standby & operating
power, and more reliable data retention compared to available serial memory alternatives.
Figure 1 – Block Diagram
Instruction Decode
Clock Generator
Control Logic
WP
CS
HOLD
SCK
Write Protect
32KB
MRAM ARRAY
Instruction Register
15
8
Address Register
Counter
SO
Data I/O Register
SI
4
Nonvolatile Status
Register
System Configuration
Single or multiple devices can be connected to the bus as shown in Figure 2. Pins SCK, SO and SI are com-
mon among devices. Each device requires CS and HOLD pins to be driven separately.
Figure 2 – System Configuration
SCK
MOSI
MISO
SO
SI
SCK
SO
SI
SCK
SPI
EVERSPIN SPI MRAM 1
EVERSPIN SPI MRAM 2
Micro Controller
CS
HOLD
CS
HOLD
CS
1
HOLD
1
2
CS
2
HOLD
MOSI = Master Out Slave In
MISO = Master In Slave Out
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
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MR25H256 / MR25H256A
DEVICE PIN ASSIGNMENT
Figuages
1
8
Cꢀ
ꢄ
ꢆꢆ
2
3
ꢉ
ꢊ
6
5
Hꢁꢅꢆ
ꢀCꢇ
ꢀꢈ
ꢀꢁ
Top View
ꢂꢃ
ꢄ
ꢀꢀ
Table ages
Signal Name Pin I/O
Function
Description
An active low chip select for the serial MRAM. When chip select is high, the
memory is powered down to minimize standby power, inputs are ignored
and the serial output pin is Hi-Z. Multiple serial memories can share a com-
mon set of data pins by using a unique chip select for each memory.
CS
1
2
Input
Chip Select
The data output pin is driven during a read operation and remains Hi-Z at
all other times. SO is Hi-Z when HOLD is low. Data transitions on the data
output occur on the falling edge of SCK.
SO
Output
Serial Output
A low on the write protect input prevents write operations to the Status
Register.
WP
VSS
3
4
Input
Write Protect
Ground
Supply
Power supply ground pin.
All data is input to the device through this pin. This pin is sampled on the
rising edge of SCK and ignored at other times. SI can be tied to SO to create
a single bidirectional data bus if desired.
SI
5
Input
Input
Serial Input
Synchronizes the operation of the MRAM. The clock can operate up to 40
MHz to shift commands, address, and data into the memory. Inputs are
captured on the rising edge of clock. Data outputs from the MRAM occur
on the falling edge of clock. The serial MRAM supports both SPI Mode 0
(CPOL=0, CPHA=0) and Mode 3 (CPOL=1, CPHA=1). In Mode 0, the clock is
normally low. In Mode 3, the clock is normally high. Memory operation is
static so the clock can be stopped at any time.
SCK
6
Serial Clock
A low on the Hold pin interrupts a memory operation for another task.
When HOLD is low, the current operation is suspended. The device will
ignore transitions on the CS and SCK when HOLD is low. All transitions of
HOLD must occur while CS is low.
HOLD
VDD
7
8
Input
Hold
Supply
Power Supply
Power supply voltage from +2.7 to +3.6 volts.
MR25H256 / MR25H256A Rev. 1.5 3/2018
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MR25H256 / MR25H256A
SPI COMMUNICATIONS PROTOCOL
MR25H256/MR25H256A can be operated in either SPI Mode 0 (CPOL=0, CPHA =0) or SPI Mode 3 (CPOL=1,
CPHA=1). For both modes, inputs are captured on the rising edge of the clock and data outputs occur on
the falling edge of the clock. When not conveying data, SCK remains low for Mode 0; while in Mode 3, SCK
is high. The memory determines the mode of operation (Mode 0 or Mode 3) based upon the state of the
SCK when CS falls.
All memory transactions start when CS is brought low to the memory. The first byte is a command code. De-
pending upon the command, subsequent bytes of address are input. Data is either input or output. There
is only one command performed per CS active period. CS must go inactive before another command can
be accepted. To ensure proper part operation according to specifications, it is necessary to terminate each
access by raising CS at the end of a byte (a multiple of 8 clock cycles from CS dropping) to avoid partial or
aborted accesses.
Table 2 – Command Codes
Instruction
Description
Binary Code
Hex Code
Address Bytes
Data Bytes
WREN
Write Enable
0000 0110
06h
0
0
WRDI
RDSR
WRSR
READ
WRITE
SLEEP
WAKE
Write Disable
Read Status Register
Write Status Register
Read Data Bytes
0000 0100
0000 0101
0000 0001
0000 0011
0000 0010
1011 1001
1010 1011
04h
05h
01h
03h
02h
B9h
ABh
0
0
0
2
2
0
0
0
1
1
1 to ∞
1 to ∞
0
Write Data Bytes
Enter Sleep Mode
Exit Sleep Mode
0
Status Register and Block Write Protection
The status register consists of the 8 bits listed in table 2.2. Status register bits BP0 and BP1 define the mem-
ory block arrays that are protected as described in table 2.3. The Status Register Write Disable bit (SRWD)
is used in conjunction with bit 1 (WEL) and the Write Protection pin (WP) as shown in table 2.4 to enable
writes to status register bits. The fast writing speed of MR25H256/MR25H256A does not require write status
bits. The state of bits 6,5,4, and 0 can be user modified and do not affect memory operation. All bits in the
status register are pre-set from the factory to the “0”state.
Table 3 – Status Register Bit Assignments
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
SRWD
Don’t Care Don’t Care Don’t Care
BP1
BP0
WEL
Don’t Care
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
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MR25H256 / MR25H256A
Table 4 – Block Memory Write Protection
Status Register
BP1 BP0
Memory Contents
Protected Area
None
Unprotected Area
All Memory
0
0
0
1
1
1
0
1
Upper Quarter
Upper Half
All
Lower Three-Quarters
Lower Half
None
Table 5 – Memory Protection Modes
Status
WEL
SRWD
WP
Protected Blocks
Unprotected Blocks
Register
Protected
Writable
Protected
Writable
0
1
1
1
X
0
1
1
X
X
Low
High
Protected
Protected
Protected
Protected
Protected
Writable
Writable
Writable
When WEL is reset to 0, writes to all blocks and the status register are protected. When WEL is set to 1, BP0
and BP1 determine which memory blocks are protected. While SRWD is reset to 0 and WEL is set to 1, status
register bits BP0 and BP1 can be modified. Once SRWD is set to 1, WP must be high to modify SRWD, BP0 and
BP1.
Read Status Register (RDSR)
The Read Status Register (RDSR) command allows the Status Register to be read. The Status Register can be
read at any time to check the status of write enable latch bit, status register write protect bit, and block write
protect bits. For MR25H256/MR25H256A, the write in progress bit (bit 0) is not written by the memory be-
cause there is no write delay. The RDSR command is entered by driving CS low, sending the command code,
and then driving CS high.
Figure 4 – RDSR
CS
Mode 3
0
1
2
3
4
5
6
7
0
1
2
3
4
5
6
7
Mode 0
SCK
0
0
0
0
0
1
0
1
SI
MSB
Status Register Out
High Impedance
High Z
SO
7
6
5
4
3
2
1
0
MSB
MR25H256 / MR25H256A Rev. 1.5 3/2018
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MR25H256 / MR25H256A
Write Enable (WREN)
The Write Enable (WREN) command sets the Write Enable Latch (WEL) bit in the status register to 1. The WEL
bit must be set prior to writing in the status register or the memory. The WREN command is entered by driv-
ing CS low, sending the command code, and then driving CS high.
Figure 5 – WREN
CS
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (06h)
0
0
0
0
0
1
1
0
SI
High Impedance
SO
Write Disable (WRDI)
The Write Disable (WRDI) command resets the WEL bit in the status register to 0. This prevents writes to
status register or memory. The WRDI command is entered by driving CS low, sending the command code,
and then driving CS high.
The WEL bit is reset to 0 on power-up or completion of WRDI.
Figure 6 – WRDI
CS
Mode 3
Mode 0
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (04h)
0
0
0
0
0
1
0
0
SI
High Impedance
SO
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
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MR25H256 / MR25H256A
Write Status Register (WRSR)
The Write Status Register (WRSR) command allows new values to be written to the Status Register. The
WRSR command is not executed unless the Write Enable Latch (WEL) has been set to 1 by executing a WREN
command while pin WP and bit SRWD correspond to values that make the status register writable as seen in
table 2.4. Status Register bits are non-volatile with the exception of the WEL which is reset to 0 upon power
cycling.
The WRSR command is entered by driving CS low, sending the command code and status register write data
byte, and then driving CS high.
Figure 7 – WRSR
CS
Mode 3
Mode 0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction (01h)
Status Register In
0
0
0
0
0
0
0
1
7
6
5
4
3
2
1
0
SI
MSB
High Impedance
SO
MR25H256 / MR25H256A Rev. 1.5 3/2018
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MR25H256 / MR25H256A
Read Data Bytes (READ)
The Read Data Bytes (READ) command allows data bytes to be read starting at an address specified by the
16-bit address. Only address bits 0-14 are decoded by the memory. The data bytes are read out sequentially
from memory until the read operation is terminated by bringing CS high The entire memory can be read in a
single command. The address counter will roll over to 0000h when the address reaches the top of memory.
The READ command is entered by driving CS low and sending the command code. The memory drives the
read data bytes on the SO pin. Reads continue as long as the memory is clocked. The command is terminat-
ed by bring CS high.
Figure 8 – READ
CS
0
1
2
3
4
5
6
7
8
9
10
20
21
22
23
24
25
26
27
28
29
30
31
SCK
Instruction (03h)
16-Bit Address
3
14
13
0
0
0
0
0
0
1
1
X
2
1
0
SI
MSB
High Impedance
Data Out 1
Data Out 2
7
6
5
4
3
2
1
0
7
SO
MSB
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
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MR25H256 / MR25H256A
Write Data Bytes (WRITE)
The Write Data Bytes (WRITE) command allows data bytes to be written starting at an address specified by
the 16-bit address. Only address bits 0-14 are decoded by the memory. The data bytes are written sequen-
tially in memory until the write operation is terminated by bringing CS high. The entire memory can be
written in a single command. The address counter will roll over to 0000h when the address reaches the top
of memory.
Unlike EEPROM or Flash Memory, MRAM can write data bytes continuously at its maximum rated clock
speed without write delays or data polling. Back to back WRITE commands to any random location in mem-
ory can be executed without write delay. MRAM is a random access memory rather than a page, sector, or
block organized memory making it ideal for both program and data storage.
The WRITE command is entered by driving CS low, sending the command code, and then sequential write
data bytes. Writes continue as long as the memory is clocked. The command is terminated by bringing CS
high.
Figure 9 – WRITE
CS
20
21
22
23
24
25
26
27
28
29
30
31
0
1
2
3
4
5
6
7
8
9
10
SCK
Instruction (02h)
16-Bit Address
3
14
0
0
0
0
0
0
1
0
X
13
2
1
0
7
6
5
4
3
2
1
0
SI
MSB
High Impedance
MSB
SO
CS
Mode 3
Mode 0
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
SCK
Data Byte 2
Data Byte 3
Data Byte N
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
SI
MSB
MSB
High Impedance
SO
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
11
MR25H256 / MR25H256A
Enter Sleep Mode (SLEEP)
The Enter Sleep Mode (SLEEP) command turns off all MRAM power regulators in order to reduce the overall
chip standby power to 3 μA typical. The SLEEP command is entered by driving CS low, sending the com-
mand code, and then driving CS high. The standby current is achieved after time, tDP. If power is removed
when the part is in sleep mode, upon power restoration, the part enters normal standby. The only valid
command following SLEEP mode entry is a WAKE command.
Figure 10 – SLEEP
CS
t DP
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (B9h)
1
0
1
1
1
0
0
1
SI
Active Current
Standby Current
Sleep Mode Current
SO
Exit Sleep Mode (WAKE)
The Exit Sleep Mode (WAKE) command turns on internal MRAM power regulators to allow normal operation.
The WAKE command is entered by driving CS low, sending the command code, and then driving CS high.
The memory returns to standby mode after tRDP. The CS pin must remain high until the tRDP period is over.
Figure 11 – WAKE
CS
t RDP
Mode 3
Mode 0
0
1
2
3
4
5
6
7
SCK
Instruction (ABh)
1
0
1
0
1
0
1
1
SI
Sleep Mode Current
Standby Current
SO
MR25H256 / MR25H256A Rev. 1.5 3/2018
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MR25H256 / MR25H256A
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or electric
fields; however, it is advised that normal precautions be taken to avoid application of any voltage greater
than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to avoid
application of any magnetic field more intense than the field intensity specified in the maximum ratings.
Table 6 – Absolute Maximum Ratings
Value 1
Symbol
Parameter
Conditions
Unit
Supply voltage 2
Voltage on any pin 2
Output current per pin
All
-0.5 to 4.0
V
VDD
All
-0.5 to VDD + 0.5
20
V
mA
W
VIN
IOUT
PD
All
Package power dissipation 3
Temperature under bias
Storage Temperature
All
0.600
Industrial
-45 to 95
-45 to 95
-45 to 135
-55 to 150
°C
°C
°C
°C
AEC-Q100 Grade 3
AEC-Q100 Grade 1
All
TBIAS
Tstg
Lead temperature during solder (3
minute max)
All
260
°C
TLead
Maximum magnetic field (Write)
During Write
12,000
12,000
A/m
A/m
Hmax_write
Hmax_read
Notes:
Maximum magnetic field (Read or During Read or
Standby) Standby
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera-
tion should be restricted to recommended operating conditions. Exposure to excessive voltages or
magnetic fields could affect device reliability.
2. All voltages are referenced to VSS. The DC value of VIN must not exceed actual applied VDD by more
than 0.5V. The AC value of VIN must not exceed applied VDD by more than 2V for 10ns with IIN limited
to less than 20mA.
3. Power dissipation capability depends on package characteristics and use environment.
MR25H256 / MR25H256A Rev. 1.5 3/2018
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MR25H256 / MR25H256A
Table 7 – Operating Conditions
Symbol Parameter
Grade
Min
2.7
2.7
3.0
Typical
Max
3.6
Unit
Industrial
-
-
-
-
V
V
V
VDD
Power supply voltage
AEC-Q100 Grade 3
AEC-Q100 Grade1
3.6
3.6
VIH
VIL
VDD + 0.3
Input high voltage
Input low voltage
All
2.2
V
All
-0.5
-40
-40
-40
-
-
-
-
0.8
85
V
Industrial
°C
°C
°C
TA
Temperature under bias AEC-Q100 Grade 3
AEC-Q100 Grade 1 1
85
125
1. AEC-Q100 Grade 1 temperature profile assumes 10 percent duty cycle at maximum temperature (2 years
out of 20-year life.)
Table 8 – DC Characteristics
Symbol Parameter
Conditions
Min
Typical
Max
Unit
ILI
Input leakage current
All
-
-
1
μA
ILO
Output leakage current All
IOL = +4 mA
-
-
-
-
-
-
-
1
μA
V
0.4
Output low voltage
VOL
IOL = +100 μA
V
+ 0.2v
-
V
SS
IOH = -4 mA
2.4
-
-
V
Output high voltage
VOH
IOH = -100 μA
V
VDD - 0.2
Table 9 – Power Supply Characteristics
Symbol Parameter
Conditions
Typical
Max
Unit
@ 1 MHz
2.5
3
10
13
27
115
30
mA
Active Read Current
IDDR
@ 40 MHz
@ 1 MHz
@ 40 MHz
6
8
mA
mA
mA
μA
Active Write Current
IDDW
23
90
7
CS High 1
CS High
ISB
Standby Current
IZZ
Standby Sleep Mode Current
μA
1. ISB current is specified with CS high and the SPI bus inactive.
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
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MR25H256 / MR25H256A
TIMING SPECIFICATIONS
Table 10 – Capacitance
Max 1
Symbol Parameter
Typical
Unit
CIn
Control input capacitance
Input/Output capacitance
-
6
pF
CI/O
-
8
pF
1. ƒ = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.
Table 11 – AC Measurement Conditions
Parameter
Value
1.5
Unit
Logic input timing measurement reference level
Logic output timing measurement reference level
Logic input pulse levels
V
V
1.5
0 or 3.0
2
V
Input rise/fall time
ns
Output load for low and high impedance parameters
Output load for all other timing parameters
See Figure 4.1
See Figure 4.2
Figure 12 – Output Load for Impedance Parameter Measurements
ZD= 50 Ω
Output
RL = 50 Ω
VL = 1.5 V
Figure 13 – Output Load for All Other Parameter Measurements
3.3 V
590 Ω
Output
30 pF
435 Ω
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
15
MR25H256 / MR25H256A
Power-Up Timing
The MR25H256/MR25H256A is not accessible for a start-up time tPU = 400 μs after power up. Users must
wait this time from the time when VDD (min) is reached until the first CS low to allow internal voltage refer-
ences to become stable. The CS signal should be pulled up to VDD so that the signal tracks the power supply
during power-up sequence.
Table 12 – Power-Up
Symbol
Parameter
Min
Typical
Max
Unit
Write Inhibit Voltage
2.2
-
2.7
V
VWI
t
Startup Time
400
-
-
μs
PU
Figure 14 – Power-Up Timing
VDD
DD(max)
V
Chip Selection not allowed
DD(min)
V
Reset state
of the
Normal Operation
t PU
device
VWI
Time
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
16
MR25H256 / MR25H256A
Synchronous Data Timing
Table 13 – AC Timing Parameters
Over the Operating Temperature Range and CL = 30 pF
Symbol
Parameter
Min
0
Max
40
50
50
-
Unit
MHz
ns
f
SCK
SCK Clock Frequency
Input Rise Time
Input Fall Time
SCK High Time
SCK Low Time
t
RI
-
t
RF
-
ns
t
WH
11
11
ns
t
WL
-
ns
Synchronous Data Timing (See “Figure 15 – Synchronous Data Timing”on page 19
t
CS
CS High Time
40
10
10
5
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
CSS
CS Setup Time
CS Hold Time
t
CSH
-
t
SU
Data In Setup Time
Data In Hold Time
-
t
H
5
-
VDD = 2.7 to 3.6v.
VDD = 3.0 to 3.6v.
VDD = 2.7 to 3.6v.
0
10
9
Industrial Grade
0
t
Output Valid
0
10
9
V
AEC Q-100 Grade 3
AEC Q-100 Grade 1
V
DD = 3.0 to 3.6v.
0
VDD = 3.0 to 3.6v.
0
10
Table continues next page.
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
17
MR25H256 / MR25H256A
AC Timing Parameters (Continued)
Symbol
Parameter
Min
Max
Unit
t
Output Hold Time
0
-
ns
HO
HOLD Timing
t
HOLD Setup Time
HOLD Hold Time
10
10
-
-
ns
ns
ns
ns
HD
t
-
CD
t
HOLD to Output Low Impedance
HOLD to Output High Impedance
20
20
LZ
t
-
HZ
Other Timing Specifications (See “Figure 16 – HOLD Timing”on page 19)
t
WP Setup To CS Low
WP Hold From CS High
Sleep Mode Entry Time
Sleep Mode Exit Time
Output Disable Time
5
5
-
-
-
-
-
ns
ns
μs
μs
ns
WPS
WPH
t
t
3
DP
t
400
12
RDP
t
DIS
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
18
MR25H256 / MR25H256A
Figure 15 – Synchronous Data Timing
Figure 16 – HOLD Timing
CS
tCD
tCD
SCK
tHD
tHD
HOLD
SO
tHZ
tLZ
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
19
MR25H256 / MR25H256A
ORDERING INFORMATION
Table 14 – Ordering Part Number Decoder Table
Table 15 – Ordering Part Numbers
Grade
Temperature Package
-40 to +85 C 8-DFN Small Flag
Shipping Container Order Part Number
Trays
MR25H256ACDF
MR25H256ACDFR
MR25H256APDF
MR25H256APDFR
MR25H256AMDF
MR25H256AMDFR
MR25H256CDF 1
MR25H256CDFR 1
MR25H256CDC 1
MR25H256CDCR 1
Industrial
Tape and Reel
Trays
AEC-Q100 Grade 3 -40 to +85 C
8-DFN Small Flag
Tape and Reel
Trays
AEC-Q100 Grade 1 -40 to +125 C 8-DFN Small Flag
Tape and Reel
Trays
Industrial
Industrial
-40 to +85 C
-40 to +85 C
8-DFN Small Flag
8-DFN
Tape and Reel
Trays
Tape and Reel
MR25H256MDF 1
MR25H256MDFR 1
MR25H256MDC 1
MR25H256MDCR 1
Trays
AEC-Q100 Grade 1 -40 to +125 C 8-DFN Small Flag
AEC-Q100 Grade 1 -40 to +125 C 8-DFN
Tape and Reel
Trays
Tape and Reel
Note:
1. Not recommended for new designs.
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
20
MR25H256 / MR25H256A
PACKAGE OUTLINE DRAWINGS
Figure 17 – 8-DFN Small Flag Package
Exposed metal Pad. Do not con-
nect anything except VSS
A
2X 0.10 C
5
8
2X 0.10 C
J
B
I
L
G
H
M
4
1
Pin 1 Index
Detail A
F
C
K
F
D
E
Detail A
Dimension
A
B
C
D
E
F
G
H
I
J
K
L
M
Max
5.10
6.10
0.90
0.85
0.80
-
0.45
0.05
1.54
0.70
2.10
2.00
1.90
2.10
0.210
-
-
1.27
Nominal
Min
5.00
4.90
6.00
5.90
0.40
0.35
-
1.40
1.26
0.60
0.50
2.00
1.90
0.200 C0.45 R0.20
0.190
BSC
-
0.00
-
-
NOTE:
1. All dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be
within 0.08 mm.
3. Refer to JEDEC MO-229-E
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
21
MR25H256 / MR25H256A
Figure 18 – 8-DFN Package
Not Recommended for New Designs
Exposed metal Pad. Do not
A
connect anything except VSS
8
5
DAP Size
4.4 x 4.4
J
B
I
L
G
H
M
4
1
Pin 1 Index
Detail A
F
C
K
N
D
E
Detail A
Dimension
A
B
C
D
E
F
G
H
I
J
K
L
M
N
Max.
5.10
6.10
1.00 1.27
0.90 BSC
0.45
0.05
0.70
4.20
4.20
0.261
0.195
0.05
0.35
Ref.
C0.35 R0.20
Min.
4.90
5.90
0.35
0.00
0.50
4.00
4.00
0.00
NOTE:
1. All dimensions are in mm. Angles in degrees.
2. Coplanarity applies to the exposed pad as well as the terminals. Coplanarity shall be
within 0.08 mm.
3. Warpage shall not exceed 0.10 mm.
4. Refer to JEDEC MO-229-E
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
22
MR25H256 / MR25H256A
REVISION HISTORY
Revision Date
Description of Change
0.1
June 1, 2015
First Draft
September 29,
2015
0.2
Added Grade 3 parameters to Table 4.4 and reformatted the table.
0.3
1.0
November 2, 2015 Revised Part Number Decoder Table.
Production release. Removed all Preliminary status statements and
October 1, 2016
October 12, 2016
indications. Added nominal values to DFN package outline dimensions
table.
Combined with MR25H256 to make single data sheet for both product
families.
1.1
1.2
1.3
December 13,
2016
Revised product name in header.
December 20,
2016
Minor Revisions. 8-DFN package option will remain.
t
t
1.4
1.5
February 1, 2017
March 23, 2018
Added HO and V relationship to Synchronous Data Timing
Updated the Contact Us table
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
23
MR25H256 / MR25H256A
HOW TO REACH US
Everspin Technologies, Inc.
Information in this document is provided solely to enable system and soft-
ware implementers to use Everspin Technologies products. There are no
express or implied licenses granted hereunder to design or fabricate any
integrated circuit or circuits based on the information in this document.
Everspin Technologies reserves the right to make changes without further
notice to any products herein. Everspin makes no warranty, representa-
tion or guarantee regarding the suitability of its products for any particu-
lar purpose, nor does Everspin Technologies assume any liability arising
out of the application or use of any product or circuit, and specifically
disclaims any and all liability, including without limitation consequential
or incidental damages. “Typical” parameters, which may be provided in
Everspin Technologies data sheets and/or specifications can and do vary
in different applications and actual performance may vary over time. All
operating parameters including “Typicals” must be validated for each cus-
tomer application by customer’s technical experts. Everspin Technologies
does not convey any license under its patent rights nor the rights of oth-
ers. Everspin Technologies products are not designed, intended, or au-
thorized for use as components in systems intended for surgical implant
into the body, or other applications intended to support or sustain life, or
for any other application in which the failure of the Everspin Technologies
product could create a situation where personal injury or death may oc-
cur. Should Buyer purchase or use Everspin Technologies products for any
such unintended or unauthorized application, Buyer shall indemnify and
hold Everspin Technologies and its officers, employees, subsidiaries, affili-
ates, and distributors harmless against all claims, costs, damages, and ex-
penses, and reasonable attorney fees arising out of, directly or indirectly,
any claim of personal injury or death associated with such unintended or
unauthorized use, even if such claim alleges that Everspin Technologies
was negligent regarding the design or manufacture of the part. Everspin™
and the Everspin logo are trademarks of Everspin Technologies, Inc. All
other product or service names are the property of their respective owners.
How to Reach Us:
Home Page:
www.everspin.com
World Wide Information Request
WW Headquarters - Chandler, AZ
5670 W. Chandler Blvd., Suite 100
Chandler, Arizona 85226
Tel: +1-877-480-MRAM (6726)
Local Tel: +1-480-347-1111
Fax: +1-480-347-1175
support@everspin.com
orders@everspin.com
sales@everspin.com
Europe, Middle East and Africa
Everspin Europe Support
support.europe@everspin.com
Japan
Everspin Japan Support
support.japan@everspin.com
Asia Pacific
Everspin Asia Support
support.asia@everspin.com
Copyright © 2018 Everspin Technologies, Inc.
Filename:
EST02896MR25H256-MR25H256ADatasheet_Rev1.5032318
MR25H256 / MR25H256A Rev. 1.5 3/2018
Copyright © 2018 Everspin Technologies
24
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