MR2A08AMA35R [EVERSPIN]

512K x 8 MRAM Memory;


型号：	MR2A08AMA35R
厂家：	Everspin Technologies
描述：	512K x 8 MRAM Memory 内存集成电路
文件：	总15页 (文件大小：901K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MR2A08A

512K x 8 MRAM Memory

FEATURES

• Fast 35ns Read/Write Cycle

• SRAM Compatible Timing, Uses Existing SRAM Controllers Without

Redesign

• Unlimited Read & Write Endurance

• Data Always Non-volatile for >20 years at Temperature

• One Memory Replaces Flash, SRAM, EEPROM and BBSRAM in

System for Simpler, More Eﬃcient Design

• Replace battery-backed SRAM solutions with MRAM to eliminate

battery assembly, improving reliability

• 3.3 Volt Power Supply

• Automatic Data Protection on Power Loss

• Commercial, Industrial, Automotive Temperatures

• RoHS-Compliant SRAM TSOP2 Package

• RoHS-Compliant SRAM BGA Package

• AEC-Q100 Grade 1 Qualiﬁed

RoHS

INTRODUCTION

The MR2A08A is a 4,194,304-bit magnetoresistive random access memory (MRAM) device organized as

524,288 words of 8 bits. The MR2A08A oﬀers SRAM compatible 35ns read/write timing with unlimited

endurance. Data is always non-volatile for greater than 20 years. Data is automatically protected on power

loss by low-voltage inhibit circuitry to prevent writes with voltage out of speciﬁcation.

The MR2A08A is the ideal memory solution for applications that must permanently store and retrieve criti-

cal data and programs quickly.

The MR2A08A is available in a small footprint 400-mil, 44-lead plastic small-outline TSOP type 2 package

or an 8 mm x 8 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. These packages are

compatible with similar low-power SRAM products and other non-volatile RAM products.

The MR2A08A provides highly reliable data storage over a wide range of temperatures. The product is of-

fered with commercial temperature range (0 to +70 °C), industrial temperature range (-40 to +85 °C), and

AEC-Q100 Grade 1 temperature range (-40 to +125 °C) options.

CONTENTS

1. DEVICE PIN ASSIGNMENT......................................................................... 2

2. ELECTRICAL SPECIFICATIONS................................................................. 4

3. TIMING SPECIFICATIONS.......................................................................... 7

4. ORDERING INFORMATION....................................................................... 11

5. MECHANICAL DRAWING.......................................................................... 12

6. REVISION HISTORY...................................................................................... 14

How to Reach Us.......................................................................................... 14

MR2A08A Rev. 6.3, 3/2018

MR2A08A

1. DEVICE PIN ASSIGNMENT

Figure 1.1 Block Diagram

OUTPUT

ENABLE

OUTPUT ENABLE

BUFFER

A[18:0] ADDRESS

ROW

DECODER

BUFFER

COLUMN

DECODER

CHIP

ENABLE

BUFFER

OUTPUT

BUFFER

SENSE

AMPS

512k x 8

BIT

MEMORY

ARRAY

WRITE

ENABLE

BUFFER

FINAL

WRITE

DRIVERS

WRITE

DRIVER

DQ[7:0]

WRITE ENABLE

Table 1.1 Pin Functions

Signal Name Function

Address Input

Chip Enable

Write Enable

Output Enable

Data I/O

V_DD

Power Supply

V_SS

Ground

Do Not Connect

No Connection - Pin 2, 43 (TSOPII); Ball H6, G2 (BGA) Reserved For Future Expansion

MR2A08A Rev. 6.3, 3/2018

DEVICE PIN ASSIGNMENT

MR2A08A

Figure 1.2 Pin Diagrams for Available Packages (Top View)

Aꢀ

Aꢁ

Aꢁꢅ

Aꢁꢄ

Aꢁꢉ

Aꢂ

Aꢀ

Aꢁ

Aꢂ

Aꢃ

Aꢇ

Aꢁꢈ

Aꢃ

Aꢅ

Aꢄ

Aꢆ

Aꢇ

DQꢄ

DQꢉ

DQꢀ

DQꢄ

DQꢀ

DQꢁ

VDD

VSS

DQꢁ

DQꢅ

VDD

Aꢁꢇ

DQꢂ

DQꢃ

DQꢈ

DQꢇ

DQꢂ

DQꢆ

VDD

VSS

Aꢁꢆ

Aꢁꢅ

Aꢁꢃ

Aꢁꢀ

DQꢃ

Aꢈ

DQꢇ

Aꢁꢄ

Aꢁꢂ

Aꢉ

Aꢁꢇ

Aꢁꢃ

Aꢈ

Aꢉ

Aꢄ

Aꢅ

Aꢆ

Aꢁꢂ

Aꢁꢁ

Aꢁꢀ

Aꢁꢈ

Aꢁꢁ

44 Pin TSOP2

48 Pin FBGA

Table 1.2 Operating Modes

E¹

G¹

W¹

Mode

Not selected

Output disabled

Byte Read

V_DDCurrent

DQ[7:0]²

Hi-Z

I_SB1, I_SB2

I_DDR

Hi-Z

I_DDR

D_Out

Byte Write

I_DDW

D_in

H = high, L = low, X = don’t care

Hi-Z = high impedance

MR2A08A Rev. 6.3, 3/2018

MR2A08A

2. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

This device contains circuitry to protect the inputs against damage caused by high static voltages or electric ﬁelds; however, it is advised that

normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic ﬁelds. Precautions should be taken to avoid application of any magnetic ﬁeld

more intense than the maximum ﬁeld intensity speciﬁed in the maximum ratings.

Table 2.1 Absolute Maximum Ratings¹

Symbol Parameter

Temp Range

Package

Value

Unit

V_DD

V_IN

Supply voltage ²

-0.5 to 4.0

Voltage on any pin ²

Output current per pin

Package power dissipation ³

-0.5 to V_DD+ 0.5

I_OUT

P_D

Note 3

0.600

Commercial

Industrial

-10 to 85

-45 to 95

-45 to 130

T_BIAS

Temperature under bias

°C

AEC-Q100 Grade 1

T_stg

Storage Temperature

-55 to 150

260

°C

Lead temperature during solder

(3 minute max)

T_Lead

Commercial

TSOP2, BGA

BGA

2,000

10,000

2,000

8,000

10,000

8,000

Maximum magnetic ﬁeld during

write

H_{max_write}

Industrial

A/m

TSOP2

AEC-Q100 Grade 1

Commercial

TSOP2

TSOP2, BGA

BGA

Maximum magnetic ﬁeld during

read or standby

H_{max_read}

Industrial

TSOP2

AEC-Q100 Grade 1

TSOP2

Notes:

1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted

to recommended operating conditions. Exposure to excessive voltages or magnetic ﬁelds could aﬀect device reliability.

2. All voltages are referenced to V_SS.

3. Power dissipation capability depends on package characteristics and use environment.

MR2A08A Rev. 6.3, 3/2018

Electrical Speciﬁcations

MR2A08A

Table 2.2 Operating Conditions

Parameter

Symbol

Min

Typical

Max

Unit

Power supply voltage ¹

V_DD

3.0

3.3

3.6

Write inhibit voltage

Input high voltage

V_WI

V_IH

V_IL

2.5

2.2

2.7

3.0¹

V_DD+ 0.3²

0.8

Input low voltage

-0.5 ³

Temperature under bias

MR2A08A (Commercial)

T_A

°C

MR2A08AC (Industrial)

MR2A08AM (AEC-Q100 Grade 1)⁴

-40

125

There is a 2 ms startup time once V_DDexceeds V_DD,(min). See Power Up and Power Down Sequencing below.

V_IH(max) = V_DD+ 0.3 V_DC; V_IH(max) = V_DD+ 2.0 V_AC(pulse width ≤ 10 ns) for I ≤ 20.0 mA.

V_IL(min) = -0.5 V_DC; V_IL(min) = -2.0 V_AC(pulse width ≤ 10 ns) for I ≤ 20.0 mA.

AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2-years out of 20-year life)

Power Up and Power Down Sequencing

The MRAM is protected from write operations whenever V_DDis less than V_WI. As soon as V_DDexceeds V_DD(min), there is a

startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize.

The E and W control signals should track V_DDon power up to V_DD- 0.2 V or V_IH(whichever is lower) and remain high

for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal

remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high

with a power-on reset signal for longer than the startup time.

During power loss or brownout where V_DDgoes below V_WI, writes are protected and a startup time must be observed

when power returns above V_DD(min).

Figure 2.1 Power Up and Power Down Diagram

VDD

BROWNOUT or POWER LOSS

2 ms

STARTUP

RECOVER

NORMAL

OPERATION

NORMAL

OPERATION

READ/WRITE

INHIBITED

READ/WRITE

INHIBITED

VIH

MR2A08A Rev. 6.3, 3/2018

Electrical Speciﬁcations

MR2A08A

Table 2.3 DC Characteristics

Parameter

Symbol

Min

Max

Unit

Input leakage current

I_lkg(I)

μA

Output leakage current

I_lkg(O)

μA

Output low voltage

(I_OL= +4 mA)

V_OL

0.4

(I_OL= +100 μA)

V_SS+ 0.2

Output high voltage

(I_OL= -4 mA)

V_OH

2.4

(I_OL= -100 μA)

V_DD- 0.2

Table 2.4 Power Supply Characteristics

Parameter

Symbol

Typical

Max

Unit

AC active supply current - read modes¹

(I_OUT= 0 mA, V_DD= max)

I_DDR

AC active supply current - write modes¹

(V_DD= max)

Commercial Grade

135

Industrial Grade

AEC-Q100 Grade

I_DDW

AC standby current

(V_DD= max, E = V_IH)

I_SB1

no other restrictions on other inputs

CMOS standby current

(E ≥ V_DD- 0.2 V and V_In≤V_SS+ 0.2 V or ≥ V_DD- 0.2 V)

(V_DD= max, f = 0 MHz)

I_SB2

All active current measurements are measured with one address transition per cycle and at minimum cycle time.

MR2A08A Rev. 6.3, 3/2018

MR2A08A

3. TIMING SPECIFICATIONS

Table 3.1 Capacitance¹

Symbol

Parameter

Typical

Max

Unit

Address input capacitance

C_In

Control input capacitance

Input/Output capacitance

C_I/O

f = 1.0 MHz, dV = 3.0 V, T_A= 25 °C, periodically sampled rather than 100% tested.

Table 3.2 AC Measurement Conditions

Parameter

Value

Unit

Logic input timing measurement reference level

Logic output timing measurement reference level

Logic input pulse levels

1.5

0 or 3.0

Input rise/fall time

Output load for low and high impedance parameters

Output load for all other timing parameters

See Figure 3.1

See Figure 3.2

Figure 3.1 Output Load Test Low and High

Z_D= 50 Ω

Output

R_L= 50 Ω

V_L= 1.5 V

Figure 3.2 Output Load Test All Others

3.3 V

590 Ω

Output

5 pF

435 Ω

MR2A08A Rev. 6.3, 3/2018

Timing Speciﬁcations

MR2A08A

Read Mode

Table 3.3 Read Cycle Timing¹

Symbol

Parameter

Min

Max

Unit

Read cycle time

t_AVAV

Address access time

t_AVQV

t_ELQV

t_GLQV

t_AXQX

t_ELQX

t_GLQX

t_EHQZ

t_GHQZ

Enable access time²

Output enable access time

Output hold from address change

Enable low to output active³

Output enable low to output active³

Enable high to output Hi-Z³

Output enable high to output Hi-Z³

W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be

minimized or eliminated during read or write cycles.

Addresses valid before or at the same time E goes low.

This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage.

Figure 3.3A Read Cycle 1

t_AVAV

A (ADDRESS)

t_AXQX

Previous Data Valid

Data Valid

Q (DATA OUT)

t_AVQV

Note: Device is continuously selected (E ≤ V_IL, G ≤ V_IL).

Figure 3.3B Read Cycle 2

t_AVAV

A (ADDRESS)

t_AVQV

t_ELQV

E (CHIP ENABLE)

t_EHQZ

t_ELQX

G (OUTPUT ENABLE)

Q (DATA OUT)

t_GHQZ

t_GLQV

t_GLQX

Data Valid

MR2A08A Rev. 6.3, 3/2018

Timing Speciﬁcations

MR2A08A

Table 3.4 Write Cycle Timing 1 (W Controlled)¹

Parameter

Symbol

t_AVAV

Min

Max

Unit

Write cycle time ²

Address set-up time

t_AVWL

Address valid to end of write (G high)

Address valid to end of write (G low)

t_AVWH

t_WLWH

t_WLEH

t_WLWH

t_WLEH

Write pulse width (G high)

Write pulse width (G low)

Data valid to end of write

Data hold time

t_DVWH

t_WHDX

t_WLQZ

t_WHQX

Write low to data Hi-Z ³

Write high to output active ³

Write recovery time

t_WHAX

All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in

steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted

low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given

voltage or temperature, t_WLQZ(max) < t_WHQX(min)

Figure 3.4 Write Cycle Timing 1 (W Controlled)

AVAV

A (ADDRESS)

AVWH

WHAX

E (CHIP ENABLE)

WLEH

WLWH

W (WRITE ENABLE)

AVWL

WHDX

DVWH

DATA VALID

D (DATA IN)

WLQZ

Hi -Z

Q (DATA OUT)

WHQX

MR2A08A Rev. 6.3, 3/2018

Timing Speciﬁcations

MR2A08A

Table 3.5 Write Cycle Timing 2 (E Controlled) ¹

Parameter

Symbol

Min

Max

Unit

Write cycle time ²

t_AVAV

Address set-up time

t_AVEL

Address valid to end of write (G high)

Address valid to end of write (G low)

t_AVEH

t_ELEH

t_ELWH

t_ELEH

t_ELWH

Enable to end of write (G high)

Enable to end of write (G low) ³

Data valid to end of write

Data hold time

t_DVEH

t_EHDX

t_EHAX

Write recovery time

All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in

steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted

low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the

same time or before W goes high, the output will remain in a high-impedance state.

Figure 3.5 Write Cycle Timing 2 (E Controlled)

t_AVAV

A (ADDRESS)

t_AVEH

t_EHAX

t_ELEH

E (CHIP ENABLE)

t_AVEL

t_ELWH

W (WRITE ENABLE)

D (DATA IN)

t_EHDX

t_DVEH

Data Valid

Hi-Z

Q (DATA OUT)

MR2A08A Rev. 6.3, 3/2018

MR2A08A

4. ORDERING INFORMATION

Figure 4.1 Part Numbering System

YS 35

Carrier

Speed

(Blank = Tray, R = Tape & Reel)

(35 ns)

Package (YS = TSOP2, MA = FBGA)

Temperature Range

(Blank= Commercial (0 to +70 °C, C=

Industrial (-40 to +85 °C, M= AEC-

Q100 Grade 1 (-40 to +125 °C)

Revision

Data Width (08 = 8-Bit, 16 = 16-bit)

Type

(A = Asynchronous, S = Synchronous)

Density (256 = 256 Kb, 0 = 1Mb, 1 =2Mb,

2 =4Mb, 4 =16Mb)

Magnetoresistive RAM

(MR)

Table 4.1 Available Parts

Part Number

Description

Package Ship Pack

44-TSOP2 Tray

Temp Range

0 to +70 °C

MR2A08AYS35

3.3 V 512Kx8 MRAM Commercial

3.3 V 512Kx8 MRAM Industrial

MR2A08ACYS35

MR2A08AMYS35

MR2A08AYS35R

MR2A08ACYS35R

MR2A08AMYS35R

MR2A08AMA35

MR2A08ACMA35

MR2A08AMA35R

MR2A08ACMA35R

44-TSOP2 Tray

-40 to +85 °C

-40 to +125 °C

0 to +70 °C

3.3 V 512Kx8 MRAM AEC-Q100 Grade 1 44-TSOP2 Tray

3.3 V 512Kx8 MRAM Commercial

3.3 V 512Kx8 MRAM Industrial

44-TSOP2 Tape & Reel

-40 to +85 °C

-40 to +125 °C

0 to +70 °C

3.3 V 512Kx8 MRAM AEC-Q100 Grade 1 44-TSOP2 Tape & Reel

3.3 V 512Kx8 MRAM Commercial

3.3 V 512Kx8 MRAM Industrial

3.3 V 512Kx8 MRAM T&R Commercial

3.3 V 512Kx8 MRAM T&R Industrial

48-BGA

Tray

Tape & Reel

-40 to +85 °C

0 to +70 °C

-40 to +85 °C

MR2A08A Rev. 6.3, 3/2018

MR2A08A

5. MECHANICAL DRAWING

Figure 5.1 TSOP2

Print Version Not To Scale

1. Dimensions and tolerances per ASME Y14.5M - 1994.

2. Dimensions in Millimeters.

3. Dimensions do not include mold protrusion.

4. Dimension does not include DAM bar protrusions.

DAM Bar protrusion shall not cause the lead width to exceed 0.58.

MR2A08A Rev. 6.3, 3/2018

Mechanical Drawings

MR2A08A

Figure 5.2 FBGA

TOP VIEW

SIDE VIEW

BOTTOM VIEW

Print Version Not To Scale

1. Dimensions in Millimeters.

2. Dimensions and tolerances per ASME Y14.5M - 1994.

3. Maximum solder ball diameter measured parallel to DATUM A

4. DATUM A, the seating plane is determined by the spherical crowns

of the solder balls.

5. Parallelism measurement shall exclude any eﬀect of mark on top

surface of package.

MR2A08A Rev. 6.3, 3/2018

MR2A08A

6. REVISION HISTORY

Revision

Date

Description of Change

Designate pin 23, 24, 42 of TSOPII as DC "Don't Connect" pins since these pins

should remain ﬂoating at all times. Functional operation of E2 pin deﬁned.

Oct 29, 2007

Reformat Datasheet for Everspin, Delete E2 pin Function, Add BGA Package Infor-

mation Add Tape & Reel Part Numbers, Add Power Sequencing Info, Correct IOH

Spec For VOH to -100 uA, Correct ac Test Conditions

Sep 12, 2008

Apr 10, 2009

July 6, 2009

Add typical and worst case current speciﬁcations

Changed datasheet from Preliminary to Production except where noted. Updated

format.

Added AEC-Q100 Grade 1 temp performance speciﬁcations to Table 2.1, Table

2.2, addition of AEC-Q100 Grade 1 and revision of I_DDWTypical values in Table 2.4.

AEC-Q100 Grade 1 ordering options added to Figure 4.1 and Table 4.1. Changed

TSOP-II to TSOP2 everywhere. New logo design. Cosmetic revision to Table 2.1.

Dec 16, 2011

Improved magnetic immunity for Industrial and Extended Grades. Revised Power

Up/Power Down Diagram.

August 2, 2012

May 19, 2015

June 11, 2015

March 23, 2018

6.1

6.2

6.3

Revised contact information.

Corrected Japan Sales Oﬃce telephone number.

Update the Contact Us table

MR2A08A Rev. 6.3, 3/2018

HOW TO CONTACT US

Everspin Technologies, Inc.

How to Reach Us:

Home Page:

Information in this document is provided solely to enable system and

software implementers to use Everspin Technologies products. There are

no express or implied licenses granted hereunder to design or fabricate

any integrated circuit or circuits based on the information in this docu-

ment. Everspin Technologies reserves the right to make changes without

further notice to any products herein. Everspin makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any

particular purpose, nor does Everspin Technologies assume any liability

arising out of the application or use of any product or circuit, and speciﬁ-

cally disclaims any and all liability, including without limitation consequen-

tial or incidental damages. “Typical”parameters, which may be provided

in Everspin Technologies data sheets and/or speciﬁcations can and do

vary in diﬀerent applications and actual performance may vary over time.

All operating parameters including “Typicals”must be validated for each

customer application by customer’s technical experts. Everspin Technolo-

gies does not convey any license under its patent rights nor the rights of

others. Everspin Technologies products are not designed, intended, or

authorized for use as components in systems intended for surgical implant

into the body, or other applications intended to support or sustain life, or

for any other application in which the failure of the Everspin Technologies

product could create a situation where personal injury or death may occur.

Should Buyer purchase or use Everspin Technologies products for any such

unintended or unauthorized application, Buyer shall indemnify and hold

Everspin Technologies and its oﬃcers, employees, subsidiaries, aﬃliates,

and distributors harmless against all claims, costs, damages, and expenses,

and reasonable attorney fees arising out of, directly or indirectly, any claim

of personal injury or death associated with such unintended or unauthor-

ized use, even if such claim alleges that Everspin Technologies was negli-

gent regarding the design or manufacture of the part. Everspin™ and the

Everspin logo are trademarks of Everspin Technologies, Inc.

www.everspin.com

World Wide Information Request

WW Headquarters - Chandler, AZ

5670 W. Chandler Blvd., Suite 100

Chandler, Arizona 85226

Tel: +1-877-480-MRAM (6726)

Local Tel: +1-480-347-1111

Fax: +1-480-347-1175

support@everspin.com

orders@everspin.com

sales@everspin.com

Europe, Middle East and Africa

Everspin Europe Support

support.europe@everspin.com

Japan

Everspin Japan Support

support.japan@everspin.com

Asia Paciﬁc

Everspin Asia Support

support.asia@everspin.com

All other product or service names are the property of their respective owners.

Filename:

EST00170_MR2A08A_Datasheet_Rev6.3032318

MR2A08A Rev. 6.3, 3/2018

MR2A08AMA35R [EVERSPIN]

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