MR2A08AMA35 [EVERSPIN]
512K x 8 MRAM Memory;型号: | MR2A08AMA35 |
厂家: | Everspin Technologies |
描述: | 512K x 8 MRAM Memory 静态存储器 内存集成电路 |
文件: | 总15页 (文件大小:901K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
MR2A08A
512K x 8 MRAM Memory
FEATURES
• Fast 35ns Read/Write Cycle
• SRAM Compatible Timing, Uses Existing SRAM Controllers Without
Redesign
• Unlimited Read & Write Endurance
• Data Always Non-volatile for >20 years at Temperature
• One Memory Replaces Flash, SRAM, EEPROM and BBSRAM in
System for Simpler, More Efficient Design
• Replace battery-backed SRAM solutions with MRAM to eliminate
battery assembly, improving reliability
• 3.3 Volt Power Supply
• Automatic Data Protection on Power Loss
• Commercial, Industrial, Automotive Temperatures
• RoHS-Compliant SRAM TSOP2 Package
• RoHS-Compliant SRAM BGA Package
• AEC-Q100 Grade 1 Qualified
RoHS
INTRODUCTION
The MR2A08A is a 4,194,304-bit magnetoresistive random access memory (MRAM) device organized as
524,288 words of 8 bits. The MR2A08A offers SRAM compatible 35ns read/write timing with unlimited
endurance. Data is always non-volatile for greater than 20 years. Data is automatically protected on power
loss by low-voltage inhibit circuitry to prevent writes with voltage out of specification.
The MR2A08A is the ideal memory solution for applications that must permanently store and retrieve criti-
cal data and programs quickly.
The MR2A08A is available in a small footprint 400-mil, 44-lead plastic small-outline TSOP type 2 package
or an 8 mm x 8 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. These packages are
compatible with similar low-power SRAM products and other non-volatile RAM products.
The MR2A08A provides highly reliable data storage over a wide range of temperatures. The product is of-
fered with commercial temperature range (0 to +70 °C), industrial temperature range (-40 to +85 °C), and
AEC-Q100 Grade 1 temperature range (-40 to +125 °C) options.
CONTENTS
1. DEVICE PIN ASSIGNMENT......................................................................... 2
2. ELECTRICAL SPECIFICATIONS................................................................. 4
3. TIMING SPECIFICATIONS.......................................................................... 7
4. ORDERING INFORMATION....................................................................... 11
5. MECHANICAL DRAWING.......................................................................... 12
6. REVISION HISTORY...................................................................................... 14
How to Reach Us.......................................................................................... 14
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
MR2A08A
1. DEVICE PIN ASSIGNMENT
Figure 1.1 Block Diagram
OUTPUT
ENABLE
G
OUTPUT ENABLE
BUFFER
9
A[18:0] ADDRESS
ROW
DECODER
10
BUFFER
COLUMN
DECODER
19
CHIP
ENABLE
BUFFER
E
8
8
OUTPUT
BUFFER
8
SENSE
AMPS
512k x 8
BIT
MEMORY
ARRAY
WRITE
ENABLE
BUFFER
W
FINAL
WRITE
DRIVERS
8
8
WRITE
DRIVER
8
DQ[7:0]
WRITE ENABLE
Table 1.1 Pin Functions
Signal Name Function
A
E
Address Input
Chip Enable
Write Enable
Output Enable
Data I/O
W
G
DQ
VDD
Power Supply
VSS
Ground
DC
NC
Do Not Connect
No Connection - Pin 2, 43 (TSOPII); Ball H6, G2 (BGA) Reserved For Future Expansion
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
DEVICE PIN ASSIGNMENT
MR2A08A
Figure 1.2 Pin Diagrams for Available Packages (Top View)
DC
NC
Aꢀ
Aꢁ
1
2
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
DC
NC
DC
Aꢁꢅ
Aꢁꢄ
Aꢁꢉ
3
1
2
3
4
5
6
4
5
Aꢂ
DC
G
Aꢀ
Aꢁ
Aꢂ
DC
A
B
C
D
E
6
Aꢃ
Aꢇ
E
7
Aꢁꢈ
Aꢃ
Aꢅ
Aꢄ
Aꢆ
Aꢇ
NC
DC
E
DC
8
G
DQꢄ
DQꢉ
9
DQꢀ
DQꢄ
DQꢀ
NC
NC
10
11
12
13
14
15
16
17
18
19
20
21
22
DQꢁ
VDD
VSS
VSS
DQꢁ
DQꢅ
VDD
Aꢁꢇ
DC
V
SS
V
DD
DQꢂ
DQꢃ
W
DQꢈ
DQꢇ
DC
DQꢂ
DQꢆ
VDD
VSS
Aꢁꢆ
Aꢁꢅ
Aꢁꢃ
Aꢁꢀ
F
DQꢃ
NC
NC
Aꢈ
DQꢇ
NC
Aꢁꢄ
Aꢁꢂ
Aꢉ
NC
W
Aꢁꢇ
Aꢁꢃ
Aꢈ
Aꢉ
Aꢄ
Aꢅ
Aꢆ
DC
DC
Aꢁꢂ
Aꢁꢁ
Aꢁꢀ
G
H
NC
Aꢁꢈ
Aꢁꢁ
NC
DC
DC
44 Pin TSOP2
48 Pin FBGA
Table 1.2 Operating Modes
E1
G1
X
W1
X
Mode
Not selected
Output disabled
Byte Read
VDD Current
DQ[7:0]2
Hi-Z
H
L
L
L
ISB1, ISB2
H
L
H
IDDR
Hi-Z
H
IDDR
DOut
X
L
Byte Write
IDDW
Din
1
2
H = high, L = low, X = don’t care
Hi-Z = high impedance
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
MR2A08A
2. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
This device contains circuitry to protect the inputs against damage caused by high static voltages or electric fields; however, it is advised that
normal precautions be taken to avoid application of any voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.
The device also contains protection against external magnetic fields. Precautions should be taken to avoid application of any magnetic field
more intense than the maximum field intensity specified in the maximum ratings.
Table 2.1 Absolute Maximum Ratings1
Symbol Parameter
Temp Range
Package
Value
Unit
VDD
VIN
Supply voltage 2
-
-
-0.5 to 4.0
V
Voltage on any pin 2
Output current per pin
Package power dissipation 3
-
-
-
-0.5 to VDD + 0.5
V
mA
W
-
IOUT
PD
-
20
Note 3
0.600
Commercial
Industrial
-
-
-
-10 to 85
-45 to 95
-45 to 130
TBIAS
Temperature under bias
°C
AEC-Q100 Grade 1
Tstg
Storage Temperature
-
-
-
-55 to 150
260
°C
°C
Lead temperature during solder
(3 minute max)
TLead
-
Commercial
TSOP2, BGA
BGA
2,000
2,000
10,000
2,000
8,000
8,000
10,000
8,000
Maximum magnetic field during
write
Hmax_write
Industrial
A/m
A/m
TSOP2
AEC-Q100 Grade 1
Commercial
TSOP2
TSOP2, BGA
BGA
Maximum magnetic field during
read or standby
Hmax_read
Industrial
TSOP2
AEC-Q100 Grade 1
TSOP2
Notes:
1. Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation should be restricted
to recommended operating conditions. Exposure to excessive voltages or magnetic fields could affect device reliability.
2. All voltages are referenced to VSS.
3. Power dissipation capability depends on package characteristics and use environment.
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
Electrical Specifications
MR2A08A
Table 2.2 Operating Conditions
Parameter
Symbol
Min
Typical
Max
Unit
Power supply voltage 1
VDD
3.0
3.3
3.6
V
Write inhibit voltage
Input high voltage
VWI
VIH
VIL
2.5
2.2
2.7
3.01
VDD + 0.32
0.8
V
V
V
-
-
Input low voltage
-0.5 3
Temperature under bias
MR2A08A (Commercial)
0
70
85
TA
°C
MR2A08AC (Industrial)
MR2A08AM (AEC-Q100 Grade 1)4
-40
-40
125
1
2
3
4
There is a 2 ms startup time once VDD exceeds VDD,(min). See Power Up and Power Down Sequencing below.
VIH(max) = VDD + 0.3 VDC ; VIH(max) = VDD + 2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
VIL(min) = -0.5 VDC ; VIL(min) = -2.0 VAC (pulse width ≤ 10 ns) for I ≤ 20.0 mA.
AEC-Q100 Grade 1 temperature profile assumes 10% duty cycle at maximum temperature (2-years out of 20-year life)
Power Up and Power Down Sequencing
The MRAM is protected from write operations whenever VDD is less than VWI. As soon as VDD exceeds VDD(min), there is a
startup time of 2 ms before read or write operations can start. This time allows memory power supplies to stabilize.
The E and W control signals should track VDD on power up to VDD- 0.2 V or VIH (whichever is lower) and remain high
for the startup time. In most systems, this means that these signals should be pulled up with a resistor so that signal
remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W should hold the signals high
with a power-on reset signal for longer than the startup time.
During power loss or brownout where VDD goes below VWI, writes are protected and a startup time must be observed
when power returns above VDD(min).
Figure 2.1 Power Up and Power Down Diagram
VDD
V
WI
BROWNOUT or POWER LOSS
2 ms
2 ms
STARTUP
RECOVER
NORMAL
OPERATION
NORMAL
OPERATION
READ/WRITE
INHIBITED
READ/WRITE
INHIBITED
VIH
VIH
E
W
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
Electrical Specifications
MR2A08A
Table 2.3 DC Characteristics
Parameter
Symbol
Min
Max
Unit
Input leakage current
Ilkg(I)
-
1
μA
Output leakage current
Ilkg(O)
-
-
1
μA
V
Output low voltage
(IOL = +4 mA)
VOL
0.4
(IOL = +100 μA)
VSS + 0.2
Output high voltage
(IOL = -4 mA)
VOH
2.4
-
V
(IOL = -100 μA)
VDD - 0.2
Table 2.4 Power Supply Characteristics
Parameter
Symbol
Typical
Max
Unit
AC active supply current - read modes1
(IOUT= 0 mA, VDD= max)
IDDR
30
66
mA
AC active supply current - write modes1
(VDD= max)
Commercial Grade
90
90
90
135
135
135
Industrial Grade
AEC-Q100 Grade
IDDW
mA
mA
mA
AC standby current
(VDD= max, E = VIH)
ISB1
13
8
20
10
no other restrictions on other inputs
CMOS standby current
(E ≥ VDD - 0.2 V and VIn ≤VSS + 0.2 V or ≥ VDD - 0.2 V)
(VDD = max, f = 0 MHz)
ISB2
1
All active current measurements are measured with one address transition per cycle and at minimum cycle time.
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
MR2A08A
3. TIMING SPECIFICATIONS
Table 3.1 Capacitance1
Symbol
Parameter
Typical
Max
Unit
Address input capacitance
CIn
CIn
-
6
pF
Control input capacitance
Input/Output capacitance
-
-
6
8
pF
pF
CI/O
1
f = 1.0 MHz, dV = 3.0 V, TA = 25 °C, periodically sampled rather than 100% tested.
Table 3.2 AC Measurement Conditions
Parameter
Value
Unit
V
Logic input timing measurement reference level
Logic output timing measurement reference level
Logic input pulse levels
1.5
1.5
V
0 or 3.0
2
V
Input rise/fall time
ns
Output load for low and high impedance parameters
Output load for all other timing parameters
See Figure 3.1
See Figure 3.2
Figure 3.1 Output Load Test Low and High
ZD= 50 Ω
Output
RL = 50 Ω
VL = 1.5 V
Figure 3.2 Output Load Test All Others
3.3 V
590 Ω
Output
5 pF
435 Ω
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
Timing Specifications
MR2A08A
Read Mode
Table 3.3 Read Cycle Timing1
Symbol
Parameter
Min
Max
Unit
Read cycle time
tAVAV
35
-
ns
Address access time
tAVQV
tELQV
tGLQV
tAXQX
tELQX
tGLQX
tEHQZ
tGHQZ
-
-
35
35
15
-
ns
ns
ns
ns
ns
ns
ns
ns
Enable access time2
Output enable access time
Output hold from address change
Enable low to output active3
Output enable low to output active3
Enable high to output Hi-Z3
-
3
3
0
0
0
-
-
15
10
Output enable high to output Hi-Z3
1
W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be
minimized or eliminated during read or write cycles.
Addresses valid before or at the same time E goes low.
2
3
This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage.
Figure 3.3A Read Cycle 1
tAVAV
A (ADDRESS)
tAXQX
Previous Data Valid
Data Valid
Q (DATA OUT)
tAVQV
Note: Device is continuously selected (E ≤ VIL, G ≤ VIL).
Figure 3.3B Read Cycle 2
tAVAV
A (ADDRESS)
tAVQV
tELQV
E (CHIP ENABLE)
tEHQZ
tELQX
G (OUTPUT ENABLE)
Q (DATA OUT)
tGHQZ
tGLQV
tGLQX
Data Valid
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
Timing Specifications
MR2A08A
Table 3.4 Write Cycle Timing 1 (W Controlled)1
Parameter
Symbol
tAVAV
Min
35
0
Max
Unit
ns
Write cycle time 2
-
-
-
-
Address set-up time
tAVWL
ns
Address valid to end of write (G high)
Address valid to end of write (G low)
tAVWH
tAVWH
18
20
ns
ns
tWLWH
tWLEH
tWLWH
tWLEH
Write pulse width (G high)
Write pulse width (G low)
15
15
-
-
ns
ns
Data valid to end of write
Data hold time
tDVWH
tWHDX
tWLQZ
tWHQX
10
0
-
-
ns
ns
ns
ns
Write low to data Hi-Z 3
Write high to output active 3
0
12
-
3
Write recovery time
tWHAX
12
-
ns
1
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given
voltage or temperature, tWLQZ(max) < tWHQX(min)
2
3
Figure 3.4 Write Cycle Timing 1 (W Controlled)
t
AVAV
A (ADDRESS)
t
t
AVWH
WHAX
E (CHIP ENABLE)
t
t
WLEH
WLWH
W (WRITE ENABLE)
t
AVWL
t
t
WHDX
DVWH
DATA VALID
D (DATA IN)
t
WLQZ
Hi -Z
Hi -Z
Q (DATA OUT)
t
WHQX
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
Timing Specifications
MR2A08A
Table 3.5 Write Cycle Timing 2 (E Controlled) 1
Parameter
Symbol
Min
35
0
Max
Unit
ns
Write cycle time 2
tAVAV
-
-
-
-
Address set-up time
tAVEL
ns
Address valid to end of write (G high)
Address valid to end of write (G low)
tAVEH
18
20
ns
tAVEH
ns
tELEH
tELWH
tELEH
tELWH
Enable to end of write (G high)
Enable to end of write (G low) 3
15
15
-
-
ns
ns
Data valid to end of write
Data hold time
tDVEH
tEHDX
tEHAX
10
0
-
-
-
ns
ns
ns
Write recovery time
12
1
All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus
contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after
W goes low, the output will remain in a high impedance state. After W or E has been brought high, the signal must remain in
steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being asserted
low in a subsequent cycle is the same as the minimum cycle time allowed for the device.
All write cycle timings are referenced from the last valid address to the first transition address.
If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the
same time or before W goes high, the output will remain in a high-impedance state.
2
3
Figure 3.5 Write Cycle Timing 2 (E Controlled)
tAVAV
A (ADDRESS)
tAVEH
tEHAX
tELEH
E (CHIP ENABLE)
tAVEL
tELWH
W (WRITE ENABLE)
D (DATA IN)
tEHDX
tDVEH
Data Valid
Hi-Z
Q (DATA OUT)
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
MR2A08A
4. ORDERING INFORMATION
Figure 4.1 Part Numbering System
MR
2
A
08
A
C
YS 35
R
Carrier
Speed
(Blank = Tray, R = Tape & Reel)
(35 ns)
Package (YS = TSOP2, MA = FBGA)
Temperature Range
(Blank= Commercial (0 to +70 °C, C=
Industrial (-40 to +85 °C, M= AEC-
Q100 Grade 1 (-40 to +125 °C)
Revision
Data Width (08 = 8-Bit, 16 = 16-bit)
Type
(A = Asynchronous, S = Synchronous)
Density (256 = 256 Kb, 0 = 1Mb, 1 =2Mb,
2 =4Mb, 4 =16Mb)
Magnetoresistive RAM
(MR)
Table 4.1 Available Parts
Part Number
Description
Package Ship Pack
44-TSOP2 Tray
Temp Range
0 to +70 °C
MR2A08AYS35
3.3 V 512Kx8 MRAM Commercial
3.3 V 512Kx8 MRAM Industrial
MR2A08ACYS35
MR2A08AMYS35
MR2A08AYS35R
MR2A08ACYS35R
MR2A08AMYS35R
MR2A08AMA35
MR2A08ACMA35
MR2A08AMA35R
MR2A08ACMA35R
44-TSOP2 Tray
-40 to +85 °C
-40 to +125 °C
0 to +70 °C
3.3 V 512Kx8 MRAM AEC-Q100 Grade 1 44-TSOP2 Tray
3.3 V 512Kx8 MRAM Commercial
3.3 V 512Kx8 MRAM Industrial
44-TSOP2 Tape & Reel
44-TSOP2 Tape & Reel
-40 to +85 °C
-40 to +125 °C
0 to +70 °C
3.3 V 512Kx8 MRAM AEC-Q100 Grade 1 44-TSOP2 Tape & Reel
3.3 V 512Kx8 MRAM Commercial
3.3 V 512Kx8 MRAM Industrial
3.3 V 512Kx8 MRAM T&R Commercial
3.3 V 512Kx8 MRAM T&R Industrial
48-BGA
48-BGA
48-BGA
48-BGA
Tray
Tray
Tape & Reel
Tape & Reel
-40 to +85 °C
0 to +70 °C
-40 to +85 °C
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
MR2A08A
5. MECHANICAL DRAWING
Figure 5.1 TSOP2
Print Version Not To Scale
1. Dimensions and tolerances per ASME Y14.5M - 1994.
2. Dimensions in Millimeters.
3. Dimensions do not include mold protrusion.
4. Dimension does not include DAM bar protrusions.
DAM Bar protrusion shall not cause the lead width to exceed 0.58.
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
Mechanical Drawings
MR2A08A
Figure 5.2 FBGA
TOP VIEW
SIDE VIEW
BOTTOM VIEW
Print Version Not To Scale
1. Dimensions in Millimeters.
2. Dimensions and tolerances per ASME Y14.5M - 1994.
3. Maximum solder ball diameter measured parallel to DATUM A
4. DATUM A, the seating plane is determined by the spherical crowns
of the solder balls.
5. Parallelism measurement shall exclude any effect of mark on top
surface of package.
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
MR2A08A
6. REVISION HISTORY
Revision
Date
Description of Change
Designate pin 23, 24, 42 of TSOPII as DC "Don't Connect" pins since these pins
should remain floating at all times. Functional operation of E2 pin defined.
1
Oct 29, 2007
Reformat Datasheet for Everspin, Delete E2 pin Function, Add BGA Package Infor-
mation Add Tape & Reel Part Numbers, Add Power Sequencing Info, Correct IOH
Spec For VOH to -100 uA, Correct ac Test Conditions
2
Sep 12, 2008
3
4
Apr 10, 2009
July 6, 2009
Add typical and worst case current specifications
Changed datasheet from Preliminary to Production except where noted. Updated
format.
Added AEC-Q100 Grade 1 temp performance specifications to Table 2.1, Table
2.2, addition of AEC-Q100 Grade 1 and revision of IDDW Typical values in Table 2.4.
AEC-Q100 Grade 1 ordering options added to Figure 4.1 and Table 4.1. Changed
TSOP-II to TSOP2 everywhere. New logo design. Cosmetic revision to Table 2.1.
5
Dec 16, 2011
Improved magnetic immunity for Industrial and Extended Grades. Revised Power
Up/Power Down Diagram.
6
August 2, 2012
May 19, 2015
June 11, 2015
March 23, 2018
6.1
6.2
6.3
Revised contact information.
Corrected Japan Sales Office telephone number.
Update the Contact Us table
Copyright © 2018 Everspin Technologies, Inc.
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MR2A08A Rev. 6.3, 3/2018
HOW TO CONTACT US
Everspin Technologies, Inc.
How to Reach Us:
Home Page:
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software implementers to use Everspin Technologies products. There are
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further notice to any products herein. Everspin makes no warranty, rep-
resentation or guarantee regarding the suitability of its products for any
particular purpose, nor does Everspin Technologies assume any liability
arising out of the application or use of any product or circuit, and specifi-
cally disclaims any and all liability, including without limitation consequen-
tial or incidental damages. “Typical”parameters, which may be provided
in Everspin Technologies data sheets and/or specifications can and do
vary in different applications and actual performance may vary over time.
All operating parameters including “Typicals”must be validated for each
customer application by customer’s technical experts. Everspin Technolo-
gies does not convey any license under its patent rights nor the rights of
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Everspin logo are trademarks of Everspin Technologies, Inc.
www.everspin.com
World Wide Information Request
WW Headquarters - Chandler, AZ
5670 W. Chandler Blvd., Suite 100
Chandler, Arizona 85226
Tel: +1-877-480-MRAM (6726)
Local Tel: +1-480-347-1111
Fax: +1-480-347-1175
support@everspin.com
orders@everspin.com
sales@everspin.com
Europe, Middle East and Africa
Everspin Europe Support
support.europe@everspin.com
Japan
Everspin Japan Support
support.japan@everspin.com
Asia Pacific
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Copyright © Everspin Technologies, Inc. 2018
Filename:
EST00170_MR2A08A_Datasheet_Rev6.3032318
Copyright © 2018 Everspin Technologies, Inc.
15
MR2A08A Rev. 6.3, 3/2018
相关型号:
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9135_11
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SI9136_11
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SI9130CG-T1-E3
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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