MR4A08BCMA35R [EVERSPIN]

2M x 8 MRAM Memory;


型号：	MR4A08BCMA35R
厂家：	Everspin Technologies
描述：	2M x 8 MRAM Memory 静态存储器内存集成电路
文件：	总15页 (文件大小：839K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

MR4A08B

2M x 8 MRAM Memory

FEATURES

• +3.3 Volt power supply

• Fast 35 ns read/write cycle

• SRAM compatible timing

• Unlimited read & write endurance

• Data always non-volatile for >20-years at temperature

• RoHS-compliant small footprint BGA and TSOP2 packages

• All products meet MSL-3 moisture sensitivity level

BENEFITS

• One memory replaces FLASH, SRAM, EEPROM and BBSRAM in systems

for simpler, more eﬃcient designs

• Improves reliability by replacing battery-backed SRAM

INTRODUCTION

The MR4A08B is a 16,777,216-bit magnetoresistive random access

memory (MRAM) device organized as 2,097,152 words of 8 bits.

The MR4A08B oﬀers SRAM compatible 35ns read/write timing with

unlimited endurance. Data is always non-volatile for greater than

20-years. Data is automatically protected on power loss by low-

voltage inhibit circuitry to prevent writes with voltage out of speciﬁcation. The

RoHS

MR4A08B is the ideal memory solution for applications that must permanently store and retrieve critical

data and programs quickly.

The MR4A08B is available in small footprint 400-mil, 44-lead plastic small-outline TSOP type-II package or

10 mm x 10 mm, 48-pin ball grid array (BGA) package with 0.75 mm ball centers. These packages are com-

patible with similar low-power SRAM products and other non-volatile RAM products.

The MR4A08B provides highly reliable data storage over a wide range of temperatures. The product is of-

fered with commercial (0 to +70 °C) and industrial (-40 to +85 °C) operating temperature range options.

CONTENTS

1. DEVICE PIN ASSIGNMENT......................................................................... 2

2. ELECTRICAL SPECIFICATIONS................................................................. 4

3. TIMING SPECIFICATIONS.......................................................................... 7

4. ORDERING INFORMATION....................................................................... 11

5. MECHANICAL DRAWING.......................................................................... 12

6. REVISION HISTORY...................................................................................... 14

How to Reach Us.......................................................................................... 15

MR4A08B Rev. 8.7 3/2018

MR4A08B

1. DEVICE PIN ASSIGNMENT

Figure 1.1 Block Diagram

OUTPUT

ENABLE

ꢀ

OUTPUT ENABLE

BUFFER

ꢂꢃ20ꢄ0ꢅ

ADDRESS

BUFFER

ROW

DECODER

COLUMN

DECODER

CHIP

ENABLE

BUFFER

OUTPUT

BUFFER

SENSE

AMPS

2M x 8

BIT

MEMORY

ARRAY

WRITE

ENABLE

BUFFER

ꢁ

FINAL

WRITE

DRIVERS

WRITE

DRIVER

ꢆꢇꢃꢈꢄ0ꢅ

WRITE ENABLE

Table 1.1 Pin Functions

Signal Name

Function

Address Input

Chip Enable

Write Enable

Output Enable

Data I/O

V_DD

Power Supply

V_SS

Ground

Do Not Connect

No Connection

MR4A08B Rev. 8 .7 3/2018

DEVICE PIN ASSIGNMENT

MR4A08B

Figure 1.2 Pin Diagrams for Available Packages (Top View)

ꢉꢉ

ꢉꢊ

ꢉ2

ꢉ1

ꢉ0

ꢊꢅ

ꢊ8

ꢊꢆ

ꢊꢇ

ꢊꢈ

ꢊꢉ

ꢊꢊ

ꢊ2

ꢊ1

ꢊ0

2ꢅ

2ꢆ

2ꢇ

2ꢈ

2ꢉ

2ꢊ

ꢂC

ꢀ_ꢀꢁ

ꢂC

ꢀ₂₀

ꢀ

ꢊ

ꢀ

ꢁ

ꢂ

ꢃ

ꢂC

ꢀ

ꢉ

ꢀ

ꢇC

ꢄ

ꢅ

ꢇC

ꢅ

ꢆ

ꢇ

ꢈ

ꢀ

ꢇ

ꢀ

ꢅ

ꢌC

ꢇꢈ

ꢇC

ꢇꢈ

ꢆ

ꢀ

ꢋ

ꢅ

ꢌC

ꢇꢈ

ꢌC

ꢇꢈ

1ꢊ

1ꢉ

1ꢈ

1ꢇ

1ꢆ

1ꢅ

ꢉꢊꢊ

ꢉꢇꢇ

ꢁꢂꢂ

ꢁ

ꢃꢃ

ꢁꢃꢃ

ꢂꢂ

ꢇꢈ

ꢌC

ꢇꢈ

ꢉꢇꢇ

ꢇC

ꢉꢊꢊ

ꢂC

ꢄ

ꢋ

ꢇꢈ_ꢂ

ꢌC

ꢇꢈ

ꢌC

ꢍ

ꢅ

ꢀ

ꢂC

ꢄ

ꢎ

ꢅ

ꢀ

ꢅ

ꢀꢁ

ꢂC

44 Pin TSOP2

48 Pin FBGA

Table 1.2 Operating Modes

E¹

G¹

W¹

Mode

Not selected

Output disabled

Byte Read

V_DDCurrent

DQ[7:0]²

Hi-Z

I_SB1, I_SB2

I_DDR

Hi-Z

I_DDR

D_Out

Byte Write

I_DDW

D_in

H = high, L = low, X = don’t care

Hi-Z = high impedance

MR4A08B Rev. 8.7 3/2018

MR4A08B

2. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

This device contains circuitry to protect the inputs against damage caused by high static voltages or

electric ﬁelds; however, it is advised that normal precautions be taken to avoid application of any

voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic ﬁelds. Precautions should be taken

to avoid application of any magnetic ﬁeld more intense than the maximum ﬁeld intensity speciﬁed

in the maximum ratings.

Table 2.1 Absolute Maximum Ratings¹

Parameter

Symbol

Value

Unit

Supply voltage²

V_DD

-0.5 to 4.0

-0.5 to V_DD

0.5

Voltage on any pin²

V_IN

Output current per pin

I_OUT

P_D

Package power dissipation ³

Temperature under bias

0.600

MR4A08B (Commercial)

MR4A08BC (Industrial)

-10 to 85

-45 to 95

T_BIAS

°C

Storage Temperature

T_stg

-55 to 150

260

°C

Lead temperature during solder (3 minute max)

Maximum magnetic ﬁeld during write

MR4A08B (All Temperatures)

T_Lead

H_{max_write}

H_{max_read}

8000

A/m

Maximum magnetic ﬁeld during read or standby

Permanent device damage may occur if absolute maximum ratings are exceeded. Functional opera-

tion should be restricted to recommended operating conditions. Exposure to excessive voltages or

magnetic ﬁelds could aﬀect device reliability.

All voltages are referenced to V_SS.

Power dissipation capability depends on package characteristics and use environment.

MR4A08B Rev. 8 .7 3/2018

Electrical Speciﬁcations

MR4A08B

Table 2.2 Operating Conditions

Parameter

Symbol

V_DD

Min

3.0 ¹

2.5

Typical

Max

Unit

Power supply voltage

Write inhibit voltage

Input high voltage

Input low voltage

3.3

2.7

3.6

3.0¹

V_DD+ 0.3²

V_WI

V_IH

2.2

-0.5 ³

V_IL

0.8

Temperature under bias

MR4A08B (Commercial)

MR4A08BC (Industrial)

T_A

°C

-40

1. There is a 2 ms startup time once V_DDexceeds V_DD,(min). See Power Up and Power Down Sequencing below.

2. V_IH(max) = V_DD+ 0.3 V_DC; V_IH(max) = V_DD+ 2.0 V_AC(pulse width ≤ 10 ns) for I ≤ 20.0 mA.

3. V_IL(min) = -0.5 V_DC; V_IL(min) = -2.0 V_AC(pulse width ≤ 10 ns) for I ≤ 20.0 mA.

Power Up and Power Down Sequencing

MRAM is protected from write operations whenever V_DDis less than V_WI. As soon as V_DDexceeds V_DD(min),

there is a startup time of 2 ms before read or write operations can start. This time allows memory power

supplies to stabilize.

The E and W control signals should track V_DDon power up to V_DD- 0.2 V or V_IH(whichever is lower) and re-

main high for the startup time. In most systems, this means that these signals should be pulled up with a

resistor so that signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and

W should hold the signals high with a power-on reset signal for longer than the startup time.

During power loss or brownout where V_DDgoes below V_WI, writes are protected and a startup time must be

observed when power returns above V_DD(min).

Figure 2.1 Power Up and Power Down Diagram

VDD

WIDD

2 ms

BROWNOUT or POWER LOSS

STARTUP

RECOVER

NORMAL

OPERATION

NORMAL

OPERATION

READ/WRITE

INHIBITED

READ/WRITE

INHIBITED

ꢀ

ꢁ

MR4A08B Rev. 8.7 3/2018

Electrical Speciﬁcations

MR4A08B

Table 2.3 DC Characteristics

Parameter

Symbol

Min

Typical

Max

Unit

Input leakage current

I_lkg(I)

μA

Output leakage current

I_lkg(O)

μA

Output low voltage

(I_OL= +4 mA)

V_OL

0.4

(I_OL= +100 μA)

V_SS+ 0.2

Output high voltage

(I_OL= -4 mA)

V_OH

2.4

(I_OL= -100 μA)

V_DD- 0.2

Table 2.4 Power Supply Characteristics

Parameter

Symbol

Typical

Max

Unit

AC active supply current - read modes¹

(I_OUT= 0 mA, V_DD= max)

I_DDR

AC active supply current - write modes¹

(V_DD= max)

I_DDW

152

180

AC standby current

(V_DD= max, E = V_IH)

I_SB1

no other restrictions on other inputs

CMOS standby current

(E ≥ V_DD- 0.2 V and V_In≤V_SS+ 0.2 V or ≥ V_DD- 0.2 V)

(V_DD= max, f = 0 MHz)

I_SB2

All active current measurements are measured with one address transition per cycle and at minimum cycle time.

MR4A08B Rev. 8 .7 3/2018

MR4A08B

3. TIMING SPECIFICATIONS

Table 3.1 Capacitance¹

Symbol

Parameter

Typical

Max

Unit

Address input capacitance

Control input capacitance

C_In

Input/Output capacitance

C_I/O

f = 1.0 MHz, dV = 3.0 V, T_A= 25 °C, periodically sampled rather than 100% tested.

Table 3.2 AC Measurement Conditions

Parameter

Value

1.5

Unit

Logic input timing measurement reference level

Logic output timing measurement reference level

Logic input pulse levels

1.5

0 or 3.0

Input rise/fall time

Output load for low and high impedance parameters

Output load for all other timing parameters

See Figure 3.1

See Figure 3.2

Figure 3.1 Output Load Test Low and High

Z_D= 50 Ω

Output

R_L= 50 Ω

V_L= 1.5 V

Figure 3.2 Output Load Test All Others

3.3 V

590 Ω

Output

5 pF

435 Ω

MR4A08B Rev. 8.7 3/2018

Timing Speciﬁcations

MR4A08B

Read Mode

Table 3.3 Read Cycle Timing¹

Parameter

Symbol

Min

Max

Unit

t_AVAV

Read cycle time

t_AVQV

t_ELQV

t_GLQV

t_AXQX

t_ELQX

t_GLQX

t_EHQZ

t_GHQZ

Address access time

Enable access time²

Output enable access time

Output hold from address change

Enable low to output active³

Output enable low to output active³

Enable high to output Hi-Z³

Output enable high to output Hi-Z³

W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be

minimized or eliminated during read or write cycles.

Addresses valid before or at the same time E goes low.

This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage.

Figure 3.3A Read Cycle 1

t_AVAV

A (ADDRESS)

t_AXQX

Previous Data Valid

Data Valid

Q (DATA OUT)

t_AVQV

Note: Device is continuously selected (E≤V_IL, G≤V_IL).

Figure 3.3B Read Cycle 2

t_AVAV

A (ADDRESS)

E (CHIP ENABLE)

t_AVQV

t_ELQV

t_EHQZ

t_ELQX

G (OUTPUT ENABLE)

t_GHQZ

t_GLQV

t_GLQX

Data Valid

Q (DATA OUT)

MR4A08B Rev. 8 .7 3/2018

Timing Speciﬁcations

MR4A08B

Table 3.4 Write Cycle Timing 1 (W Controlled)¹

Parameter

Symbol

Min

Max

Unit

Write cycle time²

t_AVAV

t_AVWL

t_AVWH

Address set-up time

Address valid to end of write (G high)

Address valid to end of write (G low)

t_WLWH

t_WLEH

t_WLWH

t_WLEH

Write pulse width (G high)

Write pulse width (G low)

t_DVWH

Data valid to end of write

Data hold time

t_WHDX

t_WLQZ

t_WHQX

t_WHAX

Write low to data Hi-Z³

Write high to output active³

Write recovery time

All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W, E or UB/LB has been brought high, the signal must

remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being

asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given

voltage or temperature, t_WLQZ(max) < t_WHQX(min)

Figure 3.4 Write Cycle Timing 1 (W Controlled)

t_AVAV

A (ADDRESS)

t_AVWH

t_WHAX

E (CHIP ENABLE)

t_WLEH

t_WLWH

W (WRITE ENABLE)

t_AVWL

t_DVWH

DATA VALID

t_WHDX

D (DATA IN)

t_WLQZ

Hi -Z

Q (DATA OUT)

t_WHQX

MR4A08B Rev. 8.7 3/2018

Timing Speciﬁcations

MR4A08B

Table 3.5 Write Cycle Timing 2 (E Controlled)¹

Parameter

Write cycle time ²

Symbol

Min

Max

Unit

t_AVAV

t_AVEL

t_AVEH

Address set-up time

Address valid to end of write (G high)

Address valid to end of write (G low)

t_ELEH

t_ELWH

t_ELEH

t_ELWH

t_DVEH

Enable to end of write (G high)

Enable to end of write (G low) ³

Data valid to end of write

Data hold time

t_EHDX

t_EHAX

Write recovery time

All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus

contention conditions must be minimized or eliminated during read and write cycles. If G goes low at the same time or after

W goes low, the output will remain in a high impedance state. After W, E or UB/ LB has been brought high, the signal must

remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted low in one cycle to E being

asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the

same time or before W goes high, the output will remain in a high-impedance state.

Figure 3.5 Write Cycle Timing 2 (E Controlled)

t_AVAV

A (ADDRESS)

t_EHAX

t_AVEH

t_ELEH

E (CHIP ENABLE)

t_AVEL

t_ELWH

W (WRITE ENABLE)

t_EHDX

t_DVEH

D (DATA IN)

Data Valid

Hi-Z

Q (DATA OUT)

MR4A08B Rev. 8 .7 3/2018

MR4A08B

4. ORDERING INFORMATION

Figure 4.1 Part Numbering System

YS 35

Carrier

Speed

(Blank = Tray, R = Tape & Reel)

(35 ns)

Package (YS = TSOP2, MA = FBGA)

Temperature Range

(Blank= Commercial (0 to +70°C),

C= Industrial (-40 to +85°C)

Revision

Data Width (08 = 8-Bit)

Type

(A = Asynchronous)

Density (4 =16Mb)

Magnetoresistive RAM (MR)

Table 4.1 Available Parts

Grade

Temp Range Package

Shipping Container Part Number

Tray

MR4A08BYS35

44-TSOP2

0 to +70°C

Tape and Reel

Tray

MR4A08BYS35R

MR4A08BMA35

MR4A08BMA35R

MR4A08BCYS35

MR4A08BCYS35R

MR4A08BCMA35

MR4A08BCMA35R

Commercial

Industrial

48-BGA

Tape and Reel

Tray

44-TSOP2

-40 to +85°C

Tape and Reel

Tray

48-BGA

Tape and Reel

MR4A08B Rev. 8.7 3/2018

MR4A08B

5. MECHANICAL DRAWING

Figure 5.1 TSOP2

Print Version Not To Scale

1. Dimensions and tolerances per ASME Y14.5M - 1994.

2. Dimensions in Millimeters.

3. Dimensions do not include mold protrusion.

4. Dimension does not include DAM bar protrusions.

DAM Bar protrusion shall not cause the lead width to exceed 0.58.

MR4A08B Rev. 8 .7 3/2018

Mechanical Drawings

MR4A08B

Figure 5.2 FBGA

BOTTOM VIEW

TOP VIEW

(DATUM B)

PIN A1

INDEX

PIN A1

INDEX

5 4 3 2 1

(DATUM A)

SEATING PLANE

SOLDER BALL DIAMETER REFERS

TO POST REFLOW CONDITION.

THE PRE-REFLOW DIAMETER IS

ø 0.35mm

Ref

Min

1.19

0.22

0.31

Nominal

Max

1.35

0.32

0.41

1.27

0.27

0.36

10.00 BSC

5.25 BSC

3.75 BSC

0.375 BSC

0.75 BSC

Not To Scale

1. Dimensions in Millimeters.

2. The ‘e’represents the basic solder ball grid pitch.

3. ‘b’is measurable at the maximum solder ball diameter

in a plane parallel to datum C.

4. Dimension ‘ddd’is measured parallel to primary datum

Ref

aaa

bbb

ddd

eee

ﬀf

Tolerance of, from and position

0.10

0.15

0.08

5. Primary datum C (seating plane) is deﬁned by the

crowns of the solder balls.

6. Package dimensions refer to JEDEC MO-205 Rev. G.

MR4A08B Rev. 8.7 3/2018

MR4A08B

6. REVISION HISTORY

Revision

Date

Description of Change

May 29, 2009

July 27, 2009

Establish Speed and Power Speciﬁcations

Increase BGA Package to 11 mm x 11 mm

Changed speed marking and timing specs to 35 ns part. Changed BGA package to

10 mm x 10mm

May 5, 2010

Aug 10, 2011

March 1, 2012

Max. magnetic ﬁeld during write (H_{max_write}) increased to 8000 A/m.

Added preliminary information on AEC-Q100 Grade 1.

September 20,

2013

Replaced missing V_OHspeciﬁcation line in Table 2.3.

April 25, 2014

AEC-Q100 removed until qualiﬁed product is available.

48-BGA package options moisture sensitivity level upgraded to MSL-5.

Revised Everspin contact information.

September 17,

2014

8.1

8.2

8.3

8.4

8.5

8.6

8.7

May 19, 2015

June 11, 2015

July 29, 2015

Corrected Japan Sales Oﬃce telephone number.

Minor correction to the ‘ddd’tolerance value for the BGA Package (Note 4.)

March 11, 2016 The BGA package moisture sensitivity level rating is changed to MSL-6 in Table 4.1.

November 22,

The BGA package moisture sensitivity level rating is changed to MSL-5 in Table 4.1.

2016

May 9, 2017

The BGA package moisture sensitivity level is upgraded to MSL-3

Updated the Contact Us table

March 23, 2018

MR4A08B Rev. 8 .7 3/2018

MR4A08B

7. HOW TO CONTACT US

Everspin Technologies, Inc.

Information in this document is provided solely to enable system

and software implementers to use Everspin Technologies products.

There are no express or implied licenses granted hereunder to design

or fabricate any integrated circuit or circuits based on the informa-

tion in this document. Everspin Technologies reserves the right to

make changes without further notice to any products herein. Ever-

spin makes no warranty, representation or guarantee regarding the

suitability of its products for any particular purpose, nor does Ever-

spin Technologies assume any liability arising out of the application

or use of any product or circuit, and speciﬁcally disclaims any and

all liability, including without limitation consequential or incidental

damages. “Typical”parameters, which may be provided in Everspin

Technologies data sheets and/or speciﬁcations can and do vary in

diﬀerent applications and actual performance may vary over time.

All operating parameters including “Typicals”must be validated for

each customer application by customer’s technical experts. Everspin

Technologies does not convey any license under its patent rights

nor the rights of others. Everspin Technologies products are not

designed, intended, or authorized for use as components in systems

intended for surgical implant into the body, or other applications

intended to support or sustain life, or for any other application in

which the failure of the Everspin Technologies product could cre-

ate a situation where personal injury or death may occur. Should

Buyer purchase or use Everspin Technologies products for any such

unintended or unauthorized application, Buyer shall indemnify and

hold Everspin Technologies and its oﬃcers, employees, subsidiaries,

aﬃliates, and distributors harmless against all claims, costs, damages,

and expenses, and reasonable attorney fees arising out of, directly

or indirectly, any claim of personal injury or death associated with

such unintended or unauthorized use, even if such claim alleges that

Everspin Technologies was negligent regarding the design or manu-

facture of the part. Everspin™ and the Everspin logo are trademarks

of Everspin Technologies, Inc. All other product or service names are

the property of their respective owners.

How to Reach Us:

Home Page:

www.everspin.com

World Wide Information Request

WW Headquarters - Chandler, AZ

5670 W. Chandler Blvd., Suite 100

Chandler, Arizona 85226

Tel: +1-877-480-MRAM (6726)

Local Tel: +1-480-347-1111

Fax: +1-480-347-1175

support@everspin.com

orders@everspin.com

sales@everspin.com

Europe, Middle East and Africa

Everspin Europe Support

support.europe@everspin.com

Japan

Everspin Japan Support

support.japan@everspin.com

Asia Paciﬁc

Everspin Asia Support

support.asia@everspin.com

Filename:

EST00356_MR4A08B_Datasheet_Rev8.7032318

MR4A08B Rev. 8.7 3/2018

MR4A08BCMA35R [EVERSPIN]

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