MR5A16AMA35_技术文档

MR5A16A

2M x 16 MRAM

ERRATA to Datasheet

The moisture sensitivity level of the BGA package is rated at MSL-6

eﬀective October 20, 2020. Please take all proper precautions to avoid

any potential damage during solder reﬂow.

Everspin will continue eﬀorts to improve the moisture sensitivity level

and will issue updates to the errata or datasheet when the MSL rating

changes.

Part numbers aﬀected are:

MR5A16AMA35, MR5A16AMA35R

MR5A16ACMA35, MR5A16ACMA35R

MR5A16AUMA45, MR5A16AUMA45R

• Reference MR5A16A datasheet Rev v1.0 11/2019

1

MR5A16A Rev v1.0 11/2019

Everspin Technologies, Inc.

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Filename:

MR5A16A Datasheet v1.0.1 w Errata

2

MR5A16A Rev v1.0 11/2019

MR5A16A

32Mb MRAM

2M x 16 MRAM

FEATURES

• +3.3 Volt power supply

• Fast 35ns read/write cycle (45ns for automotive temperature range)

• SRAM compatible timing

• Unlimited read & write endurance

• Data always non-volatile for >20 years at temperature

• RoHS-compliant small footprint 48-pin BGA and TSOP2 package

• All products meet MSL-3 moisture sensitivity level

• Commercial, Industrial and Automotive temperature ranges available

BENEFITS

RoHS

• One memory replaces FLASH, SRAM, EEPROM, NVSRAM and BBSRAM in

systems for simpler, more eﬃcient designs

• Improves reliability by replacing battery-backed SRAM

INTRODUCTION

The MR5A16A is a 33,554,432-bit magnetoresistive random access memory (MRAM) device organized as

2,097,152 words of 16 bits. The MR5A16A oﬀers SRAM compatible 35 ns read/write timing (45ns for au-

tomotive temperature option) with unlimited endurance. Data is always non-volatile for greater than 20

years. Data is automatically protected on power loss by low-voltage inhibit circuitry to prevent writes with

voltage out of speciﬁcation. To simplify fault tolerant design, the MR5A16A includes internal single bit

error correction code with 7 ECC parity bits for every 64 data bits. The MR5A16A is the ideal memory solu-

tion for applications that must permanently store and retrieve critical data and programs quickly.

The MR5A16A is available in a small footprint 48-pin ball grid array (BGA) package and a 54-pin thin small

outline package (TSOP Type 2). These packages are compatible with similar low-power SRAM products and

other nonvolatile RAM products.

The MR5A16A provides highly reliable data storage over a wide range of temperatures. The product is

oﬀered with commercial temperature (0 to +70 °C), industrial temperature (-40 to +85 °C) and automotive

temperature (-40 to +125°C ) operating temperature options. These products are not AEC Q-100 qualiﬁed.

CONTENTS

1. DEVICE PIN ASSIGNMENT.........................................................................

2. ELECTRICAL SPECIFICATIONS.................................................................

3. TIMING SPECIFICATIONS..........................................................................

3

4

7

4. ORDERING INFORMATION....................................................................... 12

5. MECHANICAL DRAWING.......................................................................... 13

6. REVISION HISTORY...................................................................................... 14

How to Reach Us...................................................................................... .......... 15

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MR5A16A Rev v1.0 11/2019

MR5A16A

1. DEVICE PIN ASSIGNMENT

Figure 1.1 Block Diagram

OUTPUT

ENABLE

BUFFER

UPPER BYTE OUTPUT ENABLE

LOWER BYTE OUTPUT ENABLE

G

10

UPPER

BYTE

OUTPUT

BUFFER

A[20:0]

21

ADDRESS

BUFFER

8

ROW

DECODER

10

COLUMN

DECODER

8

SENSE

AMPS

CHIP

ENABLE

BUFFER

E

LOWER

BYTE

OUTPUT

BUFFER

16

1M x 16

BIT

MEMORY

ARRAY

UPPER

BYTE

WRITE

DRIVER

WRITE

ENABLE

BUFFER

W

8

FINAL

WRITE

DRIVERS

16

LOWER

BYTE

WRITE

DRIVER

UB

LB

UB

LB

UPPER BYTE WRITE ENABLE

LOWER BYTE WRITE ENABLE

BYTE

ENABLE

BUFFER

DIE #1

8

DQU[15:8]

8

DQL[7:0]

OUTPUT

ENABLE

BUFFER

UPPER BYTE OUTPUT ENABLE

LOWER BYTE OUTPUT ENABLE

G

10

UPPER

BYTE

OUTPUT

BUFFER

ADDRESS

BUFFER

8

ROW

DECODER

COLUMN

DECODER

8

SENSE

AMPS

CHIP

ENABLE

BUFFER

E

LOWER

BYTE

OUTPUT

BUFFER

16

1M x 16

BIT

MEMORY

ARRAY

UPPER

BYTE

WRITE

DRIVER

WRITE

ENABLE

BUFFER

W

8

FINAL

WRITE

DRIVERS

16

LOWER

BYTE

WRITE

DRIVER

UB

LB

UB

LB

UPPER BYTE WRITE ENABLE

LOWER BYTE WRITE ENABLE

BYTE

ENABLE

BUFFER

DIE #2

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MR5A16A Rev v1.0 11/2019

DEVICE PIN ASSIGNMENT

MR5A16A

Table 1.1 Pin Functions

Figure 1.1 Package Pin Diagram (Top View)

5ꢀ

53

52

51

1

2

3

ꢀ

A₂₀

Aꢀꢁ

NC

Aꢀꢈ

Signal Name

Function

Aꢂ

Aꢀ

Aꢃ

Aꢄ

Aꢉ

Aꢀꢇ

Aꢀꢆ

Aꢀꢅ

G

UB

LB

DQꢀꢅ

DQꢀꢉ

DQꢀꢄ

DQꢀꢃ

1

2

ꢀ

ꢁ

ꢂ

ꢃ

A

Address Input

Chip Enable

5ꢄ

ꢀꢃ

ꢀꢂ

5

6

ꢁ

ꢄꢅ

ꢆ

ꢇ0

ꢇ1

ꢇ2

ꢈC

ꢇ

ꢅ

C

ꢉ

E

ꢀꢁ

ꢀ6

E

ꢂ

ꢃ

ꢉꢊꢋꢌ

ꢉꢊꢋ9

ꢉꢊꢄ0

ꢉꢊꢄ2

ꢋꢅ

ꢇꢀ

ꢇꢂ

ꢇꢁ

ꢇꢃ

E

W

G

Write Enable

Output Enable

Upper Byte Enable

DQꢂ

DQꢀ

DQꢃ

DQꢄ

ꢀ5

ꢀꢀ

ꢀ3

ꢀ2

ꢀ1

1ꢄ

11

12

13

1ꢀ

ꢉꢊꢋ10

ꢉꢊꢋ11

ꢉꢊꢋ12

ꢉꢊꢋ1ꢀ

ꢇ20

ꢉꢊꢄ1

ꢉꢊꢄꢀ

V

DD

V

SS

UB

SS

DD

ꢍꢎꢎ

ꢍꢉꢉ

ꢇꢐ

ꢇ1ꢐ

ꢉC

DQꢉ

DQꢅ

DQꢆ

DQꢇ

W

DQꢀꢀ

DQꢀꢂ

DQꢁ

DQꢈ

DC

ꢀꢄ

3ꢃ

15

16

LB

Lower Byte Enable

Data I/O

3ꢂ

3ꢁ

36

35

3ꢀ

33

32

1ꢁ

1ꢂ

1ꢃ

2ꢄ

21

22

23

ꢍꢉꢉ

ꢇ1ꢃ

ꢇ1ꢂ

ꢇ1ꢀ

ꢇ10

ꢉꢊꢄꢁ

ꢉꢊꢄꢂ

ꢍꢎꢎ

DQ

V_DD

V_SS

Aꢅ

Aꢀꢉ

ꢏ

ꢉꢊꢋ1ꢁ

ꢉꢊꢋ1ꢂ

ꢇ1ꢌ

ꢉꢊꢄꢃ

ꢉꢊꢄꢐ

ꢇ1ꢁ

ꢇ12

ꢇ9

Aꢆ

Aꢇ

Aꢈ

Aꢀꢄ

Aꢀꢃ

Aꢀꢀ

Aꢀꢂ

NC

Power Supply

Ground

ꢆ

ꢒ

ꢑ

Aꢁ

31

3ꢄ

2ꢀ

25

NC

2ꢃ

2ꢂ

26

2ꢁ

ꢇꢌ

ꢇ11

ꢇ19

DC

NC

Do Not Connect

No Connection

48-Pin BGA

54-Pin TSOP2

Table 1.2 Operating Modes

E¹

H

L

G¹W¹LB¹UB¹

Mode

Not selected

V_DDCurrent

DQL[7:0]²DQU[15:8]²

X

H

X

L

X

H

X

H

L

X

H

L

X

H

L

I_SB1, I_SB2

Hi-Z

D_Out

Hi-Z

D_Out

D_in

Hi-Z

D_Out

Hi-Z

D_in

Output disabled

Lower Byte Read

Upper Byte Read

Word Read

I_DDR

L

I_DDR

L

I_DDR

L

H

L

I_DDR

L

I_DDR

L

X

L

H

L

Lower Byte Write

Upper Byte Write

Word Write

I_DDW

L

H

L

Hi-Z

D_in

L

D_in

1

2

H = high, L = low, X = don’t care

Hi-Z = high impedance

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MR5A16A Rev v1.0 11/2019

MR5A16A

2. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings

This device contains circuitry to protect the inputs against damage caused by high static voltages or

electric ﬁelds; however, it is advised that normal precautions be taken to avoid application of any

voltage greater than maximum rated voltages to these high-impedance (Hi-Z) circuits.

The device also contains protection against external magnetic ﬁelds. Precautions should be taken

to avoid application of any magnetic ﬁeld greater than the maximum ﬁeld intensity speciﬁed

in the maximum ratings.

Table 2.1 Absolute Maximum Ratings ¹

Symbol

V_DD

Parameter

Conditions

Value

Unit

V

Supply voltage²

Voltage on an pin ²

Output current per pin

-0.5 to 4.0

-0.5 to V_DD+ 0.5

V_IN

V

I_OUT

20

mA

P_D

Package power dissipation ³

Temperature under bias

Storage Temperature

0.600

W

Commercial

Industrial

-10 to 85

-45 to 95

-55 to 150

°C

T_BIAS

T_stg

Lead temperature during solder (3

minute max)

T_Lead

260

°C

H_{max_write}

H_{max_read}

Maximum magnetic ﬁeld

During Write

8000

A/m

During Read or Standby

1

2

3

Permanent device damage may occur if absolute maximum ratings are exceeded. Functional operation

should be restricted to recommended operating conditions. Exposure to excessive voltages or magnetic

ﬁelds could aﬀect device reliability.

All voltages are referenced to V_SS. The DC value of V_INmust not exceed actual applied V_DDby more than

0.5V. The AC value of V_INmust not exceed applied V_DDby more than 2V for 10ns with I_INlimited to less than

20mA.

Power dissipation capability depends on package characteristics and use environment.

6

MR5A16A Rev v1.0 11/2019

Electrical Speciﬁcations

MR5A16A

Table 2.2 Operating Conditions

Symbol

Parameter

Temp Range

Min

3.0 ¹

Typical

Max

3.6

3.0¹

Unit

V

V_DD

Power supply voltage

Write inhibit voltage

Input high voltage

Input low voltage

3.3

V_WI

V_IH

V_IL

2.5

2.7

V

V_DD+ 0.3 ²

2.2

-0.5 ³

-

V

0.8

70

85

V

Commercial

Industrial

0

°C

Temperature under bias ⁴

-40

-

°C

T_A

Automotive

-40

125

1

2

3

4

There is a 2 ms startup time once V_DDexceeds V_DD,(min). See Power Up and Power Down Sequencing below.

V_IH(max) = V_DD+ 0.3 V_DC; V_IH(max) = V_DD+ 2.0 V_AC(pulse width ≤ 10 ns) for I ≤ 20.0 mA.

V_IL(min) = -0.5 V_DC; V_IL(min) = -2.0 V_AC(pulse width ≤ 10 ns) for I ≤ 20.0 mA.

The ambient operature temperature rating assumes a 10% duty cycle (2 years out of 20 years life) for operating temperatures between +85°C

and +125°C.

Power Up and Power Down Sequencing

The MRAM is protected from write operations whenever V_DDis less than V_WI. As soon as V_DDexceeds V_DD(min),

there is a startup time of 2 ms before read or write operations can start. This time allows memory power

supplies to stabilize.

The E and W control signals should track V_DDon power up to V_DD- 0.2 V or V_IH(whichever is lower) and remain

high for the startup time. In most systems, this means that these signals should be pulled up with a resis-

tor so that a signal remains high if the driving signal is Hi-Z during power up. Any logic that drives E and W

should hold the signals high with a power-on reset signal for longer than the startup time.

During power loss or brownout where V_DDgoes below V_WI, writes are protected and a startup time must be

observed when power returns above V_DD(min).

Figure 2.1 Power Up and Power Down Diagram

VDD

V

WI

BROWNOUT or POWER LOSS

2 ms

STARTUP

RECOVER

NORMAL

OPERATION

NORMAL

OPERATION

READ/WRITE

INHIBITED

READ/WRITE

INHIBITED

VIH

E

W

7

MR5A16A Rev v1.0 11/2019

Electrical Speciﬁcations

MR5A16A

Table 2.3 DC Characteristics

Symbol

Parameter

Conditions

Min

Max

Unit

I_lkg(I)

Input leakage current

All

-

1

μA

I_lkg(O)

Output leakage current

All

-

μA

V

I_OL= +4 mA

0.4

V_OL

Output low voltage

I_OL= +100 μA

V_SS+ 0.2

V

I_OH= -4 mA

2.4

-

V

V_OH

Output high voltage

I_OH= -100 μA

V_DD- 0.2

Table 2.4 Power Supply Characteristics

Symbol Parameter

Typical

Max

Unit

AC active supply current - read modes¹

(I_OUT= 0 mA, V_DD= max)

I_DDR

60

75

mA

AC active supply current - write modes¹

(V_DD= max)

I_DDW

152

18

180

AC standby current

I_SB1

(V_DD= max, E = V_IH)

28

18

mA

no other restrictions on other inputs

CMOS standby current

I_SB2

(E ≥ V_DD- 0.2 V and V_In≤V_SS+ 0.2 V or ≥ V_DD- 0.2 V)

(V_DD= max, f = 0 MHz)

10

1

All active current measurements are measured with one address transition per cycle and at minimum cycle time.

8

MR5A16A Rev v1.0 11/2019

MR5A16A

3. TIMING SPECIFICATIONS

Table 3.1 Capacitance ¹

Symbol Parameter

Typical

Max

Unit

pF

C_In

Address input capacitance

Control input capacitance

Input/Output capacitance

-

8

C_In

pF

C_I/O

pF

¹f = 1.0 MHz, dV = 3.0 V, T_A= 25 °C, periodically sampled rather than 100% tested.

Table 3.2 AC Measurement Conditions

Parameter

Value

1.5

Unit

V

Logic input timing measurement reference level

Logic output timing measurement reference level

Logic input pulse levels

1.5

V

0 or 3.0

2

V

Input rise/fall time

ns

Output load for low and high impedance parameters

Output load for all other timing parameters

See Figure 3.1

See Figure 3.2

Figure 3.1 Output Load Test Low and High

Z_D= 50 Ω

Output

R_L= 50 Ω

V_L= 1.5 V

Figure 3.2 Output Load Test All Others

3.3 V

590 Ω

Output

5 pF

435 Ω

9

MR5A16A Rev v1.0 11/2019

Timing Speciﬁcations

MR5A16A

Table 3.3 Read Cycle Timing ¹

Read Mode

Symbol

t_AVAV

Parameter

Min

35 [45]⁴

Max

Unit

ns

Read cycle time

Address access time

Enable access time ²

-

35 [45]⁴

t_AVQV

t_ELQV

t_GLQV

t_BLQV

t_AXQX

t_ELQX

t_GLQX

t_BLQX

Output enable access time

-

15

-

Byte enable access time

-

Output hold from address change

Enable low to output active ³

Output enable low to output active ³

Byte enable low to output active ³

Enable high to output Hi-Z ³

Output enable high to output Hi-Z ³

Byte high to output Hi-Z ³

3

0

-

t_EHQZ

t_GHQZ

t_BHQZ

15

10

1

W is high for read cycle. Power supplies must be properly grounded and decoupled, and bus contention conditions must be minimized or eliminated during

read or write cycles.

2

3

4

Addresses valid before or at the same time E goes low.

This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage.

Speciﬁcation in square brackets [xx] applicable for automotive temperature range option only.

Figure 3.3A Read Cycle 1

t_AVAV

A (ADDRESS)

t_AXQX

Previous Data Valid

Data Valid

Q (DATA OUT)

t_AVQV

Note: Device is continuously selected (E≤V_IL, G≤V_IL).

Figure 3.3B Read Cycle 2

t_AVAV

A (ADDRESS)

E (CHIP ENABLE)

t_AVQV

t_ELQV

t_EHQZ

t_ELQX

G (OUTPUT ENABLE)

LB, UB (BYTE ENABLE)

t_GHQZ

t_GLQV

t_GLQX

t_BHQZ

t_BLQV

t_BLQX

Data Valid

Q (DATA OUT)

10

MR5A16A Rev v1.0 11/2019

Timing Speciﬁcations

MR5A16A

Table 3.4 Write Cycle Timing 1 (W Controlled) ¹

Min

Symbol

Parameter

Write cycle time ²

Max

Unit

35 [45]⁴

-

ns

t_AVAV

t_AVWL

t_AVWH

Address set-up time

0

-

ns

20 [30]⁴

Address valid to end of write (G high)

Address valid to end of write (G low)

t_WLWH

t_WLEH

t_WLWH

t_WLEH

t_DVWH

15

-

ns

Write pulse width (G high)

Write pulse width (G low)

Data valid to end of write

Data hold time

10

0

-

ns

t_WHDX

t_WLQZ

t_WHQX

t_WHAX

Write low to data Hi-Z ³

Write high to output active ³

Write recovery time

0

15

-

3

12

-

1

All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be

minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state.

After W, E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted

low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

This parameter is sampled and not 100% tested. Transition is measured 200 mV from the steady-state voltage. At any given voltage or temperate, t_WLQZ(max)

< t_WHQX(min).

2

3

4

Speciﬁcation in square brackets [xx] applicable for automotive temperature range option only.

Figure 3.4 Write Cycle Timing 1 (W Controlled)

t

AVAV

A (ADDRESS)

t

AVWH

WHAX

E (CHIP ENABLE)

t

WLEH

WLWH

W (WRITE ENABLE)

t

AVWL

UB, LB (BYTE ENABLED)

D (DATA IN)

t

WHDX

DVWH

DATA VALID

t

WLQZ

Hi -Z

Q (DATA OUT)

t

WHQX

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MR5A16A Rev v1.0 11/2019

Timing Speciﬁcations

MR5A16A

Table 3.5 Write Cycle Timing 2 (E Controlled) ¹

Symbol

Parameter

Min

35 [45]⁴

Max

Unit

ns

Write cycle time ²

-

t_AVAV

t_AVEL

t_AVEH

Address set-up time

0

ns

Address valid to end of write (G high)

Address valid to end of write (G low)

20 [30]⁴

ns

t_ELEH

t_ELWH

t_ELEH

t_ELWH

Enable to end of write (G high)

Enable to end of write (G low) ³

15

-

ns

t_DVEH

t_EHDX

t_EHAX

Data valid to end of write

Data hold time

10

0

-

ns

Write recovery time

12

1

All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be

minimized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state.

After W, E or UB/ LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. The minimum time between E being asserted

low in one cycle to E being asserted low in a subsequent cycle is the same as the minimum cycle time allowed for the device.

All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

If E goes low at the same time or after W goes low, the output will remain in a high-impedance state. If E goes high at the same time or before W goes high,

the output will remain in a high-impedance state.

2

3

4

Speciﬁcation in square brackets [xx] applicable for automotive temperature range option only.

Figure 3.5 Write Cycle Timing 2 (E Controlled)

t_AVAV

A (ADDRESS)

t_EHAX

t_AVEH

t_ELEH

E (CHIP ENABLE)

t_AVEL

t_ELWH

W (WRITE ENABLE)

UB, LB (BYTE ENABLE)

D (DATA IN)

t_EHDX

t_DVEH

Data Valid

Hi-Z

Q (DATA OUT)

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MR5A16A Rev v1.0 11/2019

Timing Speciﬁcations

MR5A16A

Table 3.6 Write Cycle Timing 3 (LB/UB Controlled) ¹

Min

Symbol

Parameter

Max

Unit

Write cycle time ²

35 [45]³

-

ns

t_AVAV

t_AVBL

t_AVBH

Address set-up time

0

-

ns

Address valid to end of write (G high)

Address valid to end of write (G low)

20 [30]³

t_BLEH

t_BLWH

t_BLEH

t_BLWH

t_DVBH

Write pulse width (G high)

Write pulse width (G low)

15

-

ns

Data valid to end of write

Data hold time

10

0

-

ns

t_BHDX

t_BHAX

Write recovery time

12

1

All write occurs during the overlap of E low and W low. Power supplies must be properly grounded and decoupled and bus contention conditions must be mini-

mized or eliminated during read and write cycles. If G goes low at the same time or after W goes low, the output will remain in a high impedance state. After W,

E or UB/LB has been brought high, the signal must remain in steady-state high for a minimum of 2 ns. If both byte control signals are asserted, the two signals

must have no more than 2 ns skew between them. The minimum time between E being asserted low in one cycle to E being asserted low in a subsequent cycle

is the same as the minimum cycle time allowed for the device.

2

3

All write cycle timings are referenced from the last valid address to the ﬁrst transition address.

Speciﬁcation in square brackets [xx] applicable for automotive temperature range option only.

Figure 3.6 Write Cycle Timing 3 (LB/UB Controlled)

t

AVAV

A (ADDRESS)

t

AVEH

BHAX

E (CHIP ENABLE)

W (WRITE ENABLE)

t

AVBL

BLEH

BLWH

UB, LB (BYTE ENABLED)

D (DATA IN)

t

BHDX

DVBH

Data Valid

Hi -Z

Q (DATA OUT)

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MR5A16A

4. ORDERING INFORMATION

Figure 4.1 Part Numbering System

MR

5

A

16

A

C

MA 35

R

Carrier

Speed

Blank = Tray, R = Tape & Reel

35ns, 45ns

Package

MA = FBGA, YS = TSOP

Temperature Range Blank= Commercial (0 to +70 °C),

C= Industrial (-40 to +85°C )

U= Automotive (-40 to +125°C )

Revision

Data Width

Type

16 = 16-bit

A = Asynchronous

5 =32Mb

Density

Magnetoresistive RAM

Table 4.1 Available Parts

Shipping Con-

tainer

Grade

Temp Range

Package

Order Part Number

Trays

MR5A16AMA35

MR5A16AMA35R

MR5A16AYS35

48-BGA

Tape & Reel

Trays

Commercial

Industrial

0 to +70 °C

54-TSOP2

48-BGA

Tape & Reel

Tray

MR5A16AYS35R

MR5A16ACMA35

MR5A16ACMA35R

MR5A16ACYS35

MR5A16ACYS35R

MR5A16AUMA45

MR5A16AUMA45R

MR5A16AUYS45

MR5A16AUYS45R

Tape & Reel

Tray

-40 to +85°C

-40 to +125°C

54-TSOP2

48-BGA

Tape & Reel

Tray

Tape & Reel

Tray

Automotive¹

54-TSOP2

Tape & Reel

1. Not AEC Q-100 Qualiﬁed.

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MR5A16A

5. MECHANICAL DRAWING

Figure 5.1 48-FBGA

BOTTOM VIEW

TOP VIEW

(DATUM B)

PIN A1

INDEX

PIN A1

INDEX

6

5 4 3 2 1

A

B

C

D

E

F

G

H

(DATUM A)

SEATING PLANE

SOLDER BALL DIAMETER REFERS

TO POST REFLOW CONDITION.

THE PRE-REFLOW DIAMETER IS

ø 0.35mm

Ref

A

Min

1.19

0.22

0.31

Nominal

Max

1.35

0.32

1.27

Print Version Not To Scale

A1

b

0.27

0.36

0.41

1. Dimensions in Millimeters.

10.00 BSC

5.25 BSC

3.75 BSC

0.375 BSC

0.75 BSC

D

E

2. The ‘e’represents the basic solder ball grid pitch.

3. ‘b’is measurable at the maximum solder ball diameter

in a plane parallel to datum C.

D1

E1

DE

SE

e

4. Dimension ‘ddd’is measured parallel to primary datum

C.

5. Primary datum C (seating plane) is deﬁned by the

crowns

of the solder balls.

6. Package dimensions refer to JEDEC MO-205 Rev. G.

Ref

aaa

bbb

ddd

eee

ﬀf

Tolerance of, from and position

0.10

0.15

0.08

15

MR5A16A Rev v1.0 11/2019

MR5A16A

5. MECHANICAL DRAWING

Figure 5.2 54-TSOP2

A2

A1

A

D

54

28

θ2

θ3

c

1

27

⊕0.20(0.008) M

e

b

R1

R2

0.71 REF.

0.21(0.008)R

C

0.665(0.026)R

GAGE

0.25 mm

SEATING PLANE

0.10

C

Ref

A

Min

Nominal

Max

1.20

A1

A2

b

c

D

E

E1

e

0.05

0.95

0.10

1.00

0.35

0.15

1.05

0.45

Print Version Not To Scale

0.30

1. Dimensions in Millimeters.

0.12

0.21

2. Package dimensions refer to JEDEC MS-024

22.10

11.56

10.03

22.22

11.76

10.16

0.80 BSC

0.50

22.35

11.95

10.29

0.40

0.60

L

0.80 REF

-

L1

R1

R2

θ

0.12

0°

-

0.25

8°

-

0.40

-

θ1

θ2

θ3

15° REF

16

MR5A16A Rev v1.0 11/2019

MR5A16A

6. REVISION HISTORY

Rev Date

Description of Change

1.0

Nov 20, 2019

Released ﬁrst version of the datasheet

17

MR5A16A Rev v1.0 11/2019

7. HOW TO CONTACT US