SP6122ACU-L-1.5_技术文档

®

SP6122

Low Voltage, Micro 8, PFET, Buck Controller

Ideal for 1A to 5A, Small Footprint, DC-DC Power Converters

■ꢀ Optimized for Single Supply, 3V-5.5V Applications

■ꢀ High Efficiency, Greater than 90% Possible

■ꢀ 20ns/1nF PFET Output Driver

■ꢀ Fast Transient Response

■ꢀ Open Drain Fault Output Pin

1

2

3

4

8

7

6

5

PDRV

GND

V

CC

SP6122

FFLAG

8 Pin MSOP

V

I

OUT

SET

ENABLE

I

■ꢀ Internal Soft Start Circuit

SENSE

■ꢀ Accurate 1.5% Reference

■ꢀ Programmable Output Voltage or Fixed 1.5V Output

■ꢀ Loss-less Adjustable Current Limit with High side

Now Available in Lead Free Packaging

R

_DS(ON)Sensing

■ꢀ Hiccup or Lock-up Fault Modes

■ꢀ Low 5µA Sleep Mode Quiescent Current

■ꢀ Low 300µA Protected Mode Quiescent Current

■ꢀ Ultra Low, 150µA Unprotected Mode Quiescent

Current

■ꢀ High Light Load Efficiency

APPLICATIONS

■ꢀ Video Cards

■ꢀ High Power Portable

■ꢀ Microcontrollers

■ꢀ I/O & Logic

■ꢀ Industrial Control

■ꢀ Distributed Power

■ꢀ Low Voltage Power

■ꢀ Offered in Tiny 8 pin MSOP Package

DESCRIPTION

The SP6122 is a PWM/PFM minimum on-time controller designed to work from a single 3V-

5.5V input supply. It is engineered specifically for size and minimum component count,

simplifying the transition from a linear regulator to a switcher solution. However, unlike other

“micro” parts, the SP6122 has an array of value added features such as optional hiccup

mode, over current protection, TTL enable, “jitter and frequency stabilization” and a fault flag

pull-down pin. Combined with reference and driver specifications usually found on more

expensive integrated circuits, the SP6122 delivers great performance and value in an 8 pin

MSOP package.

TYPICAL APPLICATION CIRCUIT

3.0V to 7.0V

V

IN

R1

5Ωꢀ

C2

100µF

R

SET

C1

4.7µF

1k

Q1

PDS6375

V

PDRV

GND

CC

®®

FFLAG

SP6122

V

OUT

I

SET

1A to 5A

L1

2.2µH

DFLY

ENABLE

I

V

OUT

SENSE

C

470µF

OUT

STPS2L25U

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

1

V_CC.............................................................................................................. 7V

All other pins ...................................... -0.3V to V_CC+0.3V

Peak Output Current < 10µs

PDRV ......................................................................... 2A

Storage Temperature ..............................-65°C to 150°C

Power Dissipation

ABSOLUTE MAXIMUM RATINGS

These are stress ratings only and functional operation of

the device at these ratings or any other above those

indicated in the operation sections of the specifications

below is not implied. Exposure to absolute maximum

rating conditions for extended periods of time may affect

reliability.

Lead Temperature (Soldering, 10 sec) ................. 300°C

ESD Rating ...................................................... 2kV HBM

ELECTRICAL CHARACTERISTICS

Unless otherwise specified: 0°C < T_AMB< 70°C, 3.0V < V_CC< 5.5V, C_PDRV= 1nF, V_ENABLE= V_CC, V_FFLAG= V_CC

,

I_SET= I_SENSE= V_CC, GND = 0.0V

PARAMETER

MIN

TYP

MAX

UNITS CONDITIONS

QUIESCENT CURRENT

V_CCSupply Current,

OVC Enabled

-

300

450

µA

No Switching, I_SET= I_SENSE= V_CC

No Switching, I_SET= I_SENSE= 0

V_CCSupply Current,

OVC Disabled

-

250

150

360

225

µA

V_CCSupply Current,

OVC Disabled, Ultra Low IQ

No Switching, ISET = 0,

I_SENSE=V_CC

V_CCSupply Current, Sleep Mode

-

5

15

µA

Enable=0

REFERENCE

Output Voltage, Initial Accuracy

VR*0.985

VR

5

VR*1.015

V

VR = Factory Set Voltage,

see Note

Output Voltage, Over Line,

Load and Temperature

VR*0.980

VR*1.020

VR = Factory Set Voltage,

see Note

Reference Comparator

Hysteresis

-

mV

µA

Internal Hysteresis at Feedback

Terminal

V_OUTInput Current

23

V_OUT= VR;

SP6122ACU-1.5 ONLY

OSCILLATOR

Oscillator Frequency

210

150

300

270

390

380

kHz

ns

Minimum Pulse Width during

Startup (Blanking Time)

Soft Start

Soft Start Ramp Time

-

3.5

-

ms

V_OUT= VR – 30mV, Measure

time from ENABLE = 1V to

PDRV Low

Soft Start Voltage when

PDRV Switches

250

mV

Measure VSoft Start when

PDRV goes Low. (internal)

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

2

ELECTRICAL CHARACTERISTICS

Unless otherwise specified: 0°C < T_AMB< 70°C, 3.0V < V_CC< 5.5V, C_PDRV= 1nF, V_ENABLE= V_CC, V_FFLAG= V_CC

,

I_SET= I_SENSE= V_CC, GND = 0V

PARAMETER

MIN

TYP

MAX

UNITS CONDITIONS

RDS OVER CURRENT COMPARATOR

Over Current Comparator

Threshold Voltage

130

150

180

-

mV

V(I_SET) - V(I_SENSE) 25°C only

Current into I_SET25°C only

Threshold Voltage Temperature

Coefficient

-

3800

ppm/°C

I_SETSink Current

15

-

20

25

-

µA

I_SETCurrent Temperature

Coefficient

4300

ppm/°C

I_SENSEInput Bias Current

-

100

V_CC

nA

V

I_SET, I_SENSECommon Mode

Input Range

2.0

Over Current Peak Detection

Time Constant

-

10

-

µs

ENABLE INPUT & FFLAG OUTPUT

ENABLE Threshold

0.90

0.8

1.21

5.0

1.45

10.0

15.0

V

ENABLE Pin Source Current

FFLAG Sink Current

µA

mA

3.0

7.5

V(FFLAG) = 1V

GATE DRIVER

PDRV Rise Time

PDRV Fall Time

20

75

ns

0.5V to 4.5V

4.5V to 0.5V

NOTE: Available Output Voltages: 1.5V Fixed, 1.25V Adj.

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

3

PIN DESCRIPTION

PIN #

1

PIN NAME

V_CC

DESCRIPTION

Main Supply Pin: A RC filter as shown in the application circuit is

recommended. The decoupling capacitor needs to be close to the pin.

2

3

4

FFLAG

V_OUT

Fault Flag Pull-down Pin: Sinks current during a fault condition. Can

be hooked up to ENABLE to initiate Hiccup Timing.

Regulated Output Voltage: This voltage is divided internally and

compared to a 1.5%, 1.25V reference at the PFM comparator.

ENABLE

Enable Input: Floating this pin or pulling above 1.45V enables the

part. Pulling this pin to less than 0.9V will disable the part. A minimum

100pF capacitor is required between this pin and Ground to ensure

proper startup. If FFLAG is hooked to ENABLE, the capacitor on

ENABLE will control hiccup timing.

5

I_SENSE

Negative Input to the Over Current Amplifier/Comparator: This input

is subtracted from the I_SETinput and gained by a factor of 3.3. The

output of this amplifier is compared with a 0.5V threshold, yielding a

150mV threshold. This threshold has a 3800 ppm/°C temperature

coefficient. If the subtraction exceeds 150mV, charge is pumped into

a capacitor until the capacitor hits V_CC/2. At this time, the over current

fault is activated. If I_SET= 0V and I_SENSE= V_CC, the part enters an

unprotected, 150µA quiescent current mode.

6

I_SET

Positive Input to the Over Current Amplifier: 20µA flows into the I_SET

pin if it is pulled through a resistor to V_IN. This current has a

4300ppm/°C temperature coefficient and can be used via external

resistor to raise the overcurrent trip point from 150mV to some higher

value. If I_SET= 0V and I_SENSE= 0V, the part enters an unprotected,

250µA quiescent current mode.

7

8

GND

Power and Analog Ground: Hook directly to output ground.

Drive for PFET High Side Switch: 1nF/20ns Output Driver.

PDRV

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

4

BLOCK DIAGRAM

Reset

Dominant

SS

Soft Start

-

R

SS

Latch

+

PFET OFF

QB

S

Reset

1.25V

Dominant

4

ENABLE

Reference

-

POR

QB

Run

Latch

R

Soft Start Clock

+

V_OUT* K1

T_ON

1V

Q

S

Start On Time

Min On Time Clock

V_CC

1

RESET

Dominant

S

QB

Loop

Latch

Driver

Logic

PFET

Driver

Reference

Comparator

-

8

7

PDRV

GND

PFET OFF

R

Q

V_OUT

3

6

X K1

+

Blank

200ns Blanking

One Shot

I_SET

PDRV

20µA

(4300 ppm/°C)

Over Current

(Gated S&H)

Reset

POR

2

+

FFLAG

Dominant

X 3.3

+

S

I_SENSE

5

-

FAULT

500mV

(3800 ppm/°C)

-

Q

R

POR

I_SET

I_SENSE

I_SET< 1V

Low IQ

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

5

OPERATION

General Overview

Enable

The SP6122 is a minimum on-time,

PFM/PWM controller for low cost DC/DC

stepdownconverters.Themaincontrolloop

consistsofaREFERENCECOMPARATOR,

an ON-TIME CLOCK, a LOOP LATCH and

aBLANKINGONESHOT.TheREFERENCE

comparator has 10mV of internal hysteresis

and a 1.25V internal reference. Both

hysteresis and reference voltage are

multiplied upward by the internal feedback

resistordivider, K1(K1=1fortheadjustable

version). This value is set by the factory and

determines the output voltage of the

converter. Thisdividerisalsousedintheon-

time algorithm for the controller. If the output

voltage drops below K1*1.25V, then the

DRIVER LOGIC tells the PFET switch to be

“on”foracertainminimumtime. Theon-time

issetbytheSoftStartCLOCKfrequencyand

is factory programmed to run at 300kHz.

Whenthepartisenabled, throughV_CCorthe

ENABLE pin, the DRIVER LOGIC is

configured to first look at the fixed frequency

Soft Start loop. The output voltage is then

controlledbya0.5V/msinternalramp.When

the output voltage reaches K1*1.25V, the

Soft Start loop is switched off and the main

loop takes over.

Low quiescent mode or “Sleep Mode” is

initiated by pulling the ENABLE pin below

650mV. The ENABLE pin has an internal

4µA pull-up current and does not require

any external interface for normal operation.

If the ENABLE pin is driven from a voltage

source, the voltage must be above 1.45V in

order to guarantee proper “awake” opera-

tion. Assuming that V_CCis above about

2.9V, the SP6122 transitions from “Sleep

Mode” to “Awake Mode” in about 20µs –

30µs and from “Awake Mode” to “Sleep

Mode” in a few microseconds. SP6122 qui-

escent current in sleep mode is 5µA typical.

During Sleep Mode, the PFET switch is

turned off, the internal SS voltage is held

low and the FFLAG pin is high impedance.

Low Current Operation

Ifovercurrentfaultprotectionisnotneeded,

the SP6122 offers two options to lower its

quiescent current. By grounding both I_SET

and I_SENSEpins, the circuitry responsible for

over current detection is turned off. This

option results in a saving of about 50µA in

quiescent current. Option two requires that

I_SETis grounded and ISENSE is greater

than 1.3V. This option put the SP6122 in a

low performance mode that cuts the operat-

ing frequency roughly in half and slows

down critical comparators in the main loop.

Option two can result in additional saving of

100µA bringing the total quiescent current

to only 150µA (typ).

Fault management is controlled either

through power-on-reset (POR) or R_DS(ON)

sense over current protection. Should an

over current condition occur, the SP6122

will completely “lock-up” and turn the PFET

switch off. The only way to recover will be to

either cycle the ENABLE pin or V_CC. A Fault

flag output (FFLAG) has been included to

either signal the upstream circuitry or to

engage a hiccup mode that will restart the

SP6122. Tying FFLAG to ENABLE allows

the controller to restart without assistance.

Lastly, the SP6122 includes a powerful 4Ωꢀ

PFETdriverstagedesignedtodriveaPFET

associated with high speed converter de-

signs in the 1 A – 5 A range.

Power On Reset (POR)

The POR command is given every time the

bandgap reference is started. The internal

1.25 V reference is compared against a 1V

NFETthreshold.Whenthereferenceisbelow

the threshold, FAULT and RUN latches are

reset, the internal SS voltage is discharged

and the PFET switch is “off”. The SP6122 is

allowed to begin a soft start cycle when the

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

6

Power On Reset (POR): continued

inrush current and over current thresholds.

An expression to determine the excess in-

rush current due to the dV_OUT/dt of the

output capacitor is:

internal 1.25V is greater than the 1 V thresh-

old.Notethisisa“loose”thresholdandshould

not be used to guarantee under voltage lock

out with respect to V_CC. Care should be take

to ensure that V_CCdoes not “get stuck” on the

way to its regulated value.

V_OUT

,

IC_OUT= C_OUT*0.5 V/ms *

V_R

Soft Start

where VR is the internal reference voltage.

Soft start is required on step-down control-

lerstopreventexcessinrushcurrentthrough

the power train during start-up. On the

SP6122, this is managed through turning

the PFET switch on with a fixed frequency

clock and then turning the switch off when

divided down version of the output voltage

exceeds the internal SS voltage ramp. The

internal SS voltage ramp rises with a 0.5 V/

ms slew rate and the internal feedback

voltage follows this rate of change. The

presence of the output capacitor creates

extra current draw during startup. Since

dV_OUT/dt creates an average sustained cur-

rent in the output capacitor, this current

must be considered while calculating peak

Lock Up & Hiccup Modes

As previously stated, if the SP6122 detects

an over current condition and initiates a

fault, the power supply remains “locked up”.

That is, the FFLAG pin immediately pulls

low (if loaded) and the PFET switch turns

off. This condition is permanent unless the

either the V_CCor ENABLE is cycled. How-

everifFFLAGistiedtoENABLE,theSP6122

will restart without assistance (Hiccup

Mode). Furthermore, therestarttimecanbe

controlled by the addition of a small capaci-

tor on the ENABLE pin to ground. The

restart time is equal to the amount of time it

takes for the 5µA ENABLE pin current to

charge the external capacitor to an NFET

threshold (roughly 1V). The waveforms that

describe the Hiccup Mode operation are

shown below.

SS

Voltage

dV_SS/dt = 0.5Vms

0.25V

0V

150mV

VI_SET- VI_SENSE

Comparator

Reference

Voltage

0V

1.25V

V(V_CC

)

0V

FFLAG

Voltage

I_LOAD

0V

V(V_CC

)

Inductor

Current

ENABLE

Voltage

dV_ENABLE/dt = 4µA/C_ENABLE

0A

1.0V

0V

V(V_IN

)

V(V_CC

)

SWN

Voltage

PDRV

Voltage

0V

TIME

0V

TIME

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

7

Over Current Protection

istics of the PFET switch. It assumed that

theSP6122willbeusedincompactdesigns

where there is a high amount of thermal

coupling between the PFET and the con-

troller.

Over current protection on the SP6122 is

implemented through detection of an ex-

cess voltage condition across the PFET

switch during conduction. This is typically

referred to as high side R_DS(ON)detection.

The over current comparator charges a

sampling capacitor each time V(I_SET) –

V(I_SENSE) exceeds 150mV (typ) and the

PDRV voltage is low. The discharge cur-

rent/charge current ratio on the sampling

capacitor is about 2%. Therefore, provided

that the over current condition persists, the

capacitor voltage will be pumped up during

each time PDRV switches low and this

voltage will trigger an over current condition

upon reaching a CMOS inverter threshold.

There are many advantages to this ap-

proach. First, thefilteringactionofthegated

S/H scheme protects against false trigger-

ing during a transient load condition or sup-

ply line noise. In addition, the total amount

of time to trigger the fault depends on the

on-timeofthePFETswitch.Ten,1µspulses

are equivalent to twenty, 500ns pulses or

one, 1µs pulse, however, depending on the

period, each scenario takes a different

amount of total time to trigger a fault. There-

fore, the fault becomes an indicator of aver-

age power in the PFET switch. Also, be-

cause the CMOS trip threshold is depen-

dent on V_CC, the over current scheme is

protected against false triggering due to

changes in line voltage.

Light Load Operation

One of the advantages of the SP6122 mini-

mum on-time control scheme is the loop’s

ability to seamlessly and efficiently transi-

tion from heavy loads to light loads. In most

other control schemes, the controller is no-

tified about a light load condition and then

must abruptly change control schemes in

order to maintain efficiency. The SP6122

simply reduces the frequency when the

average load current is less than the aver-

age inductor ripple current. As a result,

switching loss decreases as the load cur-

rent decreases and overall efficiency is

maintained.

Output Driver

The driver stage consists of a high side, 4

ohm PFET driver. The following waveforms

illustrate basic behavior of the driver.

Gate Driver Test Conditions

5 V

90 %

10 %

RISE TIME

FALL TIME

PDRV

10 %

Although the 150mV threshold is fixed, the

overall R_DS(ON)detection voltage can be

increased by placing a resistor from I_SETto

V_CC. A 20µA sink current programs the

additional voltage.

V(V_CC)

PDRV

Voltage

0 V

V(V_CC)= V_IN

SWN

Voltage

The 150 mV threshold and 20µA I_SETcur-

rent have 3800 ppm/°C and 4300 ppm/°C

temperature coefficients, respectively.

These TC’s are designed into the SP6122

in an effort to match the thermal character-

0V

- V(V_DIODE

)

TIME

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

8

APPLICATION INFORMATION

7A. The body of the applications section

contains:

• Data for the Evaluation Board

• Guidelines for Component Selection

• Features and Protection

• Layout Guidelines

As an SP6122 application example, we will

use the circuit from the SP6122 Evaluation

Board Manual. This evaluation board uses

the Sipex SP6122ACU, 1.25V adjustable

PFET controller to realize a 3.3V to 1.9V

step down converter. The board is opti-

mized for 1A – 4A operation and has an

R_DS(ON)over current trip threshold of about

• Introduction to the “Buck Cad Calculator”

Spreadsheet

+3.3V

V

IN

C

IN

C1

47µF

+

4.7µF

Ceramic

1

8

7

6

5

PMOS

V

PDRV

GND

CC

Q1

®®

PDS6375

FFLAG

1

2

3

4

FFLAG

J1

RS

1.00k

SP6122

V

OUT

I

SET

2

2.2µH

+1.9V

V

OUT

ENABLE

V

OUT

ENABLE

I

SENSE

L1

CEN

4.7nF

R1

6.5k

+

3

DS

STPS2L25U

C

OUT

470µF

GND

R2

12.5k

Figure 1. SP6122 Evaluation Board Application Schematic

Data For Evaluation Board

The SP6122 is engineered for size and mini-

mum pin count, yet has a very accurate 2.0%

reference over line, load and temperature.

Figure 2 data shows a typical SP6122 Evalu-

ationBoardEfficiencyplot, withefficienciesto

88% and output currents to 4A. Load Regula-

tion plot in Figure 3 shows an essentially flat

response of only 3mV change for up to 4A

load. Figure 4 Line Regulation illustrates a

1.90V output that varies only 4mV or 0.2% for

an input voltage change from 3.0V to 5.5V.

While data on individual power supply boards

may vary, the capability of the SP6122 of

achieving high accuracy over load and line

shown here is quite impressive and desirable

for accurate power supply design.

89

88

87

86

85

84

83

0

1

2

3

4

5

I

(A)

LOAD

Figure 2. SP6122 Efficiency with V_IN= 3.3V,

V_OUT= 1.9V.

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

9

Data For Evaluation Board: continued

1.902

1.901

1.900

1.905

1.904

1.903

1

.

9

1.899

1.898

1.897

0

2

1.901

1.900

1.899

0

1

2

3

4

5

3

4

5

6

I

(A)

LOAD

I

(A)

LOAD

Figure 4. SP6122 Line Regulation with I_LOAD= 2A.

Figure 3. SP6122 Load Regulation with Input

Voltage = 3.3V.

Guidelines for Component Selection

GENERAL

cost, settheinductorripplecurrentbetween

20%to40%ofthemaximumoutputcurrent.

The SP6122 is a minimum on-time PFM

controller. This means there is no error amp

controlling the loop. Although an internal

algorithm adjusts the on-time approximate

the performance of a fixed frequency con-

troller, the loop control is generated by

looking at OUTPUT RIPPLE. The peak to

peak value of this output ripple must be no

less than 2% of the DC output voltage in

ordertomaintainreasonablefixedfrequency

operation. In addition, as with all PFM con-

trollers, board layout is critical and careful

attention must be paid to minimize paths

that can generate noise. Fortunately, the

SP6122isdesignedforsimplicityandminimal

external components, making it easy to de-

signsmall, quietpowerconvertersupto12W.

The inductor operating point and switching

frequency determine the inductor value as

seen in the following expression:

L = (V_OUT+ V_DIODE)*(V_IN– V_OUT)/

((V_IN+ V_DIODE)*( F_SK_RI_OUT(max)))

Where F_S= switching frequency (see Soft

Start Frequency Specification)

K_R= ratio of the ac inductor ripple current to

the maximum output current

V_{DIODE =}forward Schottky diode voltage

For an application with 1.9V out, 4A maxi-

mumI_OUT,3.3Vinputsupply,400mVtypical

forward diode voltage, 300kHz frequency

and a 30% inductor ripple current, a 2.2µH

inductor was selected (see Table 1 SP6122

Component Selection).

INDUCTOR SELECTION

In a SP6122 application, the main factors

for choosing an inductor are likely to be

cost, size, saturation current and efficiency.

If you use low inductor values, you get the

smallest size, but you may cause larger

ripple currents and poor efficiency and re-

quire more output capacitance to smooth

the output ripple. Increasing the inductor

valuewilldecreasetheoutputvoltageripple

but degrade the transient response. For a

goodcompromisebetweensize,lossesand

The peak to peak inductor ripple current is:

I_PP= (V_OUT+ V_DIODE)*(V_IN– V_OUT)/

((V_IN+ V_DIODE)*( F_SL))

For that same 2.2µH inductor application,

the I_PP= 1.32A.

The inductor must be selected to not satu-

rate the core at the peak inductor current:

I_PEAK= I_OUT(max)+ I_PP/2

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

10

Guidelines for Component Selection: continued

Again,forthatsame2.2µHapplication,I_PEAK

= 4.6A. Therefore, a 2.2µH inductor with at

least a 5A rating would be desired.

high switching frequencies because they

have low core losses as long as the satura-

tion current is avoided.

The type of core material to use must also

be determined. For low cost, powdered iron

cores can be used, and they have a gradual

saturationcharacteristic,buttheycancause

ac core loss when the inductor value is low

and ripple current is high. Ferrite cores, on

the other hand, have an abrupt saturation

characteristic and the inductor value drops

sharply when the peak design current is

exceeded. But, ferrites are preferred for

Table 1 lists examples of both shielded and

unshielded ferrite core inductors for applica-

tionsappropriateforSP6122applicationsfrom

2A to 5A output current. The inductors listed

are both shielded and unshielded, the cus-

tomer can decide what is needed for their

application.FortheSP6122EvaluationBoard,

theunshieldedferriteinductor2.2µHCoilcraft

DO3316P-222 was selected for its cost/per-

formance features.

INDUCTORS - SURFACE MOUNT Note: Components highlighted in bold are those used on the SP6122 Evaluation Board.

INDUCTOR SPECIFICATION

Inductance

Manufacturer/

Part No.

Series R

Isat

(A)

Size LxWxH

(mm)

Manufacturer

Website

(µH)

(Ω)

Inductor Type

1.5

Coilcraft DO3316P-152

0.010

0.012

0.015

0.006

0.008

0.010

0.019

0.024

0.029

8.0

7.0

6.4

10.0

7.5

6.0

3.7

3.2

2.7

12.9x9.4x5.0

10x10x3.8

Unshielded Ferrite Core

Shielded Ferrite Core

Unshielded Ferrite Core

www.coilcraft.com

www.sumida.com

www.murata.com

2.2 Coilcraft DO3316P-222

3.3 Coilcraft DO3316P-332

1.5 Sumida CDRH104R-1R5

2.5 Sumida CDRH104R-2R5

3.8 Sumida CDRH104R-3R8

10x10x3.8

1.5

2.2

3.3

Murata LQN6C1R5M04

Murata LQN6C2R2M04

Murata LQN6C3R3M04

5.0x5.7x4.7

CAPACITORS - SURFACE MOUNT & THROUGH HOLE Note: Components highlighted in bold are those used on the SP6122 Evaluation Board.

CAPACITOR SPECIFICATION

Capacitance

Manufacturer/

Part No.

ESR

Ripple Current

Size LxWxH

(mm)

Voltage

(V)

Capacitor

Type

Manufacturer

Website

( )

µF

Ω (max)

(A) @ 25°C

470

47

SANYO 6TPB470M

0.035

3.0

4.0

2.7

7343H

1812

10.0 SMT Tant.

6.3 SMT X5R Cer.

10.0 SMT X5R Cer.

www.sanyovideo.com

www.tdk.com

TDK C4532X5R0J476M 0.005

4.7 TDK C3216X5R1C475M 0.020

100 SANYO 16SA100M 0.030

1206

www.tdk.com

8Dx10L

16.0Thru-hole OS-CON www.sanyovideo.com

PMOS SWITCH - SURFACE MOUNT Note: Components highlighted in bold are those used on the SP6122 Evaluation Board.

PMOS SPECIFICATION

R_DS(ON)

Gate Charge

nc @ 3.3V

Crss

(pF)

Id (max)

(A)

Package

Type

Manufacturer

Website

Manufacturer/Part No.

Fairchild PDS6375

Siliconix SI4463DY

Intersil ITF86172SK8T

Ω @ 3.3V

0.022

0.015

0.023

15

34

17

300

800

400

8

10

8

SO-8

www.fairchildsemi.com

www.siliconix.com

www.intersil.com

SCHOTTKY DIODE - SURFACE MOUNT Note: Components highlighted in bold are those used on the SP6122 Evaluation Board.

DIODE SPECIFICATION

V

I_F(AV)

(A)

Size LxWxH Reverse V

Package

Type

Manufacturer

Website

F @ IF

Manufacturer/Part No.

STMicro STPS2L25U

On-Semi MBRD835L

(V)

(mm)

(V)

25

35

0.50

4.0

5.5x3.9x2.5

9.4x6.7x2.3

SMB

www.st.com

8.0

DPAK

www.onsemi.com

Table 1: SP6122 Component Selection

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

11

Guidelines for Component Selection: continued

The copper loss in the inductor can be

calculated from the equation:

waveform. For a 1.9V output voltage, the

required ripple is a reasonable 38 mV. The

designer must chose all other trade-offs

wisely to maintain this ripple

2

P_L(Cu)=I_L(RMS)

R_WINDING≅I_OUT(max)R_WINDING

For the 2.2µH example with 0.012Ω ESR in

the winding, 4A load and 1.9V output, the

copper loss in the inductor is 190mW.

0.02 * V_OUT< I_PP* R_ESR

and

∆I_LOAD* R_ESR< ∆V_TOL

OUTPUT CAPACITOR SELECTION

where:

The output capacitor is typically selected

based on its ability to maintain the output

within specified tolerance limits during load

transients. During an output load transient,

the output capacitor must supply all the

additional current demanded by the load

until the SP6122 adjusts the inductor cur-

rent to the new value. Therefore the capaci-

tance must be large enough so that the

output voltage is held up while the inductor

current ramps up or down to the value

corresponding to the new load current. For

power converters delivering greater than

1A at less than 1MHz switching frequency,

the output capacitor is typically greater than

100µF. Typically, tantalum and OSCON

capacitors are used to get high output ca-

pacitance in a small space. These capaci-

tors have a high Equivalent Series Resis-

tance (ESR) when compared to ceramic

capacitors and this ESR is both a curse and

ablessing. Unfortunately, theESR(Equiva-

lent Series Resistance) in the output ca-

pacitor causes a step in the output voltage

equal to the ESR value multiplied by the

change in load current. As a result, in a

power supply using a tantalum, aluminum

electrolytics or OSCON output capacitor,

the value of output capacitance (or number

of output capacitors) is typically chosen to

minimize the output variation due to the

load step imposed on this ESR. However,

the SP6122 takes advantage of the natural

presence of this ESR to control the loop.

Because the inductor ripple current also

flows through this ESR, and output ripple

voltage is created and the waveform is

resembles a miniature current-mode timing

V_OUT= DC output voltage

R_ESR= ESR of the output capacitor

DI_LOAD= change in current due to load

step

DV_TOL= tolerable deviation due to load

transient

I_PP= peak to peak inductor ripple current

Output ripple is due primarily to the output

ripple current and the output capacitor ESR

value as seen in the following equation:

∆V_OUT≅ I_PPR_ESR

For our SP6122 evaluation board example

with ESR = 35mΩ and I_PP= 1.32A, ∆V_OUT

=

46mV. Note that a 4A step creates a 140mV

deviation. If this is unacceptable, ESR and

I_PPmust be reconsidered in order to im-

prove step response and maintain output

ripple.

Recommendedcapacitorsthatcanbeused

effectively in SP6122 applications are: low-

ESR aluminum electrolytic capacitors,

OSCON capacitors that provide a very high

performance/size ratio for electrolytic ca-

pacitors and low-ESR tantalum capacitors.

AVX TPS series and Kemet T510 surface

mount capacitors are popular tantalum ca-

pacitors that work well in SP6122 applica-

tions. POSCAP from Sanyo is a solid elec-

trolytic chip capacitor that has low ESR and

high capacitance. For the same ESR value,

POSCAP has lower profile compared with a

tantalum capacitor.

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

12

Guidelines for Component Selection: continued

INPUT CAPACITOR SELECTION

age derating to protect the input capacitors

from surge fall-out.

The input capacitor should be selected for

ripple current rating, capacitance and volt-

age rating. The input capacitor must meet

the ripple current requirement imposed by

the switching current. In continuous con-

duction mode, the source current of the

high-side MOSFET is approximately a

square wave of duty cycle V_OUT/V_IN. Most of

this current is supplied by the input bypass

capacitors. The RMS value of input capaci-

tor current is determined at the maximum

output current and under the assumption

that the peak to peak inductor ripple current

is low, it is given by:

For accurate control it is important to keep

ripple voltages on Vin to a minimum. Vin

powers the SP6122 and its internal refer-

ence used to maintain output regulation, so

proper input bypassing is critical to reduce

referencenoise. Withareferencecompara-

tor internal hysteresis of 5mV, and a 1.25V

reference voltage, noise on the V_CCof the

I_CCshould be kept to about 20mV or less to

reduce reference noise effect on output

regulation.

The use of very low ESR capacitors is recom-

mendedforVinbypassing, throughtheuseof

parallel combinations of tantalum capacitors

or even better using some of the new large

valued multi-layer ceramic capacitors. ESR

valuesaslowas0.005Ω canbeobtainedwith

a 47µF ceramic (see table 1 capacitor selec-

tion)andtheseceramiccapacitorswillreduce

thepowerlossintheinputcapacitancegreatly

by their reduced ESR values.

I_CIN(RMS)= I_OUT(MAX)√ D(1-D)

The worse case occurs when the duty cycle

D is 50% and gives an RMS current value

equal to I_OUT/2. Select input capacitors with

adequate ripple current rating to ensure

reliable operation. The power dissipated in

the input capacitor is:

2

P_CIN= I_{CIN (RMS)}R_ESR(CIN)

For the SP6122 example using the 47µF

ceramic input capacitor, the P_CIN= 20mW,

which is very efficient, and the input ripple

voltage at the V_INpost (not the V_CCpin of the

IC) is about 90mV.

This can become a significant part of power

losses in a converter and hurt the overall

energy transfer efficiency. The input volt-

age ripple primarily depends on

the input capacitor ESR and capacitance.

Ignoring the inductor ripple current, the in-

put voltage ripple can be determined by:

MOSFET SELECTION

A SP6122 design uses a PMOS switch on

the high side, without the need for a high

side charge pump, simplifying the applica-

tion circuit. The losses associated with the

PMOS can be divided into conduction and

switching losses. Conduction losses are

related to the on resistance of the PMOS,

and increase with the load current. Switch-

ing losses occur on each on/off transition

when the PMOS experiences both high

current and voltage. The switching losses

are difficult to quantify due to all the vari-

ables affecting turnon/turnoff time. How-

ever, the following equation provides an

approximation on the switching losses as-

sociated with the PMOS driven by SP6122.

∆V_IN= I_{OUT (MAX)}R_ESR(CIN)

I_OUT(MAX)V_OUT(V_IN- V_OUT)/( F_SC_INV_IN

+

2

)

The capacitor type suitable for the output

capacitors can also be used for the input

capacitors. However, exercise extra cau-

tion when tantalum capacitors are consid-

ered. Tantalum capacitors are known for

catastrophic failure when exposed to surge

current, and input capacitors are prone to

such surge current when power supplies

areconnected‘live’tolowimpedancepower

sources. Certain tantalum capacitors, such

as AVX TPS series, are surge tested. For

generic tantalum capacitors, use 2:1 volt-

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

13

Guidelines for Component Selection: continued

_SH(MAX)≅ 1/2 I_OUT(MAX)V_IN(MAX)(t_{RISE + FALL})F_S

P

t

Thermal calculation must be conducted to

ensure the MOSFET can handle the maxi-

mum load current. The junction tempera-

tureoftheMOSFET, determinedasfollows,

must stay below the maximum rating.

where t_RISE(SP6122) for 8A PMOS is typi-

cally 20ns and t_FALL(SP6122) for 8A PMOS

is typically 40ns.

Switching losses need to be taken into

account for high switching frequency, since

they are directly proportional to switching

frequency. The conduction losses associ-

ated with the PMOS is determined by:

T_J(MAX)= T_{A (MAX)}+ P_MOSFET(MAX)Rθ_JA

where

T_{A (MAX)}= maximum ambient temperature

P_MOSFET(MAX)= maximum power dissipation

of the MOSFET, including both switching

and conduction losses

2

P_CH(MAX)= I_{OUT (MAX)}R_DS(ON)

D

Where R_DS(ON)= drain to source on resis-

tance.

Rθ_JA= junction to ambient thermal resistance.

The total power losses of the PMOS are the

sum of switching and conduction losses.

For input voltages of 3.3V and 5V, conduc-

tionlossesoftendominateswitchinglosses.

Therefore,loweringtheR_DS(ON)ofthePMOS

always improves efficiency even though it

gives rise to higher switching losses due to

Rθ_JAof the device depends greatly on the

board layout, as well as device package.

Significant thermal improvement can be

achievedinthemaximumpowerdissipation

through the proper design of copper mount-

ing pads on the circuit board. For example,

in a SO-8 package, placing two 0.04 square

inches copper pad directly under the pack-

age, without occupying additional board

space, can increase the maximum power

from approximately 1 to 1.2W.

increased C_RSS

.

For the SP6122 design example, the

Fairchild PMOS PDS6375 was selected for

its low R_DS(ON)and good switching charac-

teristics including low gate charge at the

3.3V input. Using table 1 values for R_DS(ON)

and t_RISEand t_FALLfor the SP6122, we

calculate;

For the PMOS PDS6375, assuming T_{A (MAX)}

= 20°C, P_MOSFET(MAX)= P_SH(MAX)+ P_CH(MAX)

= 321mW, and assuming per PDS6375

2

data sheet, Rθ_JA= 50°C/W if using 0.5 in

pad of 2oz Cu,

P_SH(MAX)= 119mW and P_CH(MAX)= 203mW.

T_J(MAX)= 36°C

R_DS(ON)varies greatly with the gate driver

voltage.TheMOSFETvendorsoftenspecify

R_DS(ON)on multiple gate to source voltages

(V_GS), as well as provide typical curve of

R_DS(ON)versus V_GS. For 5V input, use the

R_DS(ON)specified at 4.5V V_GS. At the time of

this publication, vendors, such as Fairchild,

Siliconix and International Rectifier, have

started to specify R_DS(ON)at V_GSless than

3V. This has provided necessary data for

designsinwhichtheseMOSFETsaredriven

with 3.3V and made it possible to use

SP6122 in 3.3V only applications.

which is only a 16°C rise from ambient.

SCHOTTKY DIODE SELECTION

The schottky diode is selected for low for-

ward voltage, current capability and fast

switching speed. The average power dissi-

pation of the schottky diode is determined

by

P_DIODE= V_FI_OUT(1- D)

Where V_Fis the forward voltage of the

Schottky diode at I_OUT

.

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

14

Guidelines for Component Selection: continued

For the SP6122 example, the schottky

STPS2L25U has V_F= 0.5V for I_OUTof 4A,

The 1.5V version of SP6122 has built in

voltage divider that presets the output

voltage. Simply connect the V_OUTpin to the

power supply output for 1.5V regulation.

Due to the internal voltage divider, the

version of SP6122 sinks 23µA current at

the V_OUTpin. Consider this error term if a

resistor voltage divider is used.

the power loss in the schottky P_DIODE

848mW.

=

Note that this power dissipation is 2.5 times

greaterthantheMOSFET.Ifweassumethe

same thermal conductivity as the MOSFET

(according to the data sheets, this is close)

weshouldgeta40°CriseduetotheSchottky

diode alone. It is apparent that due to the

proximity of all the components involved

that the board temperature is higher than

ambient and this temperature rise must be

considered when attempting to protect the

power converter.

SOFT START

The SP6122 has a built-in soft start feature

that automatically limits the inrush currents

to reasonable levels for most power sup-

plies. For our 1.9V example, the inrush cur-

rent on start up is:

I_INRUSH= 470µF * 0.5V/ms * 1.9V/1.25V

= 357mA

Features and Protection

This extra current must be factored in when

calculating over current margins.

PROGRAMMING THE SP6122 OUTPUT

VOLTAGE

LOCK-UP AND HICCUP MODES

For Applications requiring output other than

1.5V, the 1.25V adjustable version is

recommended. The output voltage can be

programmed through a simple voltage

divider shown in Figure 5. The set point for

the output voltage can be determined by

Basically, when the SP6122 sees an over

current fault, the part can react in two ways.

If the FFLAG is not tied to ENABLE, the part

will put the driver into a low impedance state

to the high rail during a fault. The ENABLE

pin must be manually cycled to remove the

fault. This mode is useful when power sup-

ply sequencing and system fault manage-

ment is complex. If the FFLAG pin is tied to

ENABLE, then a ‘hiccup’ time can be de-

signed by adding a capacitor from ENABLE

to ground. The 4µA ENABLE pin charge

current acts as a timer. The driver will be put

into a low impedance state to the high rail for

a certain amount of time.

1.25 (R1 + R2)

V_OUT

=

R2

Select R1 and R2 in the range from 1k to

100k.

V

OUT

®

R1

Vb

SP6122

Pin 3

T_OFF= C_ENABLE* 1.21V/5µA

R

IN1

R2

ForC_ENABLE=4.7nF, thistimeequals1.3ms.

This represents a ‘cool off’ time required for

the power supply to cycle and see if the fault

has been removed. This mode is useful for

shorttermfaultsorinsinglesupplysystems.

Va

–

+

Error

Amplifier

+

–

1.25V

Figure 5: Schematic: Output Voltage Divider Resistors

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

15

Layout Guidelines

Features and Protection: continued

PCB layout plays a critical role in proper

function of the converters and EMI control.

In switch mode power supplies, loops carry-

ing high di/dt give rise to EMI and ground

bounce. The goal of layout optimization is to

identify these loops and minimize them. It is

also crucial on how to connect the controller

groundsuchthatitsoperationisnotaffected

bynoise. Thefollowingguidelinesshouldbe

followed to ensure proper operation.

R_DS(ON)OVER CURRENT PROTECTION

Fault conditions are detected via an over

voltage condition across the PMOS switch

during conduction. This is commonly known

as R_DS(ON)sensing. R_DS(ON)sensing is inac-

curate but efficient and is used where an

indicatorofovercurrentbehaviorisrequired

for protection. Two advanced features are

incorporated in the SP6122 R_DS(ON)sensing

scheme. The sensing environment is very

noisy. Typical schemes require some exter-

nal filtering in order to avoid spurious faults

due to noise or load transients, often com-

promising the protection and performance

at low duty ratios. The SP6122 incorporates

a 10µs internal sample and hold filter after

the main sense comparator. In this fashion,

small pulse widths can be detected while

maintaining adequate filtering against false

glitches. In addition, temperature compen-

sation is added such that the over current

detection threshold at any temperature can

be calculated with reasonable accuracy at

room temperature. For our evaluation board

example:

1. A ground plane is recommended for

minimizing noises, copper losses and

maximizing heat dissipation.

2. Connect the ground of the feedback

divider to the GND pin of the IC. Then

connect this pin as close as possible to

the ground of the output capacitor.

3. The Vcc bypass capacitor should be right

next to the Vcc and GND pins.

4. The traces connecting to the feedback

resistorsandcurrentsensecomponents

should be short and far away from the

switch node and switching components.

5. Minimize the trace length/maximize the

trace width between the PDRV pin and

the gate of the PMOS.

I_TRIP= (150mV + I_SETR_SET)/R_DS(ON)

=

(150mV + 20µA*1kΩ)/25mΩ = 6.8A

6. Minimize the loop composed of input

capacitors, PMOS and Schottky diode,

as this loop carries high di/dt current.

Also increase the trace width to reduce

copper losses.

This is the about the same trip threshold at

room, hot or cold because a temperature

coefficienthasbeenaddedtoboththe150mV

andthe20µAsetcurrents. Thistemperature

coefficient tracks the 25mΩ R_DS(ON)of the

external FET. Due to the small size of these

power supplies, thermal coupling exists be-

tween the PFET and the SP6122, making

this thermal compensation reasonable, but

not perfect. Notice there is about a 50% pad

between the maximum usable current (5A)

and the over current trip threshold (7A) in

order to accommodate PFET and overall

system variation.

7. Maximize the trace width of the loop

connecting the inductor, output capaci-

tors, and Schottky diode.

8. For an layout example of an SP6122

powersupply(3.3Vinand1.9Voutat4A)

see the SP6122 Evaluation Board

Manual.

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

16

SP6122 Design Calculator Example: Evaluation Board with 3.3V_IN, 1.9V_OUT

Table 2, SP6122 Design Calculator, illus-

trates the calculations and formulas con-

tained in the Sipex Non-Synchronous Buck

Cad Calculator spreadsheet, (available in

theapplicationssectionoftheSipexwebsite

at www.sipex.com). The example shown is

the same SP6122 Evaluation Board used

previously with V_IN= 3.3V, V_OUT= 1.9V at

4A. As you can see, the SP6122 efficiency

at 4A output is calculated to be 84.3%.

Compare this with the Typical Performance

Characteristics curve of 84.5%, which is

very close considering the tolerances of

various components, and you see how use-

ful this easy design calculator is to evaluate

your SP6122 designs.

SP6122 Non-Synchronous Buck Design Calculator

STEADY STATE CALCULATION

Enter Values

_IN= Input Voltage (V)

_OUT= Output Voltage (V)

Calculation Results

3.3 D = Duty Cycle

Formula

V

0.58 = V_OUT/V

IN

V

1.9 Iripple = Ripple Current (A)

1.22 = (V -V_OUT)*V_OUT/(Fs*1000*L*0.000001*V )

IN

Fs = Switching Frequency (kHz)

I_OUT= Load Current (A)

300 Ipeak = Peak Inductor Current (A)

4.61 = I_OUT+Iripple/2

4

Output Ripple (mV)

2.2 Iin = Max Input Current (A)

Max Input Ripple (mV)

42.75 = Iripple*ESRout

2.56 = I_OUT*D/0.9

L = Inductance (µH)

ESRin = Input Capacitor ESR (mΩ)

5

96.99 = I_OUT*ESRin+Iin*(1-D)/(Fs*C *0.000001)

IN

C_IN= Input Capacitance (µF)

47 Iin_rms = Input Cap RMS Current (A)

1.98 = I_OUT*SQRT(D*(1-D))

ESR_OUT= Output Capacitor ESR (Ω)

35

EFFICIENCY CALCULATION

Enter Values

Calculation Results

Formula

RGH = GH Impedance (Ω)

PMOS

4

Pic = IC Power (switching) (mW)

31.35 = Icc*V +Chs*V *Fs*0.001

IN

T_RISE= SP6122 typ. PMOS rise time (ns) 20 Psch = Schottky Conducting Loss (mw) 848.48 = Vf*I_OUT*(1-D)*1000

T_FALL= SP6122 typ. PMOS rise time (ns) 40

Chs = PMOS Gate Charge @ V_IN(nc)

15 Pch = PMOS Conducting Loss (mW)

22 Psh = PMOS Switching Loss (mW)

Phs = Total PMOS Loss (mW)

202.67 = I_OUT*I_OUT*D*Rhs

Rhs = R_DS(ON)@ V_IN(mΩ)

118.80 = 1/2*I_OUT*V *(T_RISE+T_FALL)*Fs*0.001

IN

321.47 = Pch + Psh

Vf = Schottky Forward Voltage

I_CC= Supply Current (no switch) (mA)

ESR_L = Inductor ESR (mΩ)

0.5 Pl = Inductor loss (mW)

192.00 = I_OUT*I_OUT*ESR_L

19.54 = ESR_IN*Iin_rms*Iin_rms

1412.84 = Pic+Pls+Phs+Pl+Psch

5

Pc_IN= Input Capacitor Loss(mW)

12 Pltot = Total Power Losses (mW)

Efficiency (%)

84.32 = V_OUT*I_OUT/(V_OUT*I_OUT- Pltot/1000)*100

Table 2: Design Calculator

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

17

PACKAGE: 8 PIN MSOP

D

e1

Ø1

E/2

R1

R

E1

E

Gauge Plane

L2

Ø

Ø1

Seating Plane

L

L1

1

2

e

Pin #1 indentifier must be indicated within this shaded area (D/2 * E1/2)

8-PIN MSOP

JEDEC MO-187

(AA) Variation

Dimensions in (mm)

B

MIN NOM MAX

-

1.10

0.15

A

0

-

A1

A2

b

0.75 0.85 0.95

0.22

0.08

-

0.38

0.23

c

-

A2

A

D

E

3.00BSC

4.90BSC

b

A1

WITH PLATING

E1

3.00 BSC

0.65 BSC

1.95 BSC

e

(b)

e1

L

0.40 0.60 0.80

0.95 REF

L1

L2

N

0.25 BSC

c

-

0.07

0º

8

-

R

-

R1

Ø

-

Section B-B

8º

15º

BASE METAL

Ø1

0º

1

8-PIN MSOP

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

18

ORDERING INFORMATION

Operating Temperature Range

Part Number

Package Type

SP6122ACU.............................................. 0°C to 70°C ............................................. 8 Pin MSOP

SP6122ACU/TR ........................................ 0°C to 70°C ............................................ 8 Pin MSOP

SP6122ACU-1.5 ....................................... 0°C to 70°C ............................................. 8 Pin MSOP

SP6122ACU-1.5/TR.................................. 0°C to 70°C ............................................ 8 Pin MSOP

Available in lead free packaging. To order add “-L” suffix to part number.

Example: SP6122ACU-1.5/TR = standard; SP6122ACU-L-1.5/TR = lead free

/TR = Tape and Reel

Pack quantity is 2,500 for MSOP.

Corporation

ANALOG EXCELLENCE

Sipex CorporationHeadquarters

233 South Hillview Drive

Milpitas, CA 95035

TEL: (408) 934-7500

FAX: (408) 935-7600

Sipex Corporation reserves the right to make changes to any products described herein. Sipex does not assume any liability arising out of the

application or use of any product or circuit described herein; neither does it convey any license under its patent rights nor the rights of others.

Date: 10/02/04

SP6122 Low Voltage, Micro 8, PFET, Buck Controller

19


型号：	SP6122ACU-L-1.5
厂家：	EXAR CORPORATION
描述：	Switching Controller, Current-mode, 2A, 390kHz Switching Freq-Max, PDSO8, LEAD FREE, MO-187AA, MSOP-8 光电二极管
文件：	总19页 (文件大小：162K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

SP6122ACU-L-1.5 [EXAR]

相关型号：

SP6122ACU-L-1.5/TR

SP6122ACU-L-1.5/TR

SP6122ACU-L/TR

SP6122ACU/TR

SP6122CU

SP6122CUA-1.5-L/TR

SP6122CUA-1.8

SP6122CUA-2.5-L/TR

SP6122CUA-3.3

SP6122CUA-3.3-L/TR

SP6122CUA-3.3/TR

SP6122CUA-L-1.5