ST16C454IJ68-F_技术文档

ST16C454

QUAD UNIVERSAL ASYNCHRONOUS

RECEIVER/TRANSMITTER (UART)

DESCRIPTION

PLCC Package

The ST16C454 is a universal asynchronous receiver

and transmitter (UART) with a dual foot print interface.

The 454 is an enhanced UART with data rates up to

1.5Mbps and software compatible to ST16C450.

Onboard status registers provide the user with error

indications, operational status, and modem interface

control.Systeminterruptsmaybetailoredtomeetuser

requirements. An internal loop-back capability allows

onboarddiagnostics.TheST16C454offeranadditional

68 mode which allows easy integration with Motorola,

andotherpopularmicroprocessors.The454combines

the package interface modes of the ST16C454 on a

single integrated chip with a selection pin.

-DSRA 10

60 -DSRD

59 -CTSD

58 -DTRD

57 GND

56 -RTSD

55 INTD

54 -CSD

53 TXD

-CTSA 11

-DTRA 12

VCC 13

-RTSA 14

INTA 15

-CSA 16

TXA 17

ST16C454CJ68

16 MODE

-IOW 18

TXB 19

52 -IOR

51 TXC

-CSB 20

INTB 21

-RTSB 22

GND 23

-DTRB 24

-CTSB 25

-DSRB 26

50 -CSC

49 INTC

48 -RTSC

47 VCC

46 -DTRC

45 -CTSC

44 -DSRC

FEATURES

-DSRA 10

-CTSA 11

-DTRA 12

VCC 13

-RTSA 14

-IRQ 15

-CS 16

60 -DSRD

59 -CTSD

58 -DTRD

57 GND

56 -RTSD

55 N.C.

• Software compatibility with the Industry Standard

16C450

• 2.97 to 5.5 volt operation

• Intel or Motorola data bus interface select

• 1.5Mbpstransmit/receiveoperation(24MHz)

• Independent transmit and receive control

• Software selectable Baud Rate Generator

• Modem control signals (-CTS, -RTS, -DSR, -DTR,

-RI, -CD)

• Programmable character lengths (5, 6, 7, 8)

• Even, odd, ornoparitybitgenerationanddetection

• Internal loop-back diagnostics

54 N.C.

TXA 17

53 TXD

ST16C454CJ68

68 MODE

R/-W 18

TXB 19

52 N.C.

51 TXC

A3 20

50 A4

N.C. 21

49 N.C.

-RTSB 22

GND 23

-DTRB 24

-CTSB 25

-DSRB 26

48 -RTSC

47 VCC

46 -DTRC

45 -CTSC

44 -DSRC

• TTL compatible inputs, outputs

• Lowpower

ORDERING INFORMATION

Part number

ST16C454CJ68 68-Lead PLCC

ST16C454IJ68

Package

Operating temperature

0° C to + 70° C

-40° C to + 85° C

Device Status

Active

68-Lead PLCC

Rev. 3.31

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017

ST16C454

Figure 2, Block Diagram in 16 Mode

Transmit

Holding

Registers

Transmit

Shift

Register

TX A-D

D0-D7

-IOR

-IOW

RESET

Receive

Holding

Registers

Receive

Shift

Register

A0-A2

-CS A-D

RX A-D

INT A-D

INTSEL

-DTR A-D

-RTS A-D

Modem

Control

Logic

-CTS A-D

-RI A-D

-CD A-D

-DSR A-D

XTAL1

XTAL2

Rev. 3.31

2

ST16C454

Figure 3, Block Diagram in 68 Mode

Transmit

Holding

Registers

Transmit

Shift

Register

TX A-D

D0-D7

R/-W

-RESET

Receive

Holding

Registers

Receive

Shift

Register

A0-A4

-CS

RX A-D

-IRQ

-DTR A-D

-RTS A-D

Modem

Control

Logic

-CTS A-D

-RI A-D

-CD A-D

-DSR A-D

XTAL1

XTAL2

Rev. 3.31

3

ST16C454

SYMBOL DESCRIPTION

Symbol

Signal

type

Pin Description

16/-68

31

I

16/68InterfaceTypeSelect(inputwithinternalpull-up).-Thisinput

providesthe16(Intel)or68(Motorola)businterfacetypeselect.The

functionsof-IOR,-IOW,INTA-D,and-CSA-Darere-assignedwith

the logical state of this pin. When this pin is a logic 1, the 16 mode

interface ST16C454 is selected. When this pin is a logic 0, the 68

mode interface (ST68C454) is selected. When this pin is a logic 0,

-IOW is re-assigned to R/-W, RESET is re-assigned to -RESET, -

IOR is not used, and INT A-D(s) are connected in a WIRE-OR”

configuration.TheWIRE-ORoutputsareconnectedinternallytothe

open source IRQ signal output.

A0

34

33

I

Address-0SelectBit. Internalregistersaddressselectionin16and

68 modes.

A1

Address-1SelectBit. Internalregistersaddressselectionin16and

68 modes.

A2

32

Address-2 Select Bit. - Internal registers address selection in 16

and 68 modes.

A3-A4

20,50

Address 3-4 Select Bits. - When the 68 mode is selected, these

pins are used to address or select individual UART’s (providing -

CS is a logic 0). In the 16 mode, these pins are reassigned as chip

selects, see -CSB and -CSC.

-CS

16

I

Chip Select. (active low) - In the 68 mode, this pin functions as a

multiple channel chip enable. In this case, all four UART’s (A-D)

are enabled when the -CS pin is a logic 0. An individual UART

channel is selected by the data contents of address bits A3-A4.

When the 16 mode is selected, this pin functions as -CSA, see

definition under -CS A-B.

-CS A-B

-CS C-D

16,20

50,54

I

Chip Select A, B, C, D (active low) - This function is associated with

the 16 mode only, and for individual channels, “A” through “D.”

When in 16 Mode, these pins enable data transfers between the

user CPU and the ST16C454 for the channel(s) addressed.

Individual UART sections (A, B, C, D) are addressed by providing

a logic 0 on the respective -CS A-D pin. When the 68 mode is

selected, the functions of these pins are reassigned. 68 mode

functions are described under the their respective name/pin

headings.

Rev. 3.31

4

ST16C454

SYMBOL DESCRIPTION

Symbol

Signal

type

Pin Description

D0-D2

D3-D7

66-68

1-5

I/O

Data Bus (Bi-directional) - These pins are the eight bit, three state

databusfortransferringinformationtoorfromthecontrollingCPU.

D0 is the least significant bit and the first data bit in a transmit or

receive serial data stream.

GND

6,23

40,57

Pwr

O

Signal and power ground.

INT A-B

INT C-D

15,21

49,55

Interrupt A, B, C, D (active high) - This function is associated with

the 16 mode only. These pins provide individual channel inter-

rupts, INT A-D. INT A-D are enabled when MCR bit-3 is set to a

logic1, interruptsareenabledintheinterruptenableregister(IER),

and when an interrupt condition exists. Interrupt conditions in-

clude: receiver errors, available receiver buffer data, transmit

buffer empty, or when a modem status flag is detected. When the

68 mode is selected, the functions of these pins are reassigned. 68

mode functions are described under the their respective name/pin

headings.

INTSEL

65

I

Interrupt Select. (active high, with internal pull-down) - This

function is associated with the 16 mode only. When the 16 mode

is selected, this pin can be used in conjunction with MCR bit-3 to

enable or disable the three state interrupts, INT A-D or override

MCR bit-3 and force continuous interrupts. Interrupt outputs are

enabled continuously by making this pin a logic 1. Making this pin

alogic0allowsMCRbit-3tocontrolthethreestateinterruptoutput.

In this mode, MCR bit-3 is set to a logic “1” to enable the three state

outputs. This pin is disabled in the 68 mode.

-IOR

52

18

I

Read strobe. (active low Strobe) - This function is associated with

the 16 mode only. A logic 0 transition on this pin will load the

contents of an Internal register defined by address bits A0-A2 onto

the ST16C454 data bus (D0-D7) for access by an external CPU.

This pin is disabled in the 68 mode.

-IOW

Write strobe. (active low strobe) - This function is associated with

the 16 mode only. A logic 0 transition on this pin will transfer the

contents of the data bus (D0-D7) from the external CPU to an

internal register that is defined by address bits A0-A2. When the

16modeisselected,thispinfunctionsasR/-W,seedefinitionunder

Rev. 3.31

5

ST16C454

SYMBOL DESCRIPTION

Symbol

Signal

type

Pin Description

R/-W.

-IRQ

15

O

InterruptRequestorInterrupt“A”-Thisfunctionisassociatedwiththe

68 mode only. In the 68 mode, interrupts from UART channels A-D

areWIRE-OR’ed”internallytofunctionasasingleIRQinterrupt.This

pintransitionstoalogic0(ifenabledbytheinterruptenableregister)

whenever a UART channel(s) requires service. Individual channel

interrupt status can be determined by addressing each channel

throughitsassociatedinternalregister,using-CSandA3-A4.Inthe

68modeanexternalpull-upresistormustbeconnectedbetweenthis

pinandVCC.ThefunctionofthispinchangestoINTAwhenoperating

in the 16 mode, see definition under INTA.

-RESET

RESET

37

18

I

Reset. - In the 16 mode a logic 1 on this pin will reset the internal

registers and all the outputs. The UART transmitter output and the

receiver input will be disabled during reset time. (See ST16C454

External Reset Conditions for initialization details.) When 16/-68

isalogic0(68mode), thispinfunctionssimilarlybut, asaninverted

reset interface signal, -RESET.

R/-W

Read/Write Strobe (active low) - This function is associated with

the 68 mode only. This pin provides the combined functions for

Read or Write strobes. A logic 1 to 0 transition transfers the

contents of the CPU data bus (D0-D7) to the register selected by

-CS and A0-A4. Similarly a logic 0 to 1 transition places the

contents of a 454 register selected by -CS and A0-A4 on the data

bus, D0-D7, for transfer to an external CPU.

VCC

13

47,64

I

Power supply inputs.

XTAL1

35

Crystal or External Clock Input - Functions as a crystal input or as

an external clock input. A crystal can be connected between this

pin and XTAL2 to form an internal oscillator circuit (see figure 8).

Alternatively, an external clock can be connected to this pin to

provide custom data rates (see Baud Rate Generator Program-

ming).

XTAL2

36

O

Output of the Crystal Oscillator or Buffered Clock - (See also

XTAL1). Crystal oscillator output or buffered clock output.

Rev. 3.31

6

ST16C454

SYMBOL DESCRIPTION

Symbol

Signal

type

Pin Description

-CDA-B

9,27

-CDC-D

43,61

I

Carrier Detect (active low) - These inputs are associated with

individualUARTchannelsAthroughD.Alogic0onthispinindicates

that a carrier has been detected by the modem for that channel.

-CTS A-B

-CTS C-D

11,25

45,59

I

Clear to Send (active low) - These inputs are associated with

individual UART channels, A through D. A logic 0 on the -CTS pin

indicates the modem or data set is ready to accept transmit data

from the 454. Status can be tested by reading MSR bit-4.

-DSR A-B

-DSR C-D

10,26

44,60

I

Data Set Ready (active low) - These inputs are associated with

individual UART channels, A through D. A logic 0 on this pin

indicates the modem or data set is powered-on and is ready for

data exchange with the UART. This pin has no effect on the

UART’s transmit or receive operation. This pin has no effect on the

UART’s transmit or receive operation.

-DTR A-B

-DTR C-D

12,24

46,58

O

Data Terminal Ready (active low) - These inputs are associated

with individual UART channels, A through D. A logic 0 on this pin

indicates that the 454 is powered-on and ready. This pin can be

controlled via the modem control register. Writing a logic 1 to MCR

bit-0 will set the -DTR output to logic 0, enabling the modem. This

pin will be a logic 1 after writing a logic 0 to MCR bit-0. This pin has

no effect on the UART’s transmit or receive operation.

-RI A-B

-RI C-D

8,28

42,62

I

Ring Indicator (active low) - These inputs are associated with

individual UART channels, A through D. A logic 0 on this pin

indicates the modem has received a ringing signal from the

telephone line. A logic 1 transition on this input pin will generate an

interrupt.

-RTS A-B

-RTS C-D

14,22

48,56

O

Request to Send (active low) - These outputs are associated with

individual UART channels, A through D. A logic 0 on the -RTS pin

indicates the transmitter has data ready and waiting to send.

Writing a logic 1 in the modem control register (MCR bit-1) will set

this pin to a logic 0 indicating data is available. After a reset this pin

willbesettoalogic1. ThispinhasnoeffectontheUART’stransmit

Rev. 3.31

7

ST16C454

SYMBOL DESCRIPTION

Symbol

Signal

type

Pin Description

orreceiveoperation.

RXA-B

7,29

RX C-D

41,63

I

Receive Data Input RX A-D. - These inputs are associated with

individual serial channel data to the ST16C454. The RX signal will

be a logic 1 during reset, idle (no data), or when the transmitter is

disabled. During the local loop-back mode, the RX input pin is

disabledandTXdataisinternallyconnectedtotheUARTRXInput,

internally.

TX A-B

TX C-D

17,19

51,53

O

TransmitData-Theseoutputsareassociatedwithindividualserial

transmit channel data from the 454. The TX signal will be a logic

1 during reset, idle (no data), or when the transmitter is disabled.

During the local loop-back mode, the TX input pin is disabled and

TX data is internally connected to the UART RX Input.

Rev. 3.31

8

ST16C454

GENERALDESCRIPTION

The 16 Mode Interface

The16modeconfiguresthepackageinterfacepinsfor

connection as a standard 16 series (Intel) device and

operates similar to the standard CPU interface avail-

ableontheST16C454.Inthe16mode(pin16/-68logic

1) each UART is selected with individual chip select (-

CSx) pins as shown in Table 2 below.

The 454 provides serial asynchronous receive data

synchronization,parallel-to-serialandserial-to-parallel

data conversions for both the transmitter and receiver

sections.Thesefunctionsarenecessaryforconverting

the serial data stream into parallel data that is required

withdigitaldatasystems.Synchronizationfortheserial

datastreamisaccomplishedbyaddingstartandstops

bits to the transmit data to form a data character

(characterorientatedprotocol).Dataintegrityisinsured

byattachingaparitybittothedatacharacter.Theparity

bit is checked by the receiver for any transmission bit

errors. The electronic circuitry to provide all these

functions is fairly complex especially when manufac-

turedonasingleintegratedsiliconchip.TheST16C454

represents such an integration with greatly enhanced

features.The454isfabricatedwithanadvancedCMOS

process to achieve low drain power and high speed

requirements.

Table 2, SERIAL PORT CHANNEL SELECTION

GUIDE, 16 MODE INTERFACE

-CSA -CSB -CSC -CSD

UART

CHANNEL

1

0

1

0

1

0

1

0

None

A

B

C

D

The454combinesthepackageinterfacemodesofthe

ST16C454 and ST68C454 series on a single inte-

grated chip. The 16 mode interface is designed to

operatewiththeInteltypeofmicroprocessorbuswhile

the 68 mode is intended to operate with Motorola, and

other popular microprocessors.

The 68 Mode Interface

The68modeconfiguresthepackageinterfacepinsfor

connection with Motorola, and other popular micro-

processor bus types. The interface operates similar to

the ST68C454. In this mode the 454 decodes two

additional addresses, A3-A4 to select one of the four

UART ports. The A3-A4 address decode function is

used only when in the 68 mode (16/-68 logic 0), and is

shown in Table 3 below.

The 454 is capable of operation to 1.5Mbps with a 24

MHz crystal or external clock input. With a crystal of

14.7464 MHz, the user can select data rates up to

921.6Kbps.

Table 3, SERIAL PORT CHANNEL SELECTION

GUIDE, 68 MODE INTERFACE

The rich feature set of the 454 is available through

internal registers. Selectable TX and RX baud rates,

modem interface controls. In the 16 mode INTSEL

andMCRbit-3canbeconfiguredtoprovideasoftware

controlled or continuous interrupt capability.

-CS

A4

A3

UART

CHANNEL

FUNCTIONAL DESCRIPTIONS

Interface Options

1

0

N/A

0

1

N/A

0

1

0

1

None

A

B

C

D

Two user interface modes are selectable for the 454

package. These interface modes are designated as

the “16 mode” and the “68 mode.” This nomenclature

corresponds to the early ST16C454 and ST68C454

package interfaces respectively.

Rev. 3.31

9

ST16C454

InternalRegisters

trolregisters(IER/ISR),linestatusandcontrolregisters

(LCR/LSR),modemstatusandcontrolregisters(MCR/

MSR),programmabledatarate(clock)controlregisters

(DLL/DLM),andauserassessablescratchpadregister

(SPR). Register functions are more fully described in

thefollowingparagraphs.

The454provides12internalregistersformonitoringand

control. These resisters are shown in Table 4 below.

Theseregistersaresimilartothosealreadyavailablein

thestandard16C450.Theseregistersfunctionasdata

holdingregisters(THR/RHR),interruptstatusandcon-

Table4,INTERNALREGISTERDECODE

A2

A1

A0

READMODE

WRITEMODE

General Register Set (THR/RHR, IER/ISR, MCR/MSR, LCR/LSR, SPR):

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Receive Holding Register

Interrupt Status Register

Transmit Holding Register

Interrupt Enable Register

Line Control Register

Modem Control Register

Line Status Register

Modem Status Register

Scratchpad Register

Baud Rate Register Set (DLL/DLM): Note *2

0

1

LSB of Divisor Latch

MSB of Divisor Latch

LSB of Divisor Latch

MSB of Divisor Latch

Note *2: These registers are accessible only when LCR bit-7 is set to a logic 1.

Rev. 3.31

10

ST16C454

between the XTAL1 and XTAL2 pins (see figure 8).

Alternatively,anexternalclockcanbeconnectedtothe

XTAL1 pin to clock the internal baud rate generator for

standard or custom rates. (see Baud Rate Generator

Programming).

Programmable Baud Rate Generator

The454supportshighspeedmodemtechnologiesthat

have increased input data rates by employing data

compression schemes. For example a 33.6Kbps mo-

dem that employs data compression may require a

115.2Kbpsinputdatarate. A128.0KbpsISDNmodem

thatsupportsdatacompressionmayneedaninputdata

rateof460.8Kbps.The454cansupportastandarddata

rateof921.6Kbps.

The generator divides the input 16X clock by any

divisorfrom1to2¹⁶-1.The454dividesthebasiccrystal

orexternalclockby16.Furtherdivisionofthis16Xclock

provides two table rates to support low and high data

rate applications using the same system design. Cus-

tomized Baud Rates can be achieved by selecting the

proper divisor values for the MSB and LSB sections of

baudrategenerator.

Single baud rate generator is provided for the trans-

mitter and receiver, allowing independent TX/RX

channel control. The programmable Baud Rate Gen-

erator is capable of accepting an input clock up to 24

MHz, as required for supporting a 1.5Mbps data rate.

The 454 can be configured for internal or external

clock operation. For internal clock oscillator opera-

tion, anindustrystandardmicroprocessorcrystal(par-

allel resonant/ 22-33 pF load) is connected externally

Programming the Baud Rate Generator Registers

DLM (MSB) and DLL (LSB) provides a user capability

for selecting the desired final baud rate. The example

in Table 5 below, shows the two selectable baud rate

tables available when using a 1.8432MHz or 7.3728

MHz crystal.

Output

User

DLM

Program

Value

DLL

Program

Value

Baud Rate Baud Rate 16 x Clock 16 x Clock

(1.8432MHz (7.3728MHz

Divisor

(Decimal)

Divisor

(HEX)

Clock)

(HEX)

50

300

600

200

1200

2400

4800

9600

19.2K

38.4k

76.8k

153.6k

230.4k

460.8k

2304

384

192

96

48

24

12

6

900

180

C0

60

30

18

0C

06

03

02

01

09

01

00

80

C0

60

30

18

0C

06

03

02

01

1200

2400

4800

9600

19.2k

38.4k

57.6k

115.2k

3

2

1

Rev. 3.31

11

ST16C454

Figure 8, Crystal oscillator connection

Loop-back Mode

The internal loop-back capability allows onboard diag-

nostics. In the loop-back mode the normal modem

interface pins are disconnected and reconfigured for

loop-backinternally.MCRregisterbits0-3areusedfor

controlling loop-back diagnostic testing. In the loop-

back mode OP1 and OP2 in the MCR register (bits 3/

2) control the modem -RI and -CD inputs respectively.

MCR signals -DTR and -RTS (bits 0-1) are used to

controlthemodem-CTSand-DSRinputsrespectively.

Thetransmitteroutput(TX)andthereceiverinput(RX)

are disconnected from their associated interface pins,

and instead are connected together internally (See

Figure 12). The -CTS, -DSR, -CD, and -RI are discon-

nected from their normal modem control inputs pins,

and instead are connected internally to -DTR, -RTS, -

OP1 and -OP2. Loop-back test data is entered into the

transmitholdingregisterviatheuserdatabusinterface,

D0-D7. The transmit UART serializes the data and

passes the serial data to the receive UART via the

internalloop-backconnection.ThereceiveUARTcon-

verts the serial data back into parallel data that is then

made available at the user data interface, D0-D7. The

useroptionallycomparesthereceiveddatatotheinitial

transmitteddataforverifyingerrorfreeoperationofthe

UARTTX/RXcircuits.

X1

1.8432 MHz

C1

22pF

C2

33pF

In this mode, the receiver and transmitter interrupts

are fully operational. The Modem Control Interrupts

are also operational. However, the interrupts can only

be read using lower four bits of the Modem Control

Register (MCR bits 0-3) instead of the four Modem

Status Register bits 4-7. The interrupts are still con-

trolled by the IER.

Rev. 3.31

12

ST16C454

Figure12,INTERNALLOOP-BACKMODEDIAGRAM

Transmit

Holding

Transmit

Shift

TX A-D

Registers

Register

D0-D7

-IOR,-IOW

RESET

Receive

Holding

Registers

Receive

Shift

Register

RX A-D

A0-A2

-CS A-D

-RTS A-D

-CD A-D

-DTR A-D

INT A-D

-RI A-D

(-OP1 A-D)

XTAL1

XTAL2

-DSR A-D

(-OP2 A-D)

-CTS A-D

Rev. 3.31

13

ST16C454

REGISTERFUNCTIONALDESCRIPTIONS

The following table delineates the assigned bit functions for the fifteen 454 internal registers. The assigned bit

functionsaremorefullydefinedinthefollowingparagraphs.

Table6,ST16C454INTERNALREGISTERS

A2 A1 A0

Register

[Default]

Note *5

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

General Register Set

0

1

RHR[XX]

THR[XX]

IER[00]

bit-7

0

bit-6

0

bit-5

0

bit-4

0

bit-3

bit-2

bit-1

bit-0

modem

status

interrupt

receive

line

status

interrupt

transmit

holding

register

receive

holding

register

0

1

0

1

0

1

ISR[01]

LCR[00]

MCR[00]

LSR[60]

0

INT

priority

bit-2

INT

priority

bit-1

INT

priority

bit-0

INT

status

divisor

latch

enable

set

break

set

parity

even

parity

enable

stop

bits

word

length

bit-1

word

length

bit-0

0

loop

back

-OP2/

INTx

enable

-OP1

-RTS

-DTR

trans.

empty

trans.

holding

empty

break

interrupt

framing

error

parity

error

overrun

error

receive

data

ready

1

0

1

MSR[X0]

SPR[FF]

CD

RI

DSR

bit-5

CTS

bit-4

delta

-CD

delta

-RI

delta

-DSR

delta

-CTS

bit-7

bit-6

bit-3

bit-2

bit-1

bit-0

Special Register set: Note *2

0

1

DLL[XX]

DLM[XX]

bit-7

bit-6

bit-5

bit-4

bit-3

bit-2

bit-1

bit-9

bit-0

bit-8

bit-15

bit-14

bit-13

bit-12

bit-11

bit-10

Note *²: The Special register set is accessible only when LCR bit-7 is set to “1”.

Rev. 3.31

14

ST16C454

Transmit (THR) and Receive (RHR) Holding Regis-

ters

IERBIT-2:

This interrupt will be issued whenever a fully as-

sembledreceivecharacteristransferredfromtheRSR

to the RHR, data ready, LSR bit-0.

Logic 0 = Disable the receiver line status interrupt.

(normal default condition)

The serial transmitter section consists of an 8-bit

TransmitHoldRegister(THR)andTransmitShiftReg-

ister(TSR).ThestatusoftheTHRisprovidedintheLine

StatusRegister(LSR).WritingtotheTHRtransfersthe

contentsofthedatabus(D7-D0)totheTHR, providing

thattheTHRorTSRisempty.TheTHRemptyflaginthe

LSRregisterwillbesettoalogic1whenthetransmitter

is empty or when data is transferred to the TSR. Note

that a write operation can be performed when the

transmit holding register empty flag is set.

Logic 1 = Enable the receiver line status interrupt.

IERBIT-3:

Logic 0 = Disable the modem status register interrupt.

(normal default condition)

Logic 1 = Enable the modem status register interrupt.

The serial receive section also contains an 8-bit

Receive Holding Register, RHR. Receive data is

removed from the 454 by reading the RHR register.

The receive section provides a mechanism to prevent

false starts. On the falling edge of a start or false start

bit, an internal receiver counter starts counting clocks

at 16x clock rate. After 7 1/2 clocks the start bit time

should be shifted to the center of the start bit. At this

time the start bit is sampled and if it is still a logic 0 it

is validated. Evaluating the start bit in this manner

prevents the receiver from assembling a false charac-

ter. Receiver status codes will be posted in the LSR.

IER BIT 4-7:

Not used - Initialized to a logic 0.

Interrupt Status Register (ISR)

The 454 provides four levels of prioritized interrupts to

minimize external software interaction. The Interrupt

Status Register (ISR) provides the user with six inter-

ruptstatusbits. PerformingareadcycleontheISRwill

provide the user with the highest pending interrupt

level to be serviced. No other interrupts are acknowl-

edged until the pending interrupt is serviced. When-

ever the interrupt status register is read, the interrupt

status is cleared. However it should be noted that only

the current pending interrupt is cleared by the read. A

lower level interrupt may be seen after rereading the

interrupt status bits. The Interrupt Source Table 7

(below) shows the data values (bit 0-5) for the four

prioritized interrupt levels and the interrupt sources

associated with each of these interrupt levels:

Interrupt Enable Register (IER)

The Interrupt Enable Register (IER) masks the inter-

rupts from receiver ready, transmitter empty, line

status and modem status registers. These interrupts

would normally be seen on the INT A-D output pins in

the 16 mode, or on WIRE-OR IRQ output pin, in the 68

mode.

IER BIT-0:

This interrupt will be issued when the RHR is full,

cleared when the RHR is empty.

Logic 0 = Disable the receiver ready interrupt. (normal

default condition)

Logic 1 = Enable the receiver ready interrupt.

IER BIT-1:

This interrupt will be issued whenever the THR is

empty and is associated with bit-1 in the LSR register.

Logic 0 = Disable the transmitter empty interrupt.

(normal default condition)

Logic 1 = Enable the transmitter empty interrupt.

Rev. 3.31

15

ST16C454

Table7, INTERRUPTSOURCETABLE

Priority

Level

[ ISR BITS ]

Bit-3 Bit-2 Bit-1 Bit-0

Source of the interrupt

1

2

3

4

0

1

0

1

0

1

0

LSR(ReceiverLineStatusRegister)

RXRDY(ReceivedDataReady)

TXRDY(TransmitterHoldingRegisterEmpty)

MSR (Modem Status Register)

ISRBIT-0:

LCR BIT-2: (logic 0 or cleared is the default condition)

The length of stop bit is specified by this bit in conjunc-

tion with the programmed word length.

Logic 0 = An interrupt is pending and the ISR contents

may be used as a pointer to the appropriate interrupt

serviceroutine.

Logic 1 = No interrupt pending. (normal default condi-

tion)

BIT-2

Word length

Stop bit

length

ISRBIT1-3:(logic0orclearedisthedefaultcondition)

Thesebitsindicatethesourceforapendinginterruptat

interruptprioritylevels1,2,and3(SeeInterruptSource

Table).

(Bittime(s))

0

1

5,6,7,8

5

6,7,8

1

1-1/2

2

ISRBIT4-7:

Not used - Initialized to a logic 0.

LCR BIT-3:

Line Control Register (LCR)

Parity or no parity can be selected via this bit.

Logic 0 = No parity. (normal default condition)

Logic 1 = A parity bit is generated during the transmis-

sion, receiver checks the data and parity for transmis-

sion errors.

The Line Control Register is used to specify the

asynchronous data communication format. The word

length, the number of stop bits, and the parity are

selected by writing the appropriate bits in this register.

LCR BIT-4:

LCR BIT 0-1: (logic 0 or cleared is the default condi-

tion)

These two bits specify the word length to be transmit-

ted or received.

If the parity bit is enabled with LCR bit-3 set to a logic

1, LCR BIT-4 selects the even or odd parity format.

Logic 0 = ODD Parity is generated by forcing an odd

number of logic 1’s in the transmitted data. The

receiver must be programmed to check the same

format. (normal default condition)

BIT-1

BIT-0

Word length

Logic 1 = EVEN Parity is generated by forcing an even

the number of logic 1’s in the transmitted. The receiver

must be programmed to check the same format.

0

1

0

1

0

1

5

6

7

8

LCR BIT-5:

If the parity bit is enabled, LCR BIT-5 selects the

forcedparityformat.

Rev. 3.31

16

ST16C454

LCRBIT-5=logic0,parityisnotforced.(normaldefault

condition)

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 0, parity bit

is forced to a logical 1 for the transmit and receive

data.

MCR BIT-2:

This bit is used in the Loop-back mode only. In the

loop-back mode this bit is use to write the state of the

modem -RI interface signal via -OP1.

LCR BIT-5 = logic 1 and LCR BIT-4 = logic 1, parity bit

is forced to a logical 0 for the transmit and receive

data.

MCR BIT-3: (Used to control the modem -CD signal

in the loop-back mode.)

Logic 0 = Forces INT (A-D) outputs to the three state

mode during the 16 mode. (normal default condition)

In the Loop-back mode, sets -OP2 (-CD) internally to

a logic 1.

LCR

Parity selection

Bit-5 Bit-4 Bit-3

Logic 1 = Forces the INT (A-D) outputs to the active

mode during the 16 mode. In the Loop-back mode,

sets -OP2 (-CD) internally to a logic 0.

X

0

1

X

0

1

0

1

0

1

No parity

Odd parity

Even parity

Force parity “1”

Forced parity “0”

MCR BIT-4:

Logic 0 = Disable loop-back mode. (normal default

condition)

Logic 1 = Enable local loop-back mode (diagnostics).

MCR BIT 5-7:

LCR BIT-6:

Not used - Initialized to a logic 0.

When enabled the Break control bit causes a break

condition to be transmitted (the TX output is forced to

a logic 0 state). This condition exists until disabled by

setting LCR bit-6 to a logic 0.

Logic 0 = No TX break condition. (normal default

condition)

Line Status Register (LSR)

This register provides the status of data transfers

between. the 454 and the CPU.

Logic 1 = Forces the transmitter output (TX) to a logic

0 for alerting the remote receiver to a line break

condition.

LSR BIT-0:

Logic 0 = No data in receive holding register. (normal

default condition)

Logic 1 = Data has been received and is saved in the

receive holding register.

LCR BIT-7:

Not used - Initialized to a logic 0.

LSR BIT-1:

Modem Control Register (MCR)

Logic 0 = No overrun error. (normal default condition)

Logic 1 = Overrun error. A data overrun error occurred

in the receive shift register. This happens when addi-

tionaldataarriveswhiletheRHRisfull. Inthiscasethe

previous data in the shift register is overwritten. Note

that under this condition the data byte in the receive

shift register is not transferred into the RHR, therefore

the data in the RHR is not corrupted by the error.

This register controls the interface with the modem or

a peripheral device.

MCR BIT-0:

Logic 0 = Force -DTR output to a logic 1. (normal

default condition)

Logic 1 = Force -DTR output to a logic 0.

LSR BIT-2:

MCR BIT-1:

Logic 0 = No parity error. (normal default condition)

Logic 1 = Parity error. The receive character does not

have correct parity information and is suspect. In the

RHR mode, this error is associated with the character

Logic 0 = Force -RTS output to a logic 1. (normal

default condition)

Logic 1 = Force -RTS output to a logic 0.

Rev. 3.31

17

ST16C454

at the top of the RHR.

MSRBIT-1:

Logic 0 = No -DSR Change. (normal default condition)

Logic1=The-DSRinputtothe454haschangedstate

since the last time it was read. A modem Status

Interruptwillbegenerated.

LSR BIT-3:

Logic 0 = No framing error. (normal default condition)

Logic 1 = Framing error. The receive character did not

have a valid stop bit(s).

LSR BIT-4:

MSR BIT-2:

Logic 0 = No break condition. (normal default condi-

tion)

Logic 1 = The receiver received a break signal (RX

was a logic 0 for one character frame time).

Logic 0 = No -RI Change. (normal default condition)

Logic 1 = The -RI input to the 454 has changed from

a logic 0 to a logic 1. A modem Status Interrupt will be

generated.

LSR BIT-5:

This bit indicates that the 454 is ready to accept new

characters for transmission. This bit causes the 454 to

issue an interrupt to the CPU when the transmit

holding register is empty and the interrupt enable is

set.

MSR BIT-3:

Logic 0 = No -CD Change. (normal default condition)

Logic 1 = Indicates that the -CD input to the has

changed state since the last time it was read. A

modem Status Interrupt will be generated.

Logic 0 = Transmit holding register is not empty.

(normal default condition)

Logic 1 = Transmit holding register is empty.

MSR BIT-4:

-CTS (active high, logical 1). Normally MSR bit-4 bit

is the compliment of the -CTS input. However in the

loop-back mode, this bit is equivalent to the RTS bit in

the MCR register.

LSR BIT-6:

Logic 0 = Transmitter holding and shift registers are

full.

MSR BIT-5:

Logic 1 = Transmitter holding and shift registers are

empty (normal default condition).

DSR (active high, logical 1). Normally this bit is the

compliment of the -DSR input. In the loop-back mode,

this bit is equivalent to the DTR bit in the MCR register.

LSR BIT-7:

Not used - Initialized to a logic 0.

MSR BIT-6:

RI (active high, logical 1). Normally this bit is the

compliment of the -RI input. In the loop-back mode

this bit is equivalent to the OP1 bit in the MCR register.

Modem Status Register (MSR)

This register provides the current state of the control

interface signals from the modem, or other peripheral

device that the 454 is connected to. Four bits of this

register are used to indicate the changed information.

These bits are set to a logic 1 whenever a control input

from the modem changes state. These bits are set to

a logic 0 whenever the CPU reads this register.

MSR BIT-7:

CD (active high, logical 1). Normally this bit is the

compliment of the -CD input. In the loop-back mode

this bit is equivalent to the OP2 bit in the MCR register.

Scratchpad Register (SPR)

MSR BIT-0:

The ST16C454 provides a temporary data register to

store 8 bits of user information.

Logic 0 = No -CTS Change (normal default condition)

Logic 1 = The -CTS input to the 454 has changed state

since the last time it was read. A modem Status

Interrupt will be generated.

Rev. 3.31

18

ST16C454

ST16C454EXTERNALRESETCONDITIONS

REGISTERS RESET STATE

IER

IERBITS0-7=0

ISR

ISR BIT-0=1, ISR BITS 1-7=0

LCR BITS 0-7=0

MCR BITS 0-7=0

LCR

MCR

LSR

LSR BITS 0-4=0,

LSR BITS 5-6=1 LSR, BIT 7=0

MSR BITS 0-3=0,

MSR

MSR BITS 4-7= input signals

SIGNALS

RESET STATE

TX A-D

High

-RTS A-D

-DTR A-D

INT A-D

High

Three-State

Rev. 3.31

19

ST16C454

AC ELECTRICAL CHARACTERISTICS

T_A=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.

Symbol

Parameter

Limits

3.3

Limits

5.0

Units Conditions

Min

Max

Min

Max

T

1w,

3w

6s

7d

T2w

Clock pulse duration

Oscillator/Clockfrequency

Address setup time

-IOR delay from chip select

-IOR strobe width

Chip select hold time from -IOR

Read cycle delay

Delay from -IOR to data

Data disable time

-IOW delay from chip select

-IOW strobe width

Chip select hold time from -IOW

Write cycle delay

Data setup time

17

ns

MHz

ns

8

24

5

0

10

35

0

10

25

0

T

7w

7h

9d

40

30

12d

12h

13d

13w

13h

15d

16s

16h

17d

18d

35

25

15

35

10

25

0

30

15

5

10

35

0

40

20

5

Data hold time

Delay from -IOW to output

Delay to set interrupt from MODEM

input

50

40

35

ns

100 pF load

T

19d

20d

21d

22d

23d

Delay to reset interrupt from -IOR

Delay from stop to set interrupt

Delay from -IOR to reset interrupt

Delay from stop to interrupt

Delay from initial INT reset to transmit

start

40

1

45

24

35

1

40

24

ns

Rclk

ns

Rclk

100 pF load

8

T

24d

25d

26d

27d

28d

30s

30w

30h

30d

31d

31h

32s

32h

Delay from -IOW to reset interrupt

Delay from stop to set -RxRdy

Delay from -IOR to reset -RxRdy

Delay from -IOW to set -TxRdy

Delay from start to reset -TxRdy

Address setup time

Chip select strobe width

Address hold time

Read cycle delay

Delay from -CS to data

Data disable time

Write strobe setup time

Write strobe hold time

Write cycle delay

45

1

45

8

40

1

40

8

ns

Rclk

ns

Rclk

ns

10

40

15

70

15

10

40

15

70

15

10

70

ns

10

70

T32d

Rev. 3.31

20

ST16C454

AC ELECTRICAL CHARACTERISTICS

T_A=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.

Symbol

Parameter

Limits

3.3

Limits

5.0

Units Conditions

Min

Max

Min

Max

T

T33h

TR

N

33s

Data setup time

Data hold time

Reset pulse width

Baudratedevisor

20

10

40

1

15

10

40

1

ns

2¹⁶-1

Rclk

Rev. 3.31

21

ST16C454

ABSOLUTE MAXIMUM RATINGS

Supply range

7 Volts

GND - 0.3 V to VCC +0.3 V

-40° C to +85° C

Voltage at any pin

Operating temperature

Storage temperature

Package dissipation

-65° C to 150° C

500 mW

DC ELECTRICAL CHARACTERISTICS

T_A=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.

Symbol

Parameter

Limits

3.3

Limits

5.0

Units Conditions

Min

Max

Min

Max

V_ILCK

V_IHCK

V_IL

Clock input low level

Clock input high level

Inputlowlevel

-0.3

2.4

-0.3

2.0

0.6

VCC

0.8

-0.5

3.0

-0.5

2.2

0.6

VCC

0.8

VCC

0.4

V

V_IH

Inputhighlevel

V_OL

V_OH

I_IL

I_CL

I_CC

C_P

Output low level on all outputs

Output high level

Input leakage

Clock leakage

Avg power supply current

Input capacitance

I_OL= 5 mA

I_OL= 4 mA

I_OH= -5 mA

I_OH= -1 mA

0.4

2.4

V

2.0

±10

3

±10

6

5

15

µA

mA

pF

kΩ

5

RIN

Internal pull-up resistance

3

Note: See the Symbol Description Table, for a listing of pins having internal pull-up resistors.

Rev. 3.31

22

ST16C454

A0-A4

-CS

T30h

T30s

T30w

T30d

T31h

R/-W

D0-D7

T31d

8654-RD-1

General read timing in 68 mode

A0-A4

-CS

T30s

T30h

T32h

T32s

T32d

T30w

R/-W

D0-D7

T33h

T33s

8654-WD-1

General write timing in 68 mode

Rev. 3.31

23

ST16C454

Valid

Address

A0-A2

T6s

Active

-CS

T7d

T7w

T7h

T9d

-IOR

Active

T12d

T12h

D0-D7

Data

X552-RD-1

General read timing in 16 mode

Valid

Address

A0-A2

T6s

Active

-CS

T13h

T13d

T13w

T15d

Active

-IOW

T16s

T16h

Data

D0-D7

X552-WD-1

General write timing in 16 mode

Rev. 3.31

24

ST16C454

Active

-IOW

T17d

Change of state

-RTS

-DTR

Change of state

-CD

-CTS

Change of state

-DSR

T18d

Active

INT

Active

T19d

Active

-IOR

T18d

Change of state

X552-MD-1

-RI

Modem input/output timing

T1w

T2w

EXTERNAL

CLOCK

X654-CK-1

T3w

External clock timing

Rev. 3.31

25

ST16C454

STOP

BIT

START

BIT

DATA BITS (5-8)

RX

D0

D1

D2

D3

D4

D5

D6 D7

PARITY

BIT

START

BIT

5 DATA BITS

6 DATA BITS

7 DATA BITS

T20d

Active

INT

T21d

Active

-IOR

16 BAUD RATE CLOCK

X552-RX-1

Receive timing

Rev. 3.31

26

ST16C454

STOP

BIT

START

BIT

DATA BITS (5-8)

TX

D0

D1

D2

D3

D4

D5

D6 D7

PARITY

BIT

START

BIT

5 DATA BITS

6 DATA BITS

7 DATA BITS

T22d

Active

Tx Ready

INT

T24d

T23d

-IOW

Active

16 BAUD RATE CLOCK

X552-TX-1

Transmit timing

Rev. 3.31

27

ST16C454

68 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC)

REV. 1.00

D

C

Seating Plane

A₂

D₁

45° x H

1

45° x H

2

2 1 68

B₁

B

D

3

D

2

D

1

e

R

D

3

A₁

A

Note: The control dimension is the inch column.

INCHES

MILLIMETERS

SYMBOL

MIN

MAX

0.200

0.130

---

MIN

4.19

2.29

0.51

0.33

0.66

0.19

25.02

24.13

22.61

MAX

5.08

3.30

---

A

A₁

A₂

B

0.165

0.090

0.020

0.013

0.026

0.008

0.985

0.950

0.890

0.021

0.032

0.013

0.995

0.958

0.930

0.53

0.81

0.32

25.27

24.33

23.62

B₁

C

D

D₁

D₂

D₃

e

0.800 typ

0.050 BSC

20.32 typ

1.27 BSC

H₁

H₂

R

0.042

0.056

0.048

0.045

1.07

1.42

1.22

1.14

0.042

0.25

1.07

0.64

Rev. 3.31

28

ST16C454

EXPLANATIONOFDATASHEETREVISIONS:

FROM

3.20

TO

CHANGES

DATE

3.30

3.31

Added revision history. Added Device Status to front page.

RemoveddiscontinuedST68C454fromOrderingInformation.

August2004

August2005

3.30

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to

improvedesign,performanceorreliability.EXARCorporationassumesnoresponsibilityfortheuseofanycircuits

describedherein,conveysnolicenseunderanypatentorotherright,andmakesnorepresentationthatthecircuits

arefreeofpatentinfringement.Chartsandschedulescontainedhereinareonlyforillustrationpurposesandmay

vary depending upon a user's specific application. While the information in this publication has been carefully

checked; no responsibility, however, is assumed for inaccuracies.

EXARCorporationdoesnotrecommendtheuseofanyofitsproductsinlifesupportapplicationswherethefailure

of the product can reasonably be expected to cause failure of the life support system or to significantly affect its

safetyoreffectiveness.ProductsarenotauthorizedforuseinsuchapplicationsunlessEXARCorporationreceives,

in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user

assumesallsuchrisks;(c)potentialliabilityofEXARCorporationisadequatelyprotectedunderthecircumstances.

Datasheet August 2005

Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com

Reproduction, in part or whole, without prior written consent of EXAR Corporation is prohibited.

Rev. 3.31

29


型号：	ST16C454IJ68-F
厂家：	EXAR CORPORATION
描述：	Serial I/O Controller, 4 Channel(s), 0.1875MBps, CMOS, PQCC68, GREEN, PLASTIC, LCC-68 通信时钟数据传输外围集成电路
文件：	总29页 (文件大小：177K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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