ST49C101ACF8-13_技术文档

ST49C101A-XX

High Frequency Clock Multiplier

January 1999 -3

APPLICATIONS

FEATURES

• Voltage Controlled Crystal Oscillator (VCXO)

• Mask Programmable Analog Phase Locked

Loop

• System Clock Multiplication in:

• Computer Systems

• Upto200MHzOperation

• Telecommunications Systems

• Set-top Boxes

• PreprogrammedMultiplicationFactorsof2,3,4,5,

6, 8, 10 and 12X

• Low Output Jitter

• Replace Expensive High Frequency Oscillator

• Crystal Oscillator Circuit On Chip

• Low Power Single Supply 5V or 3.3V CMOS

Technology

• Small 8 Lead SOIC Package

GENERALDESCRIPTION

The ST49C101A-XX is a mask programmable mono-

lithic analog phase locked loop device, designed to

replace existing high frequency crystal oscillator with

a low frequency crystal. The high performance

ST49C101A-XX provides low jitter clock output and

operatesupto180MHz.at3.3voltspowersupply.The

ST49C101A-XXsupportspreprogrammedmultiplica-

tion factors of 2,3,4,5,6,8,10 and 12X.

ORDERING INFORMATION

Operating

Temperature Range

Part Number.

Package

8 Lead 150 Mil Jedec SOIC

ST49C101ACF8-01

ST49C101ACF8-03

ST49C101ACF8-05

ST49C101ACF8-06

ST49C101ACF8-07

ST49C101ACF8-08

ST49C101ACF8-09

ST49C101ACF8-10

ST49C101ACF8-13

ST49C101ACF8-15

Consult Factory

0^oC to 70^oC

8 Lead 150 Mil Jedec SOIC

Die

Rev. 2.20

EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017

ST49C101A-XX

XTAL1 XTAL2

Oscillator

Circuit

Programmable

Voltage

Controlled

Oscillator

Programmable

Phase

Detector

Charge

Pump

Loop

Filter

Counter

B

Counter

C

Programmable

Voltage

Reference

Circuit

Output

Buffer

Counter

A

CLOCK

VCC

OE

Figure 1. Block Diagram

Rev. 2.20

2

ST49C101A-XX

1

8

XTAL1

OE

XTAL2

AVCC

DVCC

CLOCK

2

3

7

6

AGND

DGND

4

5

8 Pin SOIC (Jedec, 0.150")

PINDESCRIPTION

Pin #

Symbol

Type

Description

1

XTAL1

OE

I

Crystal or External Clock Input. A crystal can be connected to this pin

and XTAL2 pin to generate internal phase locked loop reference clock.

For external clock, XTAL2 is left open or used as buffered clock output.

2¹

I

Clock Output Enable (Active high). CLOCK output is three stated when

this pin is low. Connect to DVCC for normal operation.

3

4

5

6

7

8

AGND

DGND

CLOCK

DV_CC

O

I

Analog Ground.

Digital Ground.

Programmed Output Clock.

Positive Supply Voltage. Single +5 or 3.3 volts.

Analog Supply Voltage. Single +5 or 3.3 volts.

Crystal Output.

AV_CC

I

XTAL2

O

1

Note: Has internal weak pull-up resistor

Rev. 2.20

3

ST49C101A-XX

MULTIPLICATIONFACTORANDOUTPUTFRE-

QUENCYSELECTION

Table 1. Preprogrammed Options

Max. Output

Frequency¹

ST49C101A-XX

Factor

VCC¹

TheST49C101A-XXcontainsananalogphaselocked

loop (PLL) circuit with digital closed loop dividers and

a final output divider to achieve the desired dividing

ratios for the clock output. The preprogrammed multi-

plication factor and output frequency are shown on

Table 1. The accuracy of the output frequency pro-

duced by the ST49C101A-XX depends on its input

frequency and multiplication factor.

200 MHz

140 MHz

5.0 V

3.3 V

ST49C101A-01

ST49C101A-03

ST49C101A-05

ST49C101A-06

ST49C101A-07

ST49C101A-08

ST49C101A-09

ST49C101A-10

ST49C101A-13

ST49C101A-15

12

8

200 MHz

140 MHz

5.0 V

3.3 V

200 MHz

140 MHz

5.0 V

3.3 V

6

APPLICATIONS

5.0 or

3.3 V

TwoapplicationexamplesareshowninFigure2and3.

Figure 2 shows a lower cost high frequency crystal

oscillator circuit using the ST49C101-xx to increase

the fundamental crystal frequency. The crystal Y1 is

connected to XTAL1 and XTAL2 pins to use the

internal oscillator circuit. The oscillator provides the

reference clock to the PLL circuit for clock rate multi-

plication. Figure 3 shows a similar circuit using

external clock input on XTAL1 pin instead.

4

120 MHz

80 MHz

70 MHz

5.0 V

3.3 V

3

80 MHz

70 MHz

5.0 V

3.3 V

2

200 MHz

140 MHz

5.0 V

3.3 V

5

If a sinewave is used for external clock, it may be

necessary to AC couple the signal with a 0.047uF

capacitor to XTAL1 pin so that the internal circuitry

can establish the proper bias. Also, keep the peak-to-

peak signal, at XTAL pin, above ground level (AGND)

and below AVCC.

10

8

180 MHz

3.3 V

6

As a general board layout rule, it is recommended to

use two 0.01µF bypass capacitors on DVCC and

AVCC power supply pins, and put them as closely as

possible to the chip.

Notes

¹See AC electrical characteristics for maximum operating

frequency.

Rev. 2.20

4

ST49C101A-XX

AVCC

DVCC

C1

0.01uF

C2

0.01uF

AGND

DGND

U1

7

6

DVCC

AVCC

XTAL1

1

Parallel Cut

Fundamental

Resonance

Y1

Crystal

ST49C101A-XX

20-30pF Load

8

2

XTAL2

5

CLOCK= Xtal Freq. x Option

CLOCK

OE

DVCC

AGND DGND

3

4

AGND

DGND

Figure 2. High Frequency Crystal Oscillator Using a Crystal for Reference.

AVCC DVCC

C1

C2

0.01uF

AGND

DGND

U1

7

6

AVCC

DVCC

1

CLKin

XTAL1

ST49C101A-XX

8

2

5

XTAL2

CLOCK = CLKin x Option

CLOCK

OE

DVCC

AGND DGND

3

4

AGND

DGND

Figure 3. High Frequency Clock Rate Multiplication Using External Clock.

Rev. 2.20

5

ST49C101A-XX

DCELECTRICALCHARACTERISTICS

Test Conditions: T_A= 25°C, V_CC= 5.0V + 10%, Operating Temperature Range 0°C to 70°C Unless

OtherwiseSpecified

Symbol Parameter

Min.

Typ. Max.

Unit

V

Conditions

V_IL

V_IH

V_OL

V_OH

I_IL

Input Low Level

0.8

Input High Level

2.0

V

Output Low Level

Output High Level

Input Low Current

Input High Current

Operating Current

Input Pull-up Resistance

0.5

V

I_OL= 8.0 mA

2.8

V

I_OH= 8.0 mA

-100

1

µA

mA

kΩ

OE Pin only

I_IH

V_IN=V_CC,OE Pin only

No Load. CLOCK=100MHz

I_CC

R_IN

35

50

75

110

155

ACELECTRICALCHARACTERISTICS

Test Conditions: T_A= 25°C, V_CC= 5.0V + 10%, Operating Temperature Range 0°C to 70°C Unless

OtherwiseSpecified

Symbol

Parameter

Min.

Typ. Max.

Unit

Conditions

T1,T2

CLOCK Rise/Fall Time

1.5

3

ns

Load=30 pF, 0.2 V_CC- 0.8 V_CC

T4

T4 + T5

Duty Cycle

45

40

50

55

%

V_CC/2 Switch Point Up To 100MHz,

Load = 20pF

T4

T4 + T5

50

60

V_CC/2 Switch Point 100-150MHz, 95Ω

(AC Terminated)

T3

Jitter 1 Sigma

+0.4

+1

+3

30

%

Of Period

Jitter Absolute

T_IN

Input Reference Frequency

Output Frequency

12

20

MHz

T_OUT

50

200

MHz

ST49C101A-01

ST49C101A-03

ST49C101A-05

50

25

50

120

80

MHz

ST49C101A-06

ST49C101A-07

ST49C101A-08

ST49C101A-09

80

200

Rev. 2.20

6

ST49C101A-XX

DCELECTRICALCHARACTERISTICS

Test Conditions: T_A= 25°C, V_CC=3.3V +/- 10%, Operating Temperature Range 0°C to 70°C Unless

OtherwiseSpecified

Symbol

V_IL

Parameter

Min.

Typ. Max.

Unit

V

Conditions

Input Low Level

Input High Level

0.8

V_IH

2.0

V

V_OL

V_OH

I_IL

Output Low Level

Output High Level

Input Low Current

Input High Current

Operating Current

0.5

V

I_OL= 4.0mA

I_OH= 4.0mA

-100

1

µA

mA

OE Pin Only

II_H

V_IN=VCC_,OE Pin only

No Load. CLOCK=100MHz

I_CC

22

40

R_IN

Input Pull–up Resistance

75

110

155

kΩ

ACELECTRICALCHARACTERISTICS

Test Conditions: T_A= 25°C, V_CC=3.3V +/- 10%, Operating Temperature Range 0°C to 70°C Unless

OtherwiseSpecified

Symbol

Parameter

Min.

45

Typ. Max.

Unit

Conditions

T1, T2

CLOCK Rise/Fall Time

2

4

ns

Load = 30 pF, 0.2 V_CC- 0.8 V_CC

T4

T4+T5

Duty Cycle

50

55

%

V_CC/2 switch point up to 100MHz,

Load = 30 pF

T4

T4+T5

40

50

60

V_CC/2 switch point 100-150MHz, 95Ω

(AC Terminated)

T3

Jitter 1 Sigma

+ 0.4

+ 1

+ 3

30

%

Of Period

Jitter Absolute

%

T_IN

Input Reference Frequency

Output Frequency

12

50

20

MHz

T_OUT

140

ST49C101A-01

50

140

MHz

ST49C101A-03

ST49C101A-05

50

25

50

25

150

120

70

MHz

ST49C101A-05 at V_CC=3.13V min.

ST49C101A-06

ST49C101A-07

70

ST49C101A-08

140

180

ST49C101A-09

ST49C101A-10 at V_CC=3.13V min.

ST49C101A-13 at V_CC=3.13V min.

ST49C101A-15 at V_CC=3.13V min.

Rev. 2.20

7

ST49C101A-XX

ABSOLUTEMAXIMUMRATINGS

StorageTemperature

PackageDissipation

-40°Cto+150°C

SupplyRange

7 V

500mW

Voltage at Any Pin

GND-0.3V to V_CC+0.3V

OperatingTemperature

0°C to +70°C

T2

T1

Output

Clock

T5

T4

T3

Figure 4. Timing Diagram

Rev. 2.20

8

ST49C101A-XX

Rev. 2.20

9

ST49C101A-XX

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to

improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any

circuits described herein, conveys no license under any patent or other right, and makes no representation that

the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration

purposes and may vary depending upon a user’s specific application. While the information in this publication

has been carefully checked; no responsibility, however, is assumed for in accuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the

failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to

significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless

EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has

been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately

protected under the circumstances.

DatasheetJanuary1999

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

Rev. 2.20

10


型号：	ST49C101ACF8-13
厂家：	EXAR CORPORATION
描述：	High Frequency Clock Multiplier 高频时钟乘法器晶体时钟发生器微控制器和处理器外围集成电路光电二极管
文件：	总10页 (文件大小：93K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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