XR16L2450IJ-F [EXAR]
Serial I/O Controller, 2 Channel(s), 0.1875MBps, CMOS, PQCC44, GREEN, PLASTIC, LCC-44;
| 型号： | XR16L2450IJ-F |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Serial I/O Controller, 2 Channel(s), 0.1875MBps, CMOS, PQCC44, GREEN, PLASTIC, LCC-44 通信 时钟 数据传输 外围集成电路 |
| 文件： | 总30页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
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XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
MAY 2005
FEATURES
GENERAL DESCRIPTION
The XR16L2450 (L2450) is a dual universal asyn-
chronous receiver and transmitter (UART). The
XR16L2450 is an improved version of the
ST16C2450 with lower operating voltage and 5 volt
tolerant inputs. The L2450 provides enhanced UART
functions, a modem control interface and data rates
up to 1.5 Mbps. Onboard status registers provide the
user with error indications and operational status. In-
dependent programmable baud rate generators are
provided to select transmit and receive clock rates up
to 1.5 Mbps. An internal loopback capability allows
onboard diagnostics. The L2450 is available in a 44-
pin PLCC and 48-pin TQFP packages. The L2450 is
fabricated in an advanced CMOS process capable of
operating from 2.25 volt to 5.5 volt power supply with
5 volt tolerant inputs.
• 2.25 to 5.5 Volt Operation
• 5 Volt Tolerant Inputs
• Pin-to-pin compatible to Exar’s ST16C2450,
ST16C2550,
XR16C2850
XR16L2550,
XR16L2750
and
• Pin-to-pin compatible to TI’s TL16C752B on the 48-
TQFP package
• 2 independent UART channels
■ Up to 1.5 Mbps data rate with a 24 MHz crystal
oscillator or external clock frequency
■ 1 byte Transmit FIFO
■ 1 byte Receive FIFO with error tags
■ Status report registers
■ Modem control signals (CTS#, RTS#, DSR#,
DTR#, RI#, CD#)
APPLICATIONS
■ Programmable character lengths (5, 6, 7, 8)
• Portable Appliances
with even, odd, or no parity
• Telecommunication Network Routers
• Ethernet Network Routers
• Cellular Data Devices
• Crystal oscillator or external clock input
• TTL compatible inputs, outputs
• Industrial temperature ranges
• Factory Automation and Process Controls
• 48-TQFP and 44-PLCC packages
FIGURE 1. XR16L2450 BLOCK DIAGRAM
2.25 to 5.5 Volt VCC
*5V Tolerant inputs
A2:A0
D7:D0
UART Channel A
TXA
THR
IOR#
IOW#
UART
Regs
RHR
RXA
CSA#
CSB#
RTSA#, CTSA#,
DTRA#, DSRA#,
CDA#, RIA#, OP2A#
Modem I/Os
8-bit Data
INTA
INTB
BRG
Bus
Interface
TXB
RXB
UART Channel B
RTSB#, CTSB#,
DTRB#, DSRB#,
CDB#, RIB#, OP2B#
(same as Channel A)
Reset
XTAL1
XTAL2
Crystal Osc/Buffer
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XR16L2450
2.25V TO 5.5V DUART
xr
REV. 1.1.1
FIGURE 2. PIN OUT ASSIGNMENT
RESET
DTRB#
DTRA#
RTSA#
OP2A#
NC
D5
1
2
3
4
5
6
36
35
34
33
32
31
30
29
28
27
26
25
D6
D7
RXB
RXA
NC
XR16L2450
48-pin TQFP
INTA
INTB
A0
TXA
TXB
OP2B#
7
8
9
A1
CSA# 10
CSB# 11
NC 12
A2
NC
D5
D6
D7
7
8
9
39 RESET
38 DTRB#
37 DTRA#
36 RTSA#
35 OP2A#
34 NC
RXB 10
RXA 11
NC 12
XR16L2450
44-pin PLCC
TXA 13
33 INTA
32 INTB
31 A0
TXB 14
OP2B# 15
CSA# 16
CSB# 17
30 A1
29 A2
Device
ORDERING INFORMATION
PART NUMBER
XR16L2450IJ
XR16L2450IM
PACKAGE
OPERATING TEMPERATURE RANGE
-40°C to +85°C
DEVICE STATUS
Active
44-Lead PLCC
48-Lead TQFP
-40°C to +85°C
Active
2
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XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
PACKAGE PIN DESCRIPTIONS
PIN DESCRIPTIONS
44-PLCC
PIN #
48-TQFP
PIN #
NAME
TYPE
DESCRIPTION
DATA BUS INTERFACE
A2
A1
A0
29
30
31
26
27
28
I
Address data lines [2:0]. These 3 address lines select one of the inter-
nal registers in UART channel A/B during a data bus transaction.
D7
D6
D5
D4
D3
D2
D1
D0
9
8
7
6
5
4
3
2
3
IO
Data bus lines [7:0] (bidirectional).
2
1
48
47
46
45
44
IOR#
24
19
I
I
Input/Output Read Strobe (active low). The falling edge instigates an
internal read cycle and retrieves the data byte from an internal register
pointed to by the address lines [A2:A0]. The data byte is placed on the
data bus to allow the host processor to read it on the rising edge.
IOW#
20
15
Input/Output Write Strobe (active low). The falling edge instigates an
internal write cycle and the rising edge transfers the data byte on the
data bus to an internal register pointed by the address lines.
CSA#
CSB#
INTA
16
17
33
10
11
30
I
I
UART channel A select (active low) to enable UART channel A in the
device for data bus operation.
UART channel B select (active low) to enable UART channel B in the
device for data bus operation.
O
UART channel A Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTA is set to the
active mode and OP2A# output to a logic 0 when MCR[3] is set to a
logic 1. INTA is set to the three state mode and OP2A# to a logic 1
when MCR[3] is set to a logic 0 (default).
INTB
32
29
O
UART channel B Interrupt output. The output state is defined by the
user and through the software setting of MCR[3]. INTB is set to the
active mode and OP2B# output to a logic 0 when MCR[3] is set to a
logic 1. INTB is set to the three state mode and OP2B# to a logic 1
when MCR[3] is set to a logic 0 (default).
MODEM OR SERIAL I/O INTERFACE
TXA
RXA
13
11
7
5
O
I
UART channel A Transmit Data. If it is not used, leave it unconnected.
UART channel A Receive Data. Normal receive data input must idle at
logic 1 condition. If it is not used, tie it to VCC or pull it high via a 100k
ohm resistor.
RTSA#
36
33
O
UART channel A Request-to-Send (active low) or general purpose out-
put. If it is not used, leave it unconnected.
3
XR16L2450
2.25V TO 5.5V DUART
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REV. 1.1.1
PIN DESCRIPTIONS
44-PLCC
48-TQFP
PIN #
NAME
PIN #
TYPE
DESCRIPTION
CTSA#
40
38
I
UART channel A Clear-to-Send (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
DTRA#
DSRA#
37
41
34
39
O
I
UART channel A Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
UART channel A Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
CDA#
RIA#
42
43
35
40
41
32
I
I
UART channel A Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel A Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
OP2A#
O
Output Port 2 Channel A - The output state is defined by the user and
through the software setting of MCR[3]. INTA is set to the active mode
and OP2A# output to a logic 0 when MCR[3] is set to a logic 1. INTA is
set to the three state mode and OP2A# to a logic 1 when MCR[3] is set
to a logic 0. This output should not be used as a general output else it
will disturb the INTA output functionality. If it is not used at all, leave it
unconnected.
TXB
RXB
14
10
8
4
O
I
UART channel B Transmit Data. If it is not used, leave it unconnected.
UART channel B Receive Data. Normal receive data input must idle at
logic 1 condition. If it is not used, tie it to VCC or pull it high via a 100k
ohm resistor.
RTSB#
CTSB#
27
28
22
23
O
I
UART channel B Request-to-Send (active low) or general purpose out-
put. If it is not used, leave it unconnected.
UART channel B Clear-to-Send (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
DTRB#
DSRB#
38
25
35
20
O
I
UART channel B Data-Terminal-Ready (active low) or general purpose
output. If it is not used, leave it unconnected.
UART channel B Data-Set-Ready (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
CDB#
RIB#
21
26
16
21
I
I
UART channel B Carrier-Detect (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
UART channel B Ring-Indicator (active low) or general purpose input.
This input should be connected to VCC when not used. This input has
no effect on the UART.
4
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XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
PIN DESCRIPTIONS
44-PLCC
48-TQFP
PIN #
NAME
PIN #
TYPE
DESCRIPTION
OP2B#
15
9
O
Output Port 2 Channel B - The output state is defined by the user and
through the software setting of MCR[3]. INTB is set to the active mode
and OP2B# output to a logic 0 when MCR[3] is set to a logic 1. INTB is
set to the three state mode and OP2B# to a logic 1 when MCR[3] is set
to a logic 0. This output should not be used as a general output else it
will disturb the INTB output functionality. If it is not used, leave it uncon-
nected.
ANCILLARY SIGNALS
XTAL1
XTAL2
RESET
18
19
39
13
14
36
I
O
I
Crystal or external clock input.
Crystal or buffered clock output.
Reset (active high) - A longer than 40 ns logic 1 pulse on this pin will
reset the internal registers and all outputs. The UART transmitter output
will be held at logic 1, the receiver input will be ignored and outputs are
reset during reset period.
VCC
GND
N.C.
44
22
42
17
Pwr 2.25V to 5.5V power supply. All inputs are 5V tolerant.
Pwr Power supply common, ground.
1, 12, 23,
34
6, 12, 18,
24, 25, 31,
37, 43
-
No Connection. These pins are not connected internally.
Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.
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XR16L2450
2.25V TO 5.5V DUART
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REV. 1.1.1
1.0 PRODUCT DESCRIPTION
The XR16L2450 (L2450) integrates the functions of 2 16C450 Universal Asynchrounous Receiver and
Transmitter (UART). Each UART is independently controlled having its own set of device configuration
registers. The L2450 provides serial asynchronous receive data synchronization, parallel-to-serial and serial-
to-parallel data conversions for both the transmitter and receiver sections. These functions are necessary for
converting the serial data stream into parallel data that is required with digital data systems. Synchronization
for the serial data stream is accomplished by adding start and stops bits to the transmit data to form a data
character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the data
character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry to
provide all these functions is fairly complex especially when manufactured on a single integrated silicon chip.
The L2450 represents such an integration with greatly enhanced features. The L2450 is fabricated with an
advanced CMOS process. The L2450 is capable of operation up to 1.5 Mbps with a 24 MHz clock. With a
crystal or external clock input of 14.7456 MHz the user can select data rates up to 921.6 Kbps.
2.0 FUNCTIONAL DESCRIPTIONS
2.1
CPU Interface
The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and
write transactions. The L2450 data interface supports the Intel compatible types of CPUs and it is compatible to
the industry standard 16C450 UART. No clock (oscillator nor external clock) is required to operate a data bus
transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share
the same data bus for host operations. The data bus interconnections are shown in Figure 3.
FIGURE 3. XR16L2450 DATA BUS INTERCONNECTIONS
VCC
VCC
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
TXA
RXA
DTRA#
RTSA#
CTSA#
DSRA#
UART
Channel A
RS-232 Serial Interface
A0
A1
A2
A0
A1
A2
CDA#
RIA#
OP2A#
IOR#
IOW#
IOR#
IOW#
TXB
RXB
CSA#
CSB#
UART_CSA#
UART_CSB#
DTRB#
RTSB#
CTSB#
DSRB#
CDB#
UART_INTA
UART_INTB
INTA
INTB
UART
Channel B
RS-232 Serial Interface
RIB#
OP2B#
UART_RESET
RESET
GND
.
2.2
5-Volt Tolerant Inputs
The L2450 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the L2450 is
operating at 2.5V, its V may not be high enough to meet the requirements of the V of a CPU or a serial
OH
IH
transceiver that is operating at 5V.
2.3 Device Reset
The RESET input resets the internal registers and the serial interface outputs in both channels to their default
state (see Table 8). An active high pulse of at least 40 ns duration will be required to activate the reset function
in the device.
6
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XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
2.4
Device Identification and Revision
The L2450 provides a Device Identification code and a Device Revision code to distinguish the part from other
devices and revisions. To read the identification code from the part, it is required to set the baud rate generator
registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x02 to indicate L2450
and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means
revision A.
2.5
Channel A and B Selection
The UART provides the user with the capability to bi-directionally transfer information between an external
CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the
user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the
UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers,
but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in
Table 1.
TABLE 1: CHANNEL A AND B SELECT
CSA#
CSB#
FUNCTION
1
0
1
0
1
1
0
0
UART de-selected
Channel A selected
Channel B selected
Channel A and B selected
2.6
Channel A and B Internal Registers
Each UART channel in the L2450 has a standard register set for controlling, monitoring and data loading and
unloading. These registers function as data holding registers (THR/RHR), interrupt status and control registers
(ISR/IER), receive line status and control registers (LSR/LCR), modem status and control registers (MSR/
MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user accessible scratch pad register
(SPR).
2.7
INTA and INTB Outputs
The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.
Table 2 summarizes the operating behavior for the transmitter and receiver. Also see Figure 12 and Figure 13.
TABLE 2: INTA AND INTB PINS OPERATION FOR TRANSMITTER
TRANSMITTER
RECEIVER
INTA/B Pin
0 = a byte in THR
1 = THR empty
0 = no data
1 = 1 byte
2.8
Crystal Oscillator or External Clock Input
The L2450 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the
device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a
system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the
oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see
“Programmable Baud Rate Generator.”
7
XR16L2450
2.25V TO 5.5V DUART
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REV. 1.1.1
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS
XTAL1
XTAL2
R1
0-120 Ω
(Optional)
R2
500 ΚΩ − 1 ΜΩ
1.8432 MHz
to
Y1
24 MHz
C1
C2
22-47 pF
22-47 pF
The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,
fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency
tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4), with an external 500 kΩ to
1 MΩ resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the internal
baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4. For
further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.
2.9
Programmable Baud Rate Generator
A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel
control. The programmable Baud Rate Generator is capable of operating with a crystal frequency or external
clock of up to 24 MHz.
The L2450 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard
and custom applications using the same system design. The Baud Rate Generator divides the input 16X clock
16
by any divisor from 1 to 2 -1. The rate table is configured via the DLL and DLM internal register functions.
Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections
of baud rate generator.
Table 3 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling
rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for
DLL/DLM with the following equation.
divisor (decimal) = (XTAL1 clock frequency) / (serial data rate x 16)
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XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
TABLE 3: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK
DATA RATE
ERROR (%)
OUTPUT Data Rate
MCR Bit-7=0
DIVISOR FOR 16x
Clock (Decimal)
DIVISOR FOR 16x
Clock (HEX)
DLM PROGRAM
VALUE (HEX)
DLL PROGRAM
VALUE (HEX)
400
2304
384
192
96
48
24
12
6
900
180
C0
60
09
01
00
00
00
00
00
00
00
00
00
00
80
C0
60
30
18
0C
06
04
02
01
0
0
0
0
0
0
0
0
0
0
0
2400
4800
9600
19.2k
38.4k
76.8k
153.6k
230.4k
460.8k
921.6k
30
18
0C
06
4
04
2
02
1
01
2.10 Transmitter
The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 1 byte FIFO or Transmit
Holding Register (THR). TSR shifts out every data bit with the 16X internal clock. A bit time is 16 clock periods.
The transmitter sends the start-bit followed by the number of data bits, inserts the proper parity-bit if enabled,
and adds the stop-bit(s). The status of the FIFO and TSR are reported in the Line Status Register (LSR bit-5
and bit-6).
2.10.1 Transmit Holding Register (THR) - Write Only
The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the
data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled
by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.
FIGURE 5. TRANSMITTER OPERATION
Transmit
Holding
Register
(THR)
Data
Byte
THR Interrupt (ISR bit-1)
Enabled by IER bit-1
16X Clock
M
S
B
L
S
B
Transmit Shift Register (TSR)
TXNOFIFO1
9
XR16L2450
2.25V TO 5.5V DUART
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REV. 1.1.1
2.11 Receiver
The receiver section contains an 8-bit Receive Shift Register (RSR) and 1 byte FIFO or Receive Holding
Register (RHR). The RSR uses the 16X clock for timing. It verifies and validates every bit on the incoming
character in the middle of each data bit. On the falling edge of a start or false start bit, an internal receiver
counter starts counting at the 16X clock rate. After 8 clocks the start bit period should be at the center of the
start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in this
manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are
sampled and validated in this same manner to prevent false framing. If there were any error(s), they are
reported in the LSR register bits 2-4. Once the data is received, the error tags are immediately updated to
reflect the status of the data byte in RHR register. RHR will generate a receive data ready interrupt upon
receiving a character if IER bit-0 has been enabled.
2.11.1 Receive Holding Register (RHR) - Read-Only
The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift
Register. It provides the receive data interface to the host processor. The RHR register is part of the 1 byte
receive FIFO that is 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. After the
RHR is read, LSR bits 2-4 willl immediately be updated to reflect the errors for the next character byte
transferred from the RSR.
FIGURE 6. RECEIVER OPERATION
16X Clock
Receive Data Shift
Register (RSR)
Data Bit
Validation
Receive Data Characters
Error
Receive
Data Byte
and Errors
Receive Data
Holding Register
(RHR)
Tags in
LSR bits
4:2
RHR Interrupt (ISR bit-2)
RXFIFO1
10
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XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
2.12 Internal Loopback
The L2450 UART provides an internal loopback capability for system diagnostic purposes. The internal
loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.
Figure 7 shows how the modem port signals are re-configured. Transmit data from the transmit shift register
output is internally routed to the receive shift register input allowing the system to receive the same data that it
was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and
CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input must be held to a logic 1 during loopback
test else upon exiting the loopback test the UART may detect and report a false “break” signal.
FIGURE 7. INTERNAL LOOP BACK IN CHANNELS A AND B
VCC
TXA/TXB
Transmit Shift Register
(THR/FIFO)
MCR bit-4=1
Receive Shift Register
RXA/RXB
(RHR/FIFO)
VCC
RTSA#/RTSB#
RTS#
CTS#
CTSA#/CTSB
VCC
DTRA#/DTRB#
DTR#
DSR#
RI#
DSRA#/DSRB#
OP1#
VCC
RIA#/RIB#
OP2A#/OP2B#
OP2#
CD#
CDA#/CDB#
11
XR16L2450
2.25V TO 5.5V DUART
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REV. 1.1.1
3.0 UART INTERNAL REGISTERS
Each of the UART channel in the L2450 has its own set of configuration registers selected by address lines A0,
A1 and A2 with CSA# or CSB# selecting the channel. The registers are 16C450 compatible. The complete
register set is shown on Table 4 and Table 5.
TABLE 4: UART CHANNEL A AND B UART INTERNAL REGISTERS
A2,A1,A0 ADDRESSES
REGISTER
READ/WRITE
COMMENTS
16C550 COMPATIBLE REGISTERS
0
0 0
RHR - Receive Holding Register
Read-only
Write-only
LCR[7] = 0
LCR[7] = 1
THR - Transmit Holding Register
DLL - Div Latch Low Byte
DLM - Div Latch High Byte
DREV - Device Revision
DVID - Device ID
0
0 0
0 1
0 0
0 1
0 1
1 0
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
0
0
0
0
0
LCR[7] = 1,
DLL = 0x00, DLM = 0x00
IER - Interrupt Enable Register
LCR[7] = 0
ISR - Interrupt Status Register
Reserved
Read-only
Write-only
0
1
1
1 1
0 0
0 1
LCR - Line Control Register
Read/Write
Read/Write
MCR - Modem Control Register
LSR - Line Status Register
Reserved
Read-only
Write-only
1
1
1 0
1 1
MSR - Modem Status Register
Reserved
Read-only
Write-only
SPR - Scratch Pad Register
Read/Write
12
xr
XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
.
TABLE 5: INTERNAL REGISTERS DESCRIPTION
ADDRESS
REG
READ/
WRITE
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
COMMENT
A2-A0
NAME
16C450 Compatible Registers
0 0 0
0 0 0
0 0 1
RHR
THR
RD
Bit-7
Bit-7
0
Bit-6
Bit-6
0
Bit-5
Bit-5
0
Bit-4
Bit-4
0
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
WR
LCR[7] = 0
IER RD/WR
Modem RXLine
Stat.
Int.
TX
Empty
Int
RX
Data
Int.
Stat.
Int.
Enable Enable Enable Enable
0 1 0
0 1 1
ISR
RD
0
0
0
0
INT INT INT INT
Source Source Source Source
Bit-3
Bit-2
Bit-1
Bit-0
LCR RD/WR Divisor Set TX Set Par-
Even
Parity Enable
Parity
Stop
Bits
Word
Length Length
Word
Enable
Break
ity
Bit-1 Bit-0
1 0 0
1 0 1
MCR RD/WR
0
0
0
Internal OP2#/ Rsrvd RTS# DTR#
Loop-
back
INT
Output
Output Output
Control Control
(OP1#)
Enable Enable
LSR
RD
0
THR &
TSR
THR
Empty
RX
RX
RX
RX
RX
Break
Fram- Parity Over-
Data
Empty
ing
Error
run
Ready
Error
Error
1 1 0
1 1 1
MSR
RD
CD#
Input
RI#
Input
DSR#
Input
CTS#
Input
Delta
CD#
Delta
RI#
Delta
DSR# CTS#
Delta
SPR RD/WR
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Baud Rate Generator Divisor
0 0 0
0 0 1
0 0 0
0 0 1
DLL RD/WR
DLM RD/WR
Bit-7
Bit-7
Bit-7
0
Bit-6
Bit-6
Bit-6
0
Bit-5
Bit-5
Bit-5
0
Bit-4
Bit-4
Bit-4
0
Bit-3
Bit-3
Bit-3
0
Bit-2
Bit-2
Bit-2
0
Bit-1
Bit-1
Bit-1
1
Bit-0
Bit-0
Bit-0
0
LCR[7] = 1
DREV
DVID
RD
RD
LCR[7]=1
DLL=0x00
DLM=0x00
4.0 INTERNAL REGISTER DESCRIPTIONS
4.1 Receive Holding Register (RHR) - Read- Only
See “Receiver” on page 10.
4.2
Transmit Holding Register (THR) - Write-Only
See “Transmitter” on page 9.
4.3
Interrupt Enable Register (IER) - Read/Write
The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status
and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).
13
XR16L2450
2.25V TO 5.5V DUART
xr
REV. 1.1.1
4.3.1
Interrupt Mode Operation
When the receive interrupt (IER BIT-0 = 1) is enabled, the RHR interrupt (see ISR bit-2) status will reflect the
following:
A. The receive data available interrupts are issued to the host when there is a character in the RHR. It will be
cleared when the character has been read out of the RHR.
B. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to
the receive FIFO. It is reset when the RHR is empty.
4.3.2
Polled Mode Operation
Since the receiver and transmitter have separate bits in the LSR either or both can be used in the polled mode
by selecting respective transmit or receive control bit(s).
A. LSR BIT-0 indicates there is data in the RHR.
B. LSR BIT-1 indicates an overrun error has occurred and that data in the RHR may not be valid.
C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.
D. LSR BIT-5 indicates THR is empty.
E. LSR BIT-6 indicates when both the THR and TSR are empty.
IER[0]: RHR Interrupt Enable
The receive data ready interrupt will be issued when RHR has a data character.
• Logic 0 = Disable the receive data ready interrupt (default).
• Logic 1 = Enable the receiver data ready interrupt.
IER[1]: THR Interrupt Enable
This bit enables the Transmit Ready interrupt which is issued whenever the Transmit FIFO becomes empty. If
the Transmit FIFO is empty when this bit is enabled, an interrupt will be generated.
• Logic 0 = Disable Transmit Ready interrupt (default).
• Logic 1 = Enable Transmit Ready interrupt.
IER[2]: Receive Line Status Interrupt Enable
If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller
about the error status of the current data byte in FIFO.
• Logic 0 = Disable the receiver line status interrupt (default).
• Logic 1 = Enable the receiver line status interrupt.
IER[3]: Modem Status Interrupt Enable
• Logic 0 = Disable the modem status register interrupt (default).
• Logic 1 = Enable the modem status register interrupt.
IER[7:4]: Reserved
4.4
Interrupt Status Register (ISR) - Read-Only
The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The
Interrupt Status Register (ISR) provides the user with four interrupt status bits. Performing a read cycle on the
ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be
serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt
Source Table, Table 6, shows the data values (bits 0-3) for the interrupt priority levels and the interrupt sources
associated with each of these interrupt levels.
14
xr
XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
4.4.1
Interrupt Generation:
• LSR is by any of the LSR bits 1, 2, 3 and 4.
• RXRDY is by data byte received in RHR.
• TXRDY is by THR empty.
• MSR is by any of the MSR bits 0, 1, 2 and 3.
4.4.2
Interrupt Clearing:
• LSR interrupt is cleared by a read to the LSR register.
• RXRDY interrupt is cleared by reading data out of RHR.
• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.
• MSR interrupt is cleared by a read to the MSR register.
]
TABLE 6: INTERRUPT SOURCE AND PRIORITY LEVEL
ISR REGISTER STATUS BITS
PRIORITY LEVEL
SOURCE OF INTERRUPT
BIT-3
BIT-2
BIT-1
BIT-0
1
2
3
4
-
0
0
0
0
0
1
1
0
0
0
1
0
1
0
0
0
0
0
0
1
LSR (Receiver Line Status Register)
RXRDY (Received Data Ready)
TXRDY (Transmit Ready)
MSR (Modem Status Register)
None (default)
ISR[0]: Interrupt Status
• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt
service routine.
• Logic 1 = No interrupt pending (default condition).
ISR[3:1]: Interrupt Status
These bits indicate the source for a pending interrupt at interrupt priority levels (See Table 6).
ISR[7:4]: Reserved
4.5
Line Control Register (LCR) - Read/Write
The Line Control Register is used to specify the asynchronous data communication format. The word or
character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this
register.
15
XR16L2450
2.25V TO 5.5V DUART
xr
REV. 1.1.1
LCR[1:0]: TX and RX Word Length Select
These two bits specify the word length to be transmitted or received.
BIT-1
BIT-0
WORD LENGTH
0
0
1
1
0
1
0
1
5 (default)
6
7
8
LCR[2]: TX and RX Stop-bit Length Select
The length of stop bit is specified by this bit in conjunction with the programmed word length.
BIT-2
WORD LENGTH
STOP BIT LENGTH (BIT TIME(S))
0
1
1
5,6,7,8
5
1 (default)
1-1/2
2
6,7,8
LCR[3]: TX and RX Parity Select
Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data
integrity check. See Table 7 for parity selection summary below.
• Logic 0 = No parity.
• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the
data character received.
LCR[4]: TX and RX Parity Select
If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.
• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format (default).
• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The
receiver must be programmed to check the same format.
LCR[5]: TX and RX Parity Select
If the parity bit is enabled, LCR BIT-5 selects the forced parity format.
• LCR[5] = logic 0, parity is not forced (default).
• LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data.
• LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.
TABLE 7: PARITY SELECTION
LCR BIT-5 LCR BIT-4 LCR BIT-3
PARITY SELECTION
No parity
X
0
0
1
1
X
0
1
0
1
0
1
1
1
1
Odd parity
Even parity
Force parity to mark, “1”
Forced parity to space, “0”
16
xr
XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
LCR[6]: Transmit Break Enable
When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a
“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.
• Logic 0 = No TX break condition (default).
• Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line
break condition.
LCR[7]: Baud Rate Divisors (DLL/DLM) Enable
• Logic 0 = Data registers are selected (default).
• Logic 1 = Divisor latch registers are selected.
4.6
Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write
The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.
MCR[0]: DTR# Output
The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force DTR# output to a logic 1 (default).
• Logic 1 = Force DTR# output to a logic 0.
MCR[1]: RTS# Output
The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a
general purpose output.
• Logic 0 = Force RTS# output to a logic 1 (default).
• Logic 1 = Force RTS# output to a logic 0.
MCR[2]: Reserved
OP1# is not available as an output pin on the L2450. But it is available for use during Internal Loopback Mode.
In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.
MCR[3]: OP2# Output / INT Output Enable
This bit enables and disables the operation of INT, interrupt output. If INT output is not used, OP2# can be
used as a general purpose output.
• Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set to a logic 1 (default).
• Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set to a logic 0.
MCR[4]: Internal Loopback Enable
• Logic 0 = Disable loopback mode (default).
• Logic 1 = Enable local loopback mode, see loopback section and Figure 7.
MCR[7:5]: Reserved
4.7
Line Status Register (LSR) - Read Only
This register provides the status of data transfers between the UART and the host.
LSR[0]: Receive Data Ready Indicator
• Logic 0 = No data in receive holding register or FIFO (default).
• Logic 1 = Data has been received and is saved in the receive holding register .
17
XR16L2450
2.25V TO 5.5V DUART
xr
REV. 1.1.1
LSR[1]: Receiver Overrun Flag
• Logic 0 = No overrun error (default).
• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens
when additional data arrives while there is data in the RHR. In this case the previous data in the receive shift
register is overwritten. Note that under this condition the data byte in the receive shift register is not
transferred into the RHR, therefore the data in the RHR is not corrupted by the error. An interrupt will be
generated immediately if LSR interrupt is enabled (IER bit-2).
LSR[2]: Receive Data Parity Error Flag
• Logic 0 = No parity error (default).
• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.
This error is associated with the character available for reading in RHR. If the LSR interrupt is enabled (IER
bit-2), an interrupt will be generated when the character is in the RHR.
LSR[3]: Receive Data Framing Error Flag
• Logic 0 = No framing error (default).
• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with
the character available for reading in RHR. If the LSR interrupt is enabled (IER bit-2), an interrupt will be
generated when the character is in the RHR.
LSR[4]: Receive Break Flag
• Logic 0 = No break condition (default).
• Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). The
break indication remains until the RX input returns to the idle condition, “mark” or logic 1. If the LSR interrupt
is enabled (IER bit-2), an interrupt will be generated when the character is in the RHR.
LSR[5]: Transmit Holding Register Empty Flag
This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to
accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host
when the THR interrupt enable is set. The THR bit is set to a logic 1 when the data byte is transferred from the
transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data
loading to the transmit holding register by the host.
LSR[6]: THR and TSR Empty Flag
This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or
TSR contains a data character.
LSR[7]: Reserved
4.8
Modem Status Register (MSR) - Read Only
This register provides the current state of the modem interface signals, or other peripheral device that the
UART is connected. Lower four bits of this register are used to indicate the changed information. These bits
are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general
purpose inputs/outputs when they are not used with modem signals.
MSR[0]: Delta CTS# Input Flag
• Logic 0 = No change on CTS# input (default).
• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
18
xr
XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
MSR[1]: Delta DSR# Input Flag
• Logic 0 = No change on DSR# input (default).
• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt
will be generated if MSR interrupt is enabled (IER bit-3).
MSR[2]: Delta RI# Input Flag
• Logic 0 = No change on RI# input (default).
• Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status
interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[3]: Delta CD# Input Flag
• Logic 0 = No change on CD# input (default).
• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem
status interrupt will be generated if MSR interrupt is enabled (IER bit-3).
MSR[4]: CTS Input Status
Normally this bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to
the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem
interface is not used.
MSR[5]: DSR Input Status
Normally this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#
bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is
not used.
MSR[6]: RI Input Status
Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the
MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.
MSR[7]: CD Input Status
Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the
MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.
4.9
Scratch Pad Register (SPR) - Read/Write
This is a 8-bit general purpose register for the user to store temporary data. The content of this register is
preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.
4.10 Baud Rate Generator Registers (DLL and DLM) - Read/Write
The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is
programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’. See
“Programmable Baud Rate Generator” on page 8. for more details.
4.11 Device Identification Register (DVID) - Read Only
This register contains the device ID (0x02 for XR16L2450). Prior to reading this register, DLL and DLM should
be set to 0x00.
4.12 Device Revision Register (DREV) - Read Only
This register contains the device revision information. For example, 0x01 means revision A. Prior to reading
this register, DLL and DLM should be set to 0x00.
19
XR16L2450
2.25V TO 5.5V DUART
xr
REV. 1.1.1
TABLE 8: UART RESET CONDITIONS FOR CHANNEL A AND B
REGISTERS
DLM
DLL
RESET STATE
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0xXX
Bits 7-0 = 0x00
Bits 7-0 = 0x01
Bits 7-0 = 0x00
Bits 7-0 = 0x00
Bits 7-0 = 0x60
Bits 3-0 = Logic 0
RHR
THR
IER
ISR
LCR
MCR
LSR
MSR
Bits 7-4 = Logic levels of the inputs
inverted
SPR
I/O SIGNALS
TX
Bits 7-0 = 0xFF
RESET STATE
Logic 1
Logic 1
OP2#
Logic 1
RTS#
Logic 1
DTR#
Three-State Condition
INT
20
xr
XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
ABSOLUTE MAXIMUM RATINGS
Power Supply Range
Voltage at Any Pin
7 Volts
GND-0.3 V to VCC+0.3 V
-40o to +85oC
Operating Temperature
-65o to +150oC
500 mW
Storage Temperature
Package Dissipation
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
theta-ja =59oC/W, theta-jc = 16oC/W
Thermal Resistance (48-TQFP)
theta-ja = 50oC/W, theta-jc = 21oC/W
Thermal Resistance (44-PLCC)
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=-40O TO +85OC, VCC IS 2.25 TO 5.5V
LIMITS
2.5V
LIMITS
3.3V
LIMITS
5.0V
SYMBOL
PARAMETER
UNITS
CONDITIONS
MIN
MAX
MIN
MAX
MIN
MAX
VILCK
VIHCK
VIL
Clock Input Low Level
Clock Input High Level
Input Low Voltage
-0.3
2.0
0.2
-0.3
2.4
0.6
-0.5
3.0
0.6
V
V
V
V
5.5
0.6
5.5
5.5
0.8
5.5
5.5
0.8
5.5
0.4
-0.3
2.0
-0.3
2.0
-0.5
2.2
VIH
Input High Voltage
Output Low Voltage
VOL
V
V
V
IOL = 6 mA
IOL = 4 mA
IOL = 2 mA
0.4
0.4
VOH
Output High Voltage
2.4
V
V
V
IOH = -6 mA
IOH = -1 mA
IOH = -400 uA
2.0
1.8
IIL
IIH
Input Low Leakage Current
Input High Leakage Current
Input Pin Capacitance
±10
±10
5
±10
±10
5
±10
±10
5
uA
uA
pF
CIN
ICC
Power Supply Current
1
1.3
3
mA
21
XR16L2450
2.25V TO 5.5V DUART
xr
REV. 1.1.1
AC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA=-40O TO +85OC, VCC IS 2.25V TO 5.5V,
70 PF LOAD WHERE APPLICABLE
LIMITS
LIMITS
3.3
LIMITS
SYMBOL
PARAMETER
2.5
5.0
UNIT
MIN
MAX
MIN
MAX MIN
MAX
-
Crystal Frequency
8
16
24
MHz
ns
CLK
OSC
TAS
External Clock Low/High Time
External Clock Frequency
Address Setup Time
31
25
21
16
20
24
MHz
ns
10
10
10
10
75
75
75
10
10
50
50
50
TAH
TCS
Address Hold Time
ns
ns
Chip Select Width
150
150
150
TRD
IOR# Strobe Width
ns
TDY
Read Cycle Delay
ns
TRDV
TDD
Data Access Time
125
45
70
30
45
30
ns
Data Disable Time
0
0
0
ns
TWR
TDY
IOW# Strobe Width
150
150
25
75
75
20
10
50
50
15
10
ns
Write Cycle Delay
ns
TDS
Data Setup Time
ns
TDH
Data Hold Time
15
ns
TWDO
TMOD
TRSI
TSSI
TINT
Delay From IOW# To Output
Delay To Set Interrupt From MODEM Input
Delay To Reset Interrupt From IOR#
Delay From Stop To Set Interrupt
150
150
150
1
75
75
75
1
50
50
50
1
ns
ns
ns
Bclk
Bclk
Delay From Initial INT Reset To Transmit
Start
8
24
8
24
8
24
TWRI
TRST
N
Delay From IOW# To Reset Interrupt
Reset Pulse Width
150
75
50
ns
ns
-
40
1
40
1
40
1
216-1
216-1
216-1
Baud Rate Divisor
Bclk
Baud Clock
16X of data rate
Hz
22
xr
XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
FIGURE 8. CLOCK TIMING
CLK
CLK
EXTERNAL
CLOCK
OSC
FIGURE 9. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B
IOW #
Active
TW DO
RTS#
DTR#
Change of state
Change of state
CD#
CTS#
DSR#
Change of state
Change of state
TMOD
TMOD
Active
INT
Active
Active
Active
TRSI
IOR#
Active
Active
TMOD
Change of state
RI#
23
XR16L2450
2.25V TO 5.5V DUART
xr
REV. 1.1.1
FIGURE 10. DATA BUS READ TIMING
A0-A2
Valid Address
Valid Address
TCS
TAS
TAS
TAH
TAH
TCS
CSA#/
CSB#
TDY
TRD
TRD
IOR#
TDD
TDD
TRDV
TRDV
D0-D7
Valid Data
Valid Data
RDTm
FIGURE 11. DATA BUS WRITE TIMING
A0-A2
Valid Address
TCS
Valid Address
TCS
TAS
TAS
TAH
TAH
CSA#/
CSB#
TDY
TWR
TWR
IOW#
TDH
TDH
TDS
Valid Data
TDS
Valid Data
D0-D7
16Write
24
xr
XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
FIGURE 12. INTERRUPT TIMING FOR CHANNELS A & B
RX
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
TSSI
TSSI
TSSI
1 Byte
1 Byte
1 Byte
in RHR
in RHR
in RHR
INT
TRSI
TRSI
TRSI
IOR#
(Reading data
out of RHR)
RXNFM
FIGURE 13. INTERRUPT TIMING FOR CHANNELS A & B
TX
(Unloading)
Stop
Bit
Start
Bit
D0:D7
D0:D7
D0:D7
TINT
TINT
TINT
IER[1]
enabled
INT*
TWRI
TWRI
ISR is read
TWRI
ISR is read
ISR is read
IOW#
(Loading data
into THR)
*INT is cleared when the ISR is read or when data is loaded into the THR.
TXNonFIFO
25
XR16L2450
2.25V TO 5.5V DUART
xr
REV. 1.1.1
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)
D
D
1
36
25
37
24
D
1
D
48
13
1
1
2
B
e
A
2
C
A
Seating
Plane
α
A
1
L
Note: The control dimension is the millimeter column
INCHES
MAX
MILLIMETERS
SYMBOL
MIN
MIN
MAX
1.20
0.15
1.05
0.27
0.20
9.20
7.10
A
A1
A2
B
0.039
0.002
0.037
0.007
0.004
0.346
0.272
0.047
0.006
0.041
0.011
0.008
0.362
0.280
1.00
0.05
0.95
0.17
0.09
8.80
6.90
C
D
D1
e
0.020 BSC
0.50 BSC
L
0.018
0.030
0.45
0.75
α
0°
7°
0°
7°
26
xr
XR16L2450
2.25V TO 5.5V DUART
REV. 1.1.1
PACKAGE DIMENSIONS (44 PIN PLCC)
44 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
Rev. 1.00
C
D
Seating Plane
D1
45° x H
1
45° x H
2
A
2
2
1
44
B
1
B
e
D
D
1
D
D
3
2
R
D
3
A
1
A
Note: The control dimension is the millimeter column
INCHES
MAX
MILLIMETERS
SYMBOL
MIN
MIN
MAX
4.57
3.05
---
A
A1
A2
B
0.165
0.090
0.020
0.013
0.026
0.008
0.685
0.650
0.590
0.180
0.120
---
4.19
2.29
0.51
0.021
0.032
0.013
0.695
0.656
0.630
0.33
0.53
0.81
0.32
17.65
16.66
16.00
B1
0.66
C
D
0.19
17.40
16.51
14.99
D1
D2
D3
0.500 typ.
0.050 BSC
12.70 typ.
1.27 BSC
1.07
e
H1
0.042
0.056
0.048
0.045
1.42
1.22
1.14
H2
R
0.042
0.025
1.07
0.64
27
XR16L2450
2.25V TO 5.5V DUART
xr
REV. 1.1.1
REVISION HISTORY
DATE
November 2002
March 2003
June 2003
REVISION
DESCRIPTION
P1.0.0
P1.0.1
P1.0.2
Preliminary Datasheet.
Updated AC Electrical Characteristics.
Added Device Status to Ordering Information.
September 2003 1.0.0
Final Production Release. Updated 5V tolerance information and AC Electrical
Characteristics.
September 2004 1.1.0
Added Device Revision and Device ID registers and descriptions.
Updated the Data Access Time (TRDV) in AC Electrical Characteristics.
May 2005
1.1.1
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2005 EXAR Corporation
Datasheet May 2005.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
28
xr
XR16L2450
2.25V TO 5.5V DUART
REV.1.1.0
TABLE OF CONTENTS
GENERAL DESCRIPTION................................................................................................. 1
APPLICATIONS ............................................................................................................................................... 1
FEATURES..................................................................................................................................................... 1
FIGURE 1. XR16L2450 BLOCK DIAGRAM ......................................................................................................................................... 1
FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2
ORDERING INFORMATION ................................................................................................................................ 2
PACKAGE PIN DESCRIPTIONS ...................................................................................... 3
PIN DESCRIPTIONS ........................................................................................................................................ 3
1.0 PRODUCT DESCRIPTION .................................................................................................................... 6
2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 6
2.1 CPU INTERFACE ............................................................................................................................................. 6
FIGURE 3. XR16L2450 DATA BUS INTERCONNECTIONS.................................................................................................................. 6
2.2 5-VOLT TOLERANT INPUTS ........................................................................................................................... 6
2.3 DEVICE RESET ................................................................................................................................................ 6
2.4 DEVICE IDENTIFICATION AND REVISION .................................................................................................... 7
2.5 CHANNEL A AND B SELECTION ................................................................................................................... 7
TABLE 1: CHANNEL A AND B SELECT ............................................................................................................................................... 7
2.6 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................ 7
2.7 INTA AND INTB OUTPUTS .............................................................................................................................. 7
TABLE 2: INTA AND INTB PINS OPERATION FOR TRANSMITTER ........................................................................................................ 7
2.8 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ............................................................................. 7
FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS................................................................................................................................. 8
2.9 PROGRAMMABLE BAUD RATE GENERATOR ............................................................................................. 8
TABLE 3: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ........................................................................ 9
2.10 TRANSMITTER ............................................................................................................................................... 9
2.10.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY......................................................................................... 9
FIGURE 5. TRANSMITTER OPERATION ............................................................................................................................................... 9
2.11 RECEIVER .................................................................................................................................................... 10
2.11.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 10
FIGURE 6. RECEIVER OPERATION................................................................................................................................................... 10
2.12 INTERNAL LOOPBACK ............................................................................................................................... 11
FIGURE 7. INTERNAL LOOP BACK IN CHANNELS A AND B ................................................................................................................ 11
3.0 UART INTERNAL REGISTERS ........................................................................................................... 12
TABLE 4: UART CHANNEL A AND B UART INTERNAL REGISTERS ..................................................................................... 12
TABLE 5: INTERNAL REGISTERS DESCRIPTION................................................................................................................... 13
4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................ 13
4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 13
4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 13
4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................. 13
4.3.1 INTERRUPT MODE OPERATION .............................................................................................................................. 14
4.3.2 POLLED MODE OPERATION .................................................................................................................................... 14
4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 14
4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 15
4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 15
TABLE 6: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 15
4.5 LINE CONTROL REGISTER (LCR) - READ/WRITE ..................................................................................... 15
TABLE 7: PARITY SELECTION .......................................................................................................................................................... 16
4.6 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 17
4.7 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 17
4.8 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 18
4.9 SCRATCH PAD REGISTER (SPR) - READ/WRITE ...................................................................................... 19
4.10 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 19
4.11 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 19
4.12 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 19
TABLE 8: UART RESET CONDITIONS FOR CHANNEL A AND B.............................................................................................. 20
ABSOLUTE MAXIMUM RATINGS .................................................................................. 21
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)21
ELECTRICAL CHARACTERISTICS................................................................................ 21
I
XR16L2450
REV. 1.1.0
xr
2.25V TO 5.5V DUART
DC ELECTRICAL CHARACTERISTICS ..............................................................................................................21
AC ELECTRICAL CHARACTERISTICS ..............................................................................................................22
Unless otherwise noted: TA=-40o to +85oC, Vcc is 2.25V to 5.5V, ..........................................................................22
70 PF LOAD WHERE APPLICABLE...................................................................................................................22
FIGURE 8. CLOCK TIMING............................................................................................................................................................... 23
FIGURE 9. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................... 23
FIGURE 11. DATA BUS WRITE TIMING............................................................................................................................................. 24
FIGURE 10. DATA BUS READ TIMING.............................................................................................................................................. 24
FIGURE 12. INTERRUPT TIMING FOR CHANNELS A & B.................................................................................................................... 25
FIGURE 13. INTERRUPT TIMING FOR CHANNELS A & B.................................................................................................................... 25
PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM)...............................................26
PACKAGE DIMENSIONS (44 PIN PLCC) .......................................................................27
REVISION HISTORY.......................................................................................................................................28
TABLE OF CONTENTS ............................................................................................................I
II
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