XR16L2550IJTR-F_技术文档

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

MAY 2007

REV. 1.1.2

FEATURES

GENERAL DESCRIPTION

• 2.25 to 5.5 Volt operation

• 5 Volt tolerant inputs

1

The XR16L2550 (L2550) is a dual universal

asynchronous receiver and transmitter (UART). The

XR16L2550 is an improved version of the

ST16C2550 UART with lower operating voltages and

5 volt tolerant inputs. The L2550 provides enhanced

UART functions with 16 byte FIFOs, a modem control

interface and data rates up to 4 Mbps. Onboard

status registers provide the user with error indications

and operational status. System interrupts and modem

control features may be tailored by external software

to meet specific user requirements. Independent

programmable baud rate generators are provided to

select transmit and receive clock rates up to 3.125

Mbps. The Baud Rate Generator can be configured

for either crystal or external clock input. An internal

loopback capability allows onboard diagnostics. The

L2550 is available in a 44-pin PLCC, 48-pin TQFP

and 32-pin QFN packages. The L2550 is fabricated in

an advanced CMOS process.

• Pin-to-pin compatible to Exar’s ST16C2450,

ST16C2550 and XR16L2750 in 44-PLCC and 48-

TQFP packages

• Pin-to-pin compatible to XR16C2850 in 44-PLCC

• Pin

alike

XR16L2551,

XR16L2751

and

XR16C2850 in 48-TQFP package

• Two independent UART channels

■ Up to 3.125Mbps with external clock of 50 MHz

■ Register Set compatible to 16C550

■ 16 byte Transmit FIFO to reduce the bandwidth

requirement of the external CPU

■ 16 byte Receive FIFO with error tags to reduce

the bandwidth requirement of the external CPU

■ 4 selectable Receive FIFO interrupt trigger

NOTE: 1 Covered by U.S. Patent #5,649,122.

levels

■ Automatic RTS/CTS hardware flow control

■ Automatic Xon/Xoff software flow control

■ Wireless infrared encoder/decoder

APPLICATIONS

• Portable Appliances

• Medical Monitors

■ Full Modem Interface (CTS#, RTS#, DSR#,

• Base Stations

DTR#, RI#, CD#)

■ Programmable character lengths (5, 6, 7, 8)

• Micro Servers

with even, odd, or no parity

• Telecommunication Network Routers

• Industrial Automation Controls

• Tiny 32-QFN, no lead package (5x5x0.9mm)

• 44-PLCC and 48-TQFP packages also available

FIGURE 1. XR16L2550 BLOCK DIAGRAM

2.25 to 5.5 Volt VCC

GND

* 5 Volt Tolerant Inputs

A2:A0

D7:D0

IOR#

IOW#

UART Channel A

16 Byte TX FIFO

UART

TXA, RXA, DTRA#,

DSRA#, RTSA#,

DTSA#, CDA#, RIA#,

OP2A#

CSA#

CSB#

Regs

TX & RX

8-bit Data

Bus

Interface

INTA

INTB

BRG

16 Byte RX FIFO

TXRDYA#

TXRDYB#

RXRDYA#

RDRXYB#

TXB, RXB, DTRB#,

DSRB#, RTSB#,

CTSB#, CDB#, RIB#,

OP2B#

UART Channel B

(same as Channel A)

Reset

XTAL1

XTAL2

Crystal Osc/Buffer

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.2

FIGURE 2. PIN OUT ASSIGNMENT

RESET

DTRB#

DTRA#

RTSA#

OP2A#

RXRDYA#

INTA

D5

D6

1

2

3

4

5

6

36

35

34

33

32

31

30

29

28

27

26

25

D7

RXB

RXA

XR16L2550

48-pin TQFP

TXRDYB#

TXA

7

INTB

TXB

8

9

A0

OP2B#

A1

CSA# 10

CSB# 11

NC 12

A2

NC

1

2

3

4

5

6

7

8

24 RESET

23 RTSA#

D6

D7

INTA

INTB

A0

22

21

20

19

18

RXB

RXA

TXA

TXB

XR16L2550

32-pin QFN

A1

A2

CSA#

CSB#

17 NC

D5

D6

D7

7

8

9

39 RESET

38 DTRB#

37 DTRA#

36 RTSA#

35 OP2A#

34 RXRDYA#

33 INTA

32 INTB

31 A0

RXB 10

RXA 11

XR16L2550

44-pin PLCC

TXRDYB# 12

TXA 13

TXB 14

OP2B# 15

CSA# 16

CSB# 17

30 A1

29 A2

ORDERING INFORMATION

PART NUMBER

XR16L2550IL

XR16L2550IJ

XR16L2550IM

PACKAGE

OPERATING TEMPERATURE RANGE

-40°C to +85°C

DEVICE STATUS

Active

32-Lead QFN

44-Lead PLCC

48-Lead TQFP

-40°C to +85°C

Active

-40°C to +85°C

Active

2

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

PIN DESCRIPTIONS

Pin Description

32-QFN 44-PLCC 48-TQFP

NAME

TYPE

DESCRIPTION

PIN #

DATA BUS INTERFACE

A2

A1

A0

18

19

20

29

30

31

26

27

28

I

Address data lines [2:0]. These 3 address lines select one of the

internal registers in UART channel A/B during a data bus transac-

tion.

D7

D6

D5

D4

D3

D2

D1

D0

2

9

8

7

6

5

4

3

2

3

IO

Data bus lines [7:0] (bidirectional).

1

2

32

31

30

29

28

27

1

48

47

46

45

44

IOR#

14

24

19

I

Input/Output Read Strobe (active low). The falling edge instigates

an internal read cycle and retrieves the data byte from an internal

register pointed to by the address lines [A2:A0]. The data byte is

placed on the data bus to allow the host processor to read it on

the rising edge.

IOW#

12

20

15

Input/Output Write Strobe (active low). The falling edge instigates

an internal write cycle and the rising edge transfers the data byte

on the data bus to an internal register pointed by the address

lines.

CSA#

CSB#

INTA

7

8

16

17

33

10

11

30

I

UART channel A select (active low) to enable UART channel A in

the device for data bus operation.

UART channel B select (active low) to enable UART channel B in

the device for data bus operation.

22

O

UART channel A Interrupt output. The output state is defined by

the user and through the software setting of MCR[3]. INTA is set

to the active mode (active high) and OP2A# output to a logic 0

when MCR[3] is set to a logic 1. INTA is set to the three state

mode and OP2A# to a logic 1 when MCR[3] is set to a logic 0

(Default).

INTB

21

32

29

O

UART channel B Interrupt output. The output state is defined by

the user and through the software setting of MCR[3]. INTB is set

to the active mode and OP2B# output to a logic 0 when MCR[3] is

set to a logic 1. INTB is set to the three state mode and OP2B# to

a logic 1 when MCR[3] is set to a logic 0 (Default).

UART channel A Transmitter Ready (active low). The output

provides the TX FIFO/THR status for transmit channel A. If

it is not used, leave it unconnected.

TXRDYA#

RXRDYA#

-

1

43

31

O

34

UART channel A Receiver Ready (active low). This output pro-

vides the RX FIFO/RHR status for receive channel A. If it is not

used, leave it unconnected.

3

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

Pin Description

REV. 1.1.2

32-QFN 44-PLCC 48-TQFP

NAME

TYPE

DESCRIPTION

PIN #

TXRDYB#

-

12

6

O

UART channel B Transmitter Ready (active low). The output pro-

vides the TX FIFO/THR status for transmit channel B. If it is not

used, leave it unconnected.

RXRDYB#

-

23

18

O

UART channel B Receiver Ready (active low). This output pro-

vides the RX FIFO/RHR status for receive channel B. If it is not

used, leave it unconnected.

MODEM OR SERIAL I/O INTERFACE

TXA

5

13

7

5

O

I

UART channel A Transmit Data. If it is not used, leave it uncon-

nected.

RXA

4

11

UART channel A Receive Data. Normal receive data input must

idle at logic 1 condition. If it is not used, tie it to VCC or pull it high

via a 100k ohm resistor.

RTSA#

CTSA#

23

25

36

40

33

38

O

I

UART channel A Request-to-Send (active low) or general pur-

pose output. This output must be asserted prior to using auto

RTS flow control, see EFR[6], MCR[1] and IER[6]. If it is not

used, leave it unconnected.

UART channel A Clear-to-Send (active low) or general purpose

input. It can be used for auto CTS flow control, see EFR[7] and

IER[7]. This input should be connected to VCC when not used.

DTRA#

DSRA#

-

37

41

34

39

O

I

UART channel A Data-Terminal-Ready (active low) or general

purpose output. If it is not used, leave it unconnected.

UART channel A Data-Set-Ready (active low) or general purpose

input. This input should be connected to VCC when not used.

This input has no effect on the UART.

CDA#

RIA#

-

42

43

35

40

41

32

I

UART channel A Carrier-Detect (active low) or general purpose

input. This input should be connected to VCC when not used.

This input has no effect on the UART.

UART channel A Ring-Indicator (active low) or general purpose

input. This input should be connected to VCC when not used.

This input has no effect on the UART.

OP2A#

O

Output Port 2 Channel A - The output state is defined by the user

and through the software setting of MCR[3]. INTA is set to the

active mode and OP2A# output to a logic 0 when MCR[3] is set to

a logic 1. INTA is set to the three state mode and OP2A# to a

logic 1 when MCR[3] is set to a logic 0. This output should not be

used as a general output else it will disturb the INTA output func-

tionality. If it is not used at all, leave it unconnected.

TXB

RXB

6

3

14

10

8

4

O

I

UART channel B Transmit Data. If it is not used, leave it uncon-

nected.

UART channel B Receive Data. Normal receive data input must

idle at logic 1 condition. If it is not used, tie it to VCC or pull it high

via a 100k ohm resistor.

4

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

Pin Description

32-QFN 44-PLCC 48-TQFP

NAME

TYPE

DESCRIPTION

PIN #

RTSB#

15

27

22

O

UART channel B Request-to-Send (active low) or general pur-

pose output. This output must be asserted prior to using auto

RTS flow control, see EFR[6], MCR[1] and IER[6]. If it is not

used, leave it unconnected.

CTSB#

16

28

23

I

UART channel B Clear-to-Send (active low) or general purpose

input. It can be used for auto CTS flow control, see EFR[7] and

IER[7]. This input should be connected to VCC when not used.

DTRB#

DSRB#

-

38

25

35

20

O

I

UART channel B Data-Terminal-Ready (active low) or general

purpose output. If it is not used, leave it unconnected.

UART channel B Data-Set-Ready (active low) or general purpose

input. This input should be connected to VCC when not used.

This input has no effect on the UART.

CDB#

RIB#

-

21

26

15

16

21

9

I

UART channel B Carrier-Detect (active low) or general purpose

input. This input should be connected to VCC when not used.

This input has no effect on the UART.

UART channel B Ring-Indicator (active low) or general purpose

input. This input should be connected to VCC when not used.

This input has no effect on the UART.

OP2B#

O

Output Port 2 Channel B - The output state is defined by the user

and through the software setting of MCR[3]. INTB is set to the

active mode and OP2B# output to a logic 0 when MCR[3] is set to

a logic 1. INTB is set to the three state mode and OP2B# to a

logic 1 when MCR[3] is set to a logic 0. This output should not be

used as a general output else it will disturb the INTB output func-

tionality. If it is not used, leave it unconnected.

ANCILLARY SIGNALS

XTAL1

XTAL2

RESET

10

11

24

18

19

39

13

14

36

I

O

I

Crystal or external clock input.

Crystal or buffered clock output.

Reset (active high) - A longer than 40 ns logic 1 pulse on this pin

will reset the internal registers and all outputs. The UART trans-

mitter output will be held at logic 1, the receiver input will be

ignored and outputs are reset during reset period.

VCC

26

13

44

42

Pwr 2.25V to 5.5V power supply. All inputs are 5V tolerant.

Pwr Power supply common, ground.

GND

22

17

Center

Pad

N/A

Pwr

The center pad on the backside of the 32-QFN package is metal-

lic and should be connected to GND on the PCB. The thermal

pad size on the PCB should be the approximate size of this cen-

ter pad and should be solder mask defined. The solder mask

opening should be at least 0.0025" inwards from the edge of the

PCB thermal pad.

N.C.

9, 17

-

12, 24,

25, 37

No Connection. These pins are open, but typically, should be con-

nected to GND for good design practice.

Pin type: I=Input, O=Output, IO= Input/output, OD=Output Open Drain.

5

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

1.0 PRODUCT DESCRIPTION

REV. 1.1.2

The XR16L2550 (L2550) provides serial asynchronous receive data synchronization, parallel-to-serial and

serial-to-parallel data conversions for both the transmitter and receiver sections. These functions are

necessary for converting the serial data stream into parallel data that is required with digital data systems.

Synchronization for the serial data stream is accomplished by adding start and stop bits to the transmit data to

form a data character (character orientated protocol). Data integrity is ensured by attaching a parity bit to the

data character. The parity bit is checked by the receiver for any transmission bit errors. The electronic circuitry

to provide all these functions is fairly complex especially when manufactured on a single integrated silicon

chip. The L2550 represents such an integration with greatly enhanced features. The L2550 is fabricated with

an advanced CMOS process.

Transmit and Receive FIFOs (16 Bytes each)

The L2550 is an upward solution that provides a dual UART capability with 16 bytes of transmit and receive

FIFO memory, instead of none in the 16C2450. The L2550 is designed to work with high speed modems and

shared network environments, that require fast data processing time. Increased performance is realized in the

L2550 by the transmit and receive FIFO’s. This allows the external processor to handle more networking tasks

within a given time. For example, the ST16C2450 without a receive FIFO, will require unloading of the RHR in

93 microseconds (This example uses a character length of 11 bits, including start/stop bits at 115.2 Kbps). This

means the external CPU will have to service the receive FIFO less than every 100 microseconds. However

with the 16 byte FIFO in the L2550, the data buffer will not require unloading/loading for 1.53 ms. This

increases the service interval giving the external CPU additional time for other applications and reducing the

overall UART interrupt servicing time. In addition, the 4 selectable receive FIFO trigger interrupt levels is

uniquely provided for maximum data throughput performance especially when operating in a multi-channel

environment. The FIFO memory greatly reduces the bandwidth requirement of the external controlling CPU,

increases performance, and reduces power consumption.

Data Rate

The L2550 is capable of operation up to 3.125 Mbps with a 50 MHz clock. With a crystal or external clock input

of 14.7456 MHz the user can select data rates up to 921.6 Kbps.

Enhanced Features

The XR16L2550 integrates the functions of 2 enhanced 16C550 Universal Asynchronous Receiver and

Transmitter (UART). Each UART is independently controlled having its own set of device configuration

registers. The configuration registers set is 16550 UART compatible for control, status and data transfer.

Additionally, each UART channel has automatic RTS/CTS hardware flow control, automatic Xon/Xoff and

special character software flow control, infrared encoder and decoder (IrDA ver 1.0), programmable baud rate

generator with a prescaler of divide by 1 or 4, and data rate up to 4 Mbps at 5V.

The rich feature set of the L2550 is available through internal registers. Selectable receive FIFO trigger levels,

selectable TX and RX baud rates, and modem interface controls are all standard features. Following a power

on reset or an external reset, the L2550 is functionally and software compatible with the previous generation

ST16C2450 and ST16C2550.

6

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

2.0 FUNCTIONAL DESCRIPTIONS

2.1

CPU Interface

The CPU interface is 8 data bits wide with 3 address lines and control signals to execute data bus read and

write transactions. The L2550 data interface supports the Intel compatible types of CPUs and it is compatible to

the industry standard 16C550 UART. No clock (oscillator nor external clock) is required to operate a data bus

transaction. Each bus cycle is asynchronous using CS#, IOR# and IOW# signals. Both UART channels share

the same data bus for host operations. The data bus interconnections are shown in Figure 3.

FIGURE 3. XR16L2550 DATA BUS INTERCONNECTIONS

VCC

D0

D1

D2

D3

D4

D5

D6

D7

D0

D1

D2

D3

D4

D5

D6

D7

TXA

RXA

DTRA#

RTSA#

CTSA#

DSRA#

UART

Channel A

RS-232 Serial Interface

A0

A1

A2

A0

A1

A2

CDA#

RIA#

OP2A#

IOR#

IOW#

IOR#

IOW#

TXB

RXB

CSA#

CSB#

UART_CSA#

UART_CSB#

DTRB#

RTSB#

CTSB#

DSRB#

CDB#

UART_INTA

UART_INTB

INTA

INTB

UART

Channel B

RS-232 Serial Interface

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

TXRDYA#

RXRDYA#

TXRDYB#

RXRDYB#

RIB#

OP2B#

UART_RESET

RESET

GND

.

2.2

5-Volt Tolerant Inputs

The L2550 can accept up to 5V inputs even when operating at 3.3V or 2.5V. But note that if the L2550 is

operating at 2.5V, its V may not be high enough to meet the requirements of the V of a CPU or a serial

OH

IH

transceiver that is operating at 5V.

2.3 Device Reset

The RESET input resets the internal registers and the serial interface outputs in both channels to their default

state (see Table 13). An active high pulse of at least 40 ns duration will be required to activate the reset

function in the device.

2.4

Device Identification and Revision

The L2550 provides a Device Identification code and a Device Revision code to distinguish the part from other

devices and revisions. To read the identification code from the part, it is required to set the baud rate generator

registers DLL and DLM both to 0x00. Now reading the content of the DLM will provide 0x02 to indicate L2550

and reading the content of DLL will provide the revision of the part; for example, a reading of 0x01 means

revision A.

2.5

Channel A and B Selection

The UART provides the user with the capability to bi-directionally transfer information between an external

CPU and an external serial communication device. A logic 0 on chip select pins, CSA# or CSB#, allows the

user to select UART channel A or B to configure, send transmit data and/or unload receive data to/from the

UART. Selecting both UARTs can be useful during power up initialization to write to the same internal registers,

7

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.2

but do not attempt to read from both uarts simultaneously. Individual channel select functions are shown in

Table 1.

TABLE 1: CHANNEL A AND B SELECT

CSA#

CSB#

FUNCTION

1

0

1

0

1

0

UART de-selected

Channel A selected

Channel B selected

Channel A and B selected

2.6

Channel A and B Internal Registers

Each UART channel in the L2550 has a standard register set for controlling, monitoring and data loading and

unloading. The configuration register set is compatible to those already available in the standard single

16C550. These registers function as data holding registers (THR/RHR), interrupt status and control registers

(ISR/IER), a FIFO control register (FCR), receive line status and control registers (LSR/LCR), modem status

and control registers (MSR/MCR), programmable data rate (clock) divisor registers (DLL/DLM), and a user

accessible scratch pad register (SPR).

2.7

DMA Mode

The device does not support direct memory access. The DMA Mode (a legacy term) in this document doesn’t

mean “direct memory access” but refers to data block transfer operation. The DMA mode affects the state of

the RXRDY# A/B and TXRDY# A/B output pins. The transmit and receive FIFO trigger levels provide additional

flexibility to the user for block mode operation. The LSR bits 5-6 provide an indication when the transmitter is

empty or has an empty location(s) for more data. The user can optionally operate the transmit and receive

FIFO in the DMA mode (FCR bit-3=1). When the transmit and receive FIFO are enabled and the DMA mode is

disabled (FCR bit-3 = 0), the L2550 is placed in single-character mode for data transmit or receive operation.

When DMA mode is enabled (FCR bit-3 = 1), the user takes advantage of block mode operation by loading or

unloading the FIFO in a block sequence determined by the programmed trigger level. The following table show

their behavior. Also see Figure 18 through Figure 23.

TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE

FCR BIT-0=0

PINS

FCR BIT-0=1 (FIFO ENABLED)

(FIFO DISABLED)

FCR Bit-3 = 0

FCR Bit-3 = 1

(DMA Mode Disabled)

(DMA Mode Enabled)

RXRDY# A/B 0 = 1 byte.

1 = no data.

0 = at least 1 byte in FIFO

1 = FIFO empty.

1 to 0 transition when FIFO reaches the trigger

level, or time-out occurs.

0 to 1 transition when FIFO empties.

TXRDY# A/B 0 = THR empty.

1 = byte in THR.

0 = FIFO empty.

0 = FIFO has at least 1 empty location.

1 = FIFO is full.

1 = at least 1 byte in FIFO.

2.8

INTA and INTB Outputs

The INTA and INTB interrupt output changes according to the operating mode and enhanced features setup.

Table 3 and Table 4 summarize the operating behavior for the transmitter and receiver. Also see Figure 18

through Figure 23.

8

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER

FCR BIT-0 = 0

FCR BIT-0 = 1

(FIFO DISABLED)

(FIFO ENABLED)

INTA/B Pin

0 = a byte in THR

1 = THR empty

0 = at least 1 byte in FIFO

1 = FIFO empty

TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER

FCR BIT-0 = 0

FCR BIT-0 = 1

(FIFO DISABLED)

(FIFO ENABLED)

INTA/B Pin

0 = no data

1 = 1 byte

0 = FIFO below trigger level

1 = FIFO above trigger level

2.9

Crystal Oscillator or External Clock Input

The L2550 includes an on-chip oscillator (XTAL1 and XTAL2) to produce a clock for both UART sections in the

device. The CPU data bus does not require this clock for bus operation. The crystal oscillator provides a

system clock to the Baud Rate Generators (BRG) section found in each of the UART. XTAL1 is the input to the

oscillator or external clock buffer input with XTAL2 pin being the output. For programming details, see

“Programmable Baud Rate Generator.”

FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS

XTAL1

XTAL2

R1

0-120 Ω

(Optional)

R2

500 ΚΩ − 1 ΜΩ

1.8432 MHz

to

Y1

24 MHz

C1

C2

22-47 pF

The on-chip oscillator is designed to use an industry standard microprocessor crystal (parallel resonant,

fundamental frequency with 10-22 pF capacitance load, ESR of 20-120 ohms and 100 ppm frequency

tolerance) connected externally between the XTAL1 and XTAL2 pins (see Figure 4), with an external 500 kΩ

to 1 MΩ resistor across it. Alternatively, an external clock can be connected to the XTAL1 pin to clock the

internal baud rate generator for standard or custom rates. Typical oscillator connections are shown in Figure 4.

For further reading on oscillator circuit please see application note DAN108 on EXAR’s web site.

9

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

2.10 Programmable Baud Rate Generator

REV. 1.1.2

A single baud rate generator is provided for the transmitter and receiver, allowing independent TX/RX channel

control. The programmable Baud Rate Generator is capable of operating with a crystal frequency of up to 24

MHz. However, with an external clock input on XTAL1 pin and a 2K ohms pull-up resistor on XTAL2 pin (as

shown in Figure 5) it can extend its operation up to 64 MHz (4Mbps serial data rate) at room temperature and

5.0V.

FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE

External Clock

vcc

XTAL1

gnd

VCC

R1

2K

XTAL2

To obtain maximum data rate, it is necessary to use full rail swing on the clock input. See external clock

operating frequency over power supply voltage chart in Figure 6.

FIGURE 6. OPERATING FREQUENCY CHART. REQUIRES A 2K OHMS PULL-UP RESISTOR

ON XTAL2 PIN TO INCREASE OPERATING SPEED

Operating frequency for XR16L2550

with external clock and a 2K ohms

pull-up resistor on XTAL2 pin.

80

-40^oC

25^oC

70

60

85^oC

50

40

30

3.0 3.5 4.0 4.5 5.0 5.5

Suppy Voltage

10

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

The L2550 divides the basic external clock by 16. The basic 16X clock provides table rates to support standard

and custom applications using the same system design. The Baud Rate Generator divides the input 16X clock

16

by any divisor from 1 to 2 -1. The rate table is configured via the DLL and DLM internal register functions.

Customized Baud Rates can be achieved by selecting the proper divisor values for the MSB and LSB sections

of baud rate generator.

Table 5 shows the standard data rates available with a 14.7456 MHz crystal or external clock at 16X sampling

rate. When using a non-standard frequency crystal or external clock, the divisor value can be calculated for

DLL/DLM with the following equation.

divisor (decimal) = (XTAL1 clock frequency) / (serial data rate x 16)

TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK

DATA RATE

ERROR (%)

OUTPUT Data Rate

MCR Bit-7=0

DIVISOR FOR 16x

Clock (Decimal)

DIVISOR FOR 16x

Clock (HEX)

DLM PROGRAM

VALUE (HEX)

DLL PROGRAM

VALUE (HEX)

400

2304

384

192

96

48

24

12

6

900

180

C0

60

09

01

00

80

C0

60

30

18

0C

06

04

02

01

0

2400

4800

9600

19.2k

38.4k

76.8k

153.6k

230.4k

460.8k

921.6k

30

18

0C

06

4

04

2

02

1

01

2.11 Transmitter

The transmitter section comprises of an 8-bit Transmit Shift Register (TSR) and 16 bytes of FIFO which

includes a byte-wide Transmit Holding Register (THR). TSR shifts out every data bit with the 16X internal

clock. A bit time is 16 clock periods. The transmitter sends the start-bit followed by the number of data bits,

inserts the proper parity-bit if enabled, and adds the stop-bit(s). The status of the FIFO and TSR are reported in

the Line Status Register (LSR bit-5 and bit-6).

2.11.1 Transmit Holding Register (THR) - Write Only

The transmit holding register is an 8-bit register providing a data interface to the host processor. The host

writes transmit data byte to the THR to be converted into a serial data stream including start-bit, data bits,

parity-bit and stop-bit(s). The least-significant-bit (Bit-0) becomes first data bit to go out. The THR is the input

register to the transmit FIFO of 16 bytes when FIFO operation is enabled by FCR bit-0. Every time a write

operation is made to the THR, the FIFO data pointer is automatically bumped to the next sequential data

location.

2.11.2 Transmitter Operation in non-FIFO Mode

The host loads transmit data to THR one character at a time. The THR empty flag (LSR bit-5) is set when the

data byte is transferred to TSR. THR flag can generate a transmit empty interrupt (ISR bit-1) when it is enabled

by IER bit-1. The TSR flag (LSR bit-6) is set when TSR becomes completely empty.

11

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.2

FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE

Transmit

Holding

Register

(THR)

Data

Byte

THR Interrupt (ISR bit-1)

Enabled by IER bit-1

16X Clock

M

S

B

L

S

B

Transmit Shift Register (TSR)

TXNOFIFO1

2.11.3 Transmitter Operation in FIFO Mode

The host may fill the transmit FIFO with up to 16 bytes of transmit data. The THR empty flag (LSR bit-5) is set

whenever the FIFO is empty. The THR empty flag can generate a transmit empty interrupt (ISR bit-1) when the

transmit empty interrupt is enabled by IER bit-1. The TSR flag (LSR bit-6) is set when the FIFO and the TSR

become empty.

FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE

Transmit

FIFO

Transmit

Data Byte

THR Interrupt (ISR bit-1) falls

below the programmed Trigger

Level and then when becomes

empty. FIFO is Enabled by FCR

bit-0=1

Auto CTS Flow Control (CTS# pin)

Flow Control Characters

(Xoff1/2 and Xon1/2 Reg.

Auto Software Flow Control

16X Clock

Transmit Data Shift Register

(TSR)

TXFIFO1

2.12 Receiver

The receiver section contains an 8-bit Receive Shift Register (RSR) and 16 bytes of FIFO which includes a

byte-wide Receive Holding Register (RHR). The RSR uses the 16X for timing. It verifies and validates every bit

on the incoming character in the middle of each data bit. On the falling edge of a start or false start bit, an

internal receiver counter starts counting at the 16X. After 8 clocks the start bit period should be at the center of

the start bit. At this time the start bit is sampled and if it is still a logic 0 it is validated. Evaluating the start bit in

this manner prevents the receiver from assembling a false character. The rest of the data bits and stop bits are

sampled and validated in this same manner to prevent false framing. If there were any error(s), they are

reported in the LSR register bits 2-4. Upon unloading the receive data byte from RHR, the receive FIFO pointer

is bumped and the error tags are immediately updated to reflect the status of the data byte in RHR register.

RHR can generate a receive data ready interrupt upon receiving a character or delay until it reaches the FIFO

trigger level. Furthermore, data delivery to the host is guaranteed by a receive data ready time-out interrupt

12

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

when data is not received for 4 word lengths as defined by LCR[1:0] plus 12 bits time. This is equivalent to 3.7-

4.6 character times. The RHR interrupt is enabled by IER bit-0.

2.12.1 Receive Holding Register (RHR) - Read-Only

The Receive Holding Register is an 8-bit register that holds a receive data byte from the Receive Shift

Register. It provides the receive data interface to the host processor. The RHR register is part of the receive

FIFO of 16 bytes by 11-bits wide, the 3 extra bits are for the 3 error tags to be reported in LSR register. When

the FIFO is enabled by FCR bit-0, the RHR contains the first data character received by the FIFO. After the

RHR is read, the next character byte is loaded into the RHR and the errors associated with the current data

byte are immediately updated in the LSR bits 2-4.

FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE

16X Clock

Receive Data Shift

Register (RSR)

Data Bit

Validation

Receive Data Characters

Error

Receive

Data Byte

and Errors

Receive Data

Holding Register

(RHR)

Tags in

LSR bits

4:2

RHR Interrupt (ISR bit-2)

RXFIFO1

FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE

16X Clock

Receive Data Shift

Register (RSR)

Data Bit

Validation

Receive Data Characters

Example

:

- RX FIFO trigger level selected at 8 bytes

16 bytes by 11-bit

wide

RTS# re-asserts when data falls below the flow

control trigger level to restart remote transmitter.

Enable by EFR bit-6=1, MCR bit-2.

FIFO

Data falls to 4

FIFO Trigger=8

Data fills to 14

Receive

Data FIFO

RHR Interrupt (ISR bit-2) programmed for

desired FIFO trigger level.

FIFO is Enabled by FCR bit-0=1

RTS# de-asserts when data fills above the flow

control trigger level to suspend remote transmitter.

Enable by EFR bit-6=1, MCR bit-2.

Receive

Data

Receive Data

Byte and Errors

RXFIFO1

13

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

2.13 Auto RTS (Hardware) Flow Control

REV. 1.1.2

Automatic RTS hardware flow control is used to prevent data overrun to the local receiver FIFO. The RTS#

output is used to request remote unit to suspend/resume data transmission. The auto RTS flow control

features is enabled to fit specific application requirement (see Figure 11):

• Enable auto RTS flow control using EFR bit-6.

• The auto RTS function must be started by asserting RTS# output pin (MCR bit-1 to logic 1 after it is enabled).

If using the Auto RTS interrupt:

• Enable RTS interrupt through IER bit-6 (after setting EFR bit-4). The UART issues an interrupt when the

RTS# pin makes a transition from low to high: ISR bit-5 will be set to logic 1.

2.14

Auto CTS Flow Control

Automatic CTS flow control is used to prevent data overrun to the remote receiver FIFO. The CTS# input is

monitored to suspend/restart the local transmitter. The auto CTS flow control feature is selected to fit specific

application requirement (see Figure 11):

• Enable auto CTS flow control using EFR bit-7.

If using the Auto CTS interrupt:

• Enable CTS interrupt through IER bit-7 (after setting EFR bit-4). The UART issues an interrupt when the

CTS# pin is de-asserted (HIGH): ISR bit-5 will be set to 1, and UART will suspend transmission as soon as

the stop bit of the character in process is shifted out. Transmission is resumed after the CTS# input is re-

asserted (LOW), indicating more data may be sent.

14

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION

Local UART

UARTA

Remote UART

UARTB

RXA

TXB

Receiver FIFO

Trigger Reached

Transmitter

RTSA#

TXA

CTSB#

Auto RTS

Trigger Level

Auto CTS

Monitor

RXB

Receiver FIFO

Trigger Reached

Transmitter

CTSA#

RTSB#

Auto CTS

Monitor

Auto RTS

Trigger Level

Assert RTS# to Begin

Transmission

1

10

11

ON

RTSA#

OFF

7

2

ON

3

CTSB#

TXB

8

Restart

9

Data Starts

6

Suspend

4

RXA FIFO

Receive

Data

RX FIFO

12

RTS High

Threshold

RTS Low

Threshold

5

RX FIFO

Trigger Level

INTA

(RXA FIFO

Interrupt)

RTSCTS1

The local UART (UARTA) starts data transfer by asserting RTSA# (1). RTSA# is normally connected to CTSB# (2) of

remote UART (UARTB). CTSB# allows its transmitter to send data (3). TXB data arrives and fills UARTA receive FIFO

(4). When RXA data fills up to its receive FIFO trigger level, UARTA activates its RXA data ready interrupt (5) and con-

tinues to receive and put data into its FIFO. If interrupt service latency is long and data is not being unloaded, UARTA

monitors its receive data fill level to match the upper threshold of RTS delay and de-assert RTSA# (6). CTSB# follows

(7) and request UARTB transmitter to suspend data transfer. UARTB stops or finishes sending the data bits in its trans-

mit shift register (8). When receive FIFO data in UARTA is unloaded to match the lower threshold of RTS delay (9),

UARTA re-asserts RTSA# (10), CTSB# recognizes the change (11) and restarts its transmitter and data flow again until

next receive FIFO trigger (12). This same event applies to the reverse direction when UARTA sends data to UARTB

with RTSB# and CTSA# controlling the data flow.

15

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

2.15 Auto Xon/Xoff (Software) Flow Control

REV. 1.1.2

When software flow control is enabled (See Table 12), the L2550 compares one or two sequential receive data

characters with the programmed Xon or Xoff-1,2 character value(s). If receive character(s) (RX) match the

programmed values, the L2550 will halt transmission (TX) as soon as the current character has completed

transmission. When a match occurs, the Xoff (if enabled via IER bit-5) flag will be set and the interrupt output

pin will be activated. Following a suspension due to a match of the Xoff character, the L2550 will monitor the

receive data stream for a match to the Xon-1,2 character. If a match is found, the L2550 will resume operation

and clear the flags (ISR bit-4).

Reset initially sets the contents of the Xon/Xoff 8-bit flow control registers to a logic 0. Following reset the user

can write any Xon/Xoff value desired for software flow control. Different conditions can be set to detect Xon/

Xoff characters (See Table 12) and suspend/resume transmissions. When double 8-bit Xon/Xoff characters

are selected, the L2550 compares two consecutive receive characters with two software flow control 8-bit

values (Xon1, Xon2, Xoff1, Xoff2) and controls TX transmissions accordingly. Under the above described flow

control mechanisms, flow control characters are not placed (stacked) in the user accessible RX data buffer or

FIFO.

In the event that the receive buffer is overfilling and flow control needs to be executed, the L2550 automatically

sends an Xoff message (when enabled) via the serial TX output to the remote modem. The L2550 sends the

Xoff-1,2 characters two-character-times (= time taken to send two characters at the programmed baud rate)

after the receive FIFO crosses the programmed trigger level. To clear this condition, the L2550 will transmit the

programmed Xon-1,2 characters as soon as receive FIFO is less than one trigger level below the programmed

trigger level. See Table 6 below.

TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL

XOFF CHARACTER(S) SENT

(CHARACTERS IN RX FIFO)

XON CHARACTER(S) SENT

(CHARACTERS IN RX FIFO)

RX TRIGGER LEVEL

INT PIN ACTIVATION

1

4

1

4

1*

4*

0

1

4

8

8*

14

14*

* After the trigger level is reached, an xoff character is sent after a short span of time (= time required to send 2

characters); for example, after 2.083ms has elapsed for 9600 baud and 8-bit word length, no parity and 1 stop bit setting.

2.16

Special Character Detect

A special character detect feature is provided to detect an 8-bit character when bit-5 is set in the Enhanced

Feature Register (EFR). When this character (Xoff2) is detected, it will be placed in the FIFO along with normal

incoming RX data.

The L2550 compares each incoming receive character with Xoff-2 data. If a match exists, the received data will

be transferred to FIFO and ISR bit-4 will be set to indicate detection of special character. Although the Internal

Register Table shows Xon, Xoff Registers with eight bits of character information, the actual number of bits is

dependent on the programmed word length. Line Control Register (LCR) bits 0-1 defines the number of

character bits, i.e., either 5 bits, 6 bits, 7 bits, or 8 bits. The word length selected by LCR bits 0-1 also

determines the number of bits that will be used for the special character comparison. Bit-0 in the Xon, Xoff

Registers corresponds with the LSB bit for the receive character.

16

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

2.17 Infrared Mode

The L2550 UART includes the infrared encoder and decoder compatible to the IrDA (Infrared Data

Association) version 1.0. The IrDA 1.0 standard that stipulates the infrared encoder sends out a 3/16 of a bit

wide HIGH-pulse for each “0” bit in the transmit data stream. This signal encoding reduces the on-time of the

infrared LED, hence reduces the power consumption. See Figure 12 below.

The infrared encoder and decoder are enabled by setting MCR register bit-6 to a ‘1’. When the infrared feature

is enabled, the transmit data output, TX, idles at logic zero level. Likewise, the RX input assumes an idle level

of logic zero from a reset and power up, see Figure 12.

Typically, the wireless infrared decoder receives the input pulse from the infrared sensing diode on the RX pin.

Each time it senses a light pulse, it returns a logic 1 to the data bit stream.

FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING

Character

Data Bits

1

0

TX Data

Transmit

IR Pulse

(TX Pin)

1/2 Bit Time

Bit Time

3/16 Bit Time

IrEncoder-1

Receive

IR Pulse

(RX pin)

Bit Time

1/16 Clock Delay

1

1 1

1

0

RX Data

Data Bits

Character

IRdecoder-

17

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.2

2.18

Sleep Mode with Auto Wake-Up

The L2550 supports low voltage system designs, hence, a sleep mode is included to reduce its power

consumption when the chip is not actively used.

All of these conditions must be satisfied for the L2550 to enter sleep mode:

■ no interrupts pending for both channels of the L2550 (ISR bit-0 = 1)

■ divisor is a non-zero value (ie. DLL = 0x1)

■ sleep mode of both channels are enabled (IER bit-4 = 1)

■ modem inputs are not toggling (MSR bits 0-3 = 0)

■ RX input pins are idling at a logic 1

The L2550 stops its crystal oscillator to conserve power in the sleep mode. User can check the XTAL2 pin for

no clock output as an indication that the device has entered the sleep mode.

The L2550 resumes normal operation by any of the following:

■ a receive data start bit transition (logic 1 to 0)

■ a data byte is loaded to the transmitter, THR or FIFO

■ a change of logic state on any of the modem or general purpose serial inputs: CTS#, DSR#, CD#, RI#

If the L2550 is awakened by any one of the above conditions, it will return to the sleep mode automatically after

all interrupting conditions have been serviced and cleared. If the 2750 is awakened by the modem inputs, a

read to the MSR is required to reset the modem inputs. In any case, the sleep mode will not be entered while

an interrupt is pending from channel A or B. The L2550 will stay in the sleep mode of operation until it is

disabled by setting IER bit-4 to a logic 0.

If the address lines, data bus lines, IOW#, IOR#, CSA#, CSB#, and modem input lines remain steady when the

L2550 is in sleep mode, the maximum current will be in the microamp range as specified in the DC Electrical

Characteristics on page 34. If the input lines are floating or are toggling while the L2550 is in sleep mode, the

current can be up to 100 times more. If any of those signals are toggling or floating, then an external buffer

would be required to keep the address, data and control lines steady to achieve the low current. As an

alternative, please refer to the XR16L2551 which is pin-to-pin and software compatible with the L2550 but with

(some additional pins and) the PowerSave feature that eliminates any unnecessary external buffer.

Important: owing to the starting up delay of the crystal oscillator after waking up from sleep mode, the first few

receive characters may be lost. The number of characters lost during the restart also depends on your

operating data rate. More characters are lost when operating at higher data rate. Also, it is important to keep

RX A/B inputs idling at logic 1 or “marking” condition during sleep mode to avoid receiving a “break” condition

upon the restart. This may occur when the external interface transceivers (RS-232, RS-485 or another type)

are also put to sleep mode and cannot maintain the “marking” condition. To avoid this, the designer can use a

47k-100k ohm pull-up resistor on the RXA and RXB pins.

18

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

2.19

Internal Loopback

The L2550 UART provides an internal loopback capability for system diagnostic purposes. The internal

loopback mode is enabled by setting MCR register bit-4 to logic 1. All regular UART functions operate normally.

Figure 13 shows how the modem port signals are re-configured. Transmit data from the transmit shift register

output is internally routed to the receive shift register input allowing the system to receive the same data that it

was sending. The TX pin is held at logic 1 or mark condition while RTS# and DTR# are de-asserted, and

CTS#, DSR# CD# and RI# inputs are ignored. Caution: the RX input pins must be held to a logic 1 during

loopback test else upon exiting the loopback test the UART may detect and report a false “break” signal. Also,

Auto RTS/CTS is not supported during internal loopback.

FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B

VCC

TXA/TXB

Transmit Shift Register

(THR/FIFO)

MCR bit-4=1

Receive Shift Register

(RHR/FIFO)

RXA/RXB

VCC

RTSA#/RTSB#

RTS#

CTS#

CTSA#/CTSB#

VCC

DTRA#/DTRB#

DTR#

DSR#

DSRA#/DSRB#

OP1#

RI#

RIA#/RIB#

VCC

OP2A#/OP2B#

OP2#

CD#

CDA#/CDB#

19

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

3.0 UART INTERNAL REGISTERS

REV. 1.1.2

Each of the UART channel in the L2550 has its own set of configuration registers selected by address lines A0,

A1 and A2 with CSA# or CSB# selecting the channel. The registers are 16C550 compatible. The complete

register set is shown on Table 7 and Table 8.

TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS

A2,A1,A0 ADDRESSES

REGISTER

READ/WRITE

COMMENTS

16C550 COMPATIBLE REGISTERS

0

0 0

RHR - Receive Holding Register

Read-only

Write-only

LCR[7] = 0

THR - Transmit Holding Register

DLL - Div Latch Low Byte

DLM - Div Latch High Byte

DREV - Device Revision

DVID - Device ID

0

0 0

0 1

0 0

0 1

1 0

Read/Write

LCR[7] = 1, LCR ≠ 0xBF

0

LCR[7] = 1, LCR ≠ 0xBF,

DLL = 0x00, DLM = 0x00

IER - Interrupt Enable Register

LCR[7] = 0

ISR - Interrupt Status Register

FCR - FIFO Control Register

Read-only

Write-only

LCR ≠ 0xBF

0

1

1 1

0 0

0 1

LCR - Line Control Register

Read/Write

MCR - Modem Control Register

LSR - Line Status Register

Reserved

Read-only

Write-only

LCR ≠ 0xBF

1

1 0

1 1

MSR - Modem Status Register

Reserved

Read-only

Write-only

SPR - Scratch Pad Register

Read/Write

ENHANCED REGISTERS

0

1

1 0

0 0

0 1

1 0

1 1

EFR - Enhanced Function Register

Xon-1 - Xon Character 1

Xon-2 - Xon Character 2

Xoff-1 - Xoff Character 1

Xoff-2 - Xoff Character 2

Read/Write

LCR = 0xBF

20

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1

ADDRESS

REG

READ/

WRITE

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

COMMENT

A2-A0

NAME

16C550 Compatible Registers

0 0 0

0 0 1

RHR

THR

RD

Bit-7

0/

Bit-6

0/

Bit-5

0/

Bit-4

0/

Bit-3

Bit-2

Bit-1

Bit-0

WR

IER RD/WR

Modem RXLine

Stat.

Int.

TX

Empty

Int

RX

Data

Int.

LCR[7] = 0

Stat.

Int.

CTS Int. RTS Int. Xoff Int.

Enable Enable Enable

Sleep

Mode

Enable

Enable Enable Enable Enable

0 1 0

ISR

RD

FIFOs

0/

INT

Enabled Enabled

Source Source Source Source

INT

Bit-3

Bit-2

Bit-1

Bit-0

Source Source

Bit-5

Bit-4

LCR ≠ 0xBF

0 1 0

0 1 1

FCR

WR RXFIFO RXFIFO

Trigger Trigger

0

DMA

Mode

TX

FIFO

RX

FIFOs

FIFO Enable

Enable Reset Reset

LCR RD/WR Divisor Set TX Set Par-

Even

Parity Enable

Parity

Stop

Bits

Word

Length Length

Bit-1 Bit-0

Word

Enable

Break

ity

1 0 0

1 0 1

MCR RD/WR

0/

Internal OP2#/ Rsvd

RTS# DTR#

Output Output

Control Control

Lopback

Enable Output

Enable

INT

(OP1#)

BRG

Pres-

caler

IR Mode XonAny

ENable

LSR

RD

RX FIFO THR &

Global

Error

THR

Empty

RX

TSR

Empty

Break

Fram- Parity Over-

Data

LCR ≠ 0xBF

ing

Error

run

Ready

Error

1 1 0

1 1 1

MSR

CD#

Input

RI#

Input

DSR#

Input

CTS#

Input

Delta

CD#

Delta

RI#

Delta

DSR# CTS#

SPR RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

Bit-3

Bit-2

Bit-1

Bit-0

Baud Rate Generator Divisor

LCR[7]=1

0 0 0

0 0 1

0 0 0

0 0 1

DLL RD/WR

DLM RD/WR

Bit-7

0

Bit-6

0

Bit-5

0

Bit-4

0

Bit-3

0

Bit-2

0

Bit-1

1

Bit-0

0

DREV

DVID

RD

LCR[7]=1

DLL=0x00

DLM=0x00

21

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.2

TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1

ADDRESS

REG

READ/

WRITE

BIT-7

BIT-6

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

COMMENT

A2-A0

NAME

Enhanced Registers

Enable

0 1 0

EFR RD/WR

Auto

CTS

Enable Enable

Auto

RTS

Special

Char

Select

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

Soft-

ware

Flow

Cntl

IER [7:4],

ISR [5:4],

FCR[5:4],

MCR[7:5]

Bit-3

Bit-2

Bit-1

Bit-0

LCR=0XBF

1 0 0

1 0 1

1 1 0

1 1 1

XON1 RD/WR

XON2 RD/WR

XOFF1 RD/WR

XOFF2 RD/WR

Bit-7

Bit-6

Bit-5

Bit-4

4.0 INTERNAL REGISTER DESCRIPTIONS

4.1 Receive Holding Register (RHR) - Read- Only

SEE”RECEIVER” ON PAGE 12.

4.2 Transmit Holding Register (THR) - Write-Only

SEE”TRANSMITTER” ON PAGE 11.

4.3 Interrupt Enable Register (IER) - Read/Write

The Interrupt Enable Register (IER) masks the interrupts from receive data ready, transmit empty, line status

and modem status registers. These interrupts are reported in the Interrupt Status Register (ISR).

4.3.1

IER versus Receive FIFO Interrupt Mode Operation

When the receive FIFO (FCR BIT-0 = 1) and receive interrupts (IER BIT-0 = 1) are enabled, the RHR interrupts

(see ISR bits 2 and 3) status will reflect the following:

A. The receive data available interrupts are issued to the host when the FIFO has reached the programmed

trigger level. It will be cleared when the FIFO drops below the programmed trigger level.

B. FIFO level will be reflected in the ISR register when the FIFO trigger level is reached. Both the ISR register

status bit and the interrupt will be cleared when the FIFO drops below the trigger level.

C. The receive data ready bit (LSR BIT-0) is set as soon as a character is transferred from the shift register to

the receive FIFO. It is reset when the FIFO is empty.

4.3.2

IER versus Receive/Transmit FIFO Polled Mode Operation

When FCR BIT-0 equals a logic 1 for FIFO enable; resetting IER bits 0-3 enables the XR16L2550 in the FIFO

polled mode of operation. Since the receiver and transmitter have separate bits in the LSR either or both can

be used in the polled mode by selecting respective transmit or receive control bit(s).

A. LSR BIT-0 indicates there is data in RHR or RX FIFO.

B. LSR BIT-1 indicates an overrun error has occurred and that data in the FIFO may not be valid.

C. LSR BIT 2-4 provides the type of receive data errors encountered for the data byte in RHR, if any.

D. LSR BIT-5 indicates Transmit FIFO is empty.

E. LSR BIT-6 indicates when both the transmit FIFO and TSR are empty.

F. LSR BIT-7 indicates a data error in at least one character in the RX FIFO.

22

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

IER[0]: RHR Interrupt Enable

The receive data ready interrupt will be issued when RHR has a data character in the non-FIFO mode or when

the receive FIFO has reached the programmed trigger level in the FIFO mode.

• Logic 0 = Disable the receive data ready interrupt (default).

• Logic 1 = Enable the receiver data ready interrupt.

IER[1]: THR Interrupt Enable

This bit enables the Transmit Ready interrupt which is issued whenever the Transmit FIFO becomes empty. If

the Transmit FIFO is empty when this bit is enabled, an interrupt will be generated.

• Logic 0 = Disable Transmit Ready interrupt (default).

• Logic 1 = Enable Transmit Ready interrupt.

IER[2]: Receive Line Status Interrupt Enable

If any of the LSR register bits 1, 2, 3 or 4 is a logic 1, it will generate an interrupt to inform the host controller

about the error status of the current data byte in FIFO. LSR bit-1 generates an interrupt immediately when the

character has been received. LSR bits 2-4 generate an interrupt when the character with errors is read out of

the FIFO.

• Logic 0 = Disable the receiver line status interrupt (default).

• Logic 1 = Enable the receiver line status interrupt.

IER[3]: Modem Status Interrupt Enable

• Logic 0 = Disable the modem status register interrupt (default).

• Logic 1 = Enable the modem status register interrupt.

IER[4]: Sleep Mode Enable (requires EFR bit-4 = 1)

• Logic 0 = Disable Sleep Mode (default).

• Logic 1 = Enable Sleep Mode. See Sleep Mode section for further details.

IER[5]: Xoff Interrupt Enable (requires EFR bit-4=1)

• Logic 0 = Disable the software flow control, receive Xoff interrupt. (default)

• Logic 1 = Enable the software flow control, receive Xoff interrupt. See Software Flow Control section for

details.

IER[6]: RTS# Output Interrupt Enable (requires EFR bit-4=1)

• Logic 0 = Disable the RTS# interrupt (default).

• Logic 1 = Enable the RTS# interrupt. The UART issues an interrupt when the RTS# pin makes a transition

from low to high.

IER[7]: CTS# Input Interrupt Enable (requires EFR bit-4=1)

• Logic 0 = Disable the CTS# interrupt (default).

• Logic 1 = Enable the CTS# interrupt. The UART issues an interrupt when CTS# pin makes a transition from

low to high.

4.4

Interrupt Status Register (ISR) - Read-Only

The UART provides multiple levels of prioritized interrupts to minimize external software interaction. The

Interrupt Status Register (ISR) provides the user with six interrupt status bits. Performing a read cycle on the

ISR will give the user the current highest pending interrupt level to be serviced, others are queued up to be

serviced next. No other interrupts are acknowledged until the pending interrupt is serviced. The Interrupt

23

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.2

Source Table, Table 9, shows the data values (bit 0-5) for the interrupt priority levels and the interrupt sources

associated with each of these interrupt levels.

4.4.1

Interrupt Generation:

• LSR is by any of the LSR bits 1, 2, 3 and 4.

• RXRDY is by RX trigger level.

• RXRDY Time-out is by a 4-char plus 12 bits delay timer.

• TXRDY is by TX FIFO empty.

• MSR is by any of the MSR bits 0, 1, 2 and 3.

• Receive Xoff/Special character is by detection of a Xoff or Special character.

• CTS# is when its transmitter toggles the input pin (from low to high) during auto CTS flow control enabled by

EFR bit-7.

• RTS# is when its receiver toggles the output pin (from low to high) during auto RTS flow control enabled by

EFR bit-6.

4.4.2

Interrupt Clearing:

• LSR interrupt is cleared by a read to the LSR register (but flags and tags not cleared until character(s) that

generated the interrupt(s) has been emptied or cleared from FIFO).

• RXRDY interrupt is cleared by reading data until FIFO falls below the trigger level.

• RXRDY Time-out interrupt is cleared by reading RHR.

• TXRDY interrupt is cleared by a read to the ISR register or writing to THR.

• MSR interrupt is cleared by a read to the MSR register.

• Xoff interrupt is cleared by a read to ISR or when Xon character(s) is received.

• Special character interrupt is cleared by a read to ISR or after the next character is received.

• RTS# and CTS# flow control interrupts are cleared by a read to the MSR register.

]

TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL

PRIORITY

ISR REGISTER STATUS BITS

SOURCE OF INTERRUPT

LEVEL

BIT-5

BIT-4

BIT-3

BIT-2

BIT-1

BIT-0

1

2

3

4

5

6

7

-

0

1

0

1

0

1

0

1

0

1

0

1

0

1

LSR (Receiver Line Status Register)

RXRDY (Receive Data Time-out)

RXRDY (Received Data Ready)

TXRDY (Transmit Ready)

MSR (Modem Status Register)

RXRDY (Received Xoff or Special character)

CTS#, RTS# change of state

None (default)

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XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

ISR[0]: Interrupt Status

• Logic 0 = An interrupt is pending and the ISR contents may be used as a pointer to the appropriate interrupt

service routine.

• Logic 1 = No interrupt pending (default condition).

ISR[3:1]: Interrupt Status

These bits indicate the source for a pending interrupt at interrupt priority levels (See Interrupt Source Table 9).

ISR[4]: Xoff or Special Character Interrupt Status

This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-4 indicates that the receiver detected a data match

of the Xoff character(s). If this is an Xoff interrupt, it can be cleared by a read to the ISR or when an Xon

character is received. If it is a special character interrupt, it will automatically clear after the next character is

received.

ISR[5]: RTS#/CTS# Interrupt Status

This bit is enabled when EFR bit-4 is set to a logic 1. ISR bit-5 indicates that the CTS# or RTS# has changed

state from low to high.

ISR[7:6]: FIFO Enable Status

These bits are set to a logic 0 when the FIFOs are disabled. They are set to a logic 1 when the FIFOs are

enabled.

4.5

FIFO Control Register (FCR) - Write-Only

This register is used to enable the FIFOs, clear the FIFOs, set the transmit/receive FIFO trigger levels, and

select the DMA mode. The DMA, and FIFO modes are defined as follows:

FCR[0]: TX and RX FIFO Enable

• Logic 0 = Disable the transmit and receive FIFO (default).

• Logic 1 = Enable the transmit and receive FIFOs. This bit must be set to logic 1 when other FCR bits are

written or they will not be programmed.

FCR[1]: RX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

• Logic 0 = No receive FIFO reset (default)

• Logic 1 = Reset the receive FIFO pointers and FIFO level counter logic (the receive shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[2]: TX FIFO Reset

This bit is only active when FCR bit-0 is a ‘1’.

• Logic 0 = No transmit FIFO reset (default).

• Logic 1 = Reset the transmit FIFO pointers and FIFO level counter logic (the transmit shift register is not

cleared or altered). This bit will return to a logic 0 after resetting the FIFO.

FCR[3]: DMA Mode Select

Controls the behavior of theTXRDY# and RXRDY# pins. See DMA operation section for details.

• Logic 0 = Normal Operation (default).

• Logic 1 = DMA Mode.

FCR[5:4]: Reserved

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XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

FCR[7:6]: Receive FIFO Trigger Select

(logic 0 = default, RX trigger level =1)

REV. 1.1.2

These 2 bits are used to set the trigger level for the receive FIFO. The UART will issue a receive interrupt when

the number of the characters in the FIFO crosses the trigger level. Table 10 shows the complete selections.

TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION

RECEIVE

FCR BIT-7

FCR BIT-6

TRIGGER

LEVEL

COMPATIBILITY

0

1

0

1

0

1

1 (default)

16C550, 16C2550,

16C2552, 16C554,

16C580 compatible.

4

8

14

4.6

Line Control Register (LCR) - Read/Write

The Line Control Register is used to specify the asynchronous data communication format. The word or

character length, the number of stop bits, and the parity are selected by writing the appropriate bits in this

register.

LCR[1:0]: TX and RX Word Length Select

These two bits specify the word length to be transmitted or received.

BIT-1

BIT-0

WORD LENGTH

0

1

0

1

0

1

5 (default)

6

7

8

LCR[2]: TX and RX Stop-bit Length Select

The length of stop bit is specified by this bit in conjunction with the programmed word length.

BIT-2

WORD LENGTH

STOP BIT LENGTH (BIT TIME(S))

0

1

5,6,7,8

5

1 (default)

1-1/2

2

6,7,8

LCR[3]: TX and RX Parity Select

Parity or no parity can be selected via this bit. The parity bit is a simple way used in communications for data

integrity check. See Table 11 for parity selection summary below.

• Logic 0 = No parity.

• Logic 1 = A parity bit is generated during the transmission while the receiver checks for parity error of the

data character received.

26

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

LCR[4]: TX and RX Parity Select

If the parity bit is enabled with LCR bit-3 set to a logic 1, LCR BIT-4 selects the even or odd parity format.

• Logic 0 = ODD Parity is generated by forcing an odd number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format (default).

• Logic 1 = EVEN Parity is generated by forcing an even number of logic 1’s in the transmitted character. The

receiver must be programmed to check the same format.

LCR[5]: TX and RX Parity Select

If the parity bit is enabled, LCR BIT-5 selects the forced parity format.

• LCR[5] = logic 0, parity is not forced (default).

• LCR[5] = logic 1 and LCR[4] = logic 0, parity bit is forced to a logical 1 for the transmit and receive data.

• LCR[5] = logic 1 and LCR[4] = logic 1, parity bit is forced to a logical 0 for the transmit and receive data.

TABLE 11: PARITY SELECTION

LCR BIT-5 LCR BIT-4 LCR BIT-3

PARITY SELECTION

No parity

X

0

1

X

0

1

0

1

0

1

Odd parity

Even parity

Force parity to mark, “1”

Forced parity to space, “0”

LCR[6]: Transmit Break Enable

When enabled, the Break control bit causes a break condition to be transmitted (the TX output is forced to a

“space’, logic 0, state). This condition remains, until disabled by setting LCR bit-6 to a logic 0.

• Logic 0 = No TX break condition (default).

• Logic 1 = Forces the transmitter output (TX) to a “space”, logic 0, for alerting the remote receiver of a line

break condition.

LCR[7]: Baud Rate Divisors (DLL/DLM) Enable

• Logic 0 = Data registers are selected (default).

• Logic 1 = Divisor latch registers are selected.

4.7

Modem Control Register (MCR) or General Purpose Outputs Control - Read/Write

The MCR register is used for controlling the serial/modem interface signals or general purpose inputs/outputs.

MCR[0]: DTR# Output

The DTR# pin is a modem control output. If the modem interface is not used, this output may be used as a

general purpose output.

• Logic 0 = Force DTR# output to a logic 1 (default).

• Logic 1 = Force DTR# output to a logic 0.

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XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

MCR[1]: RTS# Output

REV. 1.1.2

The RTS# pin is a modem control output. If the modem interface is not used, this output may be used as a

general purpose output.

• Logic 0 = Force RTS# output to a logic 1 (default).

• Logic 1 = Force RTS# output to a logic 0.

MCR[2]: Reserved

OP1# is not available as an output pin on the L2550. But it is available for use during Internal Loopback Mode.

In the Loopback Mode, this bit is used to write the state of the modem RI# interface signal.

MCR[3]: OP2# Output / INT Output Enable

This bit enables and disables the operation of INT, interrupt output. If INT output is not used, OP2# can be

used as a general purpose output.

• Logic 0 = INT (A-B) outputs disabled (three state mode) and OP2# output set to a logic 1 (default).

• Logic 1 = INT (A-B) outputs enabled (active mode) and OP2# output set to a logic 0.

MCR[4]: Internal Loopback Enable

• Logic 0 = Disable loopback mode (default).

• Logic 1 = Enable local loopback mode, see loopback section and Figure 13.

MCR[5]: Xon-Any Enable

• Logic 0 = Disable Xon-Any function (for 16C550 compatibility, default).

• Logic 1 = Enable Xon-Any function. In this mode, any RX character received will resume transmit operation.

The RX character will be loaded into the RX FIFO , unless the RX character is an Xon or Xoff character and

the L2552 is programmed to use the Xon/Xoff flow control.

MCR[6]: Infrared Encoder/Decoder Enable

• Logic 0 = Enable the standard modem receive and transmit input/output interface. (Default)

• Logic 1 = Enable infrared IrDA receive and transmit inputs/outputs. The TX/RX output/input are routed to the

infrared encoder/decoder. The data input and output levels conform to the IrDA infrared interface

requirement. While in this mode, the infrared TX output will be a logic 0 during idle data conditions.

MCR[7]: Clock Prescaler Select

• Logic 0 = Divide by one. The input clock from the crystal or external clock is fed directly to the Programmable

Baud Rate Generator without further modification, i.e., divide by one (default).

• Logic 1 = Divide by four. The prescaler divides the input clock from the crystal or external clock by four and

feeds it to the Programmable Baud Rate Generator, hence, data rates become one forth.

4.8

Line Status Register (LSR) - Read Only

This register provides the status of data transfers between the UART and the host.

LSR[0]: Receive Data Ready Indicator

• Logic 0 = No data in receive holding register or FIFO (default).

• Logic 1 = Data has been received and is saved in the receive holding register or FIFO.

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XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

LSR[1]: Receiver Overrun Flag

• Logic 0 = No overrun error (default).

• Logic 1 = Overrun error. A data overrun error condition occurred in the receive shift register. This happens

when additional data arrives while the FIFO is full. In this case the previous data in the receive shift register

is overwritten. Note that under this condition the data byte in the receive shift register is not transferred into

the FIFO, therefore the data in the FIFO is not corrupted by the error. An interrupt will be generated

immediately if LSR interrupt is enabled (IER bit-2).

LSR[2]: Receive Data Parity Error Flag

• Logic 0 = No parity error (default).

• Logic 1 = Parity error. The receive character in RHR does not have correct parity information and is suspect.

This error is associated with the character available for reading in RHR. If the LSR interrupt is enabled (IER

bit-2), an interrupt will be generated when the character is in the RHR.

LSR[3]: Receive Data Framing Error Flag

• Logic 0 = No framing error (default).

• Logic 1 = Framing error. The receive character did not have a valid stop bit(s). This error is associated with

the character available for reading in RHR. If the LSR interrupt is enabled (IER bit-2), an interrupt will be

generated when the character is in the RHR.

LSR[4]: Receive Break Flag

• Logic 0 = No break condition (default).

• Logic 1 = The receiver received a break signal (RX was a logic 0 for at least one character frame time). In the

FIFO mode, only one break character is loaded into the FIFO. The break indication remains until the RX

input returns to the idle condition, “mark” or logic 1. If the LSR interrupt is enabled (IER bit-2), an interrupt will

be generated when the character is in the RHR.

LSR[5]: Transmit Holding Register Empty Flag

This bit is the Transmit Holding Register Empty indicator. This bit indicates that the transmitter is ready to

accept a new character for transmission. In addition, this bit causes the UART to issue an interrupt to the host

when the THR interrupt enable is set. The THR bit is set to a logic 1 when the last data byte is transferred from

the transmit holding register to the transmit shift register. The bit is reset to logic 0 concurrently with the data

loading to the transmit holding register by the host. In the FIFO mode this bit is set when the transmit FIFO is

empty, it is cleared when the transmit FIFO contains at least 1 byte.

LSR[6]: THR and TSR Empty Flag

This bit is set to a logic 1 whenever the transmitter goes idle. It is set to logic 0 whenever either the THR or

TSR contains a data character. In the FIFO mode this bit is set to a logic 1 whenever the transmit FIFO and

transmit shift register are both empty.

LSR[7]: Receive FIFO Data Error Flag

• Logic 0 = No FIFO error (default).

• Logic 1 = A global indicator for the sum of all error bits in the RX FIFO. At least one parity error, framing error

or break indication is in the FIFO data. This bit clears when there is no more error(s) in the FIFO.

4.9

Modem Status Register (MSR) - Read Only

This register provides the current state of the modem interface signals, or other peripheral device that the

UART is connected. Lower four bits of this register are used to indicate the changed information. These bits

are set to a logic 1 whenever a signal from the modem changes state. These bits may be used as general

purpose inputs/outputs when they are not used with modem signals.

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XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

MSR[0]: Delta CTS# Input Flag

REV. 1.1.2

• Logic 0 = No change on CTS# input (default).

• Logic 1 = The CTS# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[1]: Delta DSR# Input Flag

• Logic 0 = No change on DSR# input (default).

• Logic 1 = The DSR# input has changed state since the last time it was monitored. A modem status interrupt

will be generated if MSR interrupt is enabled (IER bit-3).

MSR[2]: Delta RI# Input Flag

• Logic 0 = No change on RI# input (default).

• Logic 1 = The RI# input has changed from a logic 0 to a logic 1, ending of the ringing signal. A modem status

interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[3]: Delta CD# Input Flag

• Logic 0 = No change on CD# input (default).

• Logic 1 = Indicates that the CD# input has changed state since the last time it was monitored. A modem

status interrupt will be generated if MSR interrupt is enabled (IER bit-3).

MSR[4]: CTS Input Status

Normally this bit is the compliment of the CTS# input. However in the loopback mode, this bit is equivalent to

the RTS# bit in the MCR register. The CTS# input may be used as a general purpose input when the modem

interface is not used.

MSR[5]: DSR Input Status

Normally this bit is the compliment of the DSR# input. In the loopback mode, this bit is equivalent to the DTR#

bit in the MCR register. The DSR# input may be used as a general purpose input when the modem interface is

not used.

MSR[6]: RI Input Status

Normally this bit is the compliment of the RI# input. In the loopback mode this bit is equivalent to bit-2 in the

MCR register. The RI# input may be used as a general purpose input when the modem interface is not used.

MSR[7]: CD Input Status

Normally this bit is the compliment of the CD# input. In the loopback mode this bit is equivalent to bit-3 in the

MCR register. The CD# input may be used as a general purpose input when the modem interface is not used.

4.10 Scratch Pad Register (SPR) - Read/Write

This is a 8-bit general purpose register for the user to store temporary data. The content of this register is

preserved during sleep mode but becomes 0xFF (default) after a reset or a power off-on cycle.

4.11 Baud Rate Generator Registers (DLL and DLM) - Read/Write

The Baud Rate Generator (BRG) is a 16-bit counter that generates the data rate for the transmitter. The rate is

programmed through registers DLL and DLM which are only accessible when LCR bit-7 is set to ‘1’.

SEE”PROGRAMMABLE BAUD RATE GENERATOR” ON PAGE 10. for more details.

4.12 Device Identification Register (DVID) - Read Only

This register contains the device ID (0x02 for XR16L2550). Prior to reading this register, DLL and DLM should

be set to 0x00.

30

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

4.13 Device Revision Register (DREV) - Read Only

This register contains the device revision information. For example, 0x01 means revision A. Prior to reading

this register, DLL and DLM should be set to 0x00.

4.14 Enhanced Feature Register (EFR)

Enhanced features are enabled or disabled using this register. Bit 0-3 provide single or dual consecutive

character software flow control selection (see Table 12). When the Xon1 and Xon2 and Xoff1 and Xoff2 modes

are selected, the double 8-bit words are concatenated into two sequential characters. Caution: note that

whenever changing the TX or RX flow control bits, always reset all bits back to logic 0 (disable) before

programming a new setting.

EFR[3:0]: Software Flow Control Select

Single character and dual sequential characters software flow control is supported. Combinations of software

flow control can be selected by programming these bits.

TABLE 12: SOFTWARE FLOW CONTROL FUNCTIONS

EFR BIT-3

CONT-3

EFR BIT-2

CONT-2

EFR BIT-1

CONT-1

EFR BIT-0

CONT-0

TRANSMIT AND RECEIVE SOFTWARE FLOW CONTROL

0

1

0

1

X

1

0

1

X

0

X

0

1

0

1

0

X

0

No TX and RX flow control (default and reset)

No transmit flow control

Transmit Xon1, Xoff1

Transmit Xon2, Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2

No receive flow control

0

Receiver compares Xon1, Xoff1

Receiver compares Xon2, Xoff2

1

Transmit Xon1, Xoff1

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

0

1

0

1

0

1

Transmit Xon2, Xoff2

Receiver compares Xon1 or Xon2, Xoff1 or Xoff2

Transmit Xon1 and Xon2, Xoff1 and Xoff2,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

No transmit flow control,

Receiver compares Xon1 and Xon2, Xoff1 and Xoff2

EFR[4]: Enhanced Function Bits Enable

Enhanced function control bit. This bit enables IER bits 4-7, ISR bits 4-5, and MCR bits 5-7 to be modified.

After modifying any enhanced bits, EFR bit-4 can be set to a logic 0 to latch the new values. This feature

prevents legacy software from altering or overwriting the enhanced functions once set. Normally, it is

recommended to leave it enabled, logic 1.

• Logic 0 = modification disable/latch enhanced features. IER bits 4-7, ISR bits 4-5, and MCR bits 5-7 are

saved to retain the user settings. After a reset, the IER bits 4-7, ISR bits 4-5, and MCR bits 5-7are set to a

logic 0 to be compatible with ST16C550 mode (default).

• Logic 1 = Enables the above-mentioned register bits to be modified by the user.

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XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

EFR[5]: Special Character Detect Enable

REV. 1.1.2

• Logic 0 = Special Character Detect Disabled (default).

• Logic 1 = Special Character Detect Enabled. The UART compares each incoming receive character with

data in Xoff-2 register. If a match exists, the receive data will be transferred to FIFO and ISR bit-4 will be set

to indicate detection of the special character. Bit-0 corresponds with the LSB bit of the receive character. If

flow control is set for comparing Xon1, Xoff1 (EFR [1:0]= ‘10’) then flow control and special character work

normally. However, if flow control is set for comparing Xon2, Xoff2 (EFR[1:0]= ‘01’) then flow control works

normally, but Xoff2 will not go to the FIFO, and will generate an Xoff interrupt and a special character

interrupt, if enabled via IER bit-5. Special character interrupts are cleared automatically after the next

received character.

EFR[6]: Auto RTS Flow Control Enable

RTS# output may be used for hardware flow control by setting EFR bit-6 to logic 1. When Auto RTS is

selected, an interrupt will be generated when the receive FIFO is filled to the programmed trigger level and

RTS de-asserts to a logic 1 at the next upper trigger level. RTS# will return to a logic 0 when FIFO data falls

below the next lower trigger level. The RTS# output must be asserted (logic 0) before the auto RTS can take

effect. RTS# pin will function as a general purpose output when hardware flow control is disabled.

• Logic 0 = Automatic RTS flow control is disabled (default).

• Logic 1 = Enable Automatic RTS flow control.

EFR[7]: Auto CTS Flow Control Enable

Automatic CTS Flow Control.

• Logic 0 = Automatic CTS flow control is disabled (default).

• Logic 1 = Enable Automatic CTS flow control. Data transmission stops when CTS# input de-asserts to logic

1. Data transmission resumes when CTS# returns to a logic 0.

4.15 Software Flow Control Registers (XOFF1, XOFF2, XON1, XON2) - Read/Write

These registers are used as the programmable software flow control characters XOFF1, XOFF2, XON1, and

XON2. For more details, see Table 6.

32

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

TABLE 13: UART RESET CONDITIONS FOR CHANNEL A AND B

REGISTERS

DLM

DLL

RESET STATE

Bits 7-0 = 0xXX

Bits 7-0 = 0x00

Bits 7-0 = 0x01

Bits 7-0 = 0x00

Bits 7-0 = 0x60

RHR

THR

IER

FCR

ISR

LCR

MCR

LSR

MSR

Bits 3-0 = Logic 0

Bits 7-4 = Logic levels of the inputs

inverted

SPR

EFR

Bits 7-0 = 0xFF

Bits 7-0 = 0x00

RESET STATE

Logic 1

XON1

XON2

XOFF1

XOFF2

I/O SIGNALS

TX

OP2#

Logic 1

RTS#

Logic 1

DTR#

Logic 1

RXRDY#

TXRDY#

INT

Logic 1

Logic 0

Three-State Condition

33

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.2

ABSOLUTE MAXIMUM RATINGS

Power Supply Range

Voltage at Any Pin

7 Volts

GND-0.3 V to VCC+0.3 V

-40^oto +85^oC

Operating Temperature

-65^oto +150^oC

500 mW

Storage Temperature

Package Dissipation

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)

theta-ja =59^oC/W, theta-jc = 16^oC/W

Thermal Resistance (48-TQFP)

theta-ja = 50^oC/W, theta-jc = 21^oC/W

Thermal Resistance (44-PLCC)

theta-ja = ^oC/W, theta-jc = ^oC/W

Thermal Resistance (32-QFN)

ELECTRICAL CHARACTERISTICS

DC ELECTRICAL CHARACTERISTICS

UNLESS OTHERWISE NOTED: TA=-40^OTO +85^OC, VCC IS 2.25 TO 5.5V

2.5V LIMITS

MIN MAX

3.3V LIMITS

MIN MAX

5.0V LIMITS

MIN MAX

SYMBOL

PARAMETER

UNITS

CONDITIONS

V_ILCK

V_IHCK

V_IL

Clock Input Low Level

Clock Input High Level

Input Low Voltage

-0.3

0.2

-0.3

0.6

-0.5

0.6

V

2.0

-0.3

2.0

5.5

0.6

5.5

2.4

-0.3

2.0

5.5

0.8

5.5

3.0

-0.5

2.2

5.5

0.8

5.5

0.4

V_IH

Input High Voltage

Output Low Voltage

V_OL

V

I_OL= 6 mA

I_OL= 4 mA

I_OL= 2 mA

0.4

V_OH

Output High Voltage

2.4

V

I_OH= -6 mA

I_OH= -1 mA

I_OH= -400 uA

2.0

1.8

I_IL

I_IH

Input Low Leakage Current

Input High Leakage Current

Input Pin Capacitance

Power Supply Current

Sleep Current

±10

5

±10

5

±10

5

uA

pF

C_IN

I_CC

1

1.3

15

3

mA

uA

I_SLEEP

6

30

See Test 1

Test 1: The following inputs must remain steady at VCC or GND state to minimize Sleep current: A0-A2, D0-

D7, IOR#, IOW#, CSA#, CSB#, and all modem inputs. Also, RXA and RXB inputs must idle at logic 1 state

while asleep. Floating inputs will result in sleep currents in the mA range. For PowerSave feature that isolates

address, data and control signals, please see the XR16L2551 datasheet.

34

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

AC ELECTRICAL CHARACTERISTICS

UNLESS OTHERWISE NOTED: TA=-40^OTO +85^OC, VCC IS 2.25V TO 5.5V,

70 PF LOAD WHERE APPLICABLE

LIMITS

3.3

LIMITS

5.0

SYMBOL

PARAMETER

2.5

UNIT

MIN

MAX

MIN

MAX MIN

MAX

-

Crystal Frequency

16

20

24

MHz

ns

CLK

OSC

T_AS

External Clock Low/High Time

External Clock Frequency

Address Setup Time

31

17

10

16

30

50

MHz

ns

10

75

10

50

T_AH

T_CS

Address Hold Time

ns

Chip Select Width

150

T_RD

T_DY

IOR# Strobe Width

ns

Read Cycle Delay

ns

T_RDV

T_DD

T_WR

T_DY

Data Access Time

125

45

70

30

45

30

ns

Data Disable Time

0

ns

IOW# Strobe Width

150

25

75

20

10

50

15

10

ns

Write Cycle Delay

ns

T_DS

Data Setup Time

ns

T_DH

T_WDO

T_MOD

T_RSI

T_SSI

T_RRI

T_SI

Data Hold Time

15

ns

Delay From IOW# To Output

Delay To Set Interrupt From MODEM Input

Delay To Reset Interrupt From IOR#

Delay From Stop To Set Interrupt

Delay From IOR# To Reset Interrupt

Delay From Stop To Interrupt

150

1

75

1

50

1

ns

Bclk

ns

150

24

75

24

50

24

ns

T_INT

Delay From Initial INT Reset To Transmit

Start

8

Bclk

T_WRI

T_SSR

T_RR

Delay From IOW# To Reset Interrupt

Delay From Stop To Set RXRDY#

150

1

75

1

50

1

ns

Bclk

ns

Delay From IOR# To Reset RXRDY#

Delay From IOW# To Set TXRDY#

Delay From Center of Start To Reset TXRDY#

150

8

75

8

50

8

T_WT

ns

T_SRT

Bclk

35

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

AC ELECTRICAL CHARACTERISTICS

REV. 1.1.2

UNLESS OTHERWISE NOTED: TA=-40^OTO +85^OC, VCC IS 2.25V TO 5.5V,

70 PF LOAD WHERE APPLICABLE

LIMITS

3.3

LIMITS

5.0

SYMBOL

PARAMETER

2.5

UNIT

MIN

MAX

MIN

MAX MIN

MAX

T_RST

N

Reset Pulse Width

40

ns

-

2¹⁶-1

Baud Rate Divisor

Baud Clock

1

Bclk

16X of data rate

Hz

FIGURE 14. CLOCK TIMING

CLK

EXTERNAL

CLOCK

OSC

FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B

IOW #

Active

T_{W DO}

RTS#

DTR#

Change of state

CD#

CTS#

DSR#

Change of state

T_MOD

Active

INT

Active

T_RSI

IOR#

Active

T_MOD

Change of state

RI#

36

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

FIGURE 16. DATA BUS READ TIMING

A0-A2

Valid Address

T_AS

T_AH

T_CS

T_AH

T_CS

CSA#/

CSB#

T_DY

T_RD

IOR#

T_DD

T_RDV

D0-D7

Valid Data

RDTm

FIGURE 17. DATA BUS WRITE TIMING

A0-A2

Valid Address

T_CS

Valid Address

T_CS

T_AS

T_AH

CSA#/

CSB#

T_DY

T_WR

IOW#

T_DH

T_DS

Valid Data

T_DS

Valid Data

D0-D7

16Write

37

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.2

FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B

RX

Stop

Bit

Start

Bit

D0:D7

T_SSR

1 Byte

in RHR

INT

T_SSR

Active

Data

Active

Data

Active

Data

RXRDY#

Ready

T_RR

IOR#

(Reading data

out of RHR)

RXNFM

FIGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B

TX

(Unloading)

Stop

Bit

Start

Bit

D0:D7

IER[1]

enabled

ISR is read

INT*

T_WRI

T_SRT

TXRDY#

T_WT

IOW#

(Loading data

into THR)

*INT is cleared when the ISR is read or when data is loaded into the THR.

TXNonFIFO

38

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B

Start

Bit

RX

S

T

D0:D7

T

D0:D7

T_SSI

D0:D7

S

T

S

D0:D7

T

D0:D7

T

Stop

Bit

RX FIFO drops

below RX

Trigger Level

INT

T_SSR

FIFO

Empties

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

RXRDY#

First Byte is

Received in

RX FIFO

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXINTDMA#

FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B

Start

Bit

Stop

Bit

RX

S

T

D0:D7

T

D0:D7

T_SSI

D0:D7

S

T

S

D0:D7

T

D0:D7

T

RX FIFO drops

below RX

Trigger Level

INT

RX FIFO fills up to RX

Trigger Level or RX Data

Timeout

T_SSR

FIFO

Empties

RXRDY#

T_RRI

T_RR

IOR#

(Reading data out

of RX FIFO)

RXFIFODMA

39

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.2

FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX FIFO

Empty

TX

(Unloading)

T

S

T

D0:D7

S

T

S

D0:D7

T

S D0:D7

T

D0:D7

T

D0:D7

T

T_SRT

IER[1]

enabled

ISR is read

TX FIFO no

longer empty

INT*

T_SI

T_WRI

TX FIFO

Empty

Data in

TX FIFO

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT is cleared when the ISR is read or when there is at least one character in the FIFO.

TXDMA#

FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B

Stop

Bit

Start

Bit

Last Data Byte

Transmitted

TX FIFO

Empty

TX

(Unloading)

T

S

T

D0:D7

S

T

S

D0:D7

T

S D0:D7

T

D0:D7

T

D0:D7

T

IER[1]

enabled

ISR is read

T_SRT

TX FIFO no

longer empty

T_SI

INT*

T_WRI

TX FIFO

Empty

At least 1

empty location

in FIFO

TX FIFO

Full

TXRDY#

T_WT

IOW#

(Loading data

into FIFO)

*INT is cleared when the ISR is read or when there is at least one character in the FIFO.

TXDMA

40

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 mm)

D

1

36

25

37

24

D

1

D

48

13

1

2

B

e

A

2

C

A

Seating

Plane

α

A

1

L

Note: The control dimension is the millimeter column

INCHES

MAX

MILLIMETERS

SYMBOL

MIN

MAX

1.20

0.15

1.05

0.27

0.20

9.20

7.10

A

A1

A2

B

0.039

0.002

0.037

0.007

0.004

0.346

0.272

0.047

0.006

0.041

0.011

0.008

0.362

0.280

1.00

0.05

0.95

0.17

0.09

8.80

6.90

C

D

D1

e

0.020 BSC

0.50 BSC

L

0.018

0.030

0.45

0.75

α

0°

7°

0°

7°

41

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.2

PACKAGE DIMENSIONS (44 PIN PLCC)

44 LEAD PLASTIC LEADED CHIP CARRIER

(PLCC)

Rev. 1.00

C

D

Seating Plane

D₁

45° x H

1

45° x H

2

A

2

1

44

B

1

B

D

1

D

3

2

e

R

D

3

A

1

A

Note: The control dimension is the millimeter column

INCHES

MAX

MILLIMETERS

SYMBOL

MIN

MAX

4.57

3.05

---

A

A1

A2

B

0.165

0.090

0.020

0.013

0.026

0.008

0.685

0.650

0.590

0.180

0.120

---

4.19

2.29

0.51

0.021

0.032

0.013

0.695

0.656

0.630

0.33

0.53

0.81

0.32

17.65

16.66

16.00

B

0.66

1

C

D

0.19

17.40

16.51

14.99

D1

D

2

D

0.500 typ.

0.050 BSC

12.70 typ.

1.27 BSC

1.07

3

e

H

0.042

0.056

0.048

0.045

1.42

1.22

1.14

1

H

0.042

0.025

1.07

0.64

2

R

42

XR16L2550

REV. 1.1.2

LOW VOLTAGE DUART WITH 16-BYTE FIFO

PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 mm)

Note: the actual center pad

is metallic and the size (D2)

is device-dependent with a

typical tolerance of 0.3mm

Note: The control dimension is in millimeter.

INCHES

MAX

MILLIMETERS

SYMBOL

MIN

0.80

0.00

0.15

4.90

3.50

0.18

MAX

1.00

0.05

0.25

5.10

3.80

0.30

A

A1

A3

D

0.031

0.000

0.006

0.193

0.138

0.007

0.039

0.002

0.010

0.201

0.150

0.012

D2

b

e

0.0197 BSC

0.50 BSC

L

0.012

0.008

0.020

-

0.35

0.20

0.45

-

k

43

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.2

REVISION HISTORY

DATE

November 2002

March 2003

May 2003

REVISION

DESCRIPTION

P1.0.0

Preliminary Datasheet.

P1.0.1

P1.0.2

P1.0.3

P1.0.4

Updated AC Electrical Characteristics. Updated register set with enhanced features.

Added patent number to first page. Added 32 pin QFN package dimensions.

Added Device Status to Ordering Information.

June 2003

July 2003

Updated AC Electrical Characteristics.

September 2003 1.0.0

September 2004 1.1.0

Final Production Release. Updated 5V tolerance information.

Corrected 32-QFN package dimension descriptions. Added GND center pad pin

description. Added Device Revision and Device ID registers and descriptions.

May 2005

May 2007

1.1.1

1.1.2

Updated the Data Access Time (T

) in AC Electrical Characteristics.

RDV

Updated QFN package dimensions drawing to show minimum "k" parameter.

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order to

improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any

circuits described herein, conveys no license under any patent or other right, and makes no representation that

the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration

purposes and may vary depending upon a user’s specific application. While the information in this publication

has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where the

failure or malfunction of the product can reasonably be expected to cause failure of the life support system or

to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless

EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has

been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately

protected under the circumstances.

Datasheet May 2007.

Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

44

x r

XR16L2550

LOW VOLTAGE DUART WITH 16-BYTE FIFO

REV. 1.1.2

TABLE OF CONTENTS

GENERAL DESCRIPTION................................................................................................. 1

APPLICATIONS ............................................................................................................................................... 1

FEATURES..................................................................................................................................................... 1

FIGURE 1. XR16L2550 BLOCK DIAGRAM ......................................................................................................................................... 1

FIGURE 2. PIN OUT ASSIGNMENT ..................................................................................................................................................... 2

ORDERING INFORMATION ................................................................................................................................ 2

PIN DESCRIPTIONS ......................................................................................................... 3

1.0 PRODUCT DESCRIPTION .................................................................................................................... 6

2.0 FUNCTIONAL DESCRIPTIONS ............................................................................................................ 7

2.1 CPU INTERFACE ............................................................................................................................................. 7

FIGURE 3. XR16L2550 DATA BUS INTERCONNECTIONS.................................................................................................................. 7

2.2 5-VOLT TOLERANT INPUTS ........................................................................................................................... 7

2.3 DEVICE RESET ................................................................................................................................................ 7

2.4 DEVICE IDENTIFICATION AND REVISION .................................................................................................... 7

2.5 CHANNEL A AND B SELECTION ................................................................................................................... 7

TABLE 1: CHANNEL A AND B SELECT ............................................................................................................................................... 8

2.6 CHANNEL A AND B INTERNAL REGISTERS ................................................................................................ 8

2.7 DMA MODE ...................................................................................................................................................... 8

TABLE 2: TXRDY# AND RXRDY# OUTPUTS IN FIFO AND DMA MODE............................................................................................. 8

2.8 INTA AND INTB OUTPUTS .............................................................................................................................. 8

TABLE 3: INTA AND INTB PINS OPERATION FOR TRANSMITTER ........................................................................................................ 9

TABLE 4: INTA AND INTB PIN OPERATION FOR RECEIVER ............................................................................................................... 9

2.9 CRYSTAL OSCILLATOR OR EXTERNAL CLOCK INPUT ............................................................................. 9

FIGURE 4. TYPICAL OSCILLATOR CONNECTIONS................................................................................................................................. 9

2.10 PROGRAMMABLE BAUD RATE GENERATOR ......................................................................................... 10

FIGURE 5. EXTERNAL CLOCK CONNECTION FOR EXTENDED DATA RATE.......................................................................................... 10

FIGURE 6. OPERATING FREQUENCY CHART. REQUIRES A 2K OHMS PULL-UP RESISTOR ON XTAL2 PIN TO INCREASE OPERATING SPEED10

TABLE 5: TYPICAL DATA RATES WITH A 14.7456 MHZ CRYSTAL OR EXTERNAL CLOCK ...................................................................... 11

2.11 TRANSMITTER ............................................................................................................................................. 11

2.11.1 TRANSMIT HOLDING REGISTER (THR) - WRITE ONLY....................................................................................... 11

2.11.2 TRANSMITTER OPERATION IN NON-FIFO MODE................................................................................................ 11

FIGURE 7. TRANSMITTER OPERATION IN NON-FIFO MODE .............................................................................................................. 12

2.11.3 TRANSMITTER OPERATION IN FIFO MODE ......................................................................................................... 12

FIGURE 8. TRANSMITTER OPERATION IN FIFO AND FLOW CONTROL MODE ..................................................................................... 12

2.12 RECEIVER .................................................................................................................................................... 12

2.12.1 RECEIVE HOLDING REGISTER (RHR) - READ-ONLY .......................................................................................... 13

FIGURE 9. RECEIVER OPERATION IN NON-FIFO MODE.................................................................................................................... 13

FIGURE 10. RECEIVER OPERATION IN FIFO AND AUTO RTS FLOW CONTROL MODE ....................................................................... 13

2.13 AUTO RTS (HARDWARE) FLOW CONTROL ............................................................................................. 14

2.14 AUTO CTS FLOW CONTROL ..................................................................................................................... 14

FIGURE 11. AUTO RTS AND CTS FLOW CONTROL OPERATION....................................................................................................... 15

2.15 AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ................................................................................... 16

TABLE 6: AUTO XON/XOFF (SOFTWARE) FLOW CONTROL ............................................................................................................... 16

2.16 SPECIAL CHARACTER DETECT ............................................................................................................... 16

2.17 INFRARED MODE ........................................................................................................................................ 17

FIGURE 12. INFRARED TRANSMIT DATA ENCODING AND RECEIVE DATA DECODING.......................................................................... 17

2.18 SLEEP MODE WITH AUTO WAKE-UP ...................................................................................................... 18

2.19 INTERNAL LOOPBACK .............................................................................................................................. 19

FIGURE 13. INTERNAL LOOP BACK IN CHANNEL A AND B ................................................................................................................ 19

3.0 UART INTERNAL REGISTERS ........................................................................................................... 20

TABLE 7: UART CHANNEL A AND B UART INTERNAL REGISTERS ..................................................................................... 20

TABLE 8: INTERNAL REGISTERS DESCRIPTION. SHADED BITS ARE ENABLED WHEN EFR BIT-4=1......................................... 21

4.0 INTERNAL REGISTER DESCRIPTIONS ............................................................................................ 22

4.1 RECEIVE HOLDING REGISTER (RHR) - READ- ONLY ............................................................................... 22

4.2 TRANSMIT HOLDING REGISTER (THR) - WRITE-ONLY ............................................................................ 22

4.3 INTERRUPT ENABLE REGISTER (IER) - READ/WRITE ............................................................................. 22

4.3.1 IER VERSUS RECEIVE FIFO INTERRUPT MODE OPERATION ............................................................................. 22

4.3.2 IER VERSUS RECEIVE/TRANSMIT FIFO POLLED MODE OPERATION................................................................ 22

4.4 INTERRUPT STATUS REGISTER (ISR) - READ-ONLY ............................................................................... 23

I

XR16L2550

REV. 1.1.2

x r

LOW VOLTAGE DUART WITH 16-BYTE FIFO

4.4.1 INTERRUPT GENERATION: ...................................................................................................................................... 24

4.4.2 INTERRUPT CLEARING: ........................................................................................................................................... 24

TABLE 9: INTERRUPT SOURCE AND PRIORITY LEVEL ....................................................................................................................... 24

4.5 FIFO CONTROL REGISTER (FCR) - WRITE-ONLY ...................................................................................... 25

TABLE 10: RECEIVE FIFO TRIGGER LEVEL SELECTION ................................................................................................................... 26

4.6 LINE CONTROL REGISTER (LCR) - READ/WRITE ...................................................................................... 26

TABLE 11: PARITY SELECTION ........................................................................................................................................................ 27

4.7 MODEM CONTROL REGISTER (MCR) OR GENERAL PURPOSE OUTPUTS CONTROL - READ/WRITE 27

4.8 LINE STATUS REGISTER (LSR) - READ ONLY ........................................................................................... 28

4.9 MODEM STATUS REGISTER (MSR) - READ ONLY .................................................................................... 29

4.10 SCRATCH PAD REGISTER (SPR) - READ/WRITE .................................................................................... 30

4.11 BAUD RATE GENERATOR REGISTERS (DLL AND DLM) - READ/WRITE .............................................. 30

4.12 DEVICE IDENTIFICATION REGISTER (DVID) - READ ONLY .................................................................... 30

4.13 DEVICE REVISION REGISTER (DREV) - READ ONLY .............................................................................. 31

4.14 ENHANCED FEATURE REGISTER (EFR) .................................................................................................. 31

TABLE 12: SOFTWARE FLOW CONTROL FUNCTIONS........................................................................................................................ 31

4.15 SOFTWARE FLOW CONTROL REGISTERS (XOFF1, XOFF2, XON1, XON2) - READ/WRITE ................ 32

TABLE 13: UART RESET CONDITIONS FOR CHANNEL A AND B............................................................................................ 33

ABSOLUTE MAXIMUM RATINGS...................................................................................34

TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)34

ELECTRICAL CHARACTERISTICS ................................................................................34

DC ELECTRICAL CHARACTERISTICS ..............................................................................................................34

AC ELECTRICAL CHARACTERISTICS ..............................................................................................................35

Unless otherwise noted: TA=-40o to +85oC, Vcc is 2.25V to 5.5V, ..........................................................................35

70 pF load where applicable......................................................................................................................................35

FIGURE 14. CLOCK TIMING............................................................................................................................................................. 36

FIGURE 15. MODEM INPUT/OUTPUT TIMING FOR CHANNELS A & B ................................................................................................. 36

FIGURE 17. DATA BUS WRITE TIMING............................................................................................................................................. 37

FIGURE 16. DATA BUS READ TIMING.............................................................................................................................................. 37

FIGURE 18. RECEIVE READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ......................................................... 38

FIGURE 19. TRANSMIT READY & INTERRUPT TIMING [NON-FIFO MODE] FOR CHANNELS A & B ....................................................... 38

FIGURE 20. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA DISABLED] FOR CHANNELS A & B........................................ 39

FIGURE 21. RECEIVE READY & INTERRUPT TIMING [FIFO MODE, DMA ENABLED] FOR CHANNELS A & B......................................... 39

FIGURE 22. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE DISABLED] FOR CHANNELS A & B............................ 40

FIGURE 23. TRANSMIT READY & INTERRUPT TIMING [FIFO MODE, DMA MODE ENABLED] FOR CHANNELS A & B ............................ 40

PACKAGE DIMENSIONS (48 PIN TQFP - 7 X 7 X 1 MM)...............................................41

PACKAGE DIMENSIONS (44 PIN PLCC) .......................................................................42

PACKAGE DIMENSIONS (32 PIN QFN - 5 X 5 X 0.9 MM)..............................................43

REVISION HISTORY.......................................................................................................................................44

TABLE OF CONTENTS ............................................................................................................I

II


型号：	XR16L2550IJTR-F
厂家：	EXAR CORPORATION
描述：	Serial I/O Controller, CMOS, PQCC44 先进先出芯片
文件：	总46页 (文件大小：969K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

XR16L2550IJTR-F [EXAR]

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