XR68C92CV [EXAR]
DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER; 双通用异步接收器和发送器
| 型号： | XR68C92CV |
| 厂家： | 
EXAR CORPORATION |
| 描述： | DUAL UNIVERSAL ASYNCHRONOUS RECEIVER AND TRANSMITTER |
| 文件： | 总32页 (文件大小：284K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XR68C92/192
DUAL UNIVERSAL ASYNCHRONOUS
RECEIVER AND TRANSMITTER
May 2000
DESCRIPTION
TheXR68C92/192isaDualUniversalAsynchronousReceiverandTransmitter with8(XR68C92)or16(XR68C192)
bytesoftransmitandreceiveFIFOs.TheXR68C92/192is pin-to-pinandfunctionallycompatibletotheXR68C681
and Philips SCC68681 UART with additional features. The operating speed of the receiver and transmitter can be
selectedindependentlyfromatableoftwentyfourfixedbaudrates,a16Xclockderivedfromaprogrammablecounter/
timer, oranexternal1Xor16Xclock. Thebaudrategeneratorandcounter/timercanoperatedirectlyfromacrystal
or from external clock input. The XR68C92/192 provides a power down mode in which the oscillator is stopped but
theregistercontentsareretained.TheXR68C92/192isfabricatedinanadvancedCMOSprocesstoachievelowpower
andhighspeedrequirements.
FEATURES
•Pin to pin and functionally compatible to XR68C681
andSCC68692
PLCC Package
•Full duplex transmit and receive operation
•8 bytes of transmit/receive FIFOs (XR68C92)
•16 bytes of transmit/receive FIFOs (XR68C192)
•Programmable character lengths (5, 6, 7, 8)
•Parity, framing, and over run error detection
•Programmable 16-bit timer/counter
•On-chip crystal oscillator
•Single interrupt output with eight selectable interrupt-
ing conditions
A 4
IP 0
7
39
38
37
36
35
34
33
32
31
30
29
-C S
8
-R ES ET
X TAL2
X TAL1
R X A
R /-W
-D TAC K
R X B
9
10
11
12
13
14
15
16
17
•External 1X or 16X clock
•Data rate up to 1Mbps
•Independent transmit and receive baud rates from
50bps to 230.4kbps
XR68C92
XR68C192
N .C .
N .C .
TX B
TX A
O P0
O P1
•6 General purpose inputs
•8 General purpose outputs
•TTL compatible inputs, outputs
•4 Transmit/receive trigger levels
•Watch dog timer
O P2
O P3
O P5
O P4
O P7
O P6
•Multi-drop mode compatible with 8051 nine bit mode
•3.3 or 5 volts operation
•Loopback modes
•Power down mode
ORDERING INFORMATION
Part number
XR68C192CP
XR68C192CJ
XR68C192CV
XR68C192IP
XR68C192IJ
XR68C192IV
Pins PackageOperating temperature
Partnumber
XR68C92CP
XR68C92CJ
XR68C92CV
XR68C92IP
XR68C92IJ
XR68C92IV
Pins Package
40 PDIP
44 PLCC
44 TQFP
40 PDIP
44 PLCC
44 TQFP
Operatingtemperature
0° C to + 70° C
0° C to + 70° C
0° C to + 70° C
40 PDIP
44 PLCC
44 TQFP
40 PDIP
44 PLCC
44 TQFP
0° C to + 70° C
0° C to + 70° C
0° C to + 70° C
-40° C to + 85° C
-40° C to + 85° C
-40° C to + 85° C
-40° C to + 85° C
-40° C to + 85° C
-40° C to + 85° C
Rev.P2.10
www.exar.com
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 • (510) 668-7000 • FAX (510) 668-7017
XR68C92/192
Package Description
40 Pin DIP Package
44 Pin TQFP Package
VCC
IP4
A1
IP3
1
2
3
4
5
6
7
8
9
40
39
38
37
36
35
34
33
32
IP5
A2
-IACK
IP2
IP1
A3
IP 0
1
2
33
32
31
30
29
28
27
26
25
24
23
-C S
-R E SET
XTA L2
XTA L1
R XA
A3
R /-W
-D TA CK
R XB
3
-CS
A4
4
-RESET
XTAL2
XTAL1
IP0
5
XR 68C92
XR 68C192
R/-W
-DTACK
TXB
6
TXA
O P 1
7
O P 0
O P 3
8
O P 2
RXB 10
TXB 11
31 RXA
30 TXA
O P 5
9
O P 4
O P 7
10
11
O P 6
12
OP0
OP2
OP4
OP6
OP1
29
28
27
26
N .C .
N .C .
OP3 13
OP5 14
OP7 15
D1 16
25 D0
D2
D3 17
24
23
22
21
18
D4
D5
D6
D7 19
-INT
GND 20
Rev. P1.10
2
XR68C92/192
Block Diagram
T ran sm it
F IF O
R egisters
T ran sm it
S h ift
R egister
T X A /B
D 0-D 7
R /-W
-R E S E T
-D T A C K
-IA C K
F low
C on trol
L ogic
R eceive
F IF O
R egisters
R eceive
S h ift
R egister
A 1-A 4
-C S
R X A /B
F low
C on trol
L ogic
-IN T
O P 0-O P 7
IP 0-IP 5
I/O
C on trol
L ogic
X T A L 1
X T A L 2
Rev. P1.10
3
XR68C92/192
SYMBOL DESCRIPTION (* 44 TQFP Package)
Symbol
Pin
40
Signal
type
Pin Description
44
44*
-DTACK
10
9
4
O
Data transfer acknowledge (three-state active low output).
During Read, Write, or interrupt cycle goes low to indicate
proper transfer of data between the CPU and XR68C92/
192.
RX A/B
TX A/B
35,11 31,10 29,5
33,13 30,11 28,6
I
Serial data input. The serial information (data) received
from serial port to XR68C92/192 receive input circuit. A
mark (high) is logic one and a space (low) is logic zero.
O
Serial data output. The serial data is transmitted via this pin
with additional start , stop and parity bits. The TX will be held
in mark (high) state during reset, local loop back mode or
when the transmitter is disabled.
OP0
OP1
OP2
32
14
31
29
12
28
27
7
O
O
O
Multi-purpose output. General purpose output or Channel A
Request-To-Send (-RTSA active low).
Multi-purpose output. General purpose output or Channel B
Request-To-Send (-RTSB active low).
26
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programmingtheOutputPortConfigurationRegisterbits1,0:
TxAClk1 -Transmit 1X clock.
TxAClk16 -Transmit 16X clock
RxAClk1 -Receive 1X clock
OP3
OP4
15
30
13
27
8
O
O
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programmingtheOutputPortConfigurationRegisterbits3,2:
C/T -Counter timer output (Open drain output)
TxBClk1 -Transmit 1X clock
RxBClk1 -Receive 1X clock
25
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Configuration Register bit 4:
-RxARDY -Receive ready signal (Open drain output)
-RxAFULL - Receive FIFO full signal (Open drain output)
Rev. P1.10
4
XR68C92/192
SYMBOL DESCRIPTION (* 44 TQFP Package)
Symbol
Pin
40
Signal
type
Pin Description
44
44*
OP5
16
14
9
O
Multi-purpose output. General purpose output or one of the
following functions can be selected for this output pin by
programming the Output Port Configuration Register bit 5:
-RxBRDY - Receive ready signal (Open drain output)
-RxBFULL - Receive FIFO full signal (Open drain output)
OP6
OP7
29
17
26
15
24
10
O
O
Multi-purpose output. General purpose output or Transmit
A holding register empty interrupt (-TxARDY Open drain
output).
Multi-purpose output. General purpose output or Transmit
B holding register empty interrupt (-TxBRDY Open drain
output).
A1-A4
XTAL1
2,4,
6,7
1,3, 40,42,
5,6
44,1
I
I
Address select lines. To select internal registers.
36
32
30
Crystal input 1 or external clock input. A crystal can be
connected to this pin and XTAL2 pin to utilize the internal
oscillator circuit. An external clock can be used to clock
internalcircuitandbaudrategeneratorforcustomtransmis-
sion rates.
XTAL2
37
38
33
34
31
32
O
I
Crystal input 2 or buffered clock output. See XTAL1.
-RESET
Master reset. (active low) A low on this pin will reset all the
outputs and internal registers. The transmitter output and
the receiver input will be disabled during reset time.
GND
-INT
22
24
20
21
16,17
18
Pwr
O
Signal and power ground.
Interruptoutput(opendrainactivelow)Thispingoeslowupon
occurrenceofoneormoreofeightmaskableinterruptcondi-
tions(whenenabledbytheinterruptmaskregister).CPUcan
readtheinterruptstatusregistertodeterminetheinterrupting
condition(s). This output requires a pull-up resistor.
IP0
IP1
8
5
7
4
2
I
I
Multi-purpose input or Channel A Clear-To-Send (-CTSA
active low).
43
Multi-purpose input or Channel B Clear-To-Send (-CTSB
Rev. P1.10
5
XR68C92/192
SYMBOL DESCRIPTION (* 44 TQFP Package)
Symbol
Pin
40
Signal
type
Pin Description
44
44*
activelow).
IP2
40
3
36
2
34
41
I
I
Multi-purpose input or Timer/Counter External clock input.
IP3
Multi-purpose input or Channel A transmit external clock
input. The transmit data is clocked on the falling edge of the
clock.
IP4
43
42
41
39
38
37
37
36
35
I
I
I
Multi-purpose input or Channel A receive external clock
input. The received data is clocked on the rising edge of the
clock.
IP5
Multi-purpose input or Channel B Transmit external clock
input. The transmit data is clocked on the falling edge of the
clock.
-IACK
Interrupt acknowledge (active low). Indicating an interrupt
acknowledge cycle. XR68C92/192 will place the interrupt
vector on the data bus and will set -DTACK low if it has a
pendinginterrupt.
-CS
39
35
33
I
Chip select (active low). A low at this pin enables the serial
port / CPU data transfer operation.
D0-D7
28,18 25,16 22,12
27,19 24,17 21,13
26,20 23,18 20,14
25,21 22,19 19,15
Bi-directional data bus. Eight bit, three state data bus to
transfer information to or from the CPU. D0 is the least
significantbit ofthedatabusandthefirstserialdatabittobe
receivedortransmitted.
I/O
R/-W
9
8
3
I
Read/Writestrobe.When-CSisasserted,ahighlevelonthis
pin transfers the contents of the XR68C92/192 data bus to
the CPU, and a low level on this pin will transfer the contents
of the CPU data bus to the addressed register.
VCC
N.C.
44
40
38,39
11,23
Pwr
Power supply input.
NoConnection.
1,12
23,34
Rev. P1.10
6
XR68C92/192
INTERNALCONTROLLOGIC
grammedtoappearatparalleloutputOP3. Inthetimer
mode,theC/Tactsasaprogrammabledividerandcan
generate a square-wave output at OP3. In the counter
mode, the C/T can be started and stopped under
program control. When stopped, the CPU can read its
contents. The counter counts down the number of
pulses stored in the concatenation of the C/T upper
register and C/T lower register and produces an inter-
rupt.Thisisasystem-orientedfeaturethatcanbeused
torecordtimeoutswhenimplementingvariousapplica-
tion protocols.
Theinternalcontrollogicreceivesoperationcommands
from the central processing unit (CPU) and generates
appropriate signals to the internal sections to control
device operation. The internal control logic allows ac-
cess to the registers within the XR68C92/192 and
performsvariouscommandsbydecodingthefourreg-
ister-select lines (A1 through A4). Besides the four
register-select lines, there are three other inputs to the
internalcontrollogicfromtheR/-W(Read/write),which
allows read and write transfers between the CPU and
XR68C92/192viathedatabusbuffer, -CS(chip-select),
which is the XR68C92/192 chip-select, and -RESET
(reset), which initializes or resets. The -DTACK (data
transferacknowledge)signal,whichisassertedduring
read, write, or interrupt-acknowledge cycles, is the
internal control logic output. The -DTACK signal indi-
cates to the CPU that data has been latched on a CPU
write cycle or that valid data is present on the data bus
during a CPU read cycle or -IACK (interrupt-acknowl-
edge) cycle.
INTERRUPTCONTROLLOGIC
Thefollowingregistersareassociatedwiththeinterrupt
control logic:
• InterruptMaskRegister(IMR)
• Interrupt Status Register (ISR)
• Auxiliary Control Register (ACR)
• Interrupt Vector Register (IVR)
A single active-low interrupt output (-INT) can notify
the processor that any of eight internal events has
occurred. These eight events are described in the
discussion of the interrupt status register (ISR). User
can program the interrupt mask register (IMR) to allow
only certain conditions to cause -INT to be asserted
while the CPU can read the ISR to determine all
currently active interrupting conditions. When an ac-
tive-low interrupt acknowledge signal (-IACK) from
the processor is asserted while the XR68C92/192 has
an interrupt pending, the XR68C92/192 will place the
contents of the interrupt vector register (IVR) on the
data bus and assert the data transfer acknowledge
signal (-DTACK). If the XR68C92/192 has no pending
interrupt, it ignores -IACK cycles. In addition, users
canprogramthe interruptoutputsfromthetransmitters,
thereceivers,andtheC/Ttoappearattheparalleloutput
pins OP3 through OP7.
TIMINGLOGIC
Thetiminglogicconsistsofacrystaloscillator, abaud-
rate generator (BRG), a programmable 16-bit
counter/timer (C/T), and four clock selectors. The
crystal oscillator operates directly from a 3.6864 MHz
crystal connected across the XTAL1 and XTAL2 in-
puts or from an external clock of the appropriate
frequency connected to XTAL1. The XTAL1 clock
serves as the basic timing reference for the baud-rate
generator, the C/T, and other internal circuits.
The baud-rate generator operates from the XTAL1
clock input and can generate 28 commonly used data
communicationbaudratesrangingfrom50to230.4kby
producing internal clock outputs at 16 times the actual
baud rate. The C/T can produce a 16X clock for other
baud rates by counting down its programmed clock
source. Other baud rates can also be derived by
connecting 16X or 1X clocks to certain input port pins
that have alternate functions as receiver or transmitter
clock inputs. Four clock selectors allow the indepen-
dent selection of any of these baud rates for each
receiver and transmitter. Users can program the 16 bit
C/TwithintheXR68C92/192touseoneofseveralclock
sources as its input. The output of the C/T is available
to the internal clock selectors and can also be pro-
DATABUSBUFFER
Thedatabusbufferprovidestheinterfacebetweenthe
external and internal data buses. It is controlled by the
internalcontrollogictoallowreadandwritedatatransfer
operations to occur between the controlling CPU and
XR68C92/192 via the eight parallel data lines (D0
throughD7).
Rev. P1.10
7
XR68C92/192
COMMUNICATIONCHANNELSAANDB
the data having that bit-location as 1 (0 means no
change). However, itistobenotedthattheoutputsare
complements of the data contained in the OPR (eg.,
0x05 in OPR actually means 0xFA at the output pins).
Each communication channel includes a full-duplex
asynchronousreceiver/transmitter(UART).Theoperat-
ingfrequencyforeachreceiverandeachtransmittercan
beselectedindependentlyfromthebaud-rategenera-
tor, the C/T, or from an external clock. The transmitter
accepts parallel data from the CPU, converts it to a
serialbitstream,insertstheappropriatestart,stop,and
optional parity bits, and outputs a composite serial
stream of data on the TX output pin. The receiver
accepts serial data on the RX pin, converts this serial
input to parallel format, checks for a start bit, stop bit,
parity bit (if any), or break condition, and transfers an
assembled character to the CPU during read opera-
tions.
Besides general-purpose outputs, the outputs can be
individually assigned specific auxiliary functions serv-
ing the communication channels. The assignment is
accomplished by appropriately programming the
channel A and B mode registers (MR0A, MR0B,
MR1A, MR1B, MR2A, and MR2B) and the output port
configuration register (OPCR).
NOTE: The terms assertion and negation will be used
extensively to avoid confusion when dealing with a
mixture of “active low” and “active high” signals. The
termassertorassertionindicatesthatasignalisactive
or true, independent of whether that level is repre-
sented by a high or low voltage. The term negate or
negation indicates that a signal is inactive or false.
INPUTPORT
TheCPUreadstheinputstothis6-bitport(IP0through
IP5). High or low inputs to the input port result in the
CPU reading a logic one or logic zero, respectively.
Eachinputportbitalsohasanalternatecontrolfunction
capability. The alternate functions can be enabled/
disabled on a bit-by-bit basis.
CRYSTALINPUT(XTAL2)
Ifacrystalisused, itisconnectedbetweenXTAL1and
thisinput,inwhichcaseacapacitorofapproximately15
to 33pF should be connected from this pin to ground. If
anexternalCMOS-levelclockisused, thispinmustbe
leftopen.
1
Four change-of-state detectors are associated with
inputs IP0, IP1, IP2, and IP3. If a high-to-low or low-to-
high transition occurs on any of these inputs and the
new level is stable for more than 25 to 50 microsec-
onds(best-to-worstcasetimes), thecorrespondingbit
intheinputportchangeregister(IPCR)willbeset. The
sampling clock of the change detectors is the XTAL1/
96 tap of the baud-rate generator, which is 38.4kHz if
XTAL1 is 3.6864MHz. A new input level must be
sampled on two consecutive sample clocks to pro-
duce a change detect. Also, users can program the
XR68C92/192 to allow a change of state to generate
an interrupt to the CPU. The IPCR bits are cleared
when the CPU reads the register.
-RESET(RESET)
The XR68C92/192 can be reset by asserting the -
X TA L1
X TA L2
OUTPUTPORT
X 1
The 8 output port pins can either be used as a general-
purpose output port or can be controlled using internal
registerstogeneratesignalsrepresentingvariouscon-
ditions.Associatedwiththeoutputportisanoutputport
register (OPR) that can be bit-wise programmed. A bit
is set (logical 1) by performing a write operation at
address0xEwiththedatahavingthatbit-locationtobe
1 (0 means no change). Similarly, a bit is reset (logical
0) by performing a write operation at address 0xF with
3.6863M H z
C1
22pF
C2
33pF
Figure 1: Crystal Connection
Rev. P1.10
8
XR68C92/192
RESETsignalorsoft-resetbyprogrammingtheappro-
priatecommandregister.Ahardwarereset(assertionof
RESET) clears the following registers:
INTERUPTACKOWLEDGE(-IACK)
This active-low input indicates an interrupt-acknowl-
edge cycle. If there is an interrupt pending (-INT as-
serted) and this pin is asserted, the XR68C92/192
respondsbyplacingtheinterruptvectoronthedatabus
and then asserting -DTACK. If there is no interrupt
pending (-INT negated), the XR68C92/192 ignores
this signal.
• Status registers A and B (SRA and SRB)
• Interrupt mask register (IMR)
• Interrupt status register (ISR)
• Output port register (OPR)
• Output port configuration register (OPCR)
2
REGISTER-SELECT BUS (A1–A4)
The register-select bus lines during read/write opera-
tions select the XR68C92/192 internal registers or
ports.
RESET performs the following operations:
• Initializes the interrupt vector register (IVR) to “0F”
Hex
• Places parallel outputs OP0 through OP7 in the high
state
INTERUPT REQUEST (-INT)
• Places the counter/timer in timer mode
• PlaceschannelsAandBintheinactivestatewiththe
transmitter serial-data outputs (TXA and TXB) in the
mark (high) state.
This active-low, open-drain output signals the CPU
that one or more of the eight maskable interrupting
conditions is true.
CHANNEL A/B TRANSMITTER SERIAL-DATA
OUTPUT (TXA/TXB)
Software resets are not as encompassing and are
achieved by appropriately programming the channel
A and/or B command registers. Reset commands can
be programmed through the command register to
reset the receiver, transmitter, error status, or break-
change interrupts for each channel
The independent transmitter serial-data outputs for
channel A and B transmit the least-significant bit first.
The output is held high (mark condition) when its
associated transmitter is disabled, idle, or operating in
the local loopback mode. (“Mark” is high and “space”
is low). Data is shifted out from this pin on the falling
edge of the programmed clock source.
CHIP-SELECT (-CS)
This active-low input signal, when low, enables data
transfers between the CPU and XR68C92/192 on the
data lines (D0 through D7). These data transfers are
controlled by read/write (R/-W) and the register-select
inputs (A1 through A4). When chip-select is high, the
D0 through D7 data lines are placed in the high-
impedancestate.
CHANNEL A/B RECEIVER SERIAL-DATA INPUT
(RXA/RXB)
The independent receiver serial-data inputs for chan-
nel A and B receive the least-significant bit first. Data
on these pins is sampled on the rising edge of the
programmed clock source.
INPUT PORTS (IP0–IP5)
READ/WRITE (R/-W)
Whenhigh, thisinputindicatesareadcycle, whenlow,
it indicates a write cycle. Assertion of the chip-select
input initiates a cycle.
The input ports can be used as general-purpose
inputs. However, each pin also has an alternate
function(s)describedbelow:
2
DATA TRANSFER ACKOWLEDGE (-DTACK)
This three-state active low output is asserted in read,
write, or interrupt-acknowledge (-IACK) cycles to indi-
cate the proper transfer of data between the CPU and
XR68C92/192. If there is no pending interrupt on an -
IACK cycle, -DTACK is not asserted. At the end of a
transfer,itdriveshighmomentarily,thenisthree-stated
so that it can be “wire-AND”-ed with other -DTACK
sources, like an open-drain signal.
IP0
This input can be used as the channel A clear-to-send
active-low input (-CTSA). A change-of-state detector
(InputPortConfigurationRegisterbit-4)isalsoassoci-
ated with this input.
2
IP1
This input can be used as the channel B clear-to-send
active-low input (-CTSB). A change-of-state detector
Rev. P1.10
9
XR68C92/192
(IPCR bit-5) is also associated with this input.
OP1
ThisoutputisidenticaltoOP0andismeantforchannel
IP2
B of the DUART.
This input can be used as the channel B receiver
external clock input (RxBClk1), or the counter/timer
external clock input. When this input functions as the
external clock to the receiver, the received data is
sampled on the rising edge of the clock. A change-of-
state detector (IPCR bit-6) is also associated with this
input.
2
OP2
Thisoutputcanbeprogrammed(bits0&1ofOPCR)to
represent the channel A transmitter 1X-clock or 16X-
clockoutputorthechannelAreceiver1X-clockoutput.
OP3
This output can be used (when bits 2 & 3 of OPCR are
programmed) as the open-drain active-low counter-
ready output, the open-drain timer output, the channel
Btransmitter1X-clockoutput,orthechannelBreceiver
1X-clockoutput.
IP3
This input can serve as the channel A transmitter
external clock input (TxAClk1). When this input func-
tions as the external clock to the transmitter, the
transmitted data is clocked on the falling edge of the
clock. A change-of-state detector (IPCR bit-7) is also
associated with this input.
OP4
This output, when programmed using bit-4 of OPCR,
can serve as the channel A open-drain active-low
receiver-readyorbuffer-fullinterruptoutputs(RxARDY/
RxAFULL). One of RxARDY or RxAFULL can be se-
lected using bit-6 of MRA1.
IP4
This input can be used as the channel A receiver
external clock input (RxAClk1). When this input func-
tions as the external clock to the receiver, the received
data is sampled on the rising edge of the clock.
OP5
Thisoutput,whenprogrammedusingbit-5ofOPCRcan
beusedasthechannelBopen-drainactive-lowreceiver-
ready or buffer-full interrupt outputs (RxRDYB/
RxBFULL). One of RxBRDY or RxBFULL can be se-
lected using bit-6 of MRB1.
IP5
This input can serve as the channel B transmitter
external clock (TxBClk1). When this input is used as
the external clock to the transmitter, the transmitted
data is clocked on the falling edge of the clock.
OP6
This output can function as the channel A open-drain
active-low transmitter-ready interrupt output
(TxARDY).
OUTPUTPORTS(OP0–OP7)
The output ports can be used as general-purpose
outputs however, each pin also has an alternate
function(s), described below.
OP7
This output can serve as the channel B open-drain
active-lowtransmitter-readyinterruptoutput(TxBRDY).
OP0
This output can function as the channel A transmitter
active-lowrequest-to-sendoutput, orasthechannelA
receiver active-low request-to-send (-RTSA) output.
Thispin,ifassertedbyprogrammingthecorresponding
bit in OPCR, is used by the transmitter (MRA2 bit-5 =
1) to indicate end of transmission by negating it. This
isusefulbecause,evenwhenacommandtodisablethe
transmitter is sent before the data is fully transmitted,
the transmitter sends all the data, negates OP0 and
then gets disabled. When used by the receiver (MRA1
bit-7 = 1), this pin is automatically negated and reas-
serteddependingontheFIFOspaceavailable.
TRANSMITTER
The channel A and B transmitters are enabled for data
transmission through their respective command reg-
isters. The XR68C92/192 signals the CPU that it is
ready to accept a character by setting the transmitter-
ready bit in the channel's status register. Users can
program this condition to generate an interrupt re-
questonthe-INToutput,aninterruptrequestforchannel
A’s transmitter on parallel output OP6, or for channel
B’stransmitteronparalleloutputOP7.Whenacharac-
terisloadedintothetransmitbuffer,theabovecondition
Rev. P1.10
10
XR68C92/192
for the respective channel is negated. Data is trans-
ferredfromthetransmitholdingregistertothetransmit
shift register when the shift register is idle or has
completedtransmissionofthepreviouscharacter.The
transmitter ready conditions are then reasserted, pro-
viding one full character time of buffering. Characters
cannot be loaded into the transmit buffer while the
transmitter is disabled.
byissuingasend-breakcommand.ThestateofCTSis
ignored by the transmitter when it is set to send break.
Asendbreakisdeferredaslongasthetransmitterhas
characters to send, but if normal character transmis-
sion is inhibited by CTS, the send-break will proceed.
The send-break must be terminated by a stop-break,
disable, orresetbeforenormalcharactertransmission
can resume.
ThetransmitterconvertstheparalleldatafromtheCPU
to a serial bit stream on the transmitter serial-data
outputpin. Itautomaticallysendsastartbitfollowedby
theprogrammednumberofdatabits,anoptionalparity
bit,andtheprogrammednumberofstopbits.Theleast-
significant bit is sent first. Data is shifted out the
transmitserialdataoutputpinonthefallingedgeofthe
programmedclocksource.Afterthetransmissionofthe
stop bits, and a new character is not available in the
transmit holding register, the transmitter serial-data
outputremainshighandthetransmitter-emptybitinthe
status register (SRA and SRB) will be set to one.
Transmissionresumesandthetransmitter-emptybitis
cleared when the CPU loads a new character into the
transmit buffer. If the transmitter receives a disable
command, it will continue operating until the character
in the transmit shift register is completely sent out.
Othercharactersintheholdingregisterareneithersent
nor discarded, but will be sent when the transmitter is
re-enabled.Userscanprogramthetransmittertoauto-
maticallynegatetherequest-to-send(RTS)output(al-
ternate function of OP0 and OP1) on completion of a
message transmission. If the transmitter is pro-
grammed to operate in this manner, the RTS output
must be manually asserted before each message is
transmitted. If OP0 (or OP1) is programmed in auto-
matic RTS mode, the RTS output will be automatically
negated when the transmitter is disabled and the
transmit-shift register and holding register are both
empty. In automatic RTS mode, a character in the
holding register is not held back by a disable, but no
more characters can be written to the holding register
after the transmitter is disabled.
The transmitter can be reset through a software com-
mand. If it is reset, operation ceases immediately and
mustbeenabledthroughthecommandregisterbefore
resumingoperation.Resetalsodiscardsanycharacter
in the holding register.
RECEIVER
The channel A and B receivers are enabled for data
reception through the respective channels command
register. The channels receiver looks for the high-to-
low (mark-to-space) transition of a start bit on the
receiver serial-data input pin. If operating in 16X clock
mode, the serial input data is re-sampled on the next
7clocks. Ifthereceiverserialdataissampledhigh, the
start bit is invalid and the search for a valid start bit
begins again. If receiver serial data is still low, a valid
start bit is assumed and the receiver continues to
sample the input at one bit time intervals (at the
theoretical center of the bit) until the proper number of
data bits and the parity bit (if any) have been as-
sembled and one stop bit has been detected. Data on
the receiver serial data input pin is sampled on the
rising edge of the programmed clock source.
During this process, the least-significant bit is re-
ceived first. The data is then transferred to a receive
holding register (RHR) and the receiver-ready bit in
the status register (SRA or SRB) is set to one. This
condition can be programmed to generate an interrupt
request on the -INT output, an interrupt request for
channel A receiver on output pin( OP4), or an interrupt
request for channel B receiver on output pin (OP5). If
the character length is less than eight bits, the most
significant unused bits in the receive holding register
(RHR) are set to zero.
If clear-to-send (CTS) operation is enabled, the CTS
input (alternate function of IP0 or IP1) must be low in
order for the character to be transmitted. If it goes high
inthemiddleofatransmission,thecharacterintheshift
register is transmitted and TX then remains in the
markingstateuntilCTSagaingoeslow.Thetransmitter
can also be forced to send a continuous low condition
If the stop bit is sampled as a 1, the receiver will
immediately look for the next start bit. However, if the
stop bit is sampled as a 0, either a framing error or a
received break has occurred. If the stop bit is 0 and the
data and parity (if any) are not all zero, it is a framing
Rev. P1.10
11
XR68C92/192
error,thedamagedcharacteristransferredtoaholding
register with the framing error flag set. If the receiver
serialdataremainslowforone-halfofthebitperiodafter
the stop bit was sampled, the receiver operates as if a
newstartbittransitionhasbeendetected.Ifthestopbit
is 0 and the data and parity (if any) are also all zero, it
is a break. A character consisting of all zeros will be
loaded into a receive holding register (RHR) with the
received-break bit (but not the framing error bit) set to
one.Thereceiverserial-datainputmustreturntoahigh
conditionforatleastone-halfbittimebeforeasearchfor
the next start bit begins.
statuscanbeprovidedfor“character”or“block”modes.
In the “character” mode, the status register (SRA or
SRB)isupdatedonacharacter-by-characterbasisand
applies only to the character at the top of the FIFO.
Thus, the status must be read before the character is
read. Reading the character pops it and its error flags
off the FIFO. In the “block” mode, the status provided
in the status register for the parity error, framing error,
and received-break conditions are the logical OR of
these respective bits, for all characters coming to the
top of the FIFO stack since the last reset error com-
mandwasissued.Thatis,startingatthelastreset-error
command, a continuous logical-OR function of corre-
sponding status bits is produced in the status register
as each character comes to the top of the FIFO stack.
3
The receiver can detect a break that starts in the
middle of a character provided the break persists
completely through the next character time or longer.
When the break begins in the middle of a character,
the receiver will place the damaged character in a
holding register with the framing error bit set. Then,
providedthebreakpersiststhroughthenextcharacter
time, the receiver will also place an all-zero character
in the next holding register with the received-break bit
set. The parity error, framing error, overrun error, and
received-break conditions (if any) set error and break
flags in the status register at the received character
boundary and are valid only when the receiver-ready
bit (RxRDY) in the status register is set. A first-in first-
out (FIFO) stack is used in each channels receive
bufferlogicandconsistsof8(16forXR68C192)receive
holdingregisters.
The block mode is useful in applications requiring the
exchange of blocks of information where the software
overhead of checking each characters error flags
cannot be tolerated. In this mode, entire messages
can be received and only one data integrity check is
performed at the end of each message. Although data
reception in this manner has speed advantages, there
are also disadvantages. Because each character is
not individually checked for error conditions by the
software, if an error occurs within a message the error
will not be recognized until the final check is per-
formed. Also, there is no indication of which
character(s) is in error within the message.
3
The receiver buffer is composed of the FIFO and a
receive shift register connected to the receiver serial-
data input. Data is assembled in the shift register and
loaded into the top most empty FIFO receive holding
register position. The receiver-ready bit in the status
register (SRA or SRB) is set whenever one or more
characters are available to be read. A read of the
receiverbufferproducesanoutputofdatafromthetop
of the FIFO stack. After the read cycle, the data at the
top of the FIFO stack and its associated status bits are
“popped” and new data can be added at the bottom of
the stack by the receive shift register. The FIFO-full
status bit is set if all eight stack positions are filled with
data. Either the receiver-ready or the FIFO-full status
bits can be selected to cause an interrupt. In addition
to the data byte, three status bits (parity error, framing
error, and received break) are appended to each data
character in the FIFO (overrun is not). By program-
ming the error-mode control bit in the mode register,
Reading the status register (SR) does not affect the
FIFO. The FIFO is “popped” only when the receive
buffer is read. If all 8/16 of the FIFOs receive holding
registersarefullwhenanewcharacterisreceived,that
characterisheldinthereceiveshiftregisteruntilaFIFO
position is available. If an additional character is re-
ceived while this state exists, the contents of the FIFO
arenotaffected,butthecharacterpreviouslyintheshift
registerislostandtheoverrun-errorstatusbitwillbeset
upon receipt of the start bit of the new overrunning
character.
To support flow control, a receiver can automatically
negateandreasserttherequest-to-send(RTS)output
(alternate function of output ports OP0 and OP1). The
request-to-send output will automatically be negated
bythereceiverwhenavalidstartbitisreceivedandthe
FIFO stack is full. When a FIFO position becomes
available,therequest-to-sendoutputwillbereasserted
Rev. P1.10
12
XR68C92/192
automaticallybythereceiver. Connectingtherequest-
to-send output to the clear-to-send (CTS) input of a
transmitting device, prevents overrun errors in the re-
ceiver.TheRTSoutputmustbemanuallyassertedthe
first time. Thereafter, the receiver will control the RTS
output.
remotechannelreceivertobeenabled.
MULTIDROPMODE
Userscanprogramthechanneltooperateinawake-up
modeforMultidropapplications.Thismodeisselected
by setting bits 3 & 4 in Mode Register 1 (MR1). In this
modeofoperation,amasterstationchannel,connected
to several slave stations (a maximum of 256 unique
slave stations), transmits an address character fol-
lowed by a block of data characters targeted for one or
more of the slave stations. In this mode, the channel
receiverswithintheslavestationsaredisabled,butthey
continuouslymonitorthedatastreamsentoutfromthe
masterstation.Whentheslavestationschannelreceiv-
ers detect any address character in the data stream,
each receiver notifies its respective CPU by setting
receiverready(RXRDY)andgeneratinganinterrupt,if
programmed to do so. Each slave station CPU then
compares the received address to its station address
and enables its receiver if it wants to receive the
subsequent data from the master station.
If the FIFO stack contains characters and the receiver
is then disabled, the characters in the stack can still be
read but no additional characters can be received until
the receiver is again enabled. If the receiver is dis-
abled while receiving a character, or while there is a
character in the shift register waiting for a FIFO
opening, these characters are lost. If the receiver is
reset, the FIFO stack and all of the receiver status bits,
the corresponding output ports, and the interrupt
request are reset. No additional characters can be
received until the receiver is again enabled.
LOOPBACK MODES
Besides the normal operation mode in which the
receiver and transmitter operate independently, each
XR68C92/192channelcanbeconfiguredtooperatein
various looping modes that are useful for local and
remote system diagnostic functions.
Slave stations that are not addressed continue moni-
toring the data stream for the next address character.
Anaddresscharacterflagstheendofoneblockofdata
and the start of another. After receiving a block of
data, the slave stations CPU may disable the channel
receiver and re-initiate the process. A transmitted
character from the master station consists of a start
bit, the programmed number of data bits, an address/
data (A/D) bit flag, and the programmed number of
stop bits. The address/data bit identifies to the slave
stations channel whether the character should be
interpreted as an address character or a data charac-
ter. Thecharacterisinterpretedasanaddresscharac-
ter if the A/D bit is set to a one or interpreted as a data
character if it is set to a zero. The polarity of the
transmitted address/data bit is selected by program-
ming bit two in Mode Register 1 (MR1) to a '1' for an
addresscharacterandtoa'0' fordatacharacters.Users
should program the mode register prior to loading the
corresponding data or address characters into the
transmitbuffer.
3
AUTOMATIC ECHO MODE
In this mode, the channel automatically retransmits
the received data on a bit-by-bit basis. The local CPU-
to-receiver communication continues normally but
the CPU-to-transmitter link is disabled.
LOCAL LOOPBACK MODE
In this mode, the transmitter output is internally con-
nected to the receiver input. The external TX pin is
held in the mark (high) state in this mode. This mode
is useful for testing the operation of a local XR68C92/
192 channel. By sending data to the transmitter and
checking that the data assembled by the receiver is
thesamedatathatwassent,properchanneloperation
can be ensured. In this mode the CPU-to-transmitter
and CPU-to-receiver communications continue nor-
mally.
3
REMOTELOOPBACKMODE
In the Multidrop mode, the receiver continuously
monitors the received data stream regardless of
whether it is enabled or disabled. If the receiver is
disabled, it sets the receiver ready status bit and loads
the character into the FIFO receive holding register
stack provided the received address/data bit is a one
Inthismode,thechannelautomaticallyretransmitsthe
received data on a bit-by-bit basis. The local CPU-to-
receiverandCPU-to-transmitterlinksaredisabled.This
mode is useful in testing the receiver and transmitter
operationofaremotechannel. Thismoderequiresthe
Rev. P1.10
13
XR68C92/192
(addresstag).Thereceivedcharacterisdiscardedifthe
received address/data bit is a zero (data tag). If the
receiver is enabled, all received characters are trans-
ferredtotheCPUbywayofthereceiveholdingregister
stack during read operations. In either case, the data
bits are loaded into the data portion of the FIFO stack
while the address/data bit is loaded into the status
portion of the FIFO stack normally used for parity error
(StatusRegisterbit-5).Framingerror,overrunerror,and
break-detectionoperatenormallyregardlessofwhether
thereceiverisenabledordisabled.Theaddress/databit
takes the place of the parity bit and parity is neither
calculated nor checked for characters in this mode.
OP3. After 0x0000 the counter counts to 0xFFFF, and
continues counting down from there. If the CPU
changesthepre-loadvalue, thecounterwillnotrecog-
nizethenewvalueuntilitreceivesthenextstartcounter
command(andisreinitialized).Whenareadatthestop
counter command address is performed, the counter
stops the countdown sequence and clears ISR Bit-3.
The count value should only be read while the counter
is stopped because only one of the count registers
(eitherCURorCLR)canbereadatatime.Ifthecounter
is running, a decrement of CLR that requires a borrow
fromtheCURcouldtakeplacebetweenthetworeads.
TIMER MODE
COUNTER/TIMER
In timer mode, the C/T generates a square-wave
output derived from the programmed timer input
(clock source). The timer clock source can be the
external clock on the XTAL1 input pin divided by one
or sixteen, or it can be an external input on input port
pin IP2 divided by one or sixteen. The square wave
generated by the timer has a period of 2X (pre-load
value) X (period of clock source), is available as a
clock source for both communications channels and
can be programmed to appear on output pin OP3. The
timer runs continuously, the CPU cannot stop it.
Because the timer cannot be stopped, the count value
(CUR:CLR) should not be read. When a read at the
start counter command address is performed, the
timer terminates the current countdown sequence,
sets its output to 1 (appears un-inverted at OP3), is
initialized to the pre-load value, and begins a new
countdown sequence. When the counter counts from
0x0001 (terminal count), it inverts its output, is re-
initialized to the pre-load value and repeats the count-
downsequence.
The 16-bit counter/timer (C/T) can operate in a
counter mode or a timer mode. In either mode, users
canprogramtheC/Tinput(clocksource)tocomefrom
severalsourcesandprogramtheC/Toutputtoappear
atoutputportpinOP3.Thevalue(pre-loadvalue)stored
in the concatenation of the C/T upper register (CTUR)
andtheC/Tlowerregister(CTLR)canbefrom0x0001
through 0xFFFF and can be changed at any time. In
countermode,theCPUcanstartandstoptheC/T.This
modeallowstheC/Ttofunctionasasystemstopwatch,
areal-timesingleinterruptgenerator,oradevicewatch-
dog.Intimermode,theC/Trunscontinuously,theCPU
cannotstartorstopit. Instead, theCPUonlyresetsthe
C/Tinterrupt. ThismodeallowstheC/Ttobeusedasa
programmable clock source for channels A and B, or
periodicinterruptgenerator.Atpower-upandafterreset,
the C/T operates in timer mode.
COUNTERMODE
Incountermode,theC/Tcountsdownfromthepre-load
valueusingtheprogrammedcounterclocksource.The
counter clock source can be the channel A transmitter
clock, the channel B transmitter clock, the external
clockontheXTAL1pindividedbysixteen,oranexternal
clock on the input port pin IP2. The CPU can start and
stop the counter, and can read the count value
(CUR:CLR)ifthecounterisstopped.Whenareadatthe
start counter command address is performed, the
counter is initialized to the pre-load value and begins a
countdown sequence. When the counter counts from
0x0001 to0x0000(terminalcount),theC/T-readybitin
the interrupt status register (ISR Bit-3) is set.
3
After reaching terminal count a second time, the timer
sets the C/T-ready bit in the interrupt status register
(ISR Bit-3), inverts its output, is re-initialized again,
and begins a new countdown sequence. Users can
program the timer to generate an interrupt request for
thiscondition(everysecondcountdowncycle)onthe-
INT output. If the CPU changes the pre-load value, the
timer will not recognize the new value until either (a) it
reaches the next terminal count and is reinitialized
automatically, or (b) it is forced to re-initialize by a start
command. When a read at the stop counter command
address is performed, the timer clears ISR Bit-3 but
does not stop. Because in timer mode the C/T runs
continuously, it should be completely configured (pre-
Userscanprogramthecountertogenerateaninterrupt
requestforthisconditiononthe-INToutputoroutputpin
Rev. P1.10
14
XR68C92/192
PROGRAMMINGANDREGISTERDESCRIPTIONS
A3 A2 A1 A0
READ
WRITE
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Mode Register A (MR1A, MR2A)
Status Register A (SRA)
Reserved
Mode Register A (MR1A, MR2A)
Clock-Select Register A (CSRA)
CommandRegisterA(CRA)
TransmitterBufferA(TBA)
AuxiliaryControlRegister(ACR)
InterruptMaskRegister(IMR)
Counter/TimerUpperRegister(CTUR)
Counter/TimerLowerRegister(CTLR)
Mode Register B (MR1B, MR2B)
Clock-Select Register B (CSRB)
CommandRegisterB(CRB)
ReceiverBufferA(RBA)
InputPortChangeRegister(IPCR)
InterruptStatusRegister(ISR)
Counter/TimerMSB(CUR)
Counter/TimerLSB(CLR)
Mode Register B (MR1B, MR2B)
Status Register B (SRB)
Reserved
ReceiverBufferB(RBB)
Interrupt-VectorRegister(IVR)
InputPort(IP)
Start-CounterCommand
Stop-CounterCommand
TransmitterBufferB(TBB)
Interrupt-VectorRegister(IVR)
OutputPortConfigurationRegister(OPCR)
Set Output Port Register (OPR) bits
Reset Output Port Register (OPR) bits
load value loaded and start counter command issued)
beforeprogrammingthetimeroutputtoappearonOP3.
Use caution if the contents of a register are changed
during receiver/ transmitter operation as certain
changescanproduceundesiredresults. Forexample,
changing the number of bits per character while the
transmitter is active can transmit an incorrect charac-
ter.Thecontentsoftheclock-selectregister(CSR)and
ACRBit-7 shouldonlybechangedafterthereceiver(s)
andtransmitter(s)havebeenissuedsoftwareRXandTX
reset commands. Most bits of the mode registers
should not be changed during receiver/transmitter op-
eration, except that in Multidrop parity mode, the
address/data parity type bit can be changed at any
time.
areaccessedbyanidenticalpointerindependentofthe
channel A pointer. Mode, command, clock-select, and
statusregistersareduplicatedforeachchanneltoallow
independent operation and control (except that both
channels are restricted to baud rates that are in the
same set).
44
Similarly,certainchangestotheauxiliarycontrolregis-
ter (ACR Bits 4-6) should only be made while the
counter/timer(C/T)isnotused.ChannelAmoderegis-
ters MR1A and MR2A are accessed via an auxiliary
pointer.Thepointerissettomoderegisterone(MR1A)
byRESETorbyissuinga“resetpointer”commandvia
the channel A command register. Any read or write of
themoderegisterswitchesthepointertomoderegister
two (MR2A). All subsequent accesses will address
MR2AunlessthepointerisresettoMR1Aasdescribed
above.ThechannelBmoderegistersMR1BandMR2B
Rev. P1.10
15
XR68C92/192
A3 A2 A1 A0
Register
[Default]
BIT-7
BIT-6
BIT-5
BIT-4
BIT-3
BIT-2
BIT-1
BIT-0
0
1
0
0
0
0
0
0
MRA0 [00]
MRB0[00]
Watch
dog timer
RX
trigger
level
TX
trigger
level
TX
trigger
level
Not
used
Baud
rate
ext. 2
Not
used
Baud
rate
ext. 1
0
1
0
0
0
0
0
0
MRA1[00]
MRB1[00]
RX
RTS
control
RX
trigger
level
Error
mode
Parity
mode
Parity
mode
Parity
type
Word
length
Word
length
0
1
0
0
0
0
0
0
MRA2[00]
MRB2[00]
Channel
mode
Channel
mode
TX
RTS
TX
CTS
Stop
bit
Stop
bit
Stop
bit
Stop
bit
select
select
control
control
length
length
length
length
0
1
0
0
0
0
1
1
CSRA[00]
CSRB[00]
RX
clock
RX
clock
RX
clock
RX
clock
TX
clock
TX
clock
TX
clock
TX
clock
0
1
0
0
0
0
1
1
SRA[00]
SRB[00]
Received
break
Framing
error
Parity
error
Overrun
error
TX
empty
TX
ready
RX
FIFO
full
RX
ready
0
1
0
0
1
0
0
0
CRA[00]
CRB[00]
Misc.
Misc.
Misc.
Misc.
TX
disable
TX
enable
RX
disable
RX
enable
command command command command
0
1
0
0
1
1
1
1
RHRA[XX]
RHRB[XX]
Bit-7
Bit-7
Bit-6
Bit-6
Bit-5
Bit-5
Bit-4
Bit-4
Bit-3
Bit-3
Bit-2
Bit-2
Bit-1
Bit-1
Bit-0
Bit-0
0
1
0
0
1
1
1
1
THRA[XX]
THRB[XX]
0
1
0
0
ACR[00]
Baud
rate
C/T
mode
C/T
mode
C/T
mode
Delta
IP3
Delta
IP2
Delta
IP1
Delta
IP0
set
INT
INT
INT
INT
select
0
0
1
1
0
0
0
1
IPCR[00]
ISR[00]
Delta
IP3
Delta
IP2
Delta
IP1
Delta
IP0
IP3
input
IP2
input
IP1
input
IP0
input
Input
port
change
Delta
break B
RXB
ready/
FIFOfull
TXB
ready
C/T
ready
Delta
break A
RXA
ready/
FIFOfull
TXA
ready
0
1
0
1
IMR[00]
Input
port
change
Delta
break B
RXB
ready/
FIFOfull
TXB
ready
C/T
ready
Delta
break A
RXA
ready/
FIFOfull
TXA
rdy
0
0
1
1
1
1
1
1
0
0
1
1
CTU[00]
CTL[00]
IPR[XX]
Bit-15
Bit-7
Bit-14
Bit-6
Bit-13
Bit-5
IP5
Bit-12
Bit-4
IP4
Bit-11
Bit-3
IP3
Bit-10
Bit-2
IP2
Bit-9
Bit-1
IP1
Bit-8
Bit-0
IP0
Not
Not
Used
Used
1
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
0
0
1
1
OPCR[00]
STCC[XX]
SOPB[00]
SPCC[XX]
ROPB
OP7
X
OP6
X
OP5
X
OP4
X
OP3
X
OP3
X
OP2
X
OP2
X
Bit-7
X
Bit-6
X
Bit-5
X
Bit-4
X
Bit-3
X
Bit-2
X
Bit-1
X
Bit-0
X
Bit-7
Bit-6
Bit-5
Bit-4
Bit-3
Bit-2
Bit-1
Bit-0
Rev. P1.10
16
XR68C92/192
MR0A/B
MR0
MR1
Mode register 0. This register is accessed only when
command is applied via CR A/B register. After reading
or writing to MR0 A/B register, the pointer will point to
MR1 A/B register.
Bit-6
Bit-6
XR68C192
0
0
1
1
0
1
0
1
1 byte in FIFO
6 bytes in FIFO
12 bytes in FIFO
16 bytes in FIFO
MR0 A/B Bit-0.
Extended baud rate table selection.
0 = Normal baud rate tables
1 = Extend baud rate tables (1)
MR0 A/B Bit-7.
Receive time-out (watch dog timer).
0 = Disabled
MR0 A/B Bit-1.
1 = Enabled
0=RegularOperation
1 = Factory test mode
MR1 A/B
Mode register 1. MR1 A/B are accessed after reset or
by command applied via CR A/B register. After read-
ing or writing to MR1 A/B register, the pointer will point
to MR2 A/B register.
MR0 A/B Bit-2.
Extended baud rate table selection.
0 = Normal baud rate tables
1 = Extend baud rate tables (2)
MR1 A/B Bits 1-0.
Character Length
0 0 = 5
MR0 A/B Bit-3.
Not used.
0 1 = 6
MR0A/BBits5-4
1 0 = 7
Transmittriggerlevels:
1 1 = 8
MR0
Bit-5
MR0
Bit-4
MR1 A/B Bit-2.
Parity Type
XR68C92
0
0
1
1
0
1
0
1
8 FIFO locations empty
4 FIFO locations empty
6 FIFO locations empty
1 FIFO location empty
0 = Even Parity
1 = Odd Parity
MR1 A/B Bit 4-3.
Parity mode
MR0
Bit-5
0
0
1
1
MR0
Bit-4
0
1
0
1
00 = With parity
01 = Force parity
10 = No parity
XR68C192
16 FIFO locations empty
6 FIFO locations empty
12 FIFO locations empty
1 FIFO location empty
11 = Multidrop mode
MR1 A/B Bit-5.
Dataerrormode
MR0 A/B Bit-6.
Receivetriggerlevels:
0 = Single Character mode
1 = Block (FIFO) mode
MR0
MR1
MR1 A/B Bit-6.
Bit-6
Bit-6
XR68C92
ReceiveInterruptmodeselect.
0 = Single character mode (RxRdy)
1 = FIFO Full mode (FFULL)
0
0
1
1
0
1
0
1
1 byte in FIFO
3 bytes in FIFO
6 bytes in FIFO
8 bytes in FIFO
MR1 A/B Bit-7.
Auto RTS flow control.
Rev. P1.10
17
XR68C92/192
0 = Normal. No RTS control function.
1 = Auto RTS control function
CSR A/B Bits 7-4.
Receive clock select (see baud rate table)
MR2A/B
MISCELLANEOUSCOMMANDREGISTERCRA/B
CR A/B register is used to supply commands to A/B
channels. Multiple commands can be specified in a
single write to CR A/B as long as commands are non-
conflicting.
Moderegister2.Thisregisterisaccessedafteranyread
or write operation to MR1 A/B register is performed.
Access to MR2 A/B does not change the pointer.
MR2 A/B Bits 3-0.
Stop bit length
0000 = 0.563
0001 = 0.625
0010 = 0.668
0011 = 0.750
0100 = 0.813
0101 = 0.875
0110 = 0.938
0111 = 1.000
1000 = 1.563
1001 = 1.625
1010 = 1.668
1011 = 1.750
1100 = 1.813
1101 = 1.875
1110 = 1.938
1111 = 2.000
CRA/BBits1-0.
ReceiverCommands
0 0 = No Action, Stays in Present Mode
0 1 = Receiver Enabled
1 0 = Receiver Disabled
1 1 = Not Used
CRA/BBits3-2.
TransmitterCommands
0 0 = No Action, Stays in Present Mode
0 1 = Transmitter Enabled
1 0 = Transmitter Disabled
1 1 = Not Used
CRA/BBits7-4.
MiscellaneousCommands.
0 0 0 0 = NoCommand.
0 0 0 1 = Reset MR Pointer to MR1.
0 0 1 0 = Reset Receiver. Receiver is disabled and
FIFO is flushed.
MR2 A/B Bit-4.
Auto CTS flow control
0 0 1 1 = Reset Transmitter. Transmitter is disabled
and FIFO is flushed.
0 = Normal. No CTS control function
1 = Auto CTS control function.
0 1 0 0 = Reset Error Status. Clears channel A/B,
break, parity, and over-run error bits in the
status register.
MR2 A/B Bit-5.
TransmitRTScontrol.
0 1 0 1 = Reset Channels Break-Change Interrupt.
Clears channel A/B break detect change bit
in the interrupt status register (ISR Bit-2).
0 1 1 0 = StartBreak.Forcesthetransmitteroutputto
go low and stay low. If transmitter is empty
the start of the break condition will be de-
layed up to two bit times. If transmitter is
active, the break begins when transmission
ofthecharacteriscompleted.Allcontentsof
theFIFOhastobetransmittedbeforebreak
signal takes place. Transmitter must to be
enabled for this command to be accepted.
0 1 1 1 = Stop Break. Transmit output will go high
within two bit times.
0 = Normal. No control function
1 = Transmit RTS function enable.
MR2 A/B Bit 7-6.
Channel Mode.
0 0 = Normal
0 1 = Automatic Echo
1 0 = Local Loopback
1 1 = Remote Loopback
CLOCKSELECTREGISTER-CSRA/B
Transmit / Receive baud rates can be selected via this
register.
CSR A/B Bits 3-0.
1 0 0 0 = Set -RTS output to low.
Transmit clock select (see baud rate table)
1 0 0 1 = Reset -RTS output to high.
Rev. P1.10
18
XR68C92/192
Baud Rate Table (based on a 3.6864MHz clock)
MR0Bits
2,0=0
MR0Bit-0=1
(extended 1)
MR0Bit-2=1
(extended 2)
CSR
A/B
SET-1
ACR
SET-2
ACR
SET-1
ACR
SET-2
ACR
SET-1
ACR
SET-2
ACR
Bit-7=0
Bit-7=1
Bit-7=0
Bit-7=1
Bit-7=0
Bit-7=1
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
50
110
134.5
200
300
600
1200
1050
2400
4800
7200
9600
38.4k
Timer
IP4-16X
IP4-1X
75
110
134.5
150
300
600
1200
2000
2400
4800
1800
9600
19.2k
Timer
IP4-16X
IP4-1X
300
110
134.5
1200
1800
3600
450
110
134.5
900
1800
3600
4800
680
1076
19.2k
28.8k
57.6k
115.2k
1050
57.6k
4800
57.6k
9600
38.4k
Timer
IP4-16X
IP4-1X
7200
680
1076
14.4k
28.8k
57.6k
115.2k
2000
57.6k
4800
14.4k
9600
19.2k
Timer
IP4-16X
IP4-1X
7200
1050
7200
2000
14.4k
28.8k
7200
57.6k
230.4k
Timer
IP4-16X
IP4-1X
14.4k
28.8k
1800
57.6k
115.2k
Timer
IP4-16X
IP4-1X
1 01 0 = Set Timeout Mode On. The receiver in this
channel will restart the C/T as each receive
characteristransferredfromtheshiftregister
tothereceiveFIFO. TheC/Tisplacedinthe
counter mode, the START/STOP counter
commands are disabled, the counter is
stopped,andtheCounterReadyBit,ISRBit-
3 is reset. (See also Watchdog timer de-
scription in the receiver section.)
Whileinthepowerdownmode, donotissue
any commands to the CR A/B except the
disable power down mode command. The
contentsofallregisterswillbesavedwhilein
thismode.Itisrecommendedthatthetrans-
mitterandreceiverbedisabledpriortoplac-
ingtheDUARTintopowerdownmode. This
command is in CRA only.
1 1 1 1 = Disable Power Down Mode. This command
restarts the oscillator. After invoking this
command, wait for the oscillator to start up
beforewritingfurthercommandstotheCRA/
B. This command is in CRA only. For maxi-
mumpowerreductioninputpinsshouldbeat
GND or VCC.
1 0 1 1 = Set MR pointer to MR0.
1 1 0 0 = Disable Timeout Mode. This command re-
turns control of the C/T to the regular Start/
Stopcountercommands.Itdoesnotstopthe
counter, or clear any pending interrupts.
After disabling the timeout mode, a “Stop
Counter”commandshouldbeissuedtoforce
a reset of the ISR Bit-3.
STATUSREGISTER(SRA/SRB)
1 1 0 1 = Not used.
1 1 1 0 = Power Down Mode On. In this mode, the
DUART oscillator is stopped and all func-
tionsrequiringthisclockaresuspended.The
execution of commands other than disable
powerdownmode(1111)requiresaXTAL1.
SR A/B Bit-0.
ReceiveReady.
This bit indicates that one or more character(s) has
beenreceivedandiswaitingintheFIFOfortheCPUto
read it. It is set when the first character is transferred
Rev. P1.10
19
XR68C92/192
from the receive shift register to the empty FIFO, and
clearedwhentheCPUreadsthereceiverbuffer,ifthere
are no more characters in the FIFO after the read.
bitpositionstoresthereceivedaddress/databit.Thisbit
is valid only when the RxRDY bit is set (SR A/B Bit-0 =
1).
SR A/B Bit-1.
SR A/B Bit-6.
ReceiveFIFOFull.
Framing Error.
This bit is set when a character is transferred from the
receive shift register to the receiver FIFO and the
transfer fills the FIFO. All eight FIFO holding register
positions are occupied. It is cleared when the CPU
reads the receiver buffer, unless a ninth character is in
thereceiveshiftregisterwaitingforanemptyFIFOslot.
This bit (when set) indicates that a stop bit was not
detectedwhenthecorrespondingdatacharacterinthe
FIFO was received. The stop bit check is made in the
middle of the first stop bit position. This bit is valid only
when the RxRDY bit is set (SR A/B Bit-0 = 1). Framing
errorandbreakareexclusive:Atleastonedatabitand/
or the parity bit must have been a 1 to signal a framing
error.Afteraframingerror,thereceiverdoesnotwaitfor
the line to return to the marking state (high), if the line
remains low for 1/2 a bit time after the stop bit sample
(thatis,thenominalendofthefirststopbit),thereceiver
treats it as the beginning of a new start bit.
SR A/B Bit-2.
TransmitReady.
This bit (when set) indicates that the transmit holding
registerisemptyandreadytobeloadedwithacharac-
ter. Transmitter ready is set when the character is
transferred to the transmit shift register. This bit is
cleared when the CPU loads the transmit holding
register, or when the transmitter is disabled.
SR A/B Bit-7.
Received Break.
This bit indicates an all-zero character of the pro-
grammed length has been received without a stop bit.
This bit is valid only when the RxRDY bit is set (SR A/
B Bit-0 = 1). Only a single FIFO position is occupied
when a break is received, additional entries to the
FIFO are inhibited until the channel A/B receiver serial
data input line returns to the marking state. The break-
detect circuitry can detect a break that starts in the
middle of a received character, however, the break
condition must persist completely through the end of
the current character and the next character time to be
recognized.
SR A/B Bit-3.
Transmit Empty.
This bit will be set when the channel A/B transmitter
under-runs (empty). Both the transmit holding register
and the transmit shift register are empty. It is set after
transmission of the last stop bit of a character if no
character is in the transmit holding register awaiting
transmission. It is cleared when the CPU loads the
transmit holding register or when the transmitter is
disabled.
SR A/B Bit-4.
OverrunError.
OUTPUT PORT CONFIGURATION REGISTER
(OPCR)
This bit (when set) indicates one or more characters in
thereceiveddatastreamhavebeenlost.Itbecomesset
on receipt of a valid start bit when the FIFO is full and a
characterisalreadyinthereceiveshiftregisterwaiting
for an empty FIFO position. When this occurs, the
character in the receive shift register (and its break
detect, parity error, and framing error status, if any) is
lost. A reset error status command clears this bit.
This register selects following options for output
ports.4Alternate functions of OP1 and OP0 are con-
trolledbythemoderegisters,nottheOPCR.MR1ABit-
7 and MR2A Bit-5 control OP0, MR1B Bit-7 and MR2B
Bit-5 control OP1.
OP2 output select
0 0 = The complement of OPR
0 1 = TxAClk16-Transmit A 16X clock
1 0 = TxAClk1-Transmit A 1X clock
1 1 = RxAClk1- Receive A 1X clock
SR A/B Bit-5.
Parity Error.
This bit becomes set when the “with parity” or “force
parity”modeisprogrammedbymoderegisteroneand
thecorrespondingcharacterintheFIFOisreceivedwith
incorrect parity. In the Multidrop mode, the parity error
Rev. P1.10
20
XR68C92/192
OP3 output select
0 0 = The complement of OPR
0 1 = C/T Output 1
MODE CLOCK
SOURCE
1 0 = TxBClk1-Transmit B 1X clock
1 1 = RxBClk1- Receive B 1X clock
0 0 0
0 0 1
0 1 0
0 1 1
Counter External(IP2)
Counter TXAClk1-Transmit A 1X clock
Counter TXBClk1-Transmit B 1X clock
Counter Crystal or External Clock
(XTAL1/Clk) Divided by 16
If OP3 is to be used for the timer output, Users should
program the counter/timer for timer mode (ACR Bit-6
= 1), initialize the counter/timer pre-load registers
(CTUR and CTLR), and the start counter command
issued before setting OPCR Bits 3-2 = 01.
1 0 0
1 0 1
1 1 0
Timer
Timer
Timer
External (IP2)
External (IP2) Divided by 16
Crystal or External Clock
(XTAL1/Clk)
OP4 output select
0 = The complement of OPR
1 = -RxARDY/-RxAFULL
1 1 1
Timer
Crystal or External Clock
(XTAL1/Clk)Dividedby16
ACRBit-7
OP5 output select
0 = The complement of OPR
1 = -RxBRDY/-RxBFULL
Baud rate table Select. Should only be changed after
both channels have been reset and are disabled.
0 = Set 1
1 = Set 2
OP6 output select
0 = The complement of OPR
1 = -TxARDY
INPUT PORT CHANGE REGISTER (IPCR)
OP7 output select
0 = The complement of OPR
1 = -TxBRDY
IP Level Bits 3-0.
0 = Low
1 = High
Output Port Register (OPR)
All bits, unless programmed for alternate function, can
be set high or low individually:
IP Delta Bits 7-4.
0 = No
1 = Yes
0 = Sets output port high
1 = Sets output port low
For example, setting bit-4 to 1 will set OP4 low.
INTERRUPTSTATUSREGISTER(ISR)
Thisregisterprovidesthestatusofallpotentialinterrupt
sources. The contents of this register are logically
“AND”-edwiththecontentsoftheinterruptmaskregis-
ter, and the results are "NOR"-ed to produce the -INT
output.Allactiveinterruptsourcesarevisiblebyreading
theISR,regardlessofthecontentsoftheinterruptmask
register.ReadingtheISRhasnoeffectonanyinterrupt
source.Eachactiveinterruptsourcemustbeclearedin
a source-specific fashion to clear the ISR. All interrupt
sources are cleared when the XR68C92/192 is reset.
4
AUXILIARYCONTROLREGISTER(ACR)
ACRBits3-0.
This field selects which bits of the input port change
register (IPCR) cause the input change bit in the
interrupt status register (ISR Bit-7) to be set.
0 = Disabled
1 = Enabled
ACRBits6-4.
ISR Bit-0.
Counter/TimerModeandClockSource.Shouldonlybe
alteredwhiletheC/Tisnotinuse(stoppedifincounter
mode,outputand/orinterruptmaskedifintimermode).
TransmitreadyA.ThisbitisthechannelAequivalentof
ISR Bit-4.
ISR Bit-1.
Receive ready A or FIFO full. The function of this bit is
Rev. P1.10
21
XR68C92/192
programmedbyMR1ABit-6.Ifprogrammedasreceiver
ready, it is a copy of the SRA Bit-0. If programmed as
FIFO full, it is a copy of the SRA Bit-1.
zero, the state of the bit in the interrupt status register
hasnoeffectonthe-INToutput. Notethattheinterrupt
mask register does not mask the programmable inter-
rupt outputs OP7 through OP3 or the value read from
the interrupt status register.
ISR Bit-2.
Channel A change in break. This bit (when set) indi-
cates that the channel A receiver has detected the
beginning or the end of a break condition. It is reset
when the CPU issues a channel A reset break change
interrupt command.
IMR Bit-0.
0 = Normal, no interrupt.
1 = Enable channel A transmit ready interrupt.
IMR Bit-1.
ISR Bit-3.
0 = Normal, no interrupt.
Counter/Timer ready. In counter mode, this bit is set
when the counter reaches terminal count. In timer
mode, this bit is set each time the timer output
switches from low to high.
1 = Enable channel A receive ready or FIFO full
interrupt. RxRDY or FIFO-full is selected via MR1A
Bit-6.
IMR Bit-2.
ISR Bit-4.
0 = Normal, no interrupt.
Transmit ready B. This bit is a duplicate of the channel
B status register transmitter ready bit.
1 = Enable channel A received break signal interrupt.
IMR Bit-3.
ISR Bit-5.
0 = Normal, no interrupt.
1 = Enable Timer/Counter interrupt.
Receive ready B or FIFO full. The function of this bit
is programmed by MR1B Bit-6. If programmed as
receiver ready, it is a copy of the SRB Bit-0. If
programmed as FIFO full, it is a copy of the SRB Bit-
1.
IMRBit-4.
0 = Normal, no interrupt.
1 = Enable channel B transmit ready interrupt.
ISR Bit-6.
IMR Bit-5.
ChannelBchangeinbreak.Thisbit(whenset)indicates
thatthechannelBreceiverhasdetectedthebeginning
ortheendofabreakcondition.ItisresetwhentheCPU
issues a channel B reset break change interrupt com-
mand.
0 = Normal, no interrupt.
1 = Enable channel B receive ready or FIFO full
interrupt.RxRDYorFIFO-fullisselectedviaMR1BBit-
6.
IMRBit-6.
ISR Bit-7.
0 = Normal, no interrupt.
Input port change status. This bit is a “1” when a
changeofstatehasoccurredattheIP0,IP1,IP2,orIP3
inputs and that event has been enabled to cause an
interrupt by the programming of ACR Bits 3-0. This bit
is cleared when the CPU reads the input port change
register.
1 = Enable channel B received break signal interrupt.
IMRBit-7.
0 = Normal, no interrupt.
1 = Enable input port state change interrupt.
INPUT PORT REGISTER
INTERRUPTMASKREGISTER(IMR)
State of the input ports (IP0-IP6) can be read via this
register.
This register selects which bits in the interrupt status
register can cause an interrupt output. If a bit in the
interrupt status register is a “1” and the corresponding
bit in this register is also a “1”, the -INT output will be
asserted. If the corresponding bit in this register is a
IPR Bit 0-6.
0 = Inputs are in low state.
1 = Inputs are in high state.
Rev. P1.10
22
XR68C92/192
IPR Bit-7.
Not used and set to “0”.
COUNTER REGISTER (CUR and CLR)
The count upper register (CUR) and count lower
register (CLR) hold the most-significant byte and the
least-significant byte, respectively, of the current
counter value. These registers should only be read
when the C/T is in counter mode and the counter is
stopped.
START COUNTER / TIMER REGISTER
Reading from this register will start Timer counter
function. Returned data values should be ignored.
STOPCOUNTERTIMERREGISTER
Readingfromthisregisterwillissueastopcommandto
Timercounterfunction.Returneddatavaluesshouldbe
ignored.
SET OUTPUT PORT REGISTER
Output ports (OP0-OP7) can be set to low by writing a
“1”toeachindividualbits.Outputswillchangestateonly
when OPCR register bits are assigned to general
purpose output pins. When output is set to low, it can
not change state to high unless reset output port
command is issued.
SOPR Bit 0-7.
0 = No change.
1 = Set output port to low.
RESET OUTPUT PORT BITS REGISTER
Each output port bit can be changed to high state by
writing a “1” to each individual bit.
SOPR Bit 0-7.
0 = No change.
1 = Reset output port to high.
4
INTERRUPT VECTOR REGISTER (IVR)
This register contains the interrupt vector. When the
XR68C92respondstoavalidinterruptacknowledge(-
IACK) cycle, the contents of this register are placed on
thedatabus.Atreset,thisregisterwillcontain“0F”hex,
which is the M68000 exception vector assignment for
un-initializedinterruptvectors.
Rev. P1.10
23
XR68C92/192
AC ELECTRICAL CHARACTERISTICS
TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.
Symbol
Parameter
Limits
3.3
Limits
5.0
Units
Conditions
Min
Max
Min
Max
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
T
1w,
3w
AS
AH
RWS
RWH
DD
DS
DH
DF
AKL
AKH
AKT
CSL
CSH
9s
9h
10d
11d
T2w
Clock pulse duration
17
17
ns
MHz
Oscillator/Clockfrequency
Address Valid to -CS Low
-CS High to Address Invalid
R/-W Setup Time to -CS Low
R/-W Hold Time from -CS High
-CS Low to Data Valid (Read)
Data Valid to -CS High (Write)
-CS High to Data Invalid (Write)
-CS High to Data Hi-Z (Read)
-CS Low to -DACK Low
-CS High to -DACK High
-CS High to -DACK Hi-Z
-CS Low Pulse Width
-CS High Pulse Width
Port input setup time
Port input hold time
Delay from R/-W to output
Delay to reset interrupt from R/-W
Reset pulse width
8
24
ns
0
0
0
0
0
0
0
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
clks
clks
51
32
20
1
10
1
30
70
45
70
20
42
27
43
100
100
0
70
70
0
T
T
T
TR
N
0
0
110
100
110
100
2
1
2
1
Baudratedivisor
216-1
216-1
Rev. P1.10
24
XR68C92/192
ABSOLUTE MAXIMUM RATINGS
Supply range
7 Volts
GND - 0.3 V to VCC +0.3 V
-40° C to +85° C
Voltage at any pin
Operating temperature
Storage temperature
Package dissipation
-65° C to 150° C
500 mW
DC ELECTRICAL CHARACTERISTICS
TA=0° - 70°C (-40° - +85°C for Industrial grade packages), Vcc=3.3 - 5.0 V ± 10% unless otherwise specified.
Symbol
Parameter
Limits
3.3
Limits
5.0
Units
Conditions
Min
Max
Min
Max
VILCK
VIHCK
VIL
VIH
VOL
VOL
VOH
VOH
IIL
Clock input low level
Clock input high level
Inputlowlevel
-0.3
2.4
-0.3
2.0
0.6
VCC
0.8
-0.5
3.0
-0.5
2.2
0.6
VCC
0.8
VCC
0.4
V
V
V
V
V
V
V
V
Inputhighlevel
Output low level on all outputs
Output low level on all outputs
Outputhighlevel
Outputhighlevel
Inputleakage
Clockleakage
Avgpowersupplycurrent
XR68C92
IOL= 5 mA
IOL= 4 mA
IOH= -5 mA
IOH= -1 mA
0.4
2.4
2.0
±10
±10
3
±10
±10
6
µA
µA
mA
ICL
ICC
ISB
Avg stand by supply current
100
50
150
70
µA
µA
Typ.@25oC
XR68C192
ISB
CP
Avg stand by supply current
200
100
5
300
140
5
µA
µA
pF
Typ.@25oC
Inputcapacitance
Rev. P1.10
25
XR68C92/192
TAS
TAH
A4-A1
TRW S
TRW H
R /-W
-C S
TCSL
TCSH
TDD
TDF
D 7-D 0
-D AC K
Valid Data
TAK T
TAK L
TAK H
R ead C ycle Tim ing
TAS
TAH
A4-A1
TRW S
TRW H
R /-W
-C S
TCSL
TCSH
TDS
TDH
D 7-D 0
-D AC K
TAK T
TAK L
TAK H
W rite Cycle Tim ing
Figure 2: Bus Timing (Read/Write cycle)
Rev. P1.10
26
XR68C92/192
RX
D1
D2
D8
D9
D10
D11
D12
D13
D12, D13 Will be lost
due to RX disable
RX
ENABLE
-RxRDY
-FFULL
-RxRDY/
-FFULL
-CS
Status Data
(D10)
Status Data Status Data
(D2) (D3)
Status Data
(D1)
D11 Will be lost
due to overrun
Reset by
command
OVERRUN
ERROR
-RTS
XR6892-RX
Figure 3: Receive Timing
Break
D1
D2
D3
D4
D5
TX
TX
ENABLE
-TxRDY
R/-W
-CTS
-RTS
XR6892-TX
Figure 4: Transmit Timing
Rev. P1.10
27
XR68C92/192
IP6-IP0
T9s
T9h
-CS
XR6892-IP
Figure 5: Input Port Timing
R/-W
T10d
Old Data
New Data
OP7-OP0
XR6892-OP
Figure 6: Output Port Timing
R/-W
-CS
T11d
T11d
-INT
XR6892-NT
Figure 7: Interrupt Timing
T1w
T2w
ExCLK
XR92-CK
T3w
Figure 8: External clock Timing
Rev. P1.10
28
XR68C92/192
40 LEAD PLASTIC DUAL-IN-LINE
(600 MIL PDIP)
Rev. 1.00
40
1
21
E1
20
E
D
A2
A1
A
L
Seating
Plane
C
α
B
B1
e
eA
eB
INCHES
MILLIMETERS
MIN MAX
SYMBOL
MIN
0.16
MAX
0.25
0.07
0.195
0.024
0.07
0.014
2.095
0.625
0.58
A
A1
A2
B
B1
C
4.06
0.38
6.35
1.78
0.015
0.125
0.014
0.03
0.008
1.98
3.18
4.95
0.36
0.56
0.76
1.78
0.2
0.38
D
E
50.29
15.24
12.32
53.21
15.88
14.73
0.6
0.485
E1
e
eA
eB
L
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
0.6
0.115
0°
0.7
0.2
15°
15.24
2.92
0°
17.78
5.08
15°
a
Note: The control dimension is the inch column
Rev. P1.10
29
XR68C92/192
44 LEAD PLASTIC LEADED CHIP CARRIER
(PLCC)
Rev. 1.00
C
D
Seating Plane
A2
D 1
45° x H1
45° x H2
2
1
44
B1
B
D
D1
D3
D2
e
R
D3
A1
A
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.18
MIN
MAX
4.57
3.05
---
0.165
0.09
4.19
2.29
0.51
0.33
0.66
0.19
17.4
16.51
14.99
A
A1
A2
B
0.12
0.02
---.
0.013
0.026
0.008
0.685
0.65
0.021
0.032
0.013
0.695
0.656
0.63
0.53
0.81
0.32
17.65
16.66
16
B1
C
D
D1
D2
D3
e
0.59
0.500 typ.
0.050 BSC
12.70 typ.
1.27 BSC
1.07
0.042
0.056
0.048
0.045
1.42
1.22
1.14
H1
H2
R
0.042
0.025
1.07
0.64
Note: The control dimension is the inch column
Rev. P1.10
30
XR68C92/192
44 LEAD THIN QUAD FLAT PACK
(10 mm x 10 mm x 1.4 mm, TQFP)
Rev. 1.00
D
D1
33
23
34
22
D1
D
44
12
1
11
B
e
A2
C
A
α
Seating Plane
A1
L
INCHES
MIN
MILLIMETERS
SYMBOL
MAX
0.063
0.006
0.057
0.018
0.008
0.48
MIN
1.4
0.05
1.35
0.3
0.09
11.8
9.9
MAX
1.6
0.15
1.45
0.45
0.2
0.055
0.002
0.053
0.012
0.004
0.465
0.39
A
A1
A2
B
C
D
D1
e
L
12.2
10.1
0.398
0.0315 BSC
0.018 0.03
7°
0.80 BSC
0.45
0°
0.75
7°
0
°
a
Note: The control dimension is the inch column
Rev. P1.10
31
XR68C92/192
NOTICE
EXARCorporationreservestherighttomakechangestotheproductscontainedinthispublicationinordertoimprove
design,performanceorreliability.EXARCorporationassumesnoresponsibilityfortheuseofanycircuitsdescribed
herein, conveysnolicenseunderanypatentorotherright, andmakesnorepresentationthatthecircuitsarefreeof
patentinfringement.Chartsandschedulescontainedhereinareonlyforillustrationpurposesandmayvarydepending
upon a user’s specific application. While the information in this publication has been carefully checked; no
responsibility, however, is assumed for in accuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure
ormalfunctionoftheproductcanreasonablybeexpectedtocausefailureofthelifesupportsystemortosignificantly
affectitssafetyoreffectiveness.ProductsarenotauthorizedforuseinsuchapplicationsunlessEXARCorporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the
circumstances.
Copyright 2000 EXARCorporation
Datasheet May 2000
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. P1.10
32
相关型号：
XR68M752IL32-F
Serial I/O Controller, 2 Channel(s), 2MBps, CMOS, 5 X 5 MM, 0.90 MM HEIGHT, GREEN, QFN-32
EXAR
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