XRA1201PIL24TR-F [EXAR]
16-BIT I2C/SMBUS GPIO EXPANDER;
| 型号： | XRA1201PIL24TR-F |
| 厂家： | 
EXAR CORPORATION |
| 描述： | 16-BIT I2C/SMBUS GPIO EXPANDER |
| 文件： | 总17页 (文件大小：493K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRA1201/1201P
16-BIT I2C/SMBUS GPIO EXPANDER
SEPTEMBER 2011
REV. 1.0.0
FEATURES
GENERAL DESCRIPTION
• 1.65V to 3.6V operating voltage
• 16 General Purpose I/Os (GPIOs)
• 5V tolerant inputs
The XRA1201/1201P is a 16-bit GPIO expander with
2
an I C/SMBus interface.
After power-up, the
XRA1201 has internal 100K ohm pull-up resistors on
each I/O pin that can be individually enabled. The
XRA1201P has the internal pull-up resistors enabled
upon power-up in case it is necessary for the inputs
to be in a known state.
• Maximum stand-by current of 1uA at +1.8V
2
• I C/SMBus bus interface
2
■ I C clock frequency up to 400kHz
In addition, the GPIOs on the XRA1201/1201P can
individually be controlled and configured. As outputs,
the GPIOs can be outputs that are high, low or in
three-state mode. The three-state mode feature is
useful for applications where the power is removed
from the remote devices, but they may still be
connected to the GPIO expander.
■ Noise filter on SDA and SCL inputs
2
■ Up to 32 I C Slave Addresses
• Individually programmable inputs
■ Internal pull-up resistors
■ Polarity inversion
As inputs, the internal pull-up resistors can be
enabled or disabled and the input polarity can be
inverted. The interrupt can be programmed for
■ Individual interrupt enable
■ Rising edge and/or Falling edge interrupt
■ Input filter
different behaviors.
The interrupts can be
programmed to generate an interrupt on the rising
edge, falling edge or on both edges. The interrupt
can be cleared if the input changes back to its original
state or by reading the current state of the inputs.
• Individually programmable outputs
■ Output Level Control
■ Output Three-State Control
• Open-drain active low interrupt output
The XRA1201/1201P are enhanced versions of other
2
16-bit GPIO expanders with an I C/SMBus interface.
• Pin and software compatible with PCA9535,
TCA9535, MAX7312 (XRA1201)
The XRA1201 is pin and software compatible with the
PCA9535, TCA9535 and MAX7312. The XRA1201P
is pin and software compatible with the CAT9555,
PCA9555, TCA9555, MAX7311 and MAX7318.
• Pin and software compatible with CAT9555,
PCA9555, TCA9555, MAX7311 and MAX7318
(XRA1201P)
The XRA1201/1201P are available in 24-pin QFN
and 24-pin TSSOP packages.
• 3kV HBM ESD protection per JESD22-A114F
• 200mA latch-up performance per JESD78B
APPLICATIONS
• Personal Digital Assistants (PDA)
• Cellular Phones/Data Devices
• Battery-Operated Devices
• Global Positioning System (GPS)
• Bluetooth
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRA1201/1201P
16-BIT I2C/SMBUS GPIO EXPANDER
REV. 1.0.0
FIGURE 1. XRA1201 BLOCK DIAGRAM
VC C
(1.65V – 3.6V)
P0
P1
P2
P3
P4
P5
P6
P7
G PIO s
SC L
SDA
I2C/
SM Bus
Interface
G PIO
C ontrol
R egisters
A2
A1
A0
P8
P9
IR Q #
P10
P11
P12
P13
P14
P15
G PIO s
G N D
ORDERING INFORMATION
NUMBER OF
GPIOS
OPERATING TEMPERATURE
RANGE
PART NUMBER
PACKAGE
DEVICE STATUS
XRA1201IL24-F
XRA1201IL24TR-F
XRA1201PIL24-F
XRA1201PIL24TR-F
QFN-24
QFN-24
QFN-24
QFN-24
16
16
16
16
16
16
16
16
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
-40°C to +85°C
Active
Active
Active
Active
Active
Active
Active
Active
XRA1201IG24-F
XRA1201IG24TR-F
XRA1201PIG24-F
XRA1201PIG24TR-F
TSSOP-24
TSSOP-24
TSSOP-24
TSSOP-24
NOTE: TR = Tape and Reel, F = Green / RoHS
FIGURE 2. PIN OUT ASSIGNMENTS
IRQ#
A1
A2
P0
P1
P2
P3
P4
P5
P6
24 VCC
23 SDA
22 SCL
21 A0
1
2
3
4
5
6
7
8
24 23 22 21 20 19
P0
P1
P2
P3
P4
P5
1
2
3
4
5
6
18 A0
P15
P14
20
19
P15
P14
17
16
XRA1201/
XRA1201P
24-Pin
XRA1201/
XRA1201P
24-Pin QFN
15 P13
P12
18 P13
TSSOP
14
13 P11
P12
P11
17
16
7
8
9 10 11 12
9
10
15 P10
14 P9
13 P8
P7 11
GND 12
2
XRA1201/1201P
REV. 1.0.0
16-BIT I2C/SMBUS GPIO EXPANDER
PIN DESCRIPTIONS
Pin Description
QFN-24 TSSOP-24
NAME
TYPE
DESCRIPTION
PIN#
PIN#
I2C INTERFACE
SDA
SCL
20
19
22
23
22
1
I/O
I
I2C-bus data input/output (open-drain).
I2C-bus serial input clock.
IRQ#
OD
Interrupt output (open-drain, active LOW).
A0
A1
A2
18
23
24
21
2
I
I
I
These pins select the I2C slave address. See Table 1.
3
GPIOs
P0
P1
P2
P3
P4
P5
P6
P7
1
2
3
4
5
6
7
8
4
5
I/O
General purpose I/Os P0-P7. All GPIOs are configured as inputs upon power-
I/O up or after a reset. After power-up or reset, the internal pull-up resistors are
enabled for the XRA1201P. The internal pull-up resistors are disabled for the
XRA1201.
6
I/O
I/O
I/O
I/O
I/O
I/O
7
8
9
10
11
P8
10
11
12
13
14
15
16
17
13
14
15
16
17
18
19
20
I/O
General purpose I/O P8-P15. All GPIOs are configured as inputs upon power-
P9
I/O up or after a reset. After power-up or reset, the internal pull-up resistors are
enabled for the XRA1201P. The internal pull-up resistors are disabled for the
XRA1201.
P10
P11
P12
P13
P14
P15
I/O
I/O
I/O
I/O
I/O
I/O
ANCILLARY SIGNALS
VCC
GND
GND
21
9
24
12
-
Pwr
Pwr
Pwr
1.65V to 3.6V VCC supply voltage.
Power supply common, ground.
Center
Pad
The exposed pad at the bottom surface of the package is designed for thermal
performance. Use of a center pad on the PCB is strongly recommended for ther-
mal conductivity as well as to provide mechanical stability of the package on the
PCB. The center pad is recommended to be solder masked defined with open-
ing size less than or equal to the exposed thermal pad on the package bottom to
prevent solder bridging to the outer leads of the device. Thermal vias must be
connected to GND plane as the thermal pad of package is at GND potential.
Pin type: I=Input, O=Output, I/O= Input/output, OD=Output Open Drain.
3
XRA1201/1201P
16-BIT I2C/SMBUS GPIO EXPANDER
1.0 FUNCTIONAL DESCRIPTIONS
2
REV. 1.0.0
1.1
I C-bus Interface
2
2
2
The I C-bus interface is compliant with the Standard-mode and Fast-mode I C-bus specifications. The I C-bus
interface consists of two lines: serial data (SDA) and serial clock (SCL). In the Standard-mode, the serial clock
and serial data can go up to 100 kbps and in the Fast-mode, the serial clock and serial data can go up to 400
kbps.
2
The first byte sent by an I C-bus master contains a start bit (SDA transition from HIGH to LOW when SCL is
HIGH), 7-bit slave address and whether it is a read or write transaction. The next byte is the sub-address that
contains the address of the register to access. The XRA120x responds to each write with an acknowledge
2
(SDA driven LOW by XRA1201/1201P for one clock cycle when SCL is HIGH). The last byte sent by an I C-
bus master contains a stop bit (SDA transition from LOW to HIGH when SCL is HIGH). See Figures 3 - 5
2
below. For complete details, see the I C-bus specifications.
2
FIGURE 3. I C START AND STOP CONDITIONS
SDA
SCL
S
P
START condition
STOP condition
FIGURE 4. MASTER WRITES TO SLAVE
SLAVE
AD D R ESS
C O M M AN D
BYTE
D ATA
BYTE
S
W
A
A
A
P
W hite block: host to XR A120x
G rey block: XR A 120x to host
FIGURE 5. MASTER READS FROM SLAVE
SLAVE
ADDRESS
COMMAND
BYTE
SLAVE
ADDRESS
S
W
A
A
S
R
A
nDATA
A
LAST DATA
NA
P
White block: host to XRA120x
Grey block: XRA120x to host
4
XRA1201/1201P
REV. 1.0.0
16-BIT I2C/SMBUS GPIO EXPANDER
2
1.1.1
I C-bus Addressing
2
2
There could be many devices on the I C-bus. To distinguish itself from the other devices on the I C-bus, the
2
XRA1201/1201P has up to 32 I C slave addresses using the A2-A0 address lines. Table 1 below shows the
different addresses that can be selected.
2
TABLE 1: I C ADDRESS MAP
I2C ADDRESS
A2
A1
A0
GND
GND
GND
GND
VCC
VCC
VCC
VCC
GND
GND
GND
GND
VCC
VCC
VCC
VCC
GND
GND
GND
GND
VCC
VCC
VCC
VCC
GND
GND
GND
GND
VCC
VCC
VCC
VCC
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
SCL
SCL
SDA
SDA
GND
GND
VCC
VCC
GND
GND
VCC
VCC
GND
GND
VCC
VCC
GND
GND
VCC
VCC
GND
VCC
GND
VCC
GND
VCC
GND
VCC
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
GND
VCC
GND
VCC
GND
VCC
GND
VCC
SCL
SDA
SCL
SDA
SCL
SDA
SCL
SDA
0x20 (0010 000X)
0x22 (0010 001X)
0x24 (0010 010X)
0x26 (0010 011X)
0x28 (0010 100X)
0x2A (0010 101X)
0x2C (0010 110X)
0x2E (0010 111X)
0x30 (0011 000X)
0x32 (0011 001X)
0x34 (0011 010X)
0x36 (0011 011X)
0x38 (0011 100X)
0x3A (0011 101X)
0x3C (0011 110X)
0x3E (0011 111X)
0x40 (0100 000X)
0x42 (0100 001X)
0x44 (0100 010X)
0x46 (0100 011X)
0x48 (0100 100X)
0x4A (0100 101X)
0x4C (0100 110X)
0x4E (0100 111X)
0x50 (0101 000X)
0x52 (0101 001X)
0x54 (0101 010X)
0x56 (0101 011X)
0x58 (0101 100X)
0x5A (0101 101X)
0x5C (0101 110X)
0x5E (0101 111X)
5
XRA1201/1201P
16-BIT I2C/SMBUS GPIO EXPANDER
REV. 1.0.0
2
1.1.2
I C Read and Write
A read or write transaction is determined by bit-0 of the slave address. If bit-0 is ’0’, then it is a write
transaction. If bit-0 is ’1’, then it is a read transaction.
2
1.1.3
I C Command Byte
2
2
An I C command byte is sent by the I C master following the slave address. The command byte indicates the
address offset of the register that will be accessed. Table 2 below lists the command bytes for each register.
2
TABLE 2: I C COMMAND BYTE (REGISTER ADDRESS)
COMMAND BYTE
0x00
REGISTER NAME DESCRIPTION
READ/WRITE
Read-Only
Read-Only
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
DEFAULT VALUES
0xXX
GSR1 - GPIO State for P0-P7
0x01
GSR2 - GPIO State for P8-P15
0xXX
0x02
OCR1 - Output Control for P0-P7
0xFF
0x03
OCR2 - Output Control for P8-P15
0xFF
0x04
PIR1 - Input Polarity Inversion for P0-P7
PIR2 - Input Polarity Inversion for P8-P15
GCR1 - GPIO Configuration for P0-P7
GCR2 - GPIO Configuration for P8-P15
PUR1 - Input Internal Pull-up Resistor Enable/Disable for P0-P7
0x00
0x05
0x00
0x06
0xFF
0x07
0xFF
0x08
0x00 (XRA1201)
0xFF (XRA1201P)
0x09
PUR2 - Input Internal Pull-up Resistor Enable/Disable for P8-P15 Read/Write
0x00 (XRA1201)
0xFF (XRA1201P)
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x12
0x13
0x14
0x15
IER1 - Input Interrupt Enable for P0-P7
Read/Write
Read/Write
Read/Write
Read/Write
Read
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFF
IER2 - Input Interrupt Enable for P8-P15
TSCR1 - Output Three-State Control for P0-P7
TSCR2 - Output Three-State Control for P8-P15
ISR1 - Input Interrupt Status for P0-P7
ISR2 - Input Interrupt Status for P8-P15
Read
REIR1 - Input Rising Edge Interrupt Enable for P0-P7
REIR2 - Input Rising Edge Interrupt Enable for P8-P15
FEIR1 - Input Falling Edge Interrupt Enable for P0-P7
FEIR2 - Input Falling Edge Interrupt Enable for P8-P15
IFR1 - Input Filter Enable/Disable for P0-P7
IFR2 - Input Filter Enable/Disable for P8-P15
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
Read/Write
6
XRA1201/1201P
REV. 1.0.0
16-BIT I2C/SMBUS GPIO EXPANDER
1.2
Interrupts
The table below summarizes the interrupt behavior of the different register settings for the XRA1201/1201P.
TABLE 3: INTERRUPT GENERATION AND CLEARING
GCR IER REIR FEIR IFR
INTERRUPT GENERATED BY:
INTERRUPT CLEARED BY:
BIT
BIT
BIT
BIT
BIT
1
0
X
X
X
No interrupts enabled (default)
N/A
0
A rising or falling edge on the input
Reading the GSR register or if the input
changes back to its previous state (state of
input during last read to GSR)
1
A rising or falling edge on the input and
remains in the new state for more than
1075ns
1
1
0
0
0
1
A rising edge on the input
Reading the GSR register
Reading the GSR register
Reading the GSR register
1
1
1
1
1
0
0
1
A rising edge on the input and remains high
for more than 1075ns
0
1
A falling edge on the input
A falling edge on the input and remains low
for more than 1075ns
0
1
A rising or falling edge on the input
A rising or falling edge on the input and
remains in the new state for more than
1075ns
1
0
1
x
1
x
1
x
x
No interrupts in output mode
N/A
7
XRA1201/1201P
16-BIT I2C/SMBUS GPIO EXPANDER
2.0 REGISTER DESCRIPTION
REV. 1.0.0
2.1
GPIO State Register 1 (GSR1) - Read-Only
The status of P7 - P0 can be read via this register. A read will show the current state of these pins (or the
inverted state of these pins if enabled via the PIR Register). Reading this register will clear an input interrupt
(see Table 3 for complete details). Reading this register will also return the last value written to the OCR
register for any pins that are configured as outputs (ie. this is not the same as the state of the actual output pin
since the output pin can be in three-state mode). A write to this register has no effect. The MSB of this register
corresponds with P7 and the LSB of this register corresponds with P0.
2.2
GPIO State Register 2 (GSR2) - Read-Only
The status of P15 - P8 can be read via this register. A read will show the current state of these pins (or the
inverted state of these pins if enabled via the PIR Register). Reading this register will clear an input interrupt
(see Table 3 for complete details). Reading this register will also return the last value written to the OCR
register for any pins that are configured as outputs (ie. this is not the same as the state of the actual output pin
since the output pin can be in three-state mode). A write to this register has no effect. The MSB of this register
corresponds with P15 and the LSB of this register corresponds with P8.
2.3
Output Control Register 1 (OCR1) - Read/Write
When P7 - P0 are defined as outputs, they can be controlled by writing to this register. Reading this register
will return the last value written to it, however, this value may not be the actual state of the output pin since
these pins can be in three-state mode. The MSB of this register corresponds with P7 and the LSB of this
register corresponds with P0.
2.4
Output Control Register 2 (OCR2) - Read/Write
When P15 - P8 are defined as outputs, they can be controlled by writing to this register. Reading this register
will return the last value written to it, however, this value may not be the actual state of the output pin since
these pins can be in three-state mode. The MSB of this register corresponds with P15 and the LSB of this
register corresponds with P8.
2.5
Input Polarity Inversion Register 1 (PIR1) - Read/Write
When P7 - P0 are defined as inputs, this register inverts the polarity of the input value read from the Input Port
Register. If the corresponding bit in this register is set to ’1’, the value of this bit in the GSR Register will be the
inverted value of the input pin. If the corresponding bit in this register is set to ’0’, the value of this bit in the
GSR Register will be the actual value of the input pin. The MSB of this register corresponds with P7 and the
LSB of this register corresponds with P0.
2.6
Input Polarity Inversion Register 2 (PIR2) - Read/Write
When P15 - P8 are defined as inputs, this register inverts the polarity of the input value read from the Input Port
Register. If the corresponding bit in this register is set to ’1’, the value of this bit in the GSR Register will be the
inverted value of the input pin. If the corresponding bit in this register is set to ’0’, the value of this bit in the
GSR Register will be the actual value of the input pin. The MSB of this register corresponds with P15 and the
LSB of this register corresponds with P8.
2.7
GPIO Configuration Register 1 (GCR1) - Read/Write
This register configures the GPIOs as inputs or outputs. After power-up and reset, the GPIOs are inputs.
Setting these bits to ’0’ will enable the GPIOs as outputs. Setting these bits to ’1’ will enable the GPIOs as
inputs. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0.
2.8
GPIO Configuration Register 2 (GCR2) - Read/Write
This register configures the GPIOs as inputs or outputs. After power-up and reset, the GPIOs are inputs.
Setting these bits to ’0’ will enable the GPIOs as outputs. Setting these bits to ’1’ will enable the GPIOs as
inputs. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8.
8
XRA1201/1201P
REV. 1.0.0
16-BIT I2C/SMBUS GPIO EXPANDER
2.9
Input Internal Pull-up Enable/Disable Register 1 (PUR1) - Read/Write
This register enables/disables the internal pull-up resistors for an input. After power-up and reset, the internal
pull-up resistors are disabled for the XRA1201. Writing a ’1’ to these bits will enable the internal pull-up
resistors. After power-up and reset, the internal pull-up resistors are enabled for the XRA1201P. Writing a ’0’
to these bits will disable the internal pull-up resistors. The MSB of this register corresponds with P7 and the
LSB of this register corresponds with P0.
2.10 Input Internal Pull-up Enable/Disable Register 2 (PUR2) - Read/Write
This register enables/disables the internal pull-up resistors for an input. After power-up and reset, the internal
pull-up resistors are disabled for the XRA1201. Writing a ’1’ to these bits will enable the internal pull-up
resistors. After power-up and reset, the internal pull-up resistors are enabled for the XRA1201P. Writing a ’0’
to these bits will disable the internal pull-up resistors. The MSB of this register corresponds with P15 and the
LSB of this register corresponds with P8.
2.11 Input Interrupt Enable Register 1 (IER1) - Read/Write
This register enables/disables the interrupts for an input. After power-up and reset, the interrupts are disabled.
Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See Table 3 for complete
details of the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR
bit is 0. The MSB of this register corresponds with P7 and the LSB of this register corresponds with P0.
2.12 Input Interrupt Enable Register 2 (IER2) - Read/Write
This register enables/disables the interrupts for an input. After power-up and reset, the interrupts are disabled.
Writing a ’1’ to these bits will enable the interrupt for the corresponding input pins. See Table 3 for complete
details of the interrupt behavior for various register settings. No interrupts are generated for outputs when GCR
bit is 0. The MSB of this register corresponds with P15 and the LSB of this register corresponds with P8.
2.13 Output Three-State Control Register 1 (TSCR1) - Read/Write
This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the
three-state mode for the corresponding output pins. The MSB of this register corresponds with P7 and the LSB
of this register corresponds with P0.
2.14 Output Three-State Control Register 2 (TSCR2) - Read/Write
This register can enable/disable the three-state mode of an output. Writing a ’1’ to these bits will enable the
three-state mode for the corresponding output pins. The MSB of this register corresponds with P15 and the
LSB of this register corresponds with P8.
2.15 Input Interrupt Status Register 1 (ISR1) - Read-Only
This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the
interrupt behavior for various register settings. The MSB of this register corresponds with P7 and the LSB of
this register corresponds with P0.
2.16 Input Interrupt Status Register 2 (ISR2) - Read-Only
This register reports the input pins that have generated an interrupt. See Table 3 for complete details of the
interrupt behavior for various register settings. The MSB of this register corresponds with P15 and the LSB of
this register corresponds with P8.
9
XRA1201/1201P
16-BIT I2C/SMBUS GPIO EXPANDER
REV. 1.0.0
2.17 Input Rising Edge Interrupt Enable Register 1 (REIR1) - Read/Write
Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the rising edge. See
Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register
corresponds with P7 and the LSB of this register corresponds with P0.
2.18 Input Rising Edge Interrupt Enable Register 2 (REIR2) - Read/Write
Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the rising edge. See
Table 3 for complete details of the interrupt behavior for various register settings. The MSB of this register
corresponds with P15 and the LSB of this register corresponds with P8.
2.19 Input Falling Edge Interrupt Enable Register 1 (FEIR1) - Read/Write
Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the falling edge.
Writing a ’1’ to these bits will make that input generate an interrupt on the rising edge only. See Table 3 for
complete details of the interrupt behavior for various register settings. The MSB of this register corresponds
with P7 and the LSB of this register corresponds with P0.
2.20 Input Falling Edge Interrupt Enable Register 2 (FEIR2) - Read/Write
Writing a ’1’ to these bits will enable the corresponding input to generate an interrupt on the falling edge.
Writing a ’1’ to these bits will make that input generate an interrupt on the rising edge only. See Table 3 for
complete details of the interrupt behavior for various register settings. The MSB of this register corresponds
with P15 and the LSB of this register corresponds with P8.
2.21 Input Filter Enable Register 1 (IFR1) - Read/Write
By default, the input filters are enabled (IFR = 0xFF). When the input filters are enabled, any pulse that is
greater than 1075ns will generate an interrupt (if enabled). Pulses that are less than 225ns will be filtered and
will not generate an interrupt. Pulses in between this range may or may not generate an interrupt. Writing a ’0’
to these bits will disable the input filter for the corresponding inputs. With the input filters disabled, any change
on the inputs will generate an interrupt (if enabled). See Table 3 for complete details of the interrupt behavior
for various register settings. The MSB of this register corresponds with P7 and the LSB of this register
corresponds with P0.
2.22 Input Filter Enable Register 2 (IFR2) - Read/Write
By default, the input filters are enabled (IFR = 0xFF). When the input filters are enabled, any pulse that is
greater than 1075ns will generate an interrupt (if enabled). Pulses that are less than 225ns will be filtered and
will not generate an interrupt. Pulses in between this range may or may not generate an interrupt. Writing a ’0’
to these bits will disable the input filter for the corresponding inputs. With the input filters disabled, any change
on the inputs will generate an interrupt (if enabled). See Table 3 for complete details of the interrupt behavior
for various register settings. The MSB of this register corresponds with P15 and the LSB of this register
corresponds with P8.
10
XRA1201/1201P
REV. 1.0.0
16-BIT I2C/SMBUS GPIO EXPANDER
ABSOLUTE MAXIMUM RATINGS
Power supply voltage
3.6 Volts
160 mA
200 mA
25 mA
Supply current
Ground current
External current limit of each GPIO
Total current limit for GPIO[15:8] and GPIO[7:0]
Total current limit for GPIO[15:0]
Total supply current sourced by all GPIOs
Operating Temperature
100 mA
200 mA
160 mA
-40o to +85oC
-65o to +150oC
200 mW
Storage Temperature
Power Dissipation
TYPICAL PACKAGE THERMAL RESISTANCE DATA (MARGIN OF ERROR: ± 15%)
theta-ja = 38oC/W, theta-jc = 26oC/W
Thermal Resistance (24-QFN)
theta-ja = 84oC/W, theta-jc = 16oC/W
Thermal Resistance (24-TSSOP)
11
XRA1201/1201P
16-BIT I2C/SMBUS GPIO EXPANDER
REV. 1.0.0
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
UNLESS OTHERWISE NOTED: TA = -40O TO +85OC, VCC IS 1.65V TO 3.6V
LIMITS
LIMITS
LIMITS
SYMBOL
PARAMETER
UNITS
CONDITIONS
1.8V ± 10%
2.5V ± 10%
3.3V ± 10%
MIN
MAX
MIN
MAX
MIN
MAX
VIL
VIL
Input Low Voltage
Input Low Voltage
Input High Voltage
Input High Voltage
Output Low Voltage
-0.3
0.3VCC
-0.3
0.3VCC
-0.3
-0.3
2.3
0.3VCC
V
V
V
V
Note 1
Note 2
Note 1
Note 2
-0.3
1.3
1.4
0.2
VCC
5.5
-0.3
1.8
1.8
0.5
VCC
5.5
0.8
VCC
5.5
VIH
VIH
VOL
2.0
0.4
V
V
V
IOL = 3 mA
IOL = 3 mA
IOL = 3 mA
Note 3
0.4
0.4
0.5
VOL
Output Low Voltage
Output Low Voltage
0.5
0.4
0.5
0.4
V
IOL = 8 mA
Note 4
VOL
V
V
V
IOL = 6 mA
IOL = 4 mA
IOL = 1.5 mA
Note 5
0.4
VOH
Output High Voltage
2.6
V
V
V
IOH = -8 mA
IOH = -8 mA
IOH = -8 mA
Note 4
1.8
1.2
IIL
IIH
Input Low Leakage Current
Input High Leakage Current
Input Pin Capacitance
Power Supply Current
Power Supply Current
Standby Current
±10
±10
5
±10
±10
5
±10
±10
5
uA
uA
pF
uA
uA
uA
kΩ
CIN
ICC
ICC
ICCS
50
100
250
2
200
500
5
Test 1
Test 2
Test 3
150
1
RGPIO GPIO pull-up resistance
60
140
60
140
60
140
100kΩ ± 40%
NOTES:
1. For I2C input signals (SDA, SCL);
2. For GPIOs, A0, A1 and A2 signals;
3. For I2C output signal SDA;
4. For GPIOs;
5. For IRQ# signal;
12
XRA1201/1201P
REV. 1.0.0
16-BIT I2C/SMBUS GPIO EXPANDER
Test 1: SCL frequency is 400 KHz with internal pull-ups disabled. All GPIOs are configured as inputs. All inputs are steady
at VCC or GND. Outputs are floating or in the tri-state mode.
Test 2: SCL frequency is 400 KHz with internal pull-ups enabled. All GPIOs are configured as inputs. All inputs are steady
at VCC or GND. Outputs are floating or in the tri-state mode.
Test 3: All inputs are steady at VCC or GND to minimize standby current. If internal pull-up is enabled, input voltage level
should be the same as VCC. All GPIOs are configured as inputs. SCL and SDA are at VCC. Outputs are left floating or in
tri-state mode.
AC ELECTRICAL CHARACTERISTICS
o
o
Unless otherwise noted: TA=-40 to +85 C, Vcc=1.65V - 3.6V
STANDARD MODE
I2C-BUS
FAST MODE
I2C-BUS
SYMBOL
PARAMETER
UNIT
MIN
MAX
MIN
MAX
fSCL
TBUF
Operating frequency
0
100
0
400
kHz
µs
µs
µs
ns
µs
ns
ns
µs
µs
ns
ns
ns
µs
µs
µs
µs
Bus free time between STOP and START
START condition hold time
START condition setup time
Data hold time
4.7
4.0
4.7
0
1.3
0.6
0.6
0
THD;STA
TSU;STA
THD;DAT
TVD;ACK
TVD;DAT
TSU;DAT
TLOW
THIGH
TF
Data valid acknowledge
SCL LOW to data out valid
Data setup time
0.6
0.6
0.6
0.6
250
4.7
4.0
150
1.3
0.6
Clock LOW period
Clock HIGH period
Clock/data fall time
300
300
300
TR
Clock/data rise time
1000
TSP
Pulse width of spikes tolerance
50
50
I2C-bus GPIO output valid
I2C input pin interrupt valid
TD1
0.2
4
0.2
4
TD4
I2C input pin interrupt clear
SCL delay after reset
TD5
4
4
TD15
3
3
13
XRA1201/1201P
16-BIT I2C/SMBUS GPIO EXPANDER
REV. 1.0.0
2
FIGURE 6. I C-BUS TIMING DIAGRAM
START
condition
(S)
Bit 7
MSB
(A7)
Bit 0
LSB
(R/W)
STOP
condition
(P)
Bit 6
(A6)
Acknowledge
(A)
Protocol
TSU;STA
TLOW THIGH
1/FSCL
SCL
TF
TR
TSP
TBUF
SDA
THD;STA
TSU;DAT
THD;DAT
TVD;DAT
TVD;ACK
TSU;STO
FIGURE 7. WRITE TO OUTPUT
SLAVE
ADDRESS
COMMAND
BYTE
SDA
W
A
A
DATA
A
TD1
GPIOn
FIGURE 8. GPIO PIN INTERRUPT
ACK from slave
ACK from slave
ACK from master
SLAVE
ADDRESS
COMMAND
BYTE
SLAVE
ADDRESS
SDA
INT#
W
A
A
S
R
A
DATA
A
P
TD4
TD5
Px
14
XRA1201/1201P
REV. 1.0.0
16-BIT I2C/SMBUS GPIO EXPANDER
PACKAGE DIMENSIONS (24 PIN QFN - 4 X 4 X 0.9 mm)
θ
Note: the actual center pad
is metallic and the size (D2)
is device-dependent with a
typical tolerance of 0.3mm
Note: The control dimension is in millimeter.
INCHES
MAX
MILLIMETERS
SYMBOL
MIN
-
MIN
-
MAX
1.00
0.05
0.25
14o
A
0.039
0.002
0.010
14o
A1
A3
0.000
0.006
0
0.00
0.15
0
θ
D
D2
b
0.154
0.087
0.007
0.161
0.102
0.012
3.90
2.20
0.18
4.10
2.60
0.30
e
0.020 BSC
0.50 BSC
L
0.012
0.008
0.020
-
0.30
0.20
0.50
-
k
15
XRA1201/1201P
16-BIT I2C/SMBUS GPIO EXPANDER
REV. 1.0.0
PACKAGE DIMENSIONS (24 PIN TSSOP - 4.4 mm)
Note: The control dimension is in millimeter.
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
0.047
0.006
0.041
0.012
0.008
0.311
0.264
0.177
MIN
MAX
1.20
0.15
1.05
0.30
0.2
A
A1
A2
b
0.031
0.002
0.031
0.007
0.004
0.303
0.240
0.169
0.80
0.05
0.80
0.19
0.09
7.70
6.10
4.30
C
D
7.90
6.70
4.50
E
E1
e
0.0256 BSC
0.65 BSC
L
0.018
0°
0.030
8°
0.45
0°
0.75
8°
α
16
XRA1201/1201P
REV. 1.0.0
16-BIT I2C/SMBUS GPIO EXPANDER
REVISION HISTORY
DATE
REVISION
DESCRIPTION
September 2011
1.0.0
Final Datasheet.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2011 EXAR Corporation
Datasheet September 2011.
Send your UART technical inquiry with technical details to hotline: uarttechsupport@exar.com.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
17
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