XRK32309ID-1H [EXAR]
LOW-COST 3.3V ZERO DELAY BUFFER; 低成本3.3V零延迟缓冲器
| 型号： | XRK32309ID-1H |
| 厂家： | 
EXAR CORPORATION |
| 描述： | LOW-COST 3.3V ZERO DELAY BUFFER |
| 文件： | 总13页 (文件大小：335K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
XRK32309
LOW-COST 3.3V ZERO DELAY BUFFER
MAY 2006
REV.P1.0.1
In this case, the skew between the outputs of two
devices is guaranteed to be less than 700 ps.
GENERAL DESCRIPTION
FUNCTIONAL DESCRIPTION
The available versions of XRK32309 are shown in
Offered in both 16 pin SOIC and TSSOP packages, Table 12, “Ordering Information,” on page 10. The
XRK32309 is a low cost 3.3V zero delay buffer. It is XRK32309-1 is the base part.
designed to distribute high speed clocks by taking
one reference input and driving nine output clocks.
FEATURES
The feedback of its on-chip PLL is internally
• 10-MHz to 120-MHz operating range, compatible
connected to the FB output. XRK32309 devices
operate over 10-100 MHz frequency range with 30 pF
loads and up to 120MHz with lower loads (10 pF).
The -1H version has higher drive strength than the
base -1 version, featuring faster rise and fall time.
with CPU and PCI bus frequencies
• Zero input-output propagation delay
• Multiple low-skew outputs
■ Output-output skew less than 250 ps
■ Device-device skew less than 700 ps
The XRK32309 has two banks each with four
outputs. These outputs are controlled by two select
input lines according to the Table 2, “Select Input
Decoding,” on page 3. In cases where not all outputs
are needed, bank B can be tri-stated. The select
lines also enable putting the device in a bypass mode
where the input is directly applied to the outputs. This
feature is useful for chip and testing purposes.
■ One input drives nine outputs, grouped as 4 +
4 + 1
• Less than 200 ps cycle-cycle jitter, compatible with
Pentium -based systems
• Test Mode to bypass phase-locked loop (PLL) (see
“Select Input Decoding” on page 2)
• Available in space-saving 16-pin 150-mil SOIC or
Some applications may require distributing the clock
to several destinations. In such situations, multiple
XRK32309 devices can be connected to accept the
same input clock and generate several clock signals.
4.4-mm TSSOP packages
• 3.3V operation
• Industrial and commercial temperature available
FIGURE 1. BLOCK DIAGRAM OF THE XRK32309
FB
PLL
MUX
QA0
QA1
QA2
QA3
QB0
QB1
QB2
QB3
REF
S2
Select Input
Decoding
S1
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRK32309
PRELIMINARY
LOW-COST 3.3V ZERO DELAY BUFFER
REV.P1.0.1
FIGURE 2. PIN OUT OF THE XRK32309
16 SOIC/TSSOP
REF
QA0
QA1
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FB
QA3
QA2
VDD
GND
QB3
QB2
S1
GND
QB0
QB1
S2
TABLE 1: PIN DESCRIPTION FOR XRK32309
PIN
SIGNAL
DESCRIPTION
[1]
[2]
[2]
1
Input reference frequency.
Buffered clock output, Bank A
Buffered clock output, Bank A
3.3V supply
REF
QA0
QA1
2
3
4
V
DD
5
6
GND
Ground
[2]
Buffered clock output, Bank B
QB0
[2]
7
8
Buffered clock output, Bank B
Select input, bit 2
QB1
[3]
[3]
S2
9
Select input, bit 1
S1
[2]
10
11
Buffered clock output, Bank B
Buffered clock output, Bank B
QB2
[2]
QB3
12
13
GND
Ground
V
3.3V supply
DD
[2]
[2]
14
15
16
Buffered clock output, Bank A
QA2
Buffered clock output, Bank A
QA3
[2]
Buffered output, internal feedback on this pin
FB
2
PRELIMINARY
XRK32309
REV. P1.0.1
LOW-COST 3.3V ZERO DELAY BUFFER
TABLE 2: SELECT INPUT DECODING
[4]
S2
S1
QA0-QA3
QB0-QB3
OUTPUT SOURCE
FB
0
0
1
1
0
1
0
1
Tri-Stated
Driven
Tri-Stated
Tri-Stated
Driven
Driven
Driven
Driven
Driven
PLL
PLL
Driven
Reference
PLL
Driven
Driven
NOTES:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-ups on these inputs.
4. This output has an internal feedback for the PLL. The load on this output can be adjusted to change the skew
between the reference and output.
FIGURE 3. REF. INPUT TO QAX/QBX DELAY VS. LOADING DIFFERENCE BETWEEN FB AND QAX/QBX PINS
1500
1000
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
Output Load Difference: FB Load - QAx/QBx Load (pF)
Note: Target only, actual characterization curve may be slightly different.
ZERO DELAY AND SKEW CONTROL
In order to achieve Zero Delay between the input reference and the output, all outputs, including FB, must be
equally loaded even when the FB output is not being used.
Being internally connected as the PLL feedback, the FB output's capacitive loading relative to the other
outputs can adjust the input to output delay according to the characteristic shown in Figure 3. This figure
provides a tool for mapping the required delay to the capacitive load difference required between the FB and
the Clock output of interest.
For zero output to output skew, the outputs have to be loaded equally as well.
3
XRK32309
PRELIMINARY
LOW-COST 3.3V ZERO DELAY BUFFER
REV.P1.0.1
TABLE 3: ABSOLUTE MAXIMUM RATINGS
PARAMETER
RANGE
Supply Voltage to Ground Potential
-0.5V to +7.0V
DC Input Voltage (Except REF)
-0.5V to V +0.5V
DD
DC Input Voltage REF
-0.5 to 7V
-65°C to +150°C
150°C
Storage Temperature
Junction Temperature
Static Discharge Voltage (per MIL-STD-883, Method 3015)
>2000V
TABLE 4: OPERATING CONDITIONS FOR XRK32309SC-XX COMMERCIAL TEMPERATURE DEVICES
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
V
Supply Voltage
3.0
3.6
V
DD
T
Operating Temperature (Ambient Temperature)
0
70
°C
A
Load Capacitance, below 100MHz
-
-
-
30
10
7
pF
pF
pF
C
L
Load Capacitance, from 100MHz to 120MHz
C
IN
Input Capacitance
t
Power-up time for all V ’s to reach minimum
DD
0.05
50
ms
PU
specified voltage (power ramps must be monotonic)
TABLE 5: ELECTRICAL CHARACTERISTICS FOR XRK32309SC-XX COMMERCIAL TEMPERATURE DEVICES
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
MAX
UNIT
[5]
V
V
-
0.8
V
IL
IH
Input Low Voltage
[5]
2.0
-
V
µA
µA
V
Input High Voltage
Input Low Current
I
I
V =0V
-
-
-
50.0
100.0
0.4
IL
IN
Input High Current
V =V
IN DD
IH
[6]
[6]
V
I
I
= 8mA (-1)
OL
OL
Output Low Voltage
= 12mA (-1H)
OL
V
I
I
= -8mA (-1)
2.4
-
-
V
OH
OH
Output High Voltage
= -12mA (-1H)
OH
I
Supply Current
Unloaded outputs at 66.67MHz,
SEL inputs at V
32.0
mA
DD
DD
4
PRELIMINARY
XRK32309
REV. P1.0.1
LOW-COST 3.3V ZERO DELAY BUFFER
[7]
TABLE 6: SWITCHING CHARACTERISTICS FOR XRK32309SC-1 COMMERCIAL TEMPERATURE DEVICES
PARAMETER
NAME
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
Output Frequency
30-pF load
10-pF load
10
10
-
100
120
MHz
MHz
1
[6]
DC
Measured at 1.4V, F
=66.67MHz
40.0
50.0
60.0
%
OUT
Duty Cycle = t ÷ t
2
1
[6]
t
t
t
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
-
-
-
-
-
-
2.50
2.50
250
350
ns
ns
ps
ps
3
4
5
Rise Time
[6]
Fall Time
[6]
-
Output to Output Skew
t
t
Delay, REF Rising Edge to Measured at V /2
DD
0
6A
6B
[6]
FB Rising Edge
Delay, REF Rising Edge to Measured at V /2. Measured in PLL
DD
1
-
5
0
8.7
ns
ps
[6]
Bypass Mode
FB Rising Edge
[6]
t
t
Measured at V /2 on the FB pins of
DD
devices
700
7
Device to Device Skew
[6]
Measured at 66.67MHz, loaded outputs
-
-
-
-
200
1.0
ps
J
Cycle to Cycle Jitter
[6]
t
Stable power suppy, valid clock
presented on REF pin
ms
LOCK
PLL Lock Time
NOTES:
5. REF input has a threshold voltage of V /2.
DD
6. Parameter is guaranteed by design and characterization. Not 100% tested in production.
7. All parameters specified with loaded outputs.
5
XRK32309
PRELIMINARY
LOW-COST 3.3V ZERO DELAY BUFFER
REV.P1.0.1
[7]
TABLE 7: SWITCHING CHARACTERISTICS FOR XRK32309SC-1H COMMERCIAL TEMPERATURE DEVICES
PARAMETER
NAME
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
Output Frequency
30-pF load
10-pF load
10
10
-
100
120
MHz
MHz
1
Measured at 1.4V, F
Measured at 1.4V, F
=66.67MHz
<50.0MHz
40.0
50.0
60.0
55.0
1.50
1.50
250
%
%
OUT
OUT
[6]
DC
Duty Cycle = t ÷ t
2
1
45.0
50.0
[6]
t
t
t
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
-
-
-
-
-
-
ns
ns
ps
ps
3
4
5
Rise Time
[6]
Fall Time
[6]
-
Output to Output Skew
t
t
Delay, REF Rising Edge to Measured at V /2
DD
0
350
6A
6B
[6]
FB Rising Edge
Delay, REF Rising Edge to Measured at V /2. Measured in PLL
DD
1
-
5
0
-
8.7
700
-
ns
ps
[6]
Bypass Mode
FB Rising Edge
[6]
t
Measured at V /2 on the FB pins of
DD
devices
7
Device to Device Skew
[6]
t
t
Measured between 0.8V and 2.0V using
Test Circuit #2
1
V/ns
8
Output Slew Rate
[6]
Measured at 66.67MHz, loaded outputs
-
-
-
-
200
1.0
ps
J
Cycle to Cycle Jitter
[6]
t
Stable power suppy, valid clock
presented on REF pin
ms
LOCK
PLL Lock Time
6
PRELIMINARY
XRK32309
REV. P1.0.1
LOW-COST 3.3V ZERO DELAY BUFFER
TABLE 8: OPERATING CONDITIONS FOR XRK32309SI-XX INDUSTRIAL TEMPERATURE DEVICES
PARAMETER
DESCRIPTION
MIN
MAX
UNIT
V
Supply Voltage
3.0
3.6
V
DD
T
Operating Temperature (Ambient Temperature)
-40
85
°C
A
Load Capacitance, below 100MHz
Load Capacitance, from 100MHz to 120MHz
Input Capacitance
-
-
-
30
10
7
pF
pF
pF
C
L
C
IN
t
Power-up time for all V ’s to reach minimum
DD
0.05
50
ms
PU
specified voltage (power ramps must be monotonic)
TABLE 9: ELECTRICAL CHARACTERISTICS FOR XRK32309SI-XX INDUSTRIAL TEMPERATURE DEVICES
PARAMETER
DESCRIPTION
TEST CONDITIONS
MIN
MAX
UNIT
[5]
V
V
-
0.8
V
IL
IH
Input Low Voltage
[5]
2.0
-
V
µA
µA
V
Input High Voltage
Input Low Current
I
I
V =0V
-
-
-
50.0
100.0
0.4
IL
IN
Input High Current
V =V
IN DD
IH
[6]
[6]
V
I
I
= 8mA (-1)
OL
OL
Output Low Voltage
= 12mA (-1H)
OL
V
I
I
= -8mA (-1)
2.4
-
-
V
OH
OH
Output High Voltage
= -12mA (-1H)
OH
I
Supply Current
Unloaded outputs at 66.67MHz REF,
SEL inputs at V
35.0
mA
DD
DD
7
XRK32309
PRELIMINARY
LOW-COST 3.3V ZERO DELAY BUFFER
REV.P1.0.1
[7]
TABLE 10: SWITCHING CHARACTERISTICS FOR XRK32309SI-1 INDUSTRIAL TEMPERATURE DEVICES
PARAMETER
NAME
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
Output Frequency
30-pF load
10-pF load
10
10
-
100
120
MHz
MHz
1
[6]
DC
Measured at 1.4V, F
=66.67MHz
40.0
50.0
60.0
%
OUT
Duty Cycle = t ÷ t
2
1
[6]
t
t
t
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
-
-
-
-
-
-
2.50
2.50
250
350
ns
ns
ps
ps
3
4
5
Rise Time
[6]
Fall Time
[6]
-
Output to Output Skew
t
t
Delay, REF Rising Edge to Measured at V /2
DD
0
6A
6B
[6]
FB Rising Edge
Delay, REF Rising Edge to Measured at V /2. Measured in PLL
DD
1
-
5
0
8.7
ns
ps
[6]
Bypass Mode
FB Rising Edge
[6]
t
t
Measured at V /2 on the FB pins of
DD
devices
700
7
Device to Device Skew
[6]
Measured at 66.67MHz, loaded outputs
-
-
-
-
200
1.0
ps
J
Cycle to Cycle Jitter
[6]
t
Stable power suppy, valid clock
presented on REF pin
ms
LOCK
PLL Lock Time
[7]
TABLE 11: SWITCHING CHARACTERISTICS FOR XRK32309SI-1H INDUSTRIAL TEMPERATURE DEVICES
PARAMETER
NAME
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
Output Frequency
30-pF load
10-pF load
10
10
-
100
120
MHz
MHz
1
Measured at 1.4V, F
Measured at 1.4V, F
=66.67MHz
<50.0MHz
40.0
50.0
60.0
55.0
1.50
1.50
250
%
%
OUT
OUT
[6]
DC
Duty Cycle = t ÷ t
2
1
45.0
50.0
[6]
t
t
t
Measured between 0.8V and 2.0V
Measured between 0.8V and 2.0V
All outputs equally loaded
-
-
-
-
-
-
ns
ns
ps
ps
3
4
5
Rise Time
[6]
Fall Time
[6]
-
Output to Output Skew
t
t
Delay, REF Rising Edge to Measured at V /2
DD
0
350
6A
6B
[6]
FB Rising Edge
Delay, REF Rising Edge to Measured at V /2. Measured in PLL
DD
1
-
5
0
-
8.7
700
-
ns
ps
[6]
Bypass Mode
FB Rising Edge
[6]
t
t
Measured at V /2 on the FB pins of
DD
devices
7
8
Device to Device Skew
[6]
Measured between 0.8V and 2.0V using
Test Circuit #2
1
v/ns
Output Slew Rate
8
PRELIMINARY
XRK32309
REV. P1.0.1
LOW-COST 3.3V ZERO DELAY BUFFER
[7]
TABLE 11: SWITCHING CHARACTERISTICS FOR XRK32309SI-1H INDUSTRIAL TEMPERATURE DEVICES
PARAMETER
NAME
TEST CONDITIONS
MIN
TYP
MAX
UNIT
[6]
t
Measured at 66.67MHz, loaded outputs
-
-
200
ps
J
Cycle to Cycle Jitter
[6]
t
Stable power suppy, valid clock
presented on REF pin
-
-
1.0
ms
LOCK
PLL Lock Time
FIGURE 4. SWITCHING WAVEFORMS
Duty Cycle Timing
All Outputs Rise/Fall Time
t1
3.3V
0V
t2
1.4V
OUTPUT 2.0V
0.8V
2.0V
0.8V
1.4V
1.4V
t3
t4
Output-Output Skew
Input-Output Propagation Delay
1.4V
VDD/2
OUTPUT
INPUT
1.4V
VDD/2
OUTPUT
OUTPUT
t5
t6
Device-Device Skew
VDD/2
FB, Device 1
FB, Device 2
VDD/2
t7
FIGURE 5. TEST CIRCUIT
Test Circuit #1
Test Circuit #2
VDD
VDD
1KΩ
1KΩ
QAx/QBx
CLOAD
0.1µF
0.1µF
Outputs
0.1µF
0.1µF
Outputs
10pF
VDD
VDD
GND GND
GND GND
For parameters t 8 (output slew rate) on -1H devices.
9
XRK32309
PRELIMINARY
LOW-COST 3.3V ZERO DELAY BUFFER
REV.P1.0.1
TABLE 12: ORDERING INFORMATION
OPERATING TEMPERATURE RANGE
PART ORDERING NUMBER
XRK32309CD-1
PACKAGE TYPE
16 PIN SOIC
16 PIN SOIC
16 Pin SOIC
16 Pin SOIC
16 Pin SOIC
16 Pin SOIC
16 Pin SOIC
16 Pin SOIC
16 Pin TSSOP
16 Pin TSSOP
16 Pin TSSOP
16 Pin TSSOP
0° TO +70°
0° TO +70°
-40° to +85°
-40° to +85°
0° TO +70°
0° TO +70°
-40° to +85°
-40° to +85°
0° TO +70°
0° TO +70°
-40° to +85°
-40° to +85°
XRK32309CDTR-1
XRK32309ID-1
XRK32309IDTR-1
XRK32309CD-1H
XRK32309CDTR-1H
XRK32309ID-1H
XRK32309IDTR-1H
XRK32309CG-1H
XRK32309CGTR-1H
XRK32309IG-1H
XRK32309IGTR-1H
10
PRELIMINARY
XRK32309
REV. P1.0.1
LOW-COST 3.3V ZERO DELAY BUFFER
PACKAGE DRAWINGS AND DIMENSIONS
FIGURE 6. XRK32309 PACKAGE DRAWING - 16 LEAD SMALL OUTLINE
16 LEAD SMALL OUTLINE
(150 MIL JEDEC SOIC)
D
16
9
E
H
1
8
C
A
Seating
Plane
α
e
B
A1
L
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
MAX
SYMBOL
MIN
MIN
1.35
0.10
0.33
0.19
9.80
3.80
MAX
1.75
0.25
0.51
0.25
10.00
4.00
A
0.053
0.004
0.013
0.007
0.386
0.150
0.069
0.010
0.020
0.010
0.394
0.157
A
1
B
C
D
E
e
0.050 BSC
1.27 BSC
H
L
0.228
0.016
0°
0.244
0.050
8°
5.80
0.40
0°
6.20
1.27
8°
α
11
XRK32309
PRELIMINARY
LOW-COST 3.3V ZERO DELAY BUFFER
REV.P1.0.1
FIGURE 7. XRK32309 PACKAGE DRAWING - 16 LEAD THIN SHRINK SMALL OUTLINE
16 LEAD TSSOP THIN SHRINK SMALL OUTLINE
(4.4mm TSSOP)
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
A1
A2
B
C
D
E
E1
e
0.031
0.002
0.031
0.007
0.004
0.193
0.248
0.169
0.043
0.006
0.037
0.012
0.008
0.201
0.260
0.177
0.80
0.05
0.80
0.19
0.09
4.90
6.30
4.30
1.10
0.15
0.95
0.30
0.20
5.10
6.60
4.50
0.0256 BSC
0.65 BSC
L
0.018
0°
0.030
8°
0.45
0°
0.75
8°
α
12
PRELIMINARY
XRK32309
REV. P1.0.1
LOW-COST 3.3V ZERO DELAY BUFFER
REVISIONS
REV. #
P1.0.0
P1.0.1
DATE
DESCRIPTION OF CHANGES
04/05/06
05/12/06
Initial release.
Operating range changed to 10MHz to 120MHz - edit all references of this.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or
to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2006 EXAR Corporation
Datasheet May 2006.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
13
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