XRT6166CP-F [EXAR]
PCM Transceiver, 1-Func, CMOS, PDSO28, 0.300 INCH, GREEN, SOIC-28;
| 型号： | XRT6166CP-F |
| 厂家： | 
EXAR CORPORATION |
| 描述： | PCM Transceiver, 1-Func, CMOS, PDSO28, 0.300 INCH, GREEN, SOIC-28 PC 电信 光电二极管 电信集成电路 |
| 文件： | 总18页 (文件大小：259K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XR-T6166
Codirectional Digital Data
Processor
...the analog plus companyTM
June 1997–3
APPLICATIONS
FEATURES
D CCITT G.703 Compliant 64kbps Codirectional
D Low Power CMOS Technology
Interface
D All Receiver and Transmitter Inputs and Outputs are
D Performs the Digital and Analog Functions for
a Complete 64kbps Data Adaption Unit (DAU) When
Used With the XR-T6164
TTL Compatible
D Transmitter Inhibits Bipolar Violation Insertion for
Transmission of Alarm Conditions
D Alarm Output Indicates Loss of Received Bipolar
Violations
D Tolerance of 125µs Variance of Data Transfer
Timing in Both Transmit and Receive Paths
Allows Operation in Plesiochronous Networks
D Both Receiver and Transmitter Perform Byte
Insertion or Deletion in Response to Local Clock
Slips and Provide Outputs Indicating Slip Logic
Activity
GENERAL DESCRIPTION
The XR-T6166 is a CMOS device which contains the
digital circuitry necessary to interface both directions of a
64kbps data stream to 2.048Mbps transmit and receive
PCM time-slots. The XR-T6166 and the companion
XR-T6164 line interface chip together form a CCITT
G.703 compliant 64kbps codirectional interface.
stream. The receiver, which performs the reverse
operation, decodes the 64kbps data, extracts a clock
signal, and then outputs the data to a 2.048Mbps
time-slot. The XR-T6166 provides features which allow
the repetitions and deletions of both received and
transmitted data as clock skews and transients occur.
These slip occurrences are indicated by byte insertion
and deletion flags. Outputs are also provided for
extracted receive clock and clock recovery circuit loss of
lock.
The XR-T6166 contains separate transmit and receive
sections. The transmitter transforms 8 bit serial data from
a 2.048Mbps time-slot into an encoded 64kbps data
ORDERING INFORMATION
Operating
Temperature Range
Part No.
XR-T6166CP
XR-T6166IP
XR-T6166CD
XR-T6166ID
Package
28 Lead 600 Mil PDIP
0°C to +70°C
–40°C to 85°C
0°C to +70°C
–40°C to 85°C
28 Lead 600 Mil PDIP
28 Lead 300 Mil JEDEC SOIC
28 Lead 300 Mil JEDEC SOIC
Rev. 2.02
E1990
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 z (510) 668-7000 z (510) 668-7010
1
XR-T6166
19
PCMIN
D
8 Bit Input Register
8
20
TX2MHz
CLK
Byte
Deletion
10
11
18
TS1T
BDT
BIT
8 Bit Latch
8
time-slot
Mux
12
15
TS2T
Load
Byte
Insertion
TTSEL
CLK
8 Bit Output Register
Load
Q
Control
Circuitry
17
16
TX256kHz
ALARMIN
D
CLK
Octet
Counter
Violation
Insertion
Coding
Logic
13
14
T+R
T-R
Q
D
CLK
Q
Figure 1. XR-T6166 Transmitter Section Block Diagram
Byte Sync
Detection
Violation
Loss
Alarm
1
ALARM
CLK
2
S+R
S-R
Data
Decoder
CLK
3
4
5
BLS
D
Q
Q
28
8 Bit Reg 0
PCMOUT
RX2MHz
CLK
Register
Select
Logic
time-slot
Mux
TS1R 23
D
8 Bit Reg 1
CLK
REG 0 SEL
Time
Slot
Mux
24
27
TS2R
Byte
Insertion
REG 1 SEL
time-slot
BIR
26
25
RTSEL
Byte
BDR
Deletion
6
9
BLANK
128kHz Recovered Clock
7
RXCKOUT
CS
Clock
Recovery
RXCK2MHz
22
Figure 2. XR-T6166 Receiver Section Block Diagram
Rev. 2.02
2
XR-T6166
PIN CONFIGURATION
1
2
28
27
1
2
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ALARM
S+R
S-R
BLS
RX2MHz
PCMOUT
RTSEL
BIR
BDR
TS2R
ALARM
S+R
S-R
BLS
RX2MHz
PCMOUT
RTSEL
BIR
BDR
TS2R
3
4
5
26
25
24
3
4
5
6
23
22
21
20
19
18
BLANK
RXCKOUT
TS1R
CS
6
BLANK
RXCKOUT
TS1R
CS
7
7
V
SS
8
V
DD
8
V
DD
V
SS
TX2MHz
PCMIN
BIT
TX256kHz
ALARMIN
TTSEL
9
RXCK2MHz
TS1T
BDT
9
RXCK2MHz
TS1T
BDT
TX2MHz
PCMIN
BIT
10
11
10
11
12
13
14
12
13
17
16
TS2T
T+R
T-R
TX256kHz
TS2T
T+R
T-R
ALARMIN
TTSEL
14
15
28 Lead PDIP (0.600”)
28 Lead SOIC (Jedec, 0.300”)
PIN DESCRIPTION
Pin #
Symbol
Type Description
1
ALARM
O
Octet Timing Alarm. When active, indicates loss of received bipolar violations that are used
for octet timing. Active high.
2
3
4
S+R
S-R
BLS
I
I
I
Positive AMI Data to Receiver. Positive data from the XR-T6164 receive-side. Active low.
Negative AMI Data to Receiver. Negative data from the XR-T6164 receive-side. Active low.
Byte Locking Supervision. When active, causes blanking of PCMOUT under received
alarm conditions. Active low.
5
6
RX2MHz
BLANK
RXCKOUT
VDD
I
I
Receiver 2.048MHz Clock. Used to clock out PCM data.
PCMOUT Data Blanking. When active, forces PCMOUT data to all ones (AIS). Active high.
128kHz Extracted Clock. Clock recovered from received data.
+5V $10% Power Source.
7
O
8
9
RXCK2MHz
TS1T
I
I
2.048MHz Clock. Used by receiver clock recovery circuit.
Transmitter Time-slot 1 Input.
10
11
12
13
14
BDT
O
I
Transmitter Byte Deletion Flag. Active when a transmit byte is deleted. Active high.
Transmitter Time-slot 2 Input.
TS2T
T+R
O
O
Transmit Positive AMI Data Output. Data to XR-T6164 positive transmitter input. Active low.
T-R
Transmit Negative AMI Data Output. Data to XR-T6164 negative transmitter input. Active
low.
15
16
TTSEL
I
I
Transmit Time-slot Select. When high, pin 10 is selected; when low, pin 12 is selected.
ALARMIN
Alarm Input. When active, inhibits insertion of violations used for octet timing in transmitter
output. Active high.
Rev. 2.02
3
XR-T6166
PIN DESCRIPTION (CONT’D)
Pin #
17
Symbol
TX256kHz
BIT
Type Description
I
O
I
Transmitter 256kHz Clock. Used to output 64kbps encoded data.
18
Transmitter Byte Insertion Flag. Active when a transmit byte is repeated. Active high.
Transmitter PCM Input. Data read from the system PCM bus.
Transmitter 2.048MHz Clock. Clocks PCM data in PCMIN.
Ground.
19
PCMIN
TX2MHz
VSS
20
I
21
22
CS
O
Clock Seek. Indicates that clock recovery circuit has loss of lock with received data. Active
high.
23
24
25
26
27
28
TS1R
TS2R
I
I
Receiver Time-slot 1 Input.
Receiver Time-slot 2 Input.
BDR
O
O
I
Receiver Byte Deletion Flag. Active when received data byte is deleted. Active high.
Receiver Byte Insertion Flag. Active when a received data byte is repeated. Active high.
Receive Time-slot Select. When high, pin 23 is selected; when low, pin 24 is selected.
Received PCM Output Data. Data sent to the system PCM bus.
BIR
RTSEL
PCMOUT
O
Rev. 2.02
4
XR-T6166
ELECTRICAL CHARACTERISTICS
Test Conditions: V = 5V $10%, T = 25°C, Unless Otherwise Specified
DD
A
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
DC Electrical Characteristics
VIH
VIL
Logic 1
2.4
V
V
Logic 0
0.4
5.5
VDD
IDD
IIL
Supply
4.5
V
Supply Current
Input Leakage
500
µA
µA
V
Dynamic Supply Current
1
VOL
VOH
0.4
At 1.6mA
At 0.4mA
2.4
mA
AC Electrical Characteristics
General
tr, tf
Receiver
tRS
Output Rise/Fall Time
20
ns
All Outputs
RX2MHz Rising Edge to TS
Rising Edge Set Up Time
0
0
tRXL-
100
ns
ns
ns
ns
ns
Figure 3
Figure 3
Figure 3
Figure 3
Figure 3
tRH
RX2MHz Rising Edge to TS
Falling Edge Hold Time
tRXL-
100
tDRS
tDRH
tRXD
TS Rising Edge to Leading Edge
of PCMOUT D0 Bit Delay
10
10
10
TS Falling Edge to Trailing Edge
of PCMOUT D7 Bit Hold Time
0
RX2MHz Rising Egde to
PCMOUT Bits D1 Through D6
Rising Edge Delay
tPW
tRXH
PCMOUT Pulse Width
RX2MHz High Time
RX2MHz Low Time
RX2MHz Period
488
244
244
488
ns
ns
ns
ns
Figure 3
Figure 3
Figure 3
$100ppm
tRXL
tRXCLK
Transmitter
tTS
TS Rising Edge to TX2MHz Set
Up Time
20
0
tTXL-
100
ns
ns
ns
ns
Figure 5
Figure 5
Figure 5
Figure 5
tTH
tDS
tDH
TS Falling Edge to TX2MHz Hold
Time
tTXL-
100
PCMIN Edge to TX2MHz Set Up
Time
100
100
PCMIN Edge to TX2MHz Hold
Time
tTXH
tTXL
TX2MHz High Time
TX2MHz Low Time
TX2MHz Period
244
244
488
ns
ns
ns
Figure 5
Figure 5
$100ppm
tTXCLK
Rev. 2.02
5
XR-T6166
ELECTRICAL CHARACTERISTICS (CONT’D)
Symbol
Parameter
Min.
Typ.
Max.
Unit
Conditions
AC Electrical Characteristics (Cont’d)
Transmitter (Cont’d)
tKXH
tKXL
TX256kHz High Time
TX256kHz Low Time
TX256kHz Period
BDT High Time
1.95
1.95
µs
µs
µs
ns
µs
µs
tKXCLK
tBDTH
tBITH
tALH
3.9063
488
12.5
15.6
BIT High Time
ALARMIN High Time
Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20V
Storage Temperature . . . . . . . . . . . . -65°C to +150°C
Operating Temperature . . . . . . . . . . . . . 0°C to +70°C
Magnetic Supplier Information:
Pulse
Transpower Technologies, Inc.
24 Highway 28, Suite 202
Crystal Bay, NV 89402-0187
Tel. (702) 831-0140
Telecom Product Group
P.O. Box 12235
San Diego, CA 92112
Tel. (619) 674-8100
Fax. (619) 674-8262
Fax. (702) 831-3521
Rev. 2.02
6
XR-T6166
tRS
tRXL
tRXH
tRXCLK
tRH
RX2MHz
tDRS
tDRH
time-slot
tPW
tRXD
D4
PCMOUT
D0
D1
D2
D3
D5
D6
D7
Figure 3. Receive Time-slot Timing
tRCKS
S+R
S-R
tRCKP
RXCKOUT
Figure 4. Extracted Clock Timing
tTS
tTXH
tTXL
tTH
tTXCLK
TX2MHz
time-slot
tDS
tDH
PCMIN
D0
D1
D2
D3
D4
D5
D6
D7
Figure 5. Transmit Time-slot Timing
tKXCLK
tKXH
tKXL
Tr
Tf
V
IH
V
IH
50%
50%
50%
V
IL
V
IL
Clock
Figure 6. Clock Timing
Rev. 2.02
7
XR-T6166
SYSTEM DESCRIPTION
seventh and eighth data bits in each word to the same
transmitter output. This function may be inhibited by
setting ALARMIN (pin 16) high to transmit an alarm
condition.
Transmitter
Should skew occur between the TX2MHz and TX256kHz
clocks signals, or during an adjustment of the timing of the
time-slot signal, circuitry is included to delete or repeat
complete words of data. This could happen, for example,
when changing from one time-slot position to another.
Outputs are provided to indicate when a data byte is
inserted or deleted. A byte repetition or insertion occurs
onceifnonewPCMdataisreceived. TheBITflag(pin18)
is active during the transmission of inserted data. A byte
repetition just occurs once. If no new PCM data is
received, the T+R and T-R outputs stay high. A byte
deletion occurs when the transmitter receives a new byte
of data before the previous byte is transferred from the
storage latch to the output register. Under this condition,
the stored data is overwritten and the BDT flag (pin 11) is
active.
Figure 1 shows the XR-T6166 transmitter section block
diagram. The transmitter converts eight bit bursts or
octets of 2.048Mbps serial data present in a PCM
time-slot to a coded continuous 64kbps data stream.
During operation, data input is controlled by external
clock and time-slot signals, and the 64kbps data output is
timed by an external 256kHz clock. Since the input and
output rates may not be exactly equal because of slight
clock rate differences, periodic slips can occur.
Therefore, circuitryisincludedtodeleteorrepeatoctets, if
necessary. Transmitter operation is as follows.
PCM data is applied to PCMIN (pin 19), a 2.048MHz local
clock is applied to TX2MHz (pin 20), and a time-slot signal
is applied through the time-slot multiplexer. This
multiplexer allows the transmitter to be hard wired to two
time-slot positions. A time-slot signal is applied to
multiplexer inputs TS1T (pin 10) or TS2T (pin 12), and a
time-slot select logic level is applied to TTSEL (pin 15). A
high level at TTSEL selects TS1T while a low level
enables TS2T. The time-slot is an envelope derived
externally from TX2MHz that covers eight clock pulses.
The rising edge of the time-slot signal should be made to
coincide with the falling edge of TX2MHz. Eight bits of
PCM data are clocked into the transmitter input register
on the rising edge of TX2MHz while the selected time-slot
signal is high. The input register data is then transferred
to a storage latch.
Receiver
Figure 2 shows the block diagram of the XR-T6166
receiver section. The receiver converts coded continuous
64kbps data to eight bit bursts of 2.048Mbps serial data
suitable for insertion in a PCM time-slot. During
operation, data input is timed by a clock that is extracted
fromtheinputsignal, whileoutputiscontrolledbyexternal
locally supplied clock and time-slot signals. Since the
data input and output rates may not be exactly equal,
circuitry is included to delete or repeat eight bit data
blocks, if necessary. Receiver operation is as follows.
Transmission of 64kbps data is controlled by the 256kHz
local clock that is applied to TX256kHz (pin 17). It is not
necessary for this clock to be synchronized with any other
signals that are applied to the transmitter. The output
process begins by transferring data from the storage latch
to the output shift register after transmission of the
previous eight bits of data is complete. Four periods of
TX256kHz are required to encode each data bit. A “logic
0” applied to PCMIN is coded as 0101 while a “logic 1” is
coded as 0011. This data is output on either T+R (pin 13)
or T-R (pin 14) according to the AMI (alternate mark
inversion) coding rule. Note that the T+R and T-R outputs
as well as the corresponding XR-T6164 transmitterinputs
(TX+I/P, TX-I/P) are all active-low. Therefore, a “logic 0” is
coded as a 1010 and a “logic 1” as a 1100 at the bipolar
transmitter output as specified by CCITT G.703.
Transmission of octet timing is performed by feeding the
A line interface chip such as the receive section of the
XR-T6164 converts the encoded bipolar 64kbps signal to
dual-rail active-low logic levels. These signals are
applied to the XR-T6166 receiver S+R (pin 2) and S-R
(pin 3) inputs. A 128kHz clock, which is derived from the
received signal, is used to decode this data, and then to
clock it into one of two storage registers. Two registers
are used so that one may be receiving continuous data at
64kbps while the other is sending eight bit bursts at a
2.048Mbps rate to PCMOUT (pin 28) while the receiver
time-slot signal is high. The time-slot is an envelope
derived externally from RX2MHz (pin 5) that covers eight
clock pulses. The rising edge of the time-slot signal
should be made to coincide with the rising edge of
RX2MHz. Eight bits of PCM data are clocked out of the
receiver register on the rising edge of RX2MHz while the
Rev. 2.02
8
XR-T6166
time-slot signal is high. A two input multiplexer at the
time-slot input allows the receiver to be hard wired to two
time-slot positions. time-slot signals are applied to TS1R
(pin 23) and TS2R (pin 24) and the active time-slot is
selected by RTSEL (pin 27). A high level applied to
RTSEL selects TS1R and a low level selects TS2R. Data
appearing at PCMOUT is framed by the read time-slot
signal and is guaranteed glitch free.
applied to the BLANK input (pin 6) will also force
PCMOUT to an all-ones state.
Slip control logic is included in the receiver to
accommodate rate differences between input and output
data. The 64kbps input rate is determined by the remote
transmitter, while the PCMOUT rate is set by RX2MHz
which is a local clock. If this clock is slow, an octet will be
deleted periodically, while the last octet will be repeated
under fast conditions. Octet timing is maintained during
these operations. Outputs are provided to indicate when
an octet is inserted or deleted. The BIR flag (pin 26) is
high when PCMOUT data is repeated, and the BDR flag
(pin 25) is high when the receiver deletes an octet.
Recovery of the 128kHz timing signal is performed by a
variable length counter which is clocked by the 2.048MHz
signal applied to RXCK2MHz (pin 9). This clock is not
required to be synchronized with any other signals that
are applied to the XR-T6166. However, the RX2MHz
clock may also be used for this function. Positive input
data transitions are used to synchronize this counter with
the data. If synchronization is lost, the counter length is
shortened, and the clock recovery circuit enters a seek
mode until a transition is found. This mode is identified by
a high level at the CS output (pin 22). The extracted
128kHz signal is available at RXCKOUT (pin 7).
APPLICATION INFORMATION
64kbps Codirectional Interface
Figure 7 shows a codirectional interface circuit using the
XR-T6166 with the XR-T6164 line interface. The
XR-T6164 first converts the bipolar 64kbps transmit and
receive signals to active-low TTL compatible data
required by the XR-T6166. The XR-T6166 then performs
the digital functions that are necessary to interface this
64kbps continuous data to a 2.048Mbps PCM time-slot.
The 64kbps signals that have been attenuated and
Octet timing ensures that bit grouping is maintained when
the data is converted from a 64kbps continuous stream to
eight bit 2.048Mbps bursts. Bipolar violations are used to
identifythelastbitineacheightbitoctet. Intheabsenceof
these violations, for example when receiving
a
transmitted alarm condition (transmitter ALARMIN is
high), the circuit will continue to operate in
synchronizationwith respect to the last received violation.
During this time, the data present at PCMOUT is still
correct as long as synchronization based on the last
received violation is still valid, and the BLS input (pin 4) is
held high. However, if BLS is low and an octet timing
violation is not received, receiver output data is blanked
by forcing PCMOUT to a high level. Also, if eight
successive octet timing violations are not received, the
ALARM output (pin 1) goes to a high level. A high level
distorted
by
the
twisted
pair
cable
are
transformer-coupled to the line side of the XR-T6164 as
shown on the left side of Figure 7. A suggested
transformer for both the input and output applications is
the pulse type PE-65535.
TherightsideofFigure 7showstheXR-T6164LOS(Loss
of Signal) output and the XR-T6166 digital inputs and
outputs. All of these pins are TTL compatible. Please
refer to the Pin Description section of this data sheet for
detailed information about each signal.
Rev. 2.02
9
XR-T6166
T6164 LOS Output
+5V
+5V
1
ALARM
PCMOUT
BIR
Loss of TX Sync
Data to PCM Bus
Byte Repeat Flag
Byte Delete Flag
XR-T6166
28
8
V
DD
26
25
7
0.1µF
0.1µF
BDR
RXCKOUT
CS
Recovered CLK
CLK Seek Flag
0.1µF
22
4
Receive
Side
BLS
Blank O/P for Alarm
2.048MHz Clock
9
13 15
3
64kbps Data
To Line
5
V
C
C
D
V
C
C
A
T
C
M
R
X
A
L
RX2MHz
TS1R
16
12
2
3
RX+I/P
S+R
S-R
S+R
S-R
1:2
23
TIP
time-slot 1
24
27
C
O
N
480
TS2R
time-slot 2
A
R
M
5
1
2
RX-I/P
RING
RTSEL
BLANK
time-slot Select
Forces All Ones
2.048MHz Clock
6
9
I/P BIAS
PE-65535
TTI-17147
14
0.1µF
PEAK CAP
RXCK2MHz
0.1µF
XR-T6164
11
18
19
20
10
64kbps Data
To Line
BDT
BIT
Byte Delete Flag
+5V
300
Byte Insert Flag
1:2
10
8
11
6
13
14
TIP
TX+O/P
TX-O/P
T+R
T-R
TX+I/P
TX-I/P
PCMIN
Data from PCM Bus
2.048MHz Clock
Transmit
Side
G
N
D
D
G
N
D
A
TX2MHz
TS1T
300
RING
time-slot 1
0.1µF
12
15
17
PE-65535
TTI-17147
TS2T
time-slot 2
4
7
TTSEL
time-slot Select
21
V
SS
TX256kHz
ALARMIN
256kHz Clock
16
Inhibit Violations
Figure 7. Typical Codirectional Application Circuit
Rev. 2.02
10
XR-T6166
Transmitter Code Conversion
Step 2 - A binary 1 is coded as a 1100.
Step 3 - A binary 0 is coded as a 1010.
Figure 8 shows the transmitter code conversion process
that CCITT G.703 specifies for a 64kbps codirectional
interface.
Step 4 - The binary signal is converted into a three-level
signal by alternating the polarity of consecutive blocks.
Step 5 - The alternation in polarity of the blocks is violated
every eighth block. The violation block marks the last bit
in an octet.
Step 1 - A 64kbps bit period is divided into four unit
intervals.
Bit Number
7
1
8
0
1
0
2
1
3
0
4
0
5
1
6
1
7
1
8
0
1
1
64kbps data
Steps 1-3
Step 4
Step 5
Violation
Violation
Octel Timing
Figure 8. Transmitter Code Conversion for a 64kbps Bipolar Line Signal
Rev. 2.02
11
XR-T6166
Codirectional Interface Pulse Masks
Figure 9 and Figure 10 show the CCITT G.703 64kbps
codirectional interface pulse masks for single and double
pulses respectively of either polarity. Note that this mask
is for the pulse measured at the XR-T6164 transmitter
output (application circuit shown in Figure 5) when
terminated with a 120Ω resistor.
V
1.0
3.12µs
(3.9 -0.78)
0.5
0
3.51µs
(3.9 -0.39)
3.9µs
4.29µs
(3.9 + 0.39)
6.5µs
(3.9 + 2.6)
7.8µs
(3.9 + 3.9)
Figure 9. Mask for a Single Pulse
V
1.0
7.02µs
(7.8 - 0.78)
0.5
0
7.41µs
(7.8 - 0.39)
7.8µs
8.19µs
(7.8 + 0.39)
10.4µs
(7.8 + 2.6)
11.7µs
(7.8 + 3.9)
Figure 10. Mask for a Double Pulse
Rev. 2.02
12
XR-T6166
28 LEAD PLASTIC DUAL-IN-LINE
(600 MIL PDIP)
Rev. 1.00
28
1
15
E
1
14
E
D
A
2
A
L
Seating
Plane
C
α
A
1
B
B
e
1
e
e
A
B
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
0.160
0.015
0.125
0.014
0.030
0.008
1.380
0.600
0.485
0.250
0.070
0.195
0.024
0.070
0.014
1.565
0.625
0.580
4.06
0.38
6.35
1.78
A
A
B
B
1
2
3.18
4.95
0.36
0.56
0.76
1.78
1
C
D
E
0.20
0.38
35.05
15.24
12.32
39.75
15.88
14.73
E
e
1
0.100 BSC
0.600 BSC
2.54 BSC
15.24 BSC
e
A
e
B
L
0.600
0.700
0.200
15.24
17.78
5.08
0.115
2.92
α
0°
15°
0°
15°
Note: The control dimension is the inch column
Rev. 2.02
13
XR-T6166
28 LEAD SMALL OUTLINE
(300 MIL JEDEC SOIC)
D
28
15
E
H
14
C
A
Seating
Plane
e
B
A
1
L
INCHES
MILLIMETERS
SYMBOL
MIN
MAX
MIN
MAX
A
A1
B
C
D
E
e
0.093
0.004
0.013
0.009
0.697
0.291
0.104
0.012
0.020
0.013
0.713
0.299
2.35
0.10
0.33
0.23
17.70
7.40
2.65
0.30
0.51
0.32
18.10
7.60
0.050 BSC
1.27 BSC
H
L
0.394
0.016
0.419
0.050
10.00
0.40
10.65
1.27
Rev. 2.02
14
XR-T6166
Notes
Rev. 2.02
15
XR-T6166
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to im-
prove design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits de-
scribed herein, conveys no license under any patent or other right, and makes no representation that the circuits are
free of patent infringement. Charts and schedules contains herein are only for illustration purposes and may vary
depending upon a user’s specific application. While the information in this publication has been carefully checked;
no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or
malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly
affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation
receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the
user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circum-
stances.
Copyright 1990 EXAR Corporation
Datasheet June 1997
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.02
16
XRT6166 -Codirectional Digital Data Processor
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Codirectional Digital Data Processor
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5V ±10%,
2mA
●
●
Low Power CMOS Technology
All Receiver and Transmitter Inputs and Outputs are TTL-
Compatible
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●
Transmitter Inhibits Bipolar Violation Insertion for
Transmission of Alarm Conditions
Datasheets
●
●
Alarm Output Indicates Loss of Received Bipolar Violations
Tolerance of 125ms Variance of Data Transfer Timing in Both
Transmit and Receive Paths Allows Operation in
Plesiochronous Networks
Design
Datasheet
Version 2.0.2
June 1997
151.17 KB
Technical
Documentation
●
●
Both Receiver and Transmitter Perform Byte Insertion or
Deletion in Response to Local Clock Slips and Provide
Outputs Indicating Slip Logic Activity
Technical FAQs
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Pb-Free, RoHS Compliant Versions Offered
Evaluation System User Manual
Version 2.0.0
December 1996
1.49 MB
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●
●
CCITT G.703 Compliant 64kbps Codirectional Interface
Packaging
Performs the Digital and Analog Functions for a Complete
64Kbps Data Adaption Unit (DAU) When Used With the XR-
T6164
Evaluation
Boards
Cross
References
Description
Product Change
Notifications
The XRT6166 is a CMOS device which contains the digital circuitry
necessary to interface both directions of a 64kbps data stream to
2.048Mbps transmit and receive PCM time-slots. The XRT6166 and
the companion XRT6164 line interface chip together form a CCITT
Obsolescence
Communications
Brochure
G.703 compliant 64Kbps codirectional interface.
The XRT6166 contains separate transmit and receive sections. The
transmitter transforms 8-bit serial data from a 2.048Mbps time-slot
into an encoded 64Kbps data stream. The receiver, which performs
the reverse operation, decodes the 64kbps data, extracts a clock
signal, and then outputs the data to a 2.048Mbps time-slot. The
XRT6166 provides features which allow the repetitions and deletions
of both received and transmitted data as clock skews and transients
occur. These slip occurrences are indicated by byte insertion and
deletion flags. Outputs are also provided for extracted receive clock
and clock recovery circuit loss of lock.
Storage
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XRT6166 -Codirectional Digital Data Processor
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