XRT75VL00D [EXAR]
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER; E3 / DS3 / STS -1线路接口的SONET失同步单元
| 型号： | XRT75VL00D |
| 厂家： | 
EXAR CORPORATION |
| 描述： | E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER |
| 文件： | 总92页 (文件大小：789K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
FEBRUARY 2004
GENERAL DESCRIPTION
• On-chip clock synthesizer provides the appropriate
rate clock from a single 12.288 MHz Clock.
The XRT75VL00D is a single-channel fully integrated
Line Interface Unit (LIU) with Sonet Desynchronizer
for E3/DS3/STS-1 applications. It incorporates an
independent Receiver, Transmitter and Jitter
Attenuator in a single 52 pin TQFP package.
• Provides low jitter output clock.
TRANSMITTER:
• Compliant with Bellcore GR-499, GR-253 and ANSI
T1.102 Specification for transmit pulse
The XRT75VL00D can be configured to operate in
either E3 (34.368 MHz), DS3 (44.736 MHz) or STS-1
(51.84 MHz) modes. The transmitter can be turned
off (tri-stated) for redundancy support and for
conserving power.
• Tri-state Transmit output capability for redundancy
applications
• Transmitter can be turned on or off.
JITTER ATTENUATOR:
The XRT75VL00D’s differential receiver provides high
noise interference margin and is able to receive the
data over 1000 feet of cable or with up to 12 dB of
cable attenuation.
• On chip advanced crystal-less Jitter Attenuator.
• Jitter Attenuator can be selected in Receive or
Transmit paths.
The XRT75VL00D incorporates an advanced crystal-
less jitter attenuator that can be selected either in the
transmit or receive path. The jitter attenuator
performance meets the ETSI TBR-24 and Bellcore
GR-499 specifications. Also, the jitter attenuator can
be used for clock smoothing in SONET STS-1 to DS3
de-mapping.
• 16, 32 or 128 bits selectable FIFO size.
• Meets the Jitter and Wander specifications
described in T1.105.03b,ETSI TBR-24, Bellcore
GR-253 and GR-499 standards.
• Jitter Attenuator can be disabled.
• De-Synchronizer for SONET STS-1 to DS-3
demapping.
The
XRT75VL00D
provides
both
Serial
Microprocessor Interface as well as Hardware mode
for programming and control.
CONTROL AND DIAGNOSTICS:
• 5 wire Serial Microprocessor Interface for control
The XRT75VL00D supports local, remote and digital
loop-backs. The XRT75VL00D also contains an on-
board Pseudo Random Binary Sequence (PRBS)
generator and detector with the ability to insert and
detect single bit error.
and configuration.
• Supports optional internal Transmit Driver
Monitoring.
• PRBS error counter register to accumulate errors.
• Hardware Mode for control and configuration.
• Supports Local, Remote and Digital Loop-backs.
• Single 3.3 V ± 5% power supply.
FEATURES
RECEIVER:
• On chip Clock and Data Recovery circuit for high
input jitter tolerance.
• 5 V Tolerant I/O.
• Meets
E3/DS3/STS-1
Requirements.
Jitter
Tolerance
• Available in 52 pin TQFP.
• Detects and Clears LOS as per G.775.
• -40°C to 85°C Industrial Temperature Range.
• Meets Bellcore GR-499 CORE Jitter Transfer
Requirements.
APPLICATIONS
• E3/DS3 Access Equipment.
• DSLAMs.
• Receiver Monitor mode handles up to 20 dB flat
loss with 6 dB cable attenuation.
• Compliant with jitter transfer template outlined in
ITU G.751, G.752, G.755 and GR-499-CORE,1995
standards.
• Digital Cross Connect Systems.
• CSU/DSU Equipment.
• Routers.
• Meets ETSI TBR 24 Jitter Transfer Requirements.
• Fiber Optic Terminals.
• On chip B3ZS/HDB3 encoder and decoder that can
be either enabled or disabled.
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
FIGURE 1. BLOCK DIAGRAM OF THE XRT 75VL00D
SDI
SDO
INT
SClk
CS
RESET
CLK_OUT
Serial
Processor
Interface
ExClk/12M
RLOL
RxON
RxClkINV
Clock
Synthesizer
HOST/HW
STS-1/DS3
E3
REQEN
RTIP
RRING
Invert
RxClk
Peak Detector
HDB3/
B3ZS
Decoder
RPOS
Clock & Data
Recovery
Jitter
Attenuator
Slicer
AGC/
Equalizer
MUX
RNEG/
LCV
LOS
Detector
SR/DR
LLB
Remote
LoopBack
Local
LoopBack
RLB
RLOS
JATx/Rx
TPData
TNData
TxClk
TTIP
HDB3/
B3ZS
Encoder
Line
Driver
Tx
Pulse
Shaping
Jitter
Attenuator
Timing
Control
MUX
TRING
TAOS
TxLEV
TxON
MTIP
MRING
Device
Monitor
Tx
Control
DMO
Note: Serial Processor Interface input pins are shared by in "Host" Mode and redefined in the "Hardware" Mode.
TRANSMIT INTERFACE CHARACTERISTICS
• Accepts either Single-Rail or Dual-Rail data from Terminal Equipment and generates a bipolar signal to the
line
• Integrated Pulse Shaping Circuit.
• Built-in B3ZS/HDB3 Encoder (which can be disabled).
• Accepts Transmit Clock with duty cycle of 30%-70%.
• Generates pulses that comply with the ITU-T G.703 pulse template for E3 applications.
• Generates pulses that comply with the DSX-3 pulse template, as specified in Bellcore GR-499-CORE and
ANSI T1.102_1993.
• Generates pulses that comply with the STSX-1 pulse template, as specified in Bellcore GR-253-CORE.
• Transmitter can be turned off in order to support redundancy designs.
RECEIVE INTERFACE CHARACTERISTICS
• Integrated Adaptive Receive Equalization for optimal Clock and Data Recovery.
• Declares and Clears the LOS defect per ITU-T G.775 requirements for E3 and DS3 applications.
• Meets Jitter Tolerance Requirements, as specified in ITU-T G.823_1993 for E3 Applications.
• Meets Jitter Tolerance Requirements, as specified in Bellcore GR-499-CORE for DS3 Applications.
• Declares Loss of Signal (LOS) and Loss of Lock (LOL) Alarms.
• Built-in B3ZS/HDB3 Decoder (which can be disabled).
• Recovered Data can be muted while the LOS Condition is declared.
2
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
• Outputs either Single-Rail or Dual-Rail data to the Terminal Equipment.
JITTER ATTENUATORS
The XRT75VL00D includes a Jitter Attenuator that meets the Jitter requirements specified in the ETSI TBR-24,
Bellcore GR-499 and GR-253 standards. In addition, the jitter attenuator also meets the Jitter and Wander
specifications described in the ANSI T1.105.03b 1997, Bellcore GR-253 and GR-499 standards.
FIGURE 2. PIN OUT OF THE XRT75VL00D
DMO
MTIP
40
41
42
43
44
45
46
47
48
49
50
51
52
26 SCLK (TxClkINV)
25
24
23
SDI (RxON)
CS (RxClkINV)
REQEN
MRING
JaAGND
ExClk/12M
JaAVDD
TxClk
22 SR/DR
21
20
19
18
17
16
15
14
HOST/HW
E3
STS1/DS3
RLB
LLB
ICT
XRT75VL00D
(top view)
TPData
TNData
DGND
TTIP
TRING
DVDD
TEST
RESET
ORDERING INFORMATION
PART NUMBER
PACKAGE
OPERATING TEMPERATURE RANGE
-40°C to +85°C
XRT75VL00DIV
52 Pin TQFP
3
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
TABLE OF CONTENTS
GENERAL DESCRIPTION ................................................................................................. 1
FEATURES .................................................................................................................................................... 1
APPLICATIONS .............................................................................................................................................. 1
TRANSMIT INTERFACE CHARACTERISTICS ...................................................................................................... 2
RECEIVE INTERFACE CHARACTERISTICS ........................................................................................................ 2
Figure 1. Block Diagram of the XRT 75VL00D ................................................................................................. 2
JITTER ATTENUATORS ................................................................................................................................... 3
Figure 2. Pin Out of the XRT75VL00D .............................................................................................................. 3
ORDERING INFORMATION ................................................................................................................... 3
TABLE OF CONTENTS ................................................................................................................................... 1
PIN DESCRIPTIONS (BY FUNCTION) ............................................................................. 4
TRANSMIT INTERFACE ................................................................................................................................... 4
RECEIVE INTERFACE ..................................................................................................................................... 6
CLOCK INTERFACE ........................................................................................................................................ 8
OPERATING MODE SELECT ........................................................................................................................... 9
CONTROL AND ALARM INTERFACE ................................................................................................................. 9
MICROPROCESSOR SERIAL INTERFACE - (HOST MODE) ........................................................................ 11
13
JITTER ATTENUATOR INTERFACE ................................................................................................................. 13
ANALOG POWER AND GROUND ................................................................................................................... 14
DIGITAL POWER AND GROUND ................................................................................................................... 14
1.0 ELECTRICAL CHARACTERISTICS ................................................................................................. 15
TABLE 1: ABSOLUTE MAXIMUM RATINGS ............................................................................................................ 15
TABLE 2: DC ELECTRICAL CHARACTERISTICS: ................................................................................................... 15
2.0 TIMING CHARACTERISTICS ............................................................................................................ 16
Figure 3. Typical interface between terminal equipment and the XRT75VL00D (dual-rail data) .................... 16
Figure 4. Transmitter Terminal Input Timing ................................................................................................... 16
Figure 5. Receiver Data output and code violation timing .............................................................................. 17
Figure 6. Transmit Pulse Amplitude test circuit for E3, DS3 and STS-1 Rates ............................................... 17
3.0 LINE SIDE CHARACTERISTICS: ..................................................................................................... 18
3.1 E3 LINE SIDE PARAMETERS: ............................................................................................................................. 18
Figure 7. Pulse Mask for E3 (34.368 mbits/s) interface as per itu-t G.703 ..................................................... 18
TABLE 3: E3 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD = 3.3 V ± 5%) ....... 18
Figure 8. Bellcore GR-253 CORE Transmit Output Pulse Template for SONET STS-1 Applications ............ 19
TABLE 4: STS-1 PULSE MASK EQUATIONS ........................................................................................................ 19
TABLE 5: STS-1 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD =3.3V ± 5%) 20
Figure 9. Transmit Ouput Pulse Template for DS3 as per Bellcore GR-499 .................................................. 20
TABLE 6: DS3 PULSE MASK EQUATIONS ........................................................................................................... 21
TABLE 7: DS3 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD = 3.3V ± 5%) ... 21
Figure 10. Microprocessor Serial Interface Structure ...................................................................................... 22
Figure 11. Timing Diagram for the Microprocessor Serial Interface ................................................................ 22
TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF) ..... 23
4.0 The Transmitter Section: ................................................................................................................. 24
4.1 TRANSMIT CLOCK: ........................................................................................................................................... 24
4.2 B3ZS/HDB3 ENCODER: .................................................................................................................................. 24
4.2.1 B3ZS Encoding: ................................................................................................................................. 24
Figure 12. Single-Rail or NRZ Data Format (Encoder and Decoder are Enabled) ......................................... 24
Figure 13. Dual-Rail Data Format (encoder and decoder are disabled) ......................................................... 24
4.2.2 HDB3 Encoding: ................................................................................................................................. 25
4.3 TRANSMIT PULSE SHAPER: .............................................................................................................................. 25
Figure 14. B3ZS Encoding Format ................................................................................................................. 25
Figure 15. HDB3 Encoding Format ................................................................................................................. 25
4.3.1 Guidelines for using Transmit Build Out Circuit: ............................................................................ 26
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XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
4.3.2 Interfacing to the line: ....................................................................................................................... 26
4.4 TRANSMIT DRIVE MONITOR: ............................................................................................................................. 26
Figure 16. Transmit Driver Monitor set-up. ..................................................................................................... 26
4.5 TRANSMITTER SECTION ON/OFF: ...................................................................................................................... 27
5.0 The Receiver Section: ...................................................................................................................... 27
5.1 AGC/EQUALIZER: ............................................................................................................................................ 27
5.1.1 Interference Tolerance: ..................................................................................................................... 27
Figure 17. Interference Margin Test Set up for DS3/STS-1 ........................................................................... 28
Figure 18. Interference Margin Test Set up for E3. ........................................................................................ 28
5.2 CLOCK AND DATA RECOVERY: ......................................................................................................................... 29
5.3 B3ZS/HDB3 DECODER: .................................................................................................................................. 29
5.4 LOS (LOSS OF SIGNAL) DETECTOR: ................................................................................................................ 29
5.4.1 DS3/STS-1 LOS Condition: ................................................................................................................ 29
TABLE 9: INTERFERENCE MARGIN TEST RESULTS .............................................................................................. 29
DISABLING ALOS/DLOS DETECTOR: ......................................................................................................... 30
5.4.2 E3 LOS Condition: ............................................................................................................................. 30
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
REQEN (DS3 AND STS-1 APPLICATIONS) ......................................................................................... 30
Figure 19. Loss Of Signal Definition for E3 as per ITU-T G.775 .................................................................... 30
5.4.3 Muting the Recovered Data with LOS condition: ............................................................................ 31
Figure 20. Loss of Signal Definition for E3 as per ITU-T G.775. .................................................................... 31
6.0 Jitter: ................................................................................................................................................. 32
6.1 JITTER TOLERANCE - RECEIVER: ...................................................................................................................... 32
6.1.1 DS3/STS-1 Jitter Tolerance Requirements: ..................................................................................... 32
Figure 21. Jitter Tolerance Measurements ..................................................................................................... 32
6.1.2 E3 Jitter Tolerance Requirements: ................................................................................................... 33
Figure 22. Input Jitter Tolerance For DS3/STS-1 .......................................................................................... 33
Figure 23. Input Jitter Tolerance for E3 ......................................................................................................... 33
6.2 JITTER TRANSFER - RECEIVER/TRANSMITTER: .................................................................................................. 34
6.3 JITTER GENERATION: ....................................................................................................................................... 34
6.4 JITTER ATTENUATOR: ...................................................................................................................................... 34
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE) ..................................... 34
TABLE 12: JITTER TRANSFER SPECIFICATIONS ................................................................................................... 34
7.0 Serial Host interface: ....................................................................................................................... 35
TABLE 13: JITTER TRANSFER PASS MASKS ....................................................................................................... 35
Figure 24. Jitter Transfer Requirements and Jitter Attenuator Performance .................................................. 35
TABLE 14: FUNCTIONS OF SHARED PINS ............................................................................................................ 36
TABLE 15: REGISTER MAP AND BIT NAMES ....................................................................................................... 36
TABLE 16: REGISTER MAP DESCRIPTION ........................................................................................................... 37
TABLE 17: REGISTER MAP DESCRIPTION - GLOBAL ............................................................................................ 41
8.0 Diagnostic Features: ........................................................................................................................ 43
8.1 PRBS GENERATOR AND DETECTOR: ................................................................................................................ 43
8.2 LOOPBACKS: ............................................................................................................................................... 43
8.2.1 ANALOG LOOPBACK: ....................................................................................................................... 43
Figure 25. PRBS MODE ................................................................................................................................. 43
8.2.2 DIGITAL LOOPBACK: ........................................................................................................................ 44
Figure 26. Analog Loopback ........................................................................................................................... 44
8.2.3 REMOTE LOOPBACK: ....................................................................................................................... 45
8.3 TRANSMIT ALL ONES (TAOS): ................................................................................................................... 45
Figure 27. Digital Loopback ............................................................................................................................ 45
Figure 28. Remote Loopback ......................................................................................................................... 45
Figure 29. Transmit All Ones (TAOS) ............................................................................................................. 46
9.0 THE SONET/SDH DE-SYNC FUNCTION within THE liu ................................................................ 47
9.1 BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS .......................... 47
Figure 30. A Simple Illustration of a DS3 signal being mapped into and transported over the SONET Network
48
9.2 MAPPING/DE-MAPPING JITTER/WANDER ................................................................................................ 49
2
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
9.2.1 HOW DS3 DATA IS MAPPED INTO SONET ...................................................................................... 49
A Brief Description of an STS-1 Frame 49
Figure 31. A Simple Illustration of the SONET STS-1 Frame ......................................................................... 50
Figure 32. A Simple Illustration of the STS-1 Frame Structure with the TOH and the Envelope Capacity Bytes
Designated .................................................................................................................................... 51
Figure 33. The Byte-Format of the TOH within an STS-1 Frame .................................................................... 52
Figure 34. The Byte-Format of the TOH within an STS-1 Frame .................................................................... 53
Mapping DS3 data into an STS-1 SPE 54
Figure 35. Illustration of the Byte Structure of the STS-1 SPE ....................................................................... 54
Figure 36. An Illustration of Telcordia GR-253-CORE’s Recommendation on how map DS3 data into an STS-1
SPE ............................................................................................................................................... 55
Figure 37. A Simplified "Bit-Oriented" Version of Telcordia GR-253-CORE’s Recommendation on how to map
DS3 data into an STS-1 SPE ........................................................................................................ 55
9.2.2 DS3 Frequency Offsets and the Use of the "Stuff Opportunity" Bits ............................................ 56
The Ideal Case for Mapping DS3 data into an STS-1 Signal (e.g., with no Frequency Offsets) 57
Figure 38. A Simple Illustration of a DS3 Data-Stream being Mapped into an STS-1 SPE, via a PTE .......... 57
The 44.736Mbps + 1ppm Case 58
Figure 39. An Illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, when mapping in
a DS3 signal that has a bit rate of 44.736Mbps + 1ppm, into an STS-1 signal ............................ 58
The 44.736Mbps - 1ppm Case 59
9.3 JITTER/WANDER DUE TO POINTER ADJUSTMENTS ............................................................................................ 60
9.3.1 The Concept of an STS-1 SPE Pointer ............................................................................................. 60
Figure 40. An Illustration of the STS-1 SPE traffic that will be generated by the Source PTE, when mapping a
DS3 signal that has a bit rate of 44.736Mbps - 1ppm, into an STS-1 signal ................................ 60
Figure 41. An Illustration of an STS-1 SPE straddling across two consecutive STS-1 frames ....................... 61
9.3.2 Pointer Adjustments within the SONET Network ............................................................................ 62
Figure 42. The Bit-format of the 16-Bit Word (consisting of the H1 and H2 bytes) with the 10 bits, reflecting the
location of the J1 byte, designated ............................................................................................... 62
Figure 43. The Relationship between the Contents of the "Pointer Bits" (e.g., the 10-bit expression within the H1
and H2 bytes) and the Location of the J1 Byte within the Envelope Capacity of an STS-1 Frame ...
62
9.3.3 Causes of Pointer Adjustments ........................................................................................................ 63
Figure 44. An Illustration of an STS-1 signal being processed via a Slip Buffer ............................................. 64
Figure 45. An Illustration of the Bit Format within the 16-bit word (consisting of the H1 and H2 bytes) with the "I"
bits designated .............................................................................................................................. 65
Figure 46. An Illustration of the Bit-Format within the 16-bit word (consisting of the H1 and H2 bytes) with the
"D" bits designated ........................................................................................................................ 66
9.3.4 Why are we talking about Pointer Adjustments? ............................................................................ 67
9.4 CLOCK GAPPING JITTER ................................................................................................................................... 67
Figure 47. Illustration of the Typical Applications for the LIU in a SONET De-Sync Application .................... 67
9.5 A REVIEW OF THE CATEGORY I INTRINSIC JITTER REQUIREMENTS (PER TELCORDIA GR-253-CORE) FOR DS3 AP-
PLICATIONS .......................................................................................................................................................................... 68
TABLE 18: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3
APPLICATIONS ..................................................................................................................................... 68
9.5.1 DS3 De-Mapping Jitter ....................................................................................................................... 69
9.5.2 Single Pointer Adjustment ................................................................................................................ 69
9.5.3 Pointer Burst ...................................................................................................................................... 69
Figure 48. Illustration of Single Pointer Adjustment Scenario ......................................................................... 69
9.5.4 Phase Transients ............................................................................................................................... 70
Figure 49. Illustration of Burst of Pointer Adjustment Scenario ....................................................................... 70
Figure 50. Illustration of "Phase-Transient" Pointer Adjustment Scenario ...................................................... 70
9.5.5 87-3 Pattern ......................................................................................................................................... 71
9.5.6 87-3 Add .............................................................................................................................................. 71
Figure 51. An Illustration of the 87-3 Continuous Pointer Adjustment Pattern ................................................ 71
9.5.7 87-3 Cancel ......................................................................................................................................... 72
Figure 52. Illustration of the 87-3 Add Pointer Adjustment Pattern ................................................................. 72
3
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
Figure 53. Illustration of 87-3 Cancel Pointer Adjustment Scenario ............................................................... 72
9.5.8 Continuous Pattern ............................................................................................................................ 73
9.5.9 Continuous Add ................................................................................................................................ 73
Figure 54. Illustration of Continuous Periodic Pointer Adjustment Scenario ................................................. 73
9.5.10 Continuous Cancel .......................................................................................................................... 74
Figure 55. Illustration of Continuous-Add Pointer Adjustment Scenario ......................................................... 74
Figure 56. Illustration of Continuous-Cancel Pointer Adjustment Scenario .................................................... 74
9.6 A REVIEW OF THE DS3 WANDER REQUIREMENTS PER ANSI T1.105.03B-1997. ............................................... 75
9.7 A REVIEW OF THE INTRINSIC JITTER AND WANDER CAPABILITIES OF THE LIU IN A TYPICAL SYSTEM APPLICATION ...
75
9.7.1 Intrinsic Jitter Test results ................................................................................................................ 75
TABLE 19: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS ....... 75
9.7.2 Wander Measurement Test Results ................................................................................................. 76
9.8 DESIGNING WITH THE LIU ................................................................................................................................. 76
9.8.1 How to design and configure the LIU to permit a system to meet the above-mentioned Intrinsic
Jitter and Wander requirements ...................................................................................................................................... 76
Figure 57. Illustration of the LIU being connected to a Mapper IC for SONET De-Sync Applications ........... 76
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................... 77
CHANNEL 1 ADDRESS LOCATION = 0X0E ........................................... 77
CHANNEL 2 ADDRESS LOCATION = 0X16 ........................................... 77
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06 ................................................... 78
CHANNEL 1 ADDRESS LOCATION = 0X0E ................................................ 78
CHANNEL 2 ADDRESS LOCATION = 0X16 ................................................. 78
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07 ................................. 78
CHANNEL 1 ADDRESS LOCATION = 0X0F .................................... 78
CHANNEL 2 ADDRESS LOCATION = 0X17 .................................... 78
9.8.2 Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device) prior to
routing this DS3 Clock and Data-Signals to the Transmit Inputs of the LIU ............................................................... 79
SOME NOTES PRIOR TO STARTING THIS DISCUSSION: 79
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 79
CHANNEL 1 ADDRESS LOCATION = 0X0F .............................. 79
CHANNEL 2 ADDRESS LOCATION = 0X17 .............................. 79
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 79
CHANNEL 1 ADDRESS LOCATION = 0X0F ............................. 79
CHANNEL 2 ADDRESS LOCATION = 0X17 ............................. 79
OUR PRE-PROCESSING RECOMMENDATIONS 80
Figure 58. Illustration of MINOR PATTERN P1 .............................................................................................. 80
Figure 59. Illustration of MINOR PATTERN P2 .............................................................................................. 81
Figure 60. Illustration of Procedure which is used to Synthesize MAJOR PATTERN A ................................ 81
Figure 61. Illustration of MINOR PATTERN P3 .............................................................................................. 82
Figure 62. Illustration of Procedure which is used to Synthesize PATTERN B ............................................. 82
9.8.3 How does the LIU permit the user to comply with the SONET APS Recovery Time requirements
of 50ms (per Telcordia GR-253-CORE)? ......................................................................................................................... 83
Figure 63. Illustration of the SUPER PATTERN which is output via the "OC-N to DS3" Mapper IC .............. 83
Figure 64. Simple Illustration of the LIU being used in a SONET De-Synchronizer" Application ................... 83
TABLE 20: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET ............................................ 84
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 84
CHANNEL 1 ADDRESS LOCATION = 0X0F ............................. 84
CHANNEL 2 ADDRESS LOCATION = 0X17 ............................. 84
9.8.4 How should one configure the LIU, if one needs to support "Daisy-Chain" Testing at the end Cus-
tomer’s site? ..................................................................................................................................................................... 85
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07 .................................. 85
CHANNEL 1 ADDRESS LOCATION = 0X0F .................................... 85
CHANNEL 2 ADDRESS LOCATION = 0X17 .................................... 85
ORDERING INFORMATION ............................................................................................................................ 86
PACKAGE DIMENSIONS ................................................................................................. 86
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XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
REVISION HISTORY ..................................................................................................................................... 87
5
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
PIN DESCRIPTIONS (BY FUNCTION)
TRANSMIT INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
4
TxON
I
Transmitter ON Input
Setting this input pin "High" turns on the Transmitter.
NOTES:
1. Even when the XRT75VL00D is configured in HOST mode, this pin still
controls the TTIP and TRING outputs
2. When the Transmitter is turned off either in Host or Hardware
mode,the TTIP and TRING outputs are Tri-stated.
3. This pin is internally pulled down
46
TxClk
I
Transmit Clock Input for TPData and TNData
The frequency accuracy of this input clock must be of nominal bit rate ± 20 ppm.
The duty cycle can be 30%-70%.
The XRT75VL00D samples the TPData and TNData pins on the falling or rising
edge of TxClk signal based on the status of TxClkINV pin (in Hardware mode)
or the status of the bit in the Channel Register (in HOST mode).
26
TxClkINV/
SClk
I
Transmit Clock Invert or Serial Clock Input:
Function of this depends on whether the XRT75VL00D is configured to operate
in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” configures the Transmitter to
sample the TPData and TNData data on the rising edge of the TxClk.
NOTE: If the XRT75VL00D is configured in HOST mode, this pin functions as
SClk input pin (please refer to the pin description for Microprocessor
interface).
48
TNData
I
Transmit Negative Data Input
If the XRT75VL00D is configured in Dual-rail mode, this pin is sampled on the
falling or rising edge of TxClk based on the status of the TClkINV pin (in Hard-
ware mode) or the status of the control bit in the Channel Register (in HOST
mode).
NOTES:
1. This input pin is ignored and should be tied to GND if the Transmitter
Section is configured to accept Single-Rail data from the Terminal
Equipment.
47
50
TPData
TTIP
I
Transmit Positive Data Input
The XRT75VL00D samples this pin on the falling or rising edge of TxClk based
on the status of the TClkINV pin (in Hardware mode) or the status of the control
bit in the Channel Register (in HOST mode).
O
Transmit TTIP Output
The XRT75VL00D uses this pin along with TRING to transmit a bipolar signal to
the line using a 1:1 transformer.
4
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
TRANSMIT INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
51
TRING
O
Transmit Ring Output
The XRT75VL00D uses this pin along with TTIP to transmit a bipolar signal to
the line using a 1:1 transformer.
1
TxLEV
I
Transmit Line Build-Out Enable/Disable Select
This input pin is used to enable or disable the Transmit Line Build-Out circuit.
Setting this pin to "High" disables the Line Build-Out circuit. In this mode, par-
tially-shaped pulses are output onto the line via the TTIP and TRING output
pins.
Setting this pin to "Low" enables the Line Build-Out circuit. In this mode, shaped
pulses are output onto the line via the TTIPand TRING output pins.
To comply with the Isolated DSX-3/STSX-1 Pulse Template Requirements per
Bellcore GR-499-CORE or Bellcore GR-253-CORE:
1. Set this pin to "1" if the cable length between the Cross-Connect and the
transmit output is greater than 225 feet.
2. Set this pin to "0" if the cable length between the Cross-Connect and the
transmit output is less than 225 feet.
This pin is active only if the following two conditions are true:
a. The XRT75VL00D is configured to operate in either the DS3 or SONET STS-
1 Modes.
b. The XRT75VL00D is configured to operate in the Hardware Mode.
NOTES:
1. This pin is internally pulled down.
2. If the XRT75VL00D is configured in HOST mode, this pin may be tied
to GND.
5
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
RECEIVE INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
25
RxON/
SDI
I
Receiver Turn ON Input or Serial Data Input:
Function of this pin depends on whether the XRT75VL00D is configured to
operate in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” turns on and enables the
Receiver..
NOTES:
1. If the XRT75VL00D is configured in HOST mode, this pin functions as
SDI input pin (please refer to the pin description for Microprocessor
Interface)
2. This pin is internally pulled down.
23
REQEN
I
Receive Equalization Enable Input
Setting this input pin "High" enables the Internal Receive Equalizer. Setting this
pin "Low" disables the Internal Receive Equalizer.
NOTES:
1. This input pin is ignored and may be connected to GND if the
XRT75VL00D is operating in the HOST Mode
2. This pin is internally pulled down.
36
RxClk
O
Receive Clock Output
The Recovered Clock signal from the incoming line signal is output through this
pin.By default, the Receiver Section outputs data via RPOS and RNEG pins on
the rising edge of this clock signal.
Configure the Receiver Section to update data on the RPOS and RNEG pins on
the falling edge of RxClk by doing the following:
a) Operating in Hardware mode, pull the RxClkINV pin to “High”.
b) Operating in Host mode, write a “1” to RxClkINV bit field within the Receive
Control Register.
24
RxClkINV/
CS
I
RxClk INVERT or Chip Select:
Function of this pin depends on whether the XRT75VL00D is configured to
operate in Hardware mode or Host mode.
In Hardware mode, setting this input pin “High” configures the Receiver Sec-
tion to invert the RxClk output signals and outputs the recovered data via
RPOS and RNEG on the falling edge of RxClk.
NOTE: If the XRT75VL00D is configured in HOST mode, this pin functions as
CS input pin (please refer to the pin description for Microprocessor
Interface).
38
RPOS
O
Receive Positive Data Output
This output pin pulses “High" whenever the XRT75VL00D has received a Posi-
tive Polarity pulse in the incoming line signal at the RTIP/RRing inputs.
6
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
RECEIVE INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
37
RNEG/LCV
O
Receive Negative Data Output/Line Code Violation Indicator
Function of these pins depends on whether the XRT75VL00D is config-
ured in Single Rail or Dual Rail mode.
If the XRT75VL00D is configured in Dual Rail mode, a negative pulse is output
through RNEG.
In Hardware mode: Tie the pin SR/DR (pin 22) “High” to configure the
XRT75VL00D in Single Rail mode and tie “Low” to configure in Dual Rail mode.
In HOST mode: XRT75VL00D can be configured in Single Rail or Dual Rail by
setting or clearing the bit in the block control register.
Line Code Violation Indicator
If the XRT75VL00D is configured in Single Rail mode then:
Whenever the Receiver Section detects a Line Code violation, it pulses this
output pin “High”. This output pin remains “Low” at all other times.
advisable to sample this output pin using the RxClk output signal.
It is
11
12
27
RRING
RTIP
I
I
I
Receive Ring Input
This input pin along with RTIP is used to receive the bipolar line signal from the
Remote DS3/E3/STS-1 Terminal.
Receive TIP Input
This input pin along with RRNG is used to receive the bipolar line signal from
the Remote DS3/E3/STS-1 Terminal.
RxMON/
SDO
Receive Monitoring Mode or Serial Data Output:
In Hardware mode, when this pin is tied “High” XRT75VL00D configures into
monitoring channel. In the monitoring mode, the Receiver is capable of monitor-
ing the signals with 20 dB flat loss plus 6 dB cable attenuation. This allows to
monitor very weak signal before declaring LOS.
In HOST Mode, XRT75VL00D can be configured to be a monitoring channel by
setting the bits in the receive control register.
NOTE: If the XRT75VL00D is configured in HOST mode, this pin functions as
SDO pin (please refer to the pin description for the Microprocessor
Interface).
7
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
CLOCK INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
44
ExClk/12M
I
Clock Input (34.368 MHz or 44.736 MHz or 51.84 MHz ± 20 ppm):
Based on the mode selected, provide the appropriate reference clock signal.
If the XRT75VL00D is configured for Single Frequency Mode with the SFM_EN
tied “High”, then provide a 12.288 MHz ± 20 ppm clock and depending on the
mode, the correct frequency is generated internally by the clock synthesizer..
9
SFM_EN
I
Single Frequency Enable:
Tie this pin “High” to select the single frequency mode. When enabled, a single
frequency clock, 12.288 MHz is input through the ExClk input pin and the inter-
nal clock synthesizer generates the appropriate clock frequency.
NOTE: This pin is internally pulled down.
39
CLK_OUT
O
Clock out put:
When the Single Frequency Mode is selected, a low jitter clock will be out put.
The frequency of this clock depends on whether the XRT75VL00D is configured
in E3 or DS3 or STS-1 mode.
8
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
OPERATING MODE SELECT
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
21
HOST/(HW)
I
HOST/Hardware Mode Select:
Tie this pin “High” to configure the XRT75VL00D in HOST mode. Tie this “Low”
to configure in Hardware mode.
When the XRT75VL00D is configured in HOST mode, the states of many dis-
crete input pins are ignored.
NOTE: This pin is internally pulled up.
20
E3
I
E3 Mode Select Input
A "High" on this pin configures to operate in the E3 mode.
A "Low" on this pin configures to operate in either STS-1 or DS3 mode depend-
ing on the setting on pin 19.
NOTES:
1. This pin is internally pulled down
2. This pin is ignored and may be tied to GND if the XRT75VL00D is
configured to operate in HOST mode.
19
STS-1/DS3
I
STS-1/DS3 Select Input
A “High” on this pin configures to operate in STS-1 mode.
A “Low” on this pin configures to operate in DS3 mode.
This pin is ignored if the E3 pin is set to “High”.
NOTES:
1. This pin is internally pulled down
2. This pin is ignored and may be tied to GND if the XRT75VL00D is
configured to operate in HOST mode.
22
SR/DR
I
Single-Rail/Dual-Rail Select:
Setting this “High” configures both the Transmitter and Receiver to operate in
Single-rail mode and also enables the B3ZS/HDB3 Encoder and Decoder. In
Single-rail mode, Transmit input at TNData should be grounded.
Setting this “Low” configures both the Transmitter and Receiver to operate in
Dual-rail mode and disables the B3ZS/HDB3 Encoder and Decoder.
NOTE: This pin is internally pulled down.
CONTROL AND ALARM INTERFACE
42
41
40
MRING
I
Monitor Ring Input
The bipolar line output signal from TRING is connected to this pin via a 270 Ω
resistor to check for line driver failure.
NOTE: This pin is internally pulled down.
MTIP
I
Monitor Tip Input
The bipolar line output signal from TTIP is connected to this pin via a 270-ohm
resistor to check for line driver failure.
NOTE: This pin is internally pulled down.
DMO
O
Drive Monitor Output
If MTIP and MRING has no transition pulse for 128 ± 32 TxClk cycles, DMO
goes “High” to indictae the driver failure. DMO output stays “High” until the next
AMI signal is detected.
9
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
CONTROL AND ALARM INTERFACE
30
RLOS
O
Receive Loss of Signal Output Indicator
This output pin toggles "High" if Receiver has detected a Loss of Signal Condi-
tion in the incoming line signal.
The criteria for declaring/clearing an LOS Condition depends upon whether it is
operating in the E3 or STS-1/DS3 Mode and is described in Section 2.04.
29
RLOL
O
Receive Loss of Lock Output Indicator:
This output pin toggles "High" if the XRT75VL00D has detected a Loss of Lock
Condition. LOL (Loss of Lock) condition is declared if the recovered clock fre-
quency deviates from the Reference Clock frequency (available at ExClk input
pin) by more than 0.5%.
33
15
Rext
****
I
External Bias control Resistor of 3.3 KΩ ±1%.
Should be connected to RefAGND via 3.3 KΩ resistor.
TEST
Test Mode:
Connect this pin “High” to configure the XRT75VL00D in test mode.
NOTE: This pin is internally pulled Down.
16
ICT
I
In-Circuit Test Input:
Setting this pin "Low" causes all digital and analog outputs to go into a high-
impedance state to allow for in-circuit testing. For normal operation, set this pin
"High".
NOTE: This pin is internally pulled “High".
2
TAOS
I
Transmit All Ones Select
A “High" on this pin causes the Transmitter Section to generate and transmit a
continuous AMI all “1’s” pattern onto the line. The frequency of this “1’s” pattern
is determined by TxClk.
NOTES:
1. This input pin is ignored if the XRT75VL00D is operating in the HOST
Mode and should be tied to GND.
2. Analog Loopback and Remote Loopback have priority over request.
3. This pin is internally pulled down.
28
LOSMUT/
INT
I/O
MUTE-upon-LOS Enable Input or Interrupt Ouput:
In Hardware Mode, setting this pin “High” configures the XRT75VL00D to Mute
the recovered data on the RPOS and RNEG whenever an LOS condition is
declared. RPOS and RNEG outputs are pulled “Low”.
NOTE: If the XRT75VL00D is configured in HOST mode, this pin functions as
INT pin (please refer to the pin description for the Microprocessor
Interface).
10
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
CONTROL AND ALARM INTERFACE
17
LLB
I
Local Loop-back
This input pin along with RLB configures different Loop-Back modes.
RLB
LLB
Loopback Mode
Normal Operation
Analog Local
Remote
0
0
1
1
0
1
0
1
Digital
NOTE: This input pin is ignored and may be connected to GND if the
XRT75VL00D is operating in the HOST Mode.
18
RLB
I
Remote Loop-back
This input pin along with LLB configures different Loop-Back modes.
NOTE: This input pin is ignored and should be connected to GND if the
XRT75VL00D is operating in the HOST Mode.
MICROPROCESSOR SERIAL INTERFACE - (HOST MODE)
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
24
CS/RxClkINV
I
Microprocessor Serial Interface - Chip Select
Tie this “Low” to enable the communication with Serial Microprocessor Inter-
face.
NOTE: If the XRT75VL00D is configured in Hardware Mode,this pin functions as
RxClkINV.
26
25
SCLK/TxClkINV
I
I
Serial Interface Clock Input
The data on the SDI pin is sampled on the rising edge of this signal. Addition-
ally, during Read operations the Microprocessor Serial Interface updates the
SDO output on the falling edge of this signal.
NOTE: If the XRT75VL00D is configured in Hardware Mode, this pin functions
as TxClkINV.
SDI/RxON
Serial Data Input:
Data is serially input through this pin.
The input data is sampled on the rising edge of the SCLK pin (pin 26).
NOTES:
1. This pin is internally pulled down
2. If the XRT75VL00D is configured in Hardware Mode, this pin functions
as RxON.
27
SDO/RxMON
O
Serial Data Output:
This pin serially outputs the contents of the specified Command Register during
Read Operations. The data is updated on the falling edge of the SCLK and this
pin is tri-stated upon completion of data transfer.
NOTE: If the XRT75VL00D is configured in Hardware Mode, this pin functions
as RxMON.
11
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
MICROPROCESSOR SERIAL INTERFACE - (HOST MODE)
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
14
RESET
I
Register Reset:
Setting this input pin "Low" causes the XRT75VL00D to reset the contents of
the Command Registers to their default settings and default operating configu-
ration
NOTE: This pin is internally pulled up.
28
INT/LOSMUT
I/O
INTERRUPT Output:
This pin functions as Interrupt Output for Serial Interface. A transition to “Low”
indicates that an interrupt has been generated by the Serial Interface. The inter-
rupt function can be disabled by setting the interrupt enable bit to “0” in the
Channel Control Register.
NOTE: If the XRT75VL00D is in Hardware mode, this pin functions as LOSMUT.
12
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
JITTER ATTENUATOR INTERFACE
PIN #
SIGNAL NAME
TYPE
DESCRIPTION
6
JA0
I
Disable Jitter Attenuator/FIFO Size Select::
In Hardware Mode, this pin along with JA1 pin provides the following functions
in the table below.
JA0
0
JA1
0
Operation
16 bit FIFO
32 bit FIFO
128 bit FIFO
0
1
1
0
Disable Jitter
Attenuator
1
1
NOTE: This pin is internally pulled down.
7
8
JA1
I
I
Disable Jitter Attenuator/FIFO Size Select:
In Hardware Mode, this pin along with JA0 pin provides the functions in the
table above.
NOTE: This pin is internally pulled down.
JA Tx/Rx
Jitter Attenuator Select:
In Hardware Mode setting this pin “High” selects the Jitter Attenuator in the
Transmit path and setting “Low” selects in Receive path.
NOTE: This pin is internally pulled down.
13
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
ANALOG POWER AND GROUND
PIN #
3
SIGNAL NAME
TxAVDD
TYPE
****
****
****
****
****
****
****
****
DESCRIPTION
Transmitter Analog VDD 3.3 V ± 5%
Receiver Analog VDD 3.3 V ± 5%
Reference Analog VDD 3.3 V ± 5%
Transmitter Analog GND
10
32
5
RxAVDD
RefAVDD
TxAGND
RxAGND
RefAGND
JaAVDD
13
34
45
43
Receiver Analog GND
Reference Analog GND
Jitter Attenuator Analog VDD 3.3 V ± 5%
Jitter Attenuator Analog GND
JaAGND
DIGITAL POWER AND GROUND
PIN #
31
SIGNAL NAME
DVDD
TYPE
****
****
****
****
DESCRIPTION
VDD 3.3 V ± 5% Receiver Digital
35
DGND
GND
52
DVDD
VDD 3.3 V ± 5% Transmitter Digital
GND
49
DGND
14
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
1.0 ELECTRICAL CHARACTERISTICS
TABLE 1: ABSOLUTE MAXIMUM RATINGS
SYMBOL
VDD
PARAMETER
Supply Voltage
MIN
-0.5
-0.5
MAX
6.0
UNITS
V
COMMENTS
Note 1
Note 1
VIN
Input Voltage at any Pin
Input current at any pin
Storage Temperature
Ambient Operating Temperature
Thermal Resistance
5+0.5
100
150
85
V
IIN
mA
Note 1
0C
0C
STEMP
ATEMP
ThetaJA
ThetaJC
MLEVL
-65
-40
Note 1
linear airflow 0 ft./min
linear air flow 0ft/min
0C/W
20
0C/W
level
6
Exposure to Moisture
ESD Rating
5
EIA/JEDEC
JESD22-A112-A
ESD
2000
V
Note 2
NOTES:
1. Exposure to or operating near the Min or Max values for extended period may cause permanent failure and impair
reliability of the device.
2. ESD testing method is per MIL-STD-883D,M-3015.7
TABLE 2: DC ELECTRICAL CHARACTERISTICS:
SYMBOL
DVDD
AVDD
ICC
PARAMETER
MIN.
3.135
3.135
65
TYP.
3.3
MAX.
3.465
3.465
175
UNITS
V
Digital Supply Voltage
Analog Supply Voltage
3.3
V
Supply current (Measured while transmitting and receiving all
120
mA
1’s)
PDD
VIL
VIH
VOL
VOH
IL
Power Dissipation
210
2.0
2.4
385
610
0.8
5.0
0.4
mW
V
Input Low Voltage
Input High Voltage
V
Output Low Voltage, IOUT = - 4mA
Output High Voltage, IOUT = 4 mA
V
V
Input Leakage Current1
Input Capacitance
±10
10
µA
pF
pF
CI
CL
Load Capacitance
10
NOTES:
1. Not applicable for pins with pull-up or pull-down resistors.
2. The Digital inputs and outputs are TTL 5V compliant.
15
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
2.0 TIMING CHARACTERISTICS
FIGURE 3. TYPICAL INTERFACE BETWEEN TERMINAL EQUIPMENT AND THE XRT75VL00D (DUAL-RAIL DATA)
TxPOS
TxNEG
TPData
TNData
Transmit
Logic
Block
Terminal
Equipment
(E3/DS3 or STS-1
Framer)
TxLineClk TxClk
Exar E3/DS3/STS-1 LIU
FIGURE 4. TRANSMITTER TERMINAL INPUT TIMING
tRTX
tFTX
TxClk
tTSU
tTHO
TPData or
TNData
tTDY
TTIP or
TRing
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
TxClk
Duty Cycle
E3
DS3
STS-1
30
50
70
%
34.368
44.736
51.84
MHz
MHz
MHz
tRTX
tFTX
tTSU
tTHO
tTDY
TxClk Rise Time (10% to 90%)
TxClk Fall Time (10% to 90%)
4
4
ns
ns
ns
ns
ns
TPData/TNData to TxClk falling set up time
TPData/TNData to TxClk falling hold time
3
3
TTIP/TRing to TxClk rising propagation delay time
8
16
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
FIGURE 5. RECEIVER DATA OUTPUT AND CODE VIOLATION TIMING
tRRX
tFRX
RClk
LCV
tLCVO
tCO
RPOS or
RNEG
SYMBOL
PARAMETER
MIN
TYP
MAX
UNITS
RxClk
Duty Cycle
E3
DS3
STS-1
45
50
55
%
34.368
44.736
51.84
MHz
MHz
MHz
tRRX
tFRX
tCO
RxClk rise time (10% o 90%)
RxClk falling time (10% to 90%)
2
2
4
4
4
ns
ns
ns
ns
RxClk to RPOS/RNEG delay time
RxClk to rising edge of LCV output delay
tLCVO
2.5
FIGURE 6. TRANSMIT PULSE AMPLITUDE TEST CIRCUIT FOR E3, DS3 AND STS-1 RATES
R1
TTIP
TxPOS
TPData
31.6Ω +1%
R3
TxNEG
TNData
75Ω
R2
TxLineClk
TxClk
TRing
1:1
31.6Ω + 1%
Rext
RefAGND
17
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
3.0 LINE SIDE CHARACTERISTICS:
3.1 E3 line side parameters:
The XRT75VL00D meets the pulse shape specified in ITU-T G.703 for 34.368 Mbits/s operation at the
secondary of the transformer. The pulse mask as specified in ITU-T G.703 for 34.368 Mbits/s is shown in
Figure 7.
FIGURE 7. PULSE MASK FOR E3 (34.368 MBITS/S) INTERFACE AS PER ITU-T G.703
17 ns
(14.55 + 2.45)
8.65 ns
V = 100%
Nominal Pulse
50%
14.55ns
12.1ns
(14.55 - 2.45)
10%
0%
10%
20%
TABLE 3: E3 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD = 3.3 V ± 5%)
PARAMETER
MIN
TYP
MAX
UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude
0.90
1.00
1.10
Vpk
(Measured at secondary of the transformer)
Transmit Output Pulse Amplitude Ratio
Transmit Output Pulse Width
Intrinsic Jitter
0.95
12.5
1.00
14.55
0.02
1.05
16.5
0.05
ns
UIPP
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable)
1200
-15
feet
dB
Interference Margin
-20
Jitter Tolerance @ Jitter Frequency 800KHz
0.15
0.28
UIPP
Signal level to Declare Loss of Signal
Signal Level to Clear Loss of Signal
-35
dB
dB
UI
-15
10
10
Occurence of LOS to LOS Declaration Time
Termination of LOS to LOS Clearance Time
255
255
UI
18
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
FIGURE 8. BELLCORE GR-253 CORE TRANSMIT OUTPUT PULSE TEMPLATE FOR SONET STS-1 APPLICATIONS
STS-1 Pulse Template
1.2
1
0.8
0.6
Lower Curve
Upper Curve
0.4
0.2
0
-0.2
Time, in UI
TABLE 4: STS-1 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS
NORMALIZED AMPLITUDE
LOWER CURVE
- 0.03
-0.85 < T < -0.38
-0.38 < T < 0.36
π
2
T
0.18
0.5 1 + sin-- 1 + --------- – 0.03
- 0.03
0.36 < T < 1.4
UPPER CURVE
0.03
-0.85 < T < -0.68
-0.68 < T < 0.26
π
2
T
0.34
0.5 1 + sin-- 1 + --------- + 0.03
-2.4[T-0.26]
0.26 < T < 1.4
0.1 + 0.61 x e
19
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE 5: STS-1 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD =3.3V ± 5%)
PARAMETER
MIN
TYP
MAX
UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude
0.65
0.90
0.75
1.00
0.90
1.10
Vpk
Vpk
ns
(measured with TxLEV = 0)
Transmit Output Pulse Amplitude
(measured with TxLEV = 1)
Transmit Output Pulse Width
Transmit Output Pulse Amplitude Ratio
Intrinsic Jitter
8.6
9.65
1.00
0.02
10.6
1.10
0.05
0.90
UIpp
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable)
900
1100
0.60
feet
Jitter Tolerance @ Jitter Frequency 400 KHz
0.15
UIpp
Signal Level to Declare Loss of Signal
Signal Level to Clear Loss of Signal
Refer to Table 10
Refer to Table 10
FIGURE 9. TRANSMIT OUPUT PULSE TEMPLATE FOR DS3 AS PER BELLCORE GR-499
DS3 Pulse Template
1.2
1
0.8
0.6
0.4
0.2
0
Lower Curve
Upper Curve
-0.2
Time, in UI
20
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
TABLE 6: DS3 PULSE MASK EQUATIONS
TIME IN UNIT INTERVALS
NORMALIZED AMPLITUDE
LOWER CURVE
- 0.03
-0.85 < T < -0.36
-0.36 < T < 0.36
π
2
T
0.18
0.5 1 + sin-- 1 + --------- – 0.03
- 0.03
0.36 < T < 1.4
UPPER CURVE
0.03
-0.85 < T < -0.68
-0.68 < T < 0.36
π
2
T
0.34
0.5 1 + sin-- 1 + --------- + 0.03
-1.84[T-0.36]
0.36 < T < 1.4
0.08 + 0.407 x e
TABLE 7: DS3 TRANSMITTER AND RECEIVER LINE SIDE SPECIFICATIONS (TA = 250C AND VDD = 3.3V ± 5%)
PARAMETER
MIN
TYP
MAX
UNITS
TRANSMITTER LINE SIDE OUTPUT CHARACTERISTICS
Transmit Output Pulse Amplitude
0.65
0.90
0.75
1.00
0.85
1.10
Vpk
Vpk
ns
(measured with TxLEV = 0)
Transmit Output Pulse Amplitude
(measured with TxLEV = 1)
Transmit Output Pulse Width
Transmit Output Pulse Amplitude Ratio
Intrinsic Jitter
10.10
0.90
11.18
1.00
0.02
12.28
1.10
0.05
UIpp
RECEIVER LINE SIDE INPUT CHARACTERISTICS
Receiver Sensitivity (length of cable)
900
1100
0.60
feet
Jitter Tolerance @ 400 KHz (Cat II)
0.15
UIpp
Signal Level to Declare Loss of Signal
Signal Level to Clear Loss of Signal
Refer to Table 10
Refer to Table 10
21
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
FIGURE 10. MICROPROCESSOR SERIAL INTERFACE STRUCTURE
CS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SClk
SDI
R/W A0 A1 A2 A3 A4 A5
0
D0 D1 D2 D3 D4 D5 D6 D7
High Z
High Z
D0 D1 D2 D3 D4 D5 D6 D7
SDO
FIGURE 11. TIMING DIAGRAM FOR THE MICROPROCESSOR SERIAL INTERFACE
t
28
t
CS
21
t
26
t
t
27
SCLK
SDI
24
t
25
t
t
23
22
A0
R/W
A1
CS
SCLK
t
t
t
t
30
29
32
31
D0
D2
D7
SDO
SDI
D1
Hi-Z
Hi-Z
22
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
TABLE 8: MICROPROCESSOR SERIAL INTERFACE TIMINGS ( TA = 250C, VDD=3.3V± 5% AND LOAD = 10PF)
SYMBOL
PARAMETER
MIN.
TYP.
MAX
UNITS
t21
CS Low to Rising Edge of SClk
5
ns
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
SDI to Rising Edge of SClk
SDI to Rising Edge of SClk Hold Time
SClk "Low" Time
5
5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25
25
50
SClk "High" Time
SClk Period
Falling Edge of SClk to rising edge of CS
CS "Inactive" Time
0
50
Falling Edge of SClk to SDO Valid Time
Falling Edge of SClk to SDO Invalid Time
Rising edge of CS to High Z
Rise/Fall time of SDO Output
20
10
10
5
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REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
4.0 THE TRANSMITTER SECTION:
The Transmitter Section accepts TTL/CMOS level signals from the Terminal Equipment in the selectable data
formats.
• In Single-Rail or un-encoded Non-Return-to-Zero (NRZ) input data via TPData pin while the TNData pin
must be grounded. The NRZ or Single-Rail mode is selected when the SR/DR input pin is “High” (in
Hardware Mode) or bit 0 of the control register is “1” (in Host Mode). Figure 12 illustrates the Single-Rail or
NRZ format.
FIGURE 12. SINGLE-RAIL OR NRZ DATA FORMAT (ENCODER AND DECODER ARE ENABLED)
Data
1
1
0
TPData
TxClk
• In Dual-Rail mode, data is input via TPData and TNData pins. TPData contains positive data and TNData
contains negative data. The SR/DR input pin = “Low” (in Hardware Mode) or bit 0 of the control register = “0”
(in Host Mode) enables the Dual-Rail mode. Figure 13 illustrates the Dual-Rail data format.
FIGURE 13. DUAL-RAIL DATA FORMAT (ENCODER AND DECODER ARE DISABLED)
Data
1
1
0
TPData
TNData
TxClk
• Convert the CMOS level B3ZS or HDB3 encoded data into pulses with shapes that are compliant with the
various industry standard pulse template requirements. Figure 7, Figure 8 and Figure 9 illustrate the pulse
template requirements.
• Encode the un-encoded NRZ data into either B3ZS format (for DS3 or STS-1) or HDB3 format (for E3) and
convert to pulses with shapes and width that are compliant with industry standard pulse template
requirements. Figure 7,Figure 8 and Figure 9 illustrate the pulse template requirements.
4.1
TRANSMIT CLOCK:
The Transmit Clock applied via TxClk pin, for the selected data rate (for E3 = 34.368 MHz, DS3 = 44.736 MHz
or STS-1 = 51.84 MHz), is duty cycle corrected by the internal PLL circuit to provide a 50% duty cycle clock to
the pulse shaping circuit. This allows a 30% to 70% duty cycle Transmit Clock be supplied and thus eliminates
the need to use an expensive oscillator.
4.2
B3ZS/HDB3 ENCODER:
When the Single-Rail (NRZ) data format is selected, the Encoder Block encodes the data into either B3ZS
format (for either DS3 or STS-1) or HDB3 format (for E3).
4.2.1
B3ZS Encoding:
24
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
An example of B3ZS encoding is shown in Figure 14. If the encoder detects an occurrence of three
consecutive zeros in the data stream, it is replaced with either B0V or 00V, where ‘B’ refers to Bipolar pulse
that is compliant with the Alternating polarity requirement of the AMI (Alternate Mark Inversion) line code and
‘V’ refers to a Bipolar Violation (e.g., a bipolar pulse that violates the AMI line code). The substitution of B0V or
00V is made so that an odd number of bipolar pulses exist between any two consecutive violation (V) pulses.
This avoids the introduction of DC component into the line signal.
FIGURE 14. B3ZS ENCODING FORMAT
TClk
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
TPDATA
0
0
0
0
0
0
1
1
1
V
0
0
B
V
Line
Signal
B
V
V
4.2.2
HDB3 Encoding:
An example of the HDB3 encoding is shown in Figure 15.If the HDB3 encoder detects an occurrence of four
consecutive zeros in the data stream, then the four zeros are substituted with either 000V or B00V pattern. The
substitution code is made in such a way that an odd number of bipolar (B) pulses exist between any
consecutive V pulses. This avoids the introduction of DC component into the analog signal.
FIGURE 15. HDB3 ENCODING FORMAT
TClk
1
1
0
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
TPDATA
0
0
0
0
0
0
0
1
1
B
V
1
0
0
V
Line
Signal
V
NOTES:
1. When Dual-Rail data format is selected, the B3ZS/HDB3 Encoder is automatically disabled.
2. In Dual-Rail format, the Bipolar Violations in the incoming data stream is converted to valid data pulses.
3. Encoder and Decoder is enabled only in Single-Rail mode.
4.3
TRANSMIT PULSE SHAPER:
The Transmit Pulse Shaper converts the B3ZS encoded digital pulses into a single analog Alternate Mark
Inversion (AMI) pulse that meet the industry standard mask template requirements for STS-1 and DS3. See
Figure 8 and Figure 9.
25
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
For E3 mode, the pulse shaper converts the HDB3 encoded pulses into a single full amplitude square shaped
pulse with very little slope. This is illustrated in Figure 7.
The Pulse Shaper Block also consists of a Transmit Build Out Circuit, which can either be disabled or enabled
by setting the TxLEV input pin “High” or “Low” (in Hardware Mode) or setting the TxLEV bit to “1” or “0” in the
control register (in Host Mode).
For DS3/STS-1 rates, the Transmit Build Out Circuit is used to shape the transmit waveform that ensures that
transmit pulse template requirements are met at the Cross-Connect system. The distance between the
transmitter output and the Cross-Connect system can be between 0 to 450 feet.
For E3 rate, since the output pulse template is measured at the secondary of the transformer and since there is
no Cross-Connect system pulse template requirements, the Transmit Build Out Circuit is always disabled.
4.3.1
Guidelines for using Transmit Build Out Circuit:
If the distance between the transmitter and the DSX3 or STSX-1, Cross-Connect system, is less than 225 feet,
enable the Transmit Build Out Circuit by setting the TxLEV input pin “Low” (in Hardware Mode) or setting the
TxLEV control bit to “0” (in Host Mode).
If the distance between the transmitter and the DSX3 or STSX-1 is greater than 225 feet, disable the Transmit
Build Out Circuit.
4.3.2
Interfacing to the line:
The differential line driver increases the transmit waveform to appropriate level and drives into the 75Ω load as
shown in Figure 6.
4.4
Transmit Drive Monitor:
This feature is used for monitoring the transmit line for occurrence of fault conditions such as short circuit on
the line or defective line driver.The device can also be configured for internal tranmit driver monitoring.
To monitor the transmitter output of another chip, connect MTIP pin to the TTIP line via a 270 Ω resistor and
MRing pins to TRing line via 270 Ω resistor as shown in Figure 16
In order to configure the device for internal transmit driver monitoring, set the TxMON bit to “1” in the transmit
control register.
FIGURE 16. TRANSMIT DRIVER MONITOR SET-UP.
R 1
T T IP
3 1 .6 Ω + 1 %
R 3
7 5 Ω
T x P O S
T x N E G
T x L in e C lk
T P D a ta
T N D a ta
T x C lk
1 :1
R 2
T R in g
M T IP
3 1 .6 Ω
+ 1 %
R e x t
R e fA G N D
M R in g
X R T 7 5 V L 0 0
T x P O S
T x N E G
T x L in e C lk
T P D a ta
T N D a ta
T x C lk
M T IP
R 4 2 7 0 Ω
R 5 2 7 0 Ω
M R in g
R 1
1 :1
T T IP
3 1 .6 Ω + 1 %
R 3
7 5 Ω
R 2
R e x t
T R in g
3 1 .6 Ω
+ 1 %
R e fA G N D
26
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
When the MTIP and MRing are connected to the TTIP and TRing lines, the drive monitor circuit monitors the
line for transitions. The DMO (Drive Monitor Output) will be asserted “Low” as long as the transitions on the line
are detected via MTIP and MRing.
If no transitions on the line are detected for 128 ± 32 TxClk periods, the DMO output toggles “High” and when
the transitions are detected again, DMO toggles “Low”.
NOTE: The Drive Monitor Circuit is only for diagnostic purposes and does not have to be used to operate the transmitter.
4.5
Transmitter Section On/Off:
The transmitter section can be turned on or off. To turn on the transmitter in the Hardware mode, pull TxON pin
“High”. In the Host mode, write a “1” to the TxON control bit AND pull the TxON pin “High” to turn on the
transmitter.
When the transmitter is turned off, the TTIP and TRing are tri-stated.
NOTES:
1. This feature provides support for Redundancy.
2. If the XRT75VL00D is configured in Host mode, to permit a system designed for redundancy to quickly shut-off
the defective line card and turn on the back-up line card, writing a “1” to the TxON control bit transfers the control
to TxON pin.
5.0 THE RECEIVER SECTION:
This section describes the detailed operation of the various blocks in the receiver. The receiver recovers the
TTL/CMOS level data from the incoming bipolar B3ZS or HDB3 encoded input pulses.
5.1
AGC/Equalizer:
The Adaptive Gain Control circuit amplifies the incoming analog signal and compensates for the various flat
losses and also for the loss at one-half symbol rate. The AGC has a dynamic range of 30 dB.
The Equalizer restores the integrity of the signal and compensates for the frequency dependent attenuation of
up to 900 feet of coaxial cable (1300 feet for E3). The Equalizer also boosts the high frequency content of the
signal to reduce the Inter-Symbol Interference (ISI) so that, the slicer slices the signal at 50% of peak voltage to
generate Positive and Negative data.
The Equalizer can either be “IN” or “OUT” by setting the REQEN pin “High” or “Low” (in Hardware Mode) or
setting the REQEN control bit to “1” or “0” (in Host Mode).
RECOMMENDATIONS FOR EQUALIZER SETTINGS:
The Equalizer has two gain settings to provide optimum equalization. In the case of normally shaped DS3/
STS-1 pulses (pulses that meet the template requirements) that has been driven through 0 to 900 feet of cable,
the Equalizer can be left “IN” by setting the REQEN pin to “High” (in Hardware Mode) or setting the REQEN
control bit to “1” (in Host Mode).
However, for square-shaped pulses such as E3 or for DS3/STS-1 high pulses (that does not meet the pulse
template requirements), it is recommended that the Equalizer be left “OUT” for cable length less than 300 feet
by setting the REQEN pin “Low” (in Hardware Mode) or by setting the REQEN control bit to “0” (in Host
Mode).This would help to prevent over-equalization of the signal and thus optimize the performance in terms of
better jitter transfer characteristics.
NOTE: The results of extensive testing indicates that even when the Equalizer was left “IN” (REQEN = “HIGH”), regardless
of the cable length, the integrity of the E3 signal was restored properly over 0 to 12 dB cable loss at Industrial
Temperature.
The Equalizer also contain an additional 20 dB gain stage to provide the line monitoring capability of the
resistively attenuated signals which may have 20dB flat loss. This capability can be turned on by writing a “1” to
the RxMON bits in the control register or by setting the RxMON pin (pin 27) “High”.
5.1.1
Interference Tolerance:
For E3 mode, ITU-T G.703 Recommendation specifies that the receiver be able to recover error-free clock and
data in the presence of a sinusoidal interfering tone signal. For DS3 and STS-1 modes, the same
27
XRT75VL00D
REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
recommendation is being used. Figure 17 shows the configuration to test the interference margin for DS3/
STS1. Figure 18 shows the set up for E3.
FIGURE 17. INTERFERENCE MARGIN TEST SET UP FOR DS3/STS-1
ATTENUATOR
N
SINE WAVE
GENERATOR
DUT
XRT75VL00D
DS3 = 22.368 MHz
STS-1 = 25.92 MHz
Cable Simulator
Test Equipment
PATTERN
GENERATOR
223 - 1 PRBS
S
FIGURE 18. INTERFERENCE MARGIN TEST SET UP FOR E3.
ATTENUATOR 1 ATTENUATOR 2
N
NOISE
GENERATOR
DUT
XRT75VL00D
Cable Simulator
Test Equipment
S
Pattern
Generator
28
XRT75VL00D
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
TABLE 9: INTERFERENCE MARGIN TEST RESULTS
MODE
CABLE LENGTH (ATTENUATION)
INTERFERENCE TOLERANCE
0 dB
-14 dB
-18 dB
-17 dB
-16 dB
-16 dB
-16 dB
-15 dB
-15 dB
E3
12 dB
0 feet
225 feet
450 feet
0 feet
DS3
225 feet
450 feet
STS-1
5.2
Clock and Data Recovery:
The Clock and Data Recovery Circuit extracts the embedded clock, from the sliced digital data stream and
provides the retimed data to the B3ZS (HDB3) decoder.
The Clock Recovery PLL can be in one of the following two modes:
TRAINING MODE:
In the absence of input signals at RTIP and RRing pins, or when the frequency difference between the
recovered line clock signal and the reference clock applied on the ExClk input pin exceed 0.5%, the clock
recovery unit enters into Training Mode and a Loss of Lock condition is declared by toggling RLOL output pin
“High” (in Hardware Mode) or setting the RLOL bit to “1” in the control registers (in Host Mode). Also, the clock
output on the RxClk pin is the same as the reference clock applied on ExClk pin.
DATA/CLOCK RECOVERY MODE:
In the presence of input line signals on the RTIP and RRing input pins and when the frequency difference
between the recovered clock signal and the reference clock signal is less than 0.5%, the clock that is output on
the RxClk out pin is the Recovered Clock signal.
5.3
B3ZS/HDB3 Decoder:
The decoder block takes the output from clock and data recovery block and decodes the B3ZS (for DS3 or
STS-1) or HDB3 (for E3) encoded line signal and detects any coding errors or excessive zeros in the data
stream.
Whenever the input signal violates the B3ZS or HDB3 coding sequence for bipolar violation or contains three
(for B3ZS) or four (for HDB3) or more consecutive zeros, an active “High” pulse is generated on the RLCV
output pins to indicate line code violation.
NOTE: In Single- Rail (NRZ) mode, the decoder is bypassed.
5.4
LOS (Loss of Signal) Detector:
DS3/STS-1 LOS Condition:
5.4.1
A Digital Loss of Signal (DLOS) condition occurs when a string of 175 ± 75 consecutive zeros occur on the line.
When the DLOS condition occurs, the DLOS bit is set to “1” in the status control register. DLOS condition is
cleared when the detected average pulse density is greater than 33% for 175 ± 75 pulses.
Analog Loss of Signal (ALOS) condition occurs when the amplitude of the incoming line signal is below the
threshold as shown in the Table 10.The status of the ALOS condition is reflected in the ALOS status control
register.
RLOS is the logical OR of the DLOS and ALOS states. When the RLOS condition occurs the RLOS output pin
is toggled “High” and the RLOS bit is set to “1” in the status control register.
29
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REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE 10: THE ALOS (ANALOG LOS) DECLARATION AND CLEARANCE THRESHOLDS FOR A GIVEN SETTING OF
REQEN (DS3 AND STS-1 APPLICATIONS)
APPLICATION
DS3
REQEN SETTING
SIGNAL LEVEL TO DECLARE ALOS SIGNAL LEVEL TO CLEAR ALOS
1
<20mV
<25mV
>90mV
1
>115mV
STS-1
DISABLING ALOS/DLOS DETECTOR:
For debugging purposes it is useful to disable the ALOS/DLOS detector. Writing a “1” to the ALOS and DLOS
bits disables the LOS detector on a per channel basis.
5.4.2
E3 LOS Condition:
If the level of incoming line signal drops below the threshold as described in the ITU-T G.775 standard, the
LOS condition is detected. Loss of signal level is defined to be between 15 and 35 dB below the normal level. If
the signal drops below 35 dB for 175 ± 75 consecutive pulse periods, LOS condition is declared. This is
illustrated in Figure 19.
FIGURE 19. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775
0 dB
Maximum Cable Loss for E3
LOS Signal Must be Cleared
-12 dB
-15dB
LOS Signal may be Cleared or Declared
-35dB
LOS Signal Must be Declared
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E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
As defined in ITU-T G.775, an LOS condition is also declared between 10 and 255 UI (or E3 bit periods) after
the actual time the LOS condition has occurred. The LOS condition is cleared within 10 to 255 UI after
restoration of the incoming line signal. Figure 20 shows the LOS declaration and clearance conditions.
FIGURE 20. LOSS OF SIGNAL DEFINITION FOR E3 AS PER ITU-T G.775.
Actual Occurrence
of LOS Condition
Line Signal
is Restored
RTIP/
RRing
Time Range for
LOS Declaration
10 UI
10 UI
255 UI
255 UI
RLOS Output Pin
0 UI
0 UI
G.775
Compliance
Time Range for
LOS Clearance
G.775
Compliance
5.4.3
Muting the Recovered Data with LOS condition:
When the LOS condition is declared, the clock recovery circuit locks into the reference clock applied to the
ExClk pin and output this clock on the RxClk output. The data on the RPOS and RNEG pins can be forced to
zero by pulling the LOSMUT pin “High” (in Hardware Mode) or by setting the LOSMUT bits in the individual
channel control register to “1” (in Host Mode).
NOTE: When the LOS condition is cleared, the recovered data is output on RPOS and RNEG pins.
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E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
6.0 JITTER:
There are three fundamental parameters that describe circuit performance relative to jitter:
• Jitter Tolerance (Receiver)
• Jitter Transfer (Receiver/Transmitter)
• Jitter Generation
6.1
JITTER TOLERANCE - RECEIVER:
Jitter tolerance is a measure of how well a Clock and Data Recovery unit can successfully recover data in the
presence of various forms of jitter. It is characterized by the amount of jitter required to produce a specified bit
error rate. The tolerance depends on the frequency content of the jitter. Jitter Tolerance is measured as the
jitter amplitude over a jitter spectrum for which the clock and data recovery unit achieves a specified bit error
rate (BER). To measure the jitter tolerance as shown in Figure 21, jitter is introduced by the sinusoidal
modulation of the serial data bit sequence.
FIGURE 21. JITTER TOLERANCE MEASUREMENTS
Data
Error
Pattern
DUT
Error
Pattern
DUT
Detector
Generator
XRT75VL00D
Detector
Generator
XRT75VL00D
Clock
Modulation
Freq.
FREQ
FREQ
Synthesizer
Synthesizer
Input jitter tolerance requirements are specified in terms of compliance with jitter mask which is represented as
a combination of points.Each point corresponds to a minimum amplitude of sinusoidal jitter at a given jitter
frequency.
6.1.1
DS3/STS-1 Jitter Tolerance Requirements:
Bellcore GR-499 CORE, Issue 1, December 1995 specifies the minimum requirement of jitter tolerance for
Category I and Category II. The jitter tolerance requirement for Category II is the most stringent. Figure 22
shows the jitter tolerance curve as per GR-499 specification along with the measured performance for the
device.
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E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
REV. 1.0.3
FIGURE 22. INPUT JITTER TOLERANCE FOR DS3/STS-1
64
GR-253 STS-1
41
15
GR-499 Cat II
GR-499 Cat I
XRT75VL00D
10
5
1.5
0.3
0.15
0.1
0.01
2
20
0.03
JITTER FREQUENCY (kHz)
0.3
100
6.1.2
E3 Jitter Tolerance Requirements:
ITU-T G.823 standard specifies that the clock and data recovery unit must be able to accommodate and
tolerate jitter up to certain specified limits. Figure 23 shows the tolerance curve and the actual measured data
for the device.
FIGURE 23. INPUT JITTER TOLERANCE FOR E3
ITU-T G.823
XRT75VL00D
64
10
1.5
0.3
10
0.1
1
800
JITTER FREQUENCY (kHz)
The Figure 11 below shows the jitter amplitude versus the modulation frequency for various standards.
33
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REV. 1.0.3
E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
TABLE 11: JITTER AMPLITUDE VERSUS MODULATION FREQUENCY (JITTER TOLERANCE)
INPUT JITTER AMPLITUDE (UI P-P
)
MODULATION FREQUENCY
BIT RATE
(KB/S)
STANDARD
A1
1.5
5
A2
0.15
0.1
A3
F1(HZ)
100
F2(HZ)
F3(KHZ)
10
F4(KHZ)
F5(KHZ)
34368
44736
ITU-T G.823
-
-
1000
2.3k
800
300
-
-
GR-499
10
60
CORE Cat I
44736
51840
GR-499
CORE Cat II
10
15
0.3
1.5
-
10
10
669
30
22.3
300
300
2
-
GR-253
0.15
20
CORE Cat II
6.2
JITTER TRANSFER - RECEIVER/TRANSMITTER:
Jitter Transfer function is defined as the ratio of jitter on the output relative to the jitter applied on the input
versus frequency.
There are two distinct characteristics in jitter transfer: jitter gain (jitter peaking) defined as the highest ratio
above 0 dB; and jitter transfer bandwidth.The overall jitter transfer bandwidth is controller by a low bandwidth
loop,which is part of the XRT75VL00D.
The jitter transfer function is a ratio between the jitter output and jitter input for a component, or system often
expressed in dB. A negative dB jitter transfer indicates the element removed jitter. A positive dB jitter transfer
indicates the element added jitter.A zero dB jitter transfer indicates the element had no effect on jitter.
Table 12 shows the jitter transfer characteristics and/or jitter attenuation specifications for various data rates:
TABLE 12: JITTER TRANSFER SPECIFICATIONS
E3
DS3
STS-1
ETSI TBR-24
GR-499 CORE section 7.3.2
Category I and Category II
GR-253 CORE section 5.6.2.1
The XRT75VL00D meets the above Jitter Specifications.
6.3
JITTER GENERATION:
Jitter Generation is defined as the process whereby jitter appears at the output port of the digital equipment in
the absence of applied input jitter. Jitter Generation is measured by sending jitter free data to the clock and
data recovery circuit and measuring the amount of jitter on the output clock or the re-timed data. Since this is
essentially a noise measurement, it requires a definition of bandwidth to be meaningful. The bandwidth is set
according to the data rate. In general, the jitter is measured over a band of frequencies.
6.4
Jitter Attenuator:
An advanced crystal-less jitter attenuator is included in the XRT75VL00D. The jitter attenuator uses the internal
reference clock.
In Host mode, by clearing or setting the JATx/Rx bit in the control register selects the jitter attenuator either in
the Receive or Transmit path. In Hardware mode, JATx/Rx pin selects the jitter attenuator in Receive or
Transmit path.
The FIFO is either a 16-bit, 32-bit or 128-bit register. In Host mode, the bits JA0 and JA1can be set to
appropriate combination to select the different FIFO sizes or to disable the jitter attenuator. In Hardware mode,
appropriate setting of the pins JA0 and JA1 selects the different FIFO sizes or disable the jitter attenuator. Data
is clocked into the FIFO with the associated clock signal (TxClk or RxClk) and clocked out of the FIFO with the
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dejittered clock. When the FIFO is within two bits of overflowing or underflowing, the FIFO limit status bit, FL is
set to “1” in the Alarm status register. Reading this bit clears the FIFO and resets the bit into default state.
NOTE: It is recommended to select the 16-bit FIFO for delay-sensitive applications as well as for removing smaller amounts
of jitter.
Table 13 specifies the jitter transfer mask requirements for various data rates:
TABLE 13: JITTER TRANSFER PASS MASKS
RATE
F1
F2
F3
F4
MASK
A1(dB)
A2(dB)
(KBITS)
(HZ)
(HZ)
(HZ)
(KHZ)
G.823
100
300
3K
800K
0.5
-19.5
34368
44736
ETSI-TBR-24
GR-499, Cat I
GR-499, Cat II
GR-253 CORE
10
10
10
10k
56.6k
40
-
-
-
15k
300k
15k
0.1
0.1
0.1
-
-
-
51840
GR-253 CORE
10
40k
-
400k
0.1
-
The jitter attenuator within the XRT75VL00D meets the latest jitter attenuation specifications and/or jitter
transfer characteristics as shown in the Figure 24.
FIGURE 24. JITTER TRANSFER REQUIREMENTS AND JITTER ATTENUATOR PERFORMANCE
A1
A2
F1
F2
F3
F4
JITTER FREQ UENCY (kHz)
7.0 SERIAL HOST INTERFACE:
A flexible serial microprocessor interface is incorporated in the XRT75VL00D. The interface is generic and is
designed to support the common microprocessors/microcontrollers. The XRT75VL00D operates in Host mode
when the HOST/HW pin is tied “High”. The serial interface includes a serial clock (SClk), serial data input
(SDI), serial data output (SDO), chip select (CS) and interrupt output (INT). The serial interface timing is shown
in Figure 11.
The active low interrupt output signal (INT pin) indicates alarm conditions like LOS, DMO and FL to the
processor.
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When the XRT75VL00D is configured in Host mode, the following input pins,TxLEV, TAOS, RLB, LLB, E3,
STS-1/DS3, REQEN, JATx/Rx, JA0 and JA1 are disabled and must be connected to ground.
Table 14 below illustrates the functions of the shared pins in either Host mode or in Hardware mode.
TABLE 14: FUNCTIONS OF SHARED PINS
PIN NUMBER
IN HOST MODE
IN HARDWARE MODE
RxClkINV
TxClkINV
RxON
24
26
25
27
28
CS
SClk
SDI
SDO
INT
RxMON
LOSMUT
NOTE: While configured in Host mode, the TxON input pin will be active if the TxON bit in the control register is set to “1”,
and can be used to turn on and off the transmit output drivers. This permits a system designed for redundancy to
quickly switch out a defective line card and switch-in the backup line card.
TABLE 15: REGISTER MAP AND BIT NAMES
DATA BITS
ADDRESS
(HEX)
PARAMETER
NAME
7
6
5
4
3
2
1
0
0x00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
APS/Redundancy Reserved Reserved Reserved
(read/write)
RxON
Reserved Reserved Reserved
TxON
Interrupt Enable
(read/write)
Reserved
CNT_SATIE PRBSIE
FLIE
FLIS
FL
RLOLIE RLOSIE
RLOLIS RLOSIS
DMOIE
DMOIS
DMO
Interrupt Status
(reset on read)
Reserved
CNT_SATIS PRBSIS
Alarm Status
(read only)
Reserved PRBSLS
Reserved
DLOS
ALOS
RLOL
TAOS
RLOS
Transmit Control
(read/write)
TxMON
INSPRBS Reserved
TxClkINV TxLEV
Receive Control
(read/write)
Reserved
DLOSDIS ALOSDIS RxClkINV LOSMUT RxMON REQEN
Block Control
(read/write)
Reserved
PRBSEN
RLB
LLB
E3
STS1/
DS3
SR/DR
JA0
Jitter Attenuator
(read/write)
Reserved
DFLCK PNTRST
JA1
JATx/Rx
0x08-
0x1F
Reserved
0x20
Interrupt Enable-
Global
Reserved
Reserved
Reserved Reserved INTEN
Reserved Reserved INTST
(read/write)
0x21
Interrupt Status
(read only)
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TABLE 15: REGISTER MAP AND BIT NAMES
DATA BITS
ADDRESS
(HEX)
PARAMETER
NAME
7
6
5
4
3
2
1
0
0x22-
0x2F
Reserved
Reserved
0x30
PRBS Error Count
(MSB)
MSB
MSB
LSB
LSB
0x31
PRBS Error Count
(LSB)
0x32-0x37
0x38
Reserved
PRBS Holding
MSB
LSB
0x39-
0x3D
Reserved
0x3E
Chip_id
Device part number (7:0)
Chip revision number (7:0)
(read only)
0x3F
Chip_version
(read only)
TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
DEFAULT
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
VALUE(BIN)
0x00
R/W
D0
RxON
Bit 4 = RxON, Receiver Turn On. Writing a “1” to the
bit field turns on the Receiver and a “0” turn off the
Receiver.
0
0
D4
TxON
Bit 0 = TxON, Transmitter Turn On. Writing a “1” to
the bit field turn on the Transmitter. Writing a “0” turns
off the transmitter and tri-state the transmitter output
(TTIP/TRing).
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TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
DEFAULT
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
VALUE(BIN)
0x01
R/W
D0
DMOIE
Writing a “1” to this bit field enables the DMO inter-
rupt and triggers an interrupt when the transmitter
driver fails. Writing a “0” disables the interrupt.
0
D1
D2
D3
RLOSIE
RLOLIE
FLIE
Writing a “1” to this bit field enables the RLOS inter-
rupt and triggers an interrupt when the RLOS condi-
tion occurs. Writing a “0” disables the interrupt.
0
0
0
Writing a “1” to this bit field enables the RLOL inter-
rupt and triggers an interrupt when RLOL condition
occurs. Writing a “0” disables the interrupt.
Writing a “1” to this bit field enables the FL interrupt
and triggers an interrupt when the FIFO Limit of the
Jitter Attenuator is within 2 bits of overflow/underflow
condition. Writing a “0” disables the interrupt.
NOTE: This bit field is ignored when the Jitter
Attenuator is disabled.
D4
D5
PRBSIE
Writing a “1” to this bit enables the PRBS bit error
interrupt.
0
0
CNT_SATIE Writing a “1” to this bit enables the PRBS error-
counter saturation interrupt. When the PRBS error
counter reaches 0xFFFF, an interrupt will be gener-
ated.
0x02
Reset
Upon
Read
D0
D1
D2
D3
DMOIS
RLOSIS
RLOLIS
FLIS
This bit is set to “1” every time a DMO status change
has occurred since the last cleared interrupt.This bit
is cleared when read.
0
0
0
0
This bit is set to “1” every time a RLOS status change
has occurred since the last cleared interrupt. This bit
is cleared when read.
This bit is set to “1” every time a RLOL status change
has occurred since the last cleared interrupt. This bit
is cleared when read.
This bit is set to “1” every time a FIFO Limit status
change has occurred since the last cleared interrupt.
This bit is cleared when read.
D4
D5
PRBSIS
This bit is set to “1” when a PRBS bit error is
detected. This bit is cleared when read.
0
0
CNT_SATIS This bit is set to “1” when the PRBS error counter has
saturated (0xFFFF). This bit is cleared when read.
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TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
DEFAULT
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
(HEX)
VALUE(BIN)
0x03
Read
Only
D0
DMO
This bit is set to “1” every time the MTIP/MRing input
pins have not detected any bipolar pulses for 128
consecutive bit periods.
0
D1
D2
D3
RLOS
RLOL
FL
This bit is set to “1” every time the receiver declares
an LOS condition.
0
0
0
This bit is set to “1” every time when the receiver
declares a Loss of Lock condition.
This bit is set to “1” every time the FIFO in the Jitter
Attenuator is within 2 bit of underflow/overflow condi-
tion.
D4
D5
D6
D0
ALOS
DLOS
This bit is set to “1” every time the receiver declares
Analog LOS condition.
0
0
0
0
This bit is set to “1” every time the receiver declares
Digital LOS condition.
PRBSLS
TxLEV
This bit is set to “1” every time the PRBS detects a bit
error.
0x04
R/W
Writing a “1” to this bit disables the Transmit Build-out
circuit and writing a “0” enables the Transmit Build-out
circuit.
NOTE: See section 4.03 for detailed description.
D1
D2
TxClkINV
TAOS
Writing a “1” to this bit configures the transmitter to
sample the data on TPData/TNData input pins on the
rising edge of TxClk.
0
0
Setting this bit to “1” causes a continuous stream of
marks to be sent out at the TTIP and TRing pins.
D3
D4
Reserved
INSPRBS
This Bit Location is Not Used.
Writing a “1” to this bit causes the PRBS generator to
insert a single-bit error onto the transmit PRBS data
stream.
0
0
NOTE: PRBS Generator/Detector must be enabled
for this bit to have any effect.
D5
TxMON
When this bit is set to “1”, the driver monitor is con-
nected to its own transmit channel and monitors the
transmit driver. When a transmit failure is detected,
the DMO output will go high.
When this bit is “0”, MTIP and MRing can be con-
nected to other transmit channel for monitoring.
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TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
(HEX)
DEFAULT
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
VALUE(BIN)
0x05
R/W
D0
REQEN
Setting this bit to “1” enables the Receive Equalizer .
0
NOTE: See section 2.01 for detailed description.
D1
D2
RxMON
Writing a “1” to this bit configures the Receiver into
monitoring mode. In this mode, the Receiver can
monitor a signal at the RTIP/RRing pins that be atten-
uated up to 20dB flat loss.
0
0
LOSMUT
Writing a “1” to this bit causes the RPOS/RNEG out-
puts to be grounded while the LOS condition is
declared.
NOTE: If this bit has ben set, it will remain set evan
after LOS condition is cleared.
D3
RxClkINV
Writing a “1” to this bit configures the Receiver to out-
put RPOS/RNEG data on the falling edge of RxClk.
0
D4
D5
D0
ALOSDIS
DLOSDIS
SR/DR
Writing a “1” to this bit disables the ALOS detector.
Writing a “1” to this bit disables the DLOS detector.
0
0
0
0x06
R/W
Writing a “1” to this bit configures the Receiver and
Transmitter into Single-Rail (NRZ) mode.
D1
STS-1/DS3 Writing a “1” to this bit configures the channel 0 into
STS-1 mode.
0
NOTE: This bit field is ignored if the chip is configured
to operate in E3 mode.
D2
D3
D4
E3
Writing a “1” to this bit configures the chip in E3
mode.
0
0
0
LLB
RLB
Writing a “1” to this bit configures the chip in Local
Loopback mode.
Writing a “1” to this bit configures the chip in Remote
Loopback mode.
RLB
LLB
Loopback Mode
Normal Operation
Analog Local
Remote
0
0
1
1
0
1
0
1
Digital
D5
PRBSEN
Writing a “1” to this bit enables the PRBS generator/
detector.PRBS generator generate and detect either
0
215-1 (DS3 or STS-1) or 223-1 (for E3).
The pattern generated and detected are unframed
pattern.
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TABLE 16: REGISTER MAP DESCRIPTION
ADDRESS
DEFAULT
TYPE
BIT LOCATION
SYMBOL
DESCRIPTION
(HEX)
VALUE(BIN)
0x07
R/W
D0
JA0
This bit along with JA1 bit configures the Jitter Attenu-
ator as shown in the table below.
0
JA0
JA1
Mode
0
0
1
1
0
1
0
1
16 bit FIFO
32 bit FIFO
128 bit FIFO
Disable Jitter
Attenuator
D1
D2
D3
D4
JATx/Rx
JA1
Writing a “1” to this bit selects the Jitter Attenuator in
the Transmit Path. A “0” selects in the Receive Path.
0
0
0
0
This bit along with the JA0 configures the Jitter Atten-
uator as shown in the table.
PNTRST
DFLCK
Setting this bit to “1” resets the Read and Write point-
ers of the jitter attenuator FIFO.
Set this bit to "1" to disable the SONET APS Recov-
ery Time of the PLL. When this bit is "0", the APS
Recovery Time is enabled. This helps to reduce the
time for the PLL to lock to the incoming frequency
when the Jitter Attenuator switches to narrow band.
This is required for SONET to DS-3 Mapping/Demap-
ping De-Synchronization applications.
0x08
Reserved
TABLE 17: REGISTER MAP DESCRIPTION - GLOBAL
ADDRESS
(HEX)
DEFAULT
BIT
LOCATION
TYPE
SYMBOL
DESCRIPTION
VALUE(BIN)
0x20
R/W
D0
D0
INTEN
Bit 0 = INTEN Writing a “1” to this bit enables the
interrupts.
0
0x21
Read
Only
INTST
Bit 0 = INTST bit is set to “1” if an interrupt service is
required. The source level interrupt status register is
read to determine the cause of interrupt.
0
0x22 -
0x2F
Reserved
0x30
Reset
Upon
Read
D[7:0]
PRBSmsb
PRBS error counter MSB [15:8]
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ADDRESS
(HEX)
DEFAULT
BIT
LOCATION
TYPE
SYMBOL
DESCRIPTION
VALUE(BIN)
0x31
Reset
Upon
Read
D[7:0]
PRBSlsb
PRBS error counter LSB [7:0]
0x32-
0x37
Reserved
0x38
Read
Only
D[7:0]
PRBShold
Chip_id
PRBS Holding Register
Reserved
0x39-
0x3D
0x3E
Read
Only
D[7:0]
D[7:0]
This read only register contains device id.
01010001
00000001
0x3F
Read
Only
Chip_version This read only register contains chip version number
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8.0 DIAGNOSTIC FEATURES:
8.1
PRBS Generator and Detector:
The XRT75VL00D contains an on-chip Pseudo Random Binary Sequence (PRBS) generator and detector for
diagnostic purpose. This feature is only available in Host mode. With the PRBSEN bit = “1”, the transmitter will
send out PRBS of 223-1 in E3 rate or 215-1 in STS-1/DS3 rate. At the same time, the receiver PRBS detector is
also enabled. When the correct PRBS pattern is detected by the receiver, the RNEG/LCV pin will go “Low” to
indicate PRBS synchronization has been achieved. When the PRBS detector is not in sync the PRBSLS bit will
be set to “1” and RNEG/LCV pin will go “High”.
With the PRBS mode enabled, the user can also insert a single bit error by toggling “INSPRBS” bit. This is
done by writing a “1” to INSPRBS bit. The receiver at RNEG/LCV pin will pulse “High” for half RxClk cycle for
every bit error detected. Any subsequent single bit error insertion must be done by first writing a “0” to
INSPRBS bit and followed by a “1”.
When PRBS mode is enabled, the PRBS counter starts counting each single bit error. The PRBS counter is 16
bits wide. The current value in the counter can be read via two readback operations of the Serial I/O registers.
1) Either the Least Significant Byte (LSB, address 0x30) or the Most Significant Byte (MSB, address 0x31) can
be read first. The value of the un-read register will be copied into the Holding register (address 0x38) and both
the LSB and MSB registers will be reset to zero.
2) Read the Holding register and concatenate the result with the value from the first read operation to get the
full 16 bit counter value.
When the PRBS mode is first enabled, errors will be counted while the receiver logic is synchronizing to the
PRBS pattern. When RNEG/LCV goes “Low” indicating PRBS synchronization, reset the counter by reading
either the LSB or the MSB register.
Figure 25 shows the status of RNEG/LCV pin when the XRT75VL00D is configured in PRBS mode.
FIGURE 25. PRBS MODE
RClk
SYNC LOSS
RNEG/LCV
PRBS SYNC
Single Bit Error
8.2
LOOPBACKS:
The XRT75VL00D offers three loopback modes for diagnostic purposes. In Hardware mode, the loopback
modes are selected via the RLB and LLB pins. In Host mode, the RLB and LLB bits in the control registers
select the loopback modes.
8.2.1
ANALOG LOOPBACK:
In this mode, the transmitter outputs (TTIP and TRING) are connected internally to the receiver inputs (RTIP
and RRING) as shown in Figure 26. Data and clock are output at RCLK, RPOS and RNEG pins for the
corresponding transceiver. Analog loopback exercises most of the functional blocks of the device including the
jitter attenuator which can be selected in either the transmit or receive path.
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XRT75VL00D can be configured in Analog Loopback either in Hardware mode via the LLB and RLB pins or in
Host mode via LLB and RLB bits in the channel control registers.
NOTES:
1. In the Analog loopback mode, data is also output via TTIP and TRING pins.
2. Signals on the RTIP and RRING pins are ignored during analog loopback.
FIGURE 26. ANALOG LOOPBACK
TCLK
TTIP
1
HDB3/B3ZS
ENCODER
TIMING
CONTROL
TPDATA
Tx
TNDATA
TRING
RCLK
RPOS
RNEG
RTIP
DATA &
CLOCK
RECOVERY
1
HDB3/B3ZS
Rx
DECODER
RRING
1 if enabled
2 if enabled and selected in either Receive or Transmit path
8.2.2
DIGITAL LOOPBACK:
The Digital Loopback function is available either in Hardware mode or Host mode. When the Digital Loopback
is selected, the transmit clock (TxClk) and transmit data inputs (TPDATA & TNDATA) are looped back and
output onto the RxClk, RPOS and RNEG pins as shown in Figure 27. The data presented on TxClk, TPDATA
and TNDATA are not output on the TTIP and TRING pins.This provides the capability to configure the
protection card (in redundancy applications) in Digital Loopback mode without affecting the traffic on the
primary card.
NOTE: Signals on the RTIP and RRING pins are ignored during digital loopback.
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FIGURE 27. DIGITAL LOOPBACK
TCLK
TTIP
1
HDB3/B3ZS
ENCODER
TIMING
CONTROL
TPDATA
TNDATA
Tx
TRING
RCLK
RPOS
RNEG
RTIP
DATA &
CLOCK
RECOVERY
1
HDB3/B3ZS
Rx
DECODER
RRING
1 if enabled
2 if enabled and selected in either Receive or Transmit path
8.2.3
REMOTE LOOPBACK:
With Remote loopback activated as shown in Figure 28,the receive data on RTIP and RRING is looped back
after the jitter attenuator (if selected in receive or transmit path) to the transmit path using RxClk as transmit
timing. The receive data is also output via the RPOS and RNEG pins.
During the remote loopback mode, if the jitter attenuator is selected in the transmit path, the receive data after
the Clock and Data Recovery Block is looped back to the transmit path and pass through the jitter attenuator
using RxClk as the transmit timing.
NOTE: Input signals on TxClk, TPDATA and TNDATA are ignored during Remote loopback.
FIGURE 28. REMOTE LOOPBACK
TCLK
TTIP
1
HDB3/B3ZS
ENCODER
TIMING
CONTROL
TPDATA
TNDATA
Tx
TRING
RCLK
RPOS
RNEG
RTIP
DATA &
CLOCK
RECOVERY
1
HDB3/B3ZS
DECODER
Rx
RRING
1 if enabled
2
if enabled and selected in either Receive or Transmit path
8.3
TRANSMIT ALL ONES (TAOS):
Transmit All Ones (TAOS) can be set either in Hardware mode by pulling the TAOS pins “High” or in Host mode
by setting the TAOS control bits to “1” in the Channel control registers. When the TAOS is set, the Transmit
Section generates and transmits a continuous AMI all “1’s” pattern on TTIP and TRING pins. The frequency of
this “1’s” pattern is determined by TClk.TAOS data path is shown in Figure 29.
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FIGURE 29. TRANSMIT ALL ONES (TAOS)
1
TCLK
TTIP
Transmit All 1
HDB3/B3ZS
ENCODER
TIMING
CONTROL
TPDATA
Tx
TNDATA
TRING
TAOS
RCLK
1
RTIP
DATA &
CLOCK
RECOVERY
HDB3/B3ZS
RPOS
DECODER
RNEG
Rx
RRING
1 if enabled
2 if enabled and selected in either Receive or Transmit path
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9.0 THE SONET/SDH DE-SYNC FUNCTION WITHIN THE LIU
The LIU with D-SYNC is very similar to the non D-SYNC LIU in that they both contain Jitter Attenuator blocks
within each channel. They are also pin to pin compatible with each other. However, the Jitter Attenuators
within the D-SYNC have some enhancements over and above those within the non D-SYNC device. The Jitter
Attenuator blocks will support all of the modes and features that exist in the non D-SYNC device and in
addition they also support a SONET/SDH De-Sync Mode.
NOTE: The "D" suffix within the part number stands for "De-Sync".
The SONET/SDH De-Sync feature of the Jitter Attenuator blocks permits the user to design a SONET/SDH
PTE (Path Terminating Equipment) that will comply with all of the following Intrinsic Jitter and Wander
requirements.
• For SONET Applications
■ Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 Applications)
■ ANSI T1.105.03b-1997 - SONET Jitter at Network Interfaces - DS3 Wander Supplement
• For SDH Applications
■ Jitter and Wander Generation Requirements per ITU-T G.783 (for DS3 and E3 Applications)
Specifically, if the user designs in the LIU along with a SONET/SDH Mapper IC (which can be realized as
either a standard product or as a custom logic solution, in an ASIC or FPGA), then the following can be
accomplished.
• The Mapper can receive an STS-N or an STM-M signal (which is carrying asynchronously-mapped DS3 and/
or E3 signals) and byte de-interleave this data into N STS-1 or 3*M VC-3 signals
• The Mapper will then terminate these STS-1 or VC-3 signals and will de-map out this DS3 or E3 data from
the incoming STS-1 SPEs or VC-3s, and output this DS3 or E3 to the DS3/E3 Facility-side towards the LIU
• This DS3 or E3 signal (as it is output from these Mapper devices) will contain a large amount of intrinsic jitter
and wander due to (1) the process of asynchronously mapping a DS3 or E3 signal into a SONET or SDH
signal, (2) the occurrence of Pointer Adjustments within the SONET or SDH signal (transporting these DS3
or E3 signals) as it traverses the SONET/SDH network, and (3) clock gapping.
• When the LIU has been configured to operate in the "SONET/SDH De-Sync" Mode, then it will (1) accept this
jittery DS3 or E3 clock and data signal from the Mapper device (via the Transmit System-side interface) and
(2) through the Jitter Attenuator, the LIU will reduce the Jitter and Wander amplitude within these DS3 or E3
signals such that they (when output onto the line) will comply with the above-mentioned intrinsic jitter and
wander specifications.
9.1
BACKGROUND AND DETAILED INFORMATION - SONET DE-SYNC APPLICATIONS
This section provides an in-depth discussion on the mechanisms that will cause Jitter and Wander within a
DS3 or E3 signal that is being transported across a SONET or SDH Network. A lot of this material is
introductory, and can be skipped by the engineer that is already experienced in SONET/SDH designs.
In the wide-area network (WAN) in North America it is often necessary to transport a DS3 signal over a long
distance (perhaps over a thousand miles) in order to support a particular service. Now rather than realizing
this transport of DS3 data, by using over a thousand miles of coaxial cable (interspaced by a large number of
DS3 repeaters) a common thing to do is to route this DS3 signal to a piece of equipment (such as a Terminal
MUX, which in the "SONET Community" is known as a PTE or Path Terminating Equipment). This Terminal
MUX will asynchronously map the DS3 signal into a SONET signal. At this point, the SONET network will now
transport this asynchronously mapped DS3 signal from one PTE to another PTE (which is located at the other
end of the SONET network). Once this SONET signal arrives at the remote PTE, this DS3 signal will then be
extracted from the SONET signal, and will be output to some other DS3 Terminal Equipment for further
processing.
Similar things are done outside of North America. In this case, this DS3 or E3 signal is routed to a PTE, where
it is asynchronously mapped into an SDH signal. This asynchronously mapped DS3 or E3 signal is then
transported across the SDH network (from one PTE to the PTE at the other end of the SDH network). Once
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this SDH signal arrives at the remote PTE, this DS3 or E3 signal will then be extracted from the SDH signal,
and will be output to some other DS3/E3 Terminal Equipment for further processing.
Figure 30 presents an illustration of this approach to transporting DS3 data over a SONET Network
FIGURE 30. A SIMPLE ILLUSTRATION OF A DS3 SIGNAL BEING MAPPED INTO AND TRANSPORTED OVER THE SONET
NETWORK
SONET
Network
PTE
DS3 Data
PTE
DS3 Data
As mentioned above a DS3 or E3 signal will be asynchronously mapped into a SONET or SDH signal and then
transported over the SONET or SDH network. At the remote PTE this DS3 or E3 signal will be extracted (or
de-mapped) from this SONET or SDH signal, where it will then be routed to DS3 or E3 terminal equipment for
further processing.
In order to insure that this "de-mapped" DS3 or E3 signal can be routed to any industry-standard DS3 or E3
terminal equipment, without any complications or adverse effect on the network, the Telcordia and ITU-T
standard committees have specified some limits on both the Intrinsic Jitter and Wander that may exist within
these DS3 or E3 signals as they are de-mapped from SONET/SDH. As a consequence, all PTEs that maps
and de-mapped DS3/E3 signals into/from SONET/SDH must be designed such that the DS3 or E3 data that is
de-mapped from SONET/SDH by these PTEs must meet these Intrinsic Jitter and Wander requirements.
As mentioned above, the LIU can assist the System Designer (of SONET/SDH PTE) by ensuring that their
design will meet these Intrinsic Jitter and Wander requirements.
This section of the data sheet will present the following information to the user.
• Some background information on Mapping DS3/E3 signals into SONET/SDH and de-mapping DS3/E3
signals from SONET/SDH.
• A brief discussion on the causes of jitter and wander within a DS3 or E3 signal that mapped into a SONET/
SDH signal, and is transported across the SONET/SDH Network.
• A brief review of these Intrinsic Jitter and Wander requirements in both SONET and SDH applications.
• A brief review on the Intrinsic Jitter and Wander measurement results (of a de-mapped DS3 or E3 signal)
whenever the LIU device is used in a system design.
• A detailed discussion on how to design with and configure the LIU device such that the end-system will meet
these Intrinsic Jitter and Wander requirements.
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In a SONET system, the relevant specification requirements for Intrinsic Jitter and Wander (within a DS3 signal
that is mapped into and then de-mapped from SONET) are listed below.
• Telcordia GR-253-CORE Category I Intrinsic Jitter Requirements for DS3 Applications (Section 5.6), and
• ANSI T1.105.03b-1997 - SONET Jitter at Network Interfaces - DS3 Wander Supplement
In general, there are three (3) sources of Jitter and Wander within an asynchronously-mapped DS3 signal that
the system designer must be aware of. These sources are listed below.
• Mapping/De-Mapping Jitter
• Pointer Adjustments
• Clock Gapping
Each of these sources of jitter/wander will be defined and discussed in considerable detail within this Section.
In order to accomplish all of this, this particular section will discuss all of the following topics in details.
• How DS3 data is mapped into SONET, and how this mapping operation contributes to Jitter and Wander
within this "eventually de-mapped" DS3 signal.
• How this asynchronously-mapped DS3 data is transported throughout the SONET Network, and how
occurrences on the SONET network (such as pointer adjustments) will further contributes to Jitter and
Wander within the "eventually de-mapped" DS3 signal.
• A review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications
• A review of the DS3 Wander requirements per ANSI T1.105.03b-1997
• A review of the Intrinsic Jitter and Wander Capabilities of the LIU in a typical system application
• An in-depth discussion on how to design with and configure the LIU to permit the system to the meet the
above-mentioned Intrinsic Jitter and Wander requirements
NOTE: An in-depth discussion on SDH De-Sync Applications will be presented in the next revision of this data sheet.
9.2
MAPPING/DE-MAPPING JITTER/WANDER
Mapping/De-Mapping Jitter (or Wander) is defined as that intrinsic jitter (or wander) that is induced into a DS3
signal by the "Asynchronous Mapping" process. This section will discuss all of the following aspects of
Mapping/De-Mapping Jitter.
• How DS3 data is mapped into an STS-1 SPE
• How frequency offsets within either the DS3 signal (being mapped into SONET) or within the STS-1 signal
itself contributes to intrinsic jitter/wander within the DS3 signal (being transported via the SONET network).
9.2.1
HOW DS3 DATA IS MAPPED INTO SONET
Whenever a DS3 signal is asynchronously mapped into SONET, this mapping is typically accomplished by a
PTE accepting DS3 data (from some remote terminal) and then loading this data into certain bit-fields within a
given STS-1 SPE (or Synchronous Payload Envelope). At this point, this DS3 signal has now been
asynchronously mapped into an STS-1 signal. In most applications, the SONET Network will then take this
particular STS-1 signal and will map it into "higher-speed" SONET signals (e.g., STS-3, STS-12, STS-48, etc.)
and will then transport this asynchronously mapped DS3 signal across the SONET network, in this manner. As
this "asynchronously-mapped" DS3 signal approaches its "destination" PTE, this STS-1 signal will eventually
be de-mapped from this STS-N signal. Finally, once this STS-1 signal reaches the "destination" PTE, then this
asynchronously-mapped DS3 signal will be extracted from this STS-1 signal.
9.2.1.1
A Brief Description of an STS-1 Frame
In order to be able to describe how a DS3 signal is asynchronously mapped into an STS-1 SPE, it is important
to define and understand all of the following.
• The STS-1 frame structure
• The STS-1 SPE (Synchronous Payload Envelope)
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• Telcordia GR-253-CORE’s recommendation on mapping DS3 data into an STS-1 SPE
An STS-1 frame is a data-structure that consists of 810 bytes (or 6480 bits). A given STS-1 frame can be
viewed as being a 9 row by 90 byte column array (making up the 810 bytes). The frame-repetition rate (for an
STS-1 frame) is 8000 frames/second. Therefore, the bit-rate for an STS-1 signal is (6480 bits/frame * 8000
frames/sec =) 51.84Mbps.
A simple illustration of this SONET STS-1 frame is presented below in Figure 31.
FIGURE 31. A SIMPLE ILLUSTRATION OF THE SONET STS-1 FRAME
90 Bytes
9 Rows
STS-1 Frame (810 Bytes)
Last Byte of the STS-1 Frame
First Byte of the STS-1 Frame
Figure 31 indicates that the very first byte of a given STS-1 frame (to be transmitted or received) is located in
the extreme upper left hand corner of the 90 column by 9 row array, and that the very last byte of a given STS-
1 frame is located in the extreme lower right-hand corner of the frame structure. Whenever a Network Element
transmits a SONET STS-1 frame, it starts by transmitting all of the data, residing within the top row of the STS-
1 frame structure (beginning with the left-most byte, and then transmitting the very next byte, to the right). After
the Network Equipment has completed its transmission of the top or first row, it will then proceed to transmit the
second row of data (again starting with the left-most byte, first). Once the Network Equipment has transmitted
the last byte of a given STS-1 frame, it will proceed to start transmitting the very next STS-1 frame.
The illustration of the STS-1 frame (in Figure 31) is very simplistic, for multiple reasons. One major reason is
that the STS-1 frame consists of numerous types of bytes. For the sake of discussion within this data sheet,
the STS-1 frame will be described as consisting of the following types (or groups) of bytes.
• The Transport Overheads (or TOH) Bytes
• The Envelope Capacity Bytes
9.2.1.1.1
The Transport Overhead (TOH) Bytes
The Transport Overhead or TOH bytes occupy the very first three (3) byte columns within each STS-1 frame.
Figure 32 presents another simple illustration of an STS-1 frame structure. However, in this case, both the
TOH and the Envelope Capacity bytes are designated in this Figure.
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FIGURE 32. A SIMPLE ILLUSTRATION OF THE STS-1 FRAME STRUCTURE WITH THE TOH AND THE ENVELOPE
CAPACITY BYTES DESIGNATED
90 Bytes
3 Bytes
87 Bytes
9 Row
TOH
Envelope Capacity
Since the TOH bytes occupy the first three byte columns of each STS-1 frame, and since each STS-1 frame
consists of nine (9) rows, then we can state that the TOH (within each STS-1 frame) consists of 3 byte columns
x 9 rows = 27 bytes. The byte format of the TOH is presented below in Figure 33.
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FIGURE 33. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME
3 Byte Columns
87 Byte Columns
A1
A2
C1
B1
E1
F1
D1
D2
D3
H1
H2
H3
Envelope Capacity
9 Rows
B2
K1
K2
Bytes
D4
D5
D6
D7
D8
D9
D10
D11
D12
S1
M0
E2
The TOH Bytes
In general, the role/purpose of the TOH bytes is to fulfill the following functions.
• To support STS-1 Frame Synchronization
• To support Error Detection within the STS-1 frame
• To support the transmission of various alarm conditions such as RDI-L (Line - Remote Defect Indicator) and
REI-L (Line - Remote Error Indicator)
• To support the Transmission and Reception of "Section Trace" Messages
• To support the Transmission and Reception of OAM&P Messages via the DCC Bytes (Data Communication
Channel bytes - D1 through D12 byte)
The roles of most of the TOH bytes is beyond the scope of this Data Sheet and will not be discussed any
further. However, there are a three TOH bytes that are important from the stand-point of this data sheet, and
will discussed in considerable detail throughout this document. These are the H1 and H2 (e.g., the SPE
Pointer) bytes and the H3 (e.g., the Pointer Action) byte.
Figure 34 presents an illustration of the Byte-Format of the TOH within an STS-1 Frame, with the H1, H2 and
H3 bytes highlighted.
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FIGURE 34. THE BYTE-FORMAT OF THE TOH WITHIN AN STS-1 FRAME
3 Byte Columns
87 Byte Columns
A1
A2
C1
B1
E1
F1
D1
D2
D3
H1
H2
H3
Envelope Capacity
9 Rows
B2
K1
K2
Bytes
D4
D5
D6
D7
D8
D9
D10
D11
D12
S1
M0
E2
The TOH Bytes
Although the role of the H1, H2 and H3 bytes will be discussed in much greater detail in “Section 9.3, Jitter/
Wander due to Pointer Adjustments” on page 60. For now, we will simply state that the role of these bytes is
two-fold.
• To permit a given PTE (Path Terminating Equipment) that is receiving an STS-1 data to be able to locate the
STS-1 SPE (Synchronous Payload Envelope) within the Envelope Capacity of this incoming STS-1 data
stream and,
• To inform a given PTE whenever Pointer Adjustment and NDF (New Data Flag) events occur within the
incoming STS-1 data-stream.
9.2.1.1.2
The Envelope Capacity Bytes within an STS-1 Frame
In general, the Envelope Capacity Bytes are any bytes (within an STS-1 frame) that exist outside of the TOH
bytes. In short, the Envelope Capacity contains the STS-1 SPE (Synchronous Payload Envelope). In fact,
every single byte that exists within the Envelope Capacity also exists within the STS-1 SPE. The only
difference that exists between the "Envelope Capacity" as defined in Figure 33 and Figure 34 above and the
STS-1 SPE is that the Envelope Capacity is aligned with the STS-1 framing boundaries and the TOH bytes;
whereas the STS-1 SPE is NOT aligned with the STS-1 framing boundaries, nor the TOH bytes.
The STS-1 SPE is an "87 byte column x 9 row" data-structure (which is the exact same size as is the Envelope
Capacity) that is permitted to "float" within the "Envelope Capacity". As a consequence, the STS-1 SPE (within
an STS-1 data-stream) will typically straddle across an STS-1 frame boundary.
9.2.1.1.3
The Byte Structure of the STS-1 SPE
As mentioned above, the STS-1 SPE is an 87 byte column x 9 row structure. The very first column within the
STS-1 SPE consists of some overhead bytes which are known as the "Path Overhead" (or POH) bytes. The
remaining portions of the STS-1 SPE is available for "user" data. The Byte Structure of the STS-1 SPE is
presented below in Figure 35.
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FIGURE 35. ILLUSTRATION OF THE BYTE STRUCTURE OF THE STS-1 SPE
87 Bytes
1 Byte
86 Bytes
J1
B3
C2
G1
F2
H4
Z3
Z4
Z5
9 Rows
Payload (or User) Data
In general, the role/purpose of the POH bytes is to fulfill the following functions.
• To support error detection within the STS-1 SPE
• To support the transmission of various alarm conditions such as RDI-P (Path - Remote Defect Indicator) and
REI-P (Path - Remote Error Indicator)
• To support the transmission and reception of "Path Trace" Messages
The role of the POH bytes is beyond the scope of this data sheet and will not be discussed any further.
9.2.1.2
Mapping DS3 data into an STS-1 SPE
Now that we have defined the STS-1 SPE, we can now describe how a DS3 signal is mapped into an STS-1
SPE. As mentioned above, the STS-1 SPE is basically an 87 byte column x 9 row structure of data. The very
first byte column (e.g., in all 9 bytes) consists of the POH (Path Overhead) bytes. All of the remaining bytes
within the STS-1 SPE is simply referred to as "user" or "payload" data because this is the portion of the STS-1
signal that is used to transport "user data" from one end of the SONET network to the other. Telcordia GR-253-
CORE specifies the approach that one must use to asynchronously map DS3 data into an STS-1 SPE. In
short, this approach is presented below in Figure 36.
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FIGURE 36. AN ILLUSTRATION OF TELCORDIA GR-253-CORE’S RECOMMENDATION ON HOW MAP DS3 DATA INTO
AN STS-1 SPE
• For DS3 Mapping, the STS-1 SPE has the following structure.
87 bytes
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
C1 25I
C1 25I
C1 25I
C1 25I
C1 25I
C1 25I
C1 25I
C1 25I
C1 25I
R
R
R
R
R
R
R
R
R
C2
C2
C2
C2
C2
C2
C2
C2
C2
I
I
I
I
I
I
I
I
I
25I
25I
25I
25I
25I
25I
25I
25I
25I
R
R
R
R
R
R
R
R
R
C3
C3
C3
C3
C3
C3
C3
C3
C3
I
I
I
I
I
I
I
I
I
25I
25I
25I
25I
25I
25I
25I
25I
25I
i = DS3 data
POH
I = [i, i, i, i, i, i, i, i]
r = fixed stuff bit
c = stuff control bit
R = [r, r, r, r, r, r, r, r]
Fixed
Stuff
C1 = [r, r, c, i, i, i, i, i]
C2 = [c, c, r, r, r, r, r, r]
C3 = [c, c, r, r, o, o, r, s]
s = stuff opportunity bit
o = overhead communications channel bit
Figure 36 was copied directly out of Telcordia GR-253-CORE. However, this figure can be simplified and
redrawn as depicted below in Figure 37.
FIGURE 37. A SIMPLIFIED "BIT-ORIENTED" VERSION OF TELCORDIA GR-253-CORE’S RECOMMENDATION ON HOW
TO MAP DS3 DATA INTO AN STS-1 SPE
18r
18r
18r
18r
18r
18r
18r
18r
18r
c
c
c
c
c
c
c
c
c
205i 16r 2c
205i 16r 2c
205i 16r 2c
205i 16r 2c
205i 16r 2c
205i 16r 2c
205i 16r 2c
205i 16r 2c
205i 16r 2c
6r 208i 16r 2c
6r 208i 16r 2c
6r 208i 16r 2c
6r 208i 16r 2c
6r 208i 16r 2c
6r 208i 16r 2c
6r 208i 16r 2c
6r 208i 16r 2c
6r 208i 16r 2c
2r
2r
2r
2r
2r
2r
2r
2r
2r
2o
2o
2o
2o
2o
2o
2o
2o
2o
1r
1r
1r
1r
1r
1r
1r
1r
1r
s
s
s
s
s
s
s
s
s
208i
208i
208i
208i
208i
208i
208i
208i
208i
- Overhead Communication Bits
- Fixed Stuff Bits
o
r
c
i
POH
- Stuff Control/Indicator Bits
- DS3 Data Bits
- Stuff Opportunity Bits
s
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Figure 37 presents an alternative illustration of Telcordia GR-253-CORE’s recommendation on how to
asynchronously map DS3 data into an STS-1 SPE. In this case, the STS-1 SPE bit-format is expressed purely
in the form of "bit-types" and "numbers of bits within each of these types of bits". If one studies this figure
closely he/she will notice that this is the same "87 byte column x 9 row" structure that we have been talking
about when defining the STS-1 SPE. However, in this figure, the "user-data" field is now defined and is said to
consist of five (5) different types of bits. Each of these bit-types play a role when asynchronously mapping a
DS3 signal into an STS-1 SPE. Each of these types of bits are listed and described below.
Fixed Stuff Bits
Fixed Stuff bits are simply "space-filler" bits that simply occupy space within the STS-1 SPE. These bit-fields
have no functional role other than "space occupation". Telcordia GR-253-CORE does not define any particular
value that these bits should be set to. Each of the 9 rows, within the STS-1 SPE will contain 59 of these "fixed
stuff" bits.
DS3 Data Bits
The DS3 Data-Bits are (as its name implies) used to transport the DS3 data-bits within the STS-1 SPE. If the
STS-1 SPE is transporting a framed DS3 data-stream, then these DS3 Data bits will carry both the "DS3
payload data" and the "DS3 overhead bits". Each of the 9 rows, within the STS-1 SPE will contain 621 of these
"DS3 Data bits". This means that each STS-1 SPE contains 5,589 of these DS3 Data bit-fields.
Stuff Opportunity Bits
The "Stuff" Opportunity bits will function as either a "stuff" (or junk) bit, or it will carry a DS3 data-bit. The
decision as to whether to have a "Stuff Opportunity" bit transport a "DS3 data-bit" or a "stuff" bit depends upon
the "timing differences" between the DS3 data that is being mapped into the STS-1 SPE and the timing source
that is driving the STS-1 circuitry within the PTE.
As will be described later on, these "Stuff Opportunity" Bits play a very important role in "frequency-justifying"
the DS3 data that is being mapped into the STS-1 SPE. These "Stuff Opportunity" bits also play a critical role
in inducing Intrinsic Jitter and Wander within the DS3 signal (as it is de-mapped by the remote PTE).
Each of the 9 rows, within the STS-1 SPE consists of one (1) Stuff Opportunity bit. Hence, there are a total of
nine "Stuff Opportunity" bits within each STS-1 SPE.
Stuff Control/Indicator Bits
Each of the nine (9) rows within the STS-1 SPE contains five (5) Stuff Control/Indicator bits. The purpose of
these "Stuff Control/Indicator" bits is to indicate (to the de-mapping PTE) whether the "Stuff Opportunity" bits
(that resides in the same row) is a "Stuff" bit or is carrying a DS3 data bit.
If all five of these "Stuff Control/Indicator" bits, within a given row are set to "0", then this means that the
corresponding "Stuff Opportunity" bit (e.g., the "Stuff Opportunity" bit within the same row) is carrying a DS3
data bit.
Conversely, if all five of these "Stuff Control/Indicator" bits, within a given row are set to "1" then this means
that the corresponding "Stuff Opportunity" bit is carrying a "stuff" bit.
Overhead Communication Bits
Telcordia GR-253-CORE permits the user to use these two bits (for each row) as some sort of
"Communications" bit. Some Mapper devices, such as the XRT94L43 12-Channel DS3/E3/STS-1 to STS-12/
STM-1 Mapper and the XRT94L33 3-Channel DS3/E3/STS-1 to STS-3/STM-1 Mapper IC (both from Exar
Corporation) do permit the user to have access to these bit-fields.
However, in general, these particular bits can also be thought of as "Fixed Stuff" bits, that mostly have a "space
occupation" function.
9.2.2
DS3 Frequency Offsets and the Use of the "Stuff Opportunity" Bits
In order to fully convey the role that the "stuff-opportunity" bits play, when mapping DS3 data into SONET, we
will present a detailed discussion of each of the following "Mapping DS3 into STS-1" scenarios.
• The Ideal Case (e.g., with no frequency offsets)
• The 44.736Mbps + 1 ppm Case
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• The 44.736MHz - 1ppm Case
Throughout each of these cases, we will discuss how the resulting "bit-stuffing" (that was done when mapping
the DS3 signal into SONET) affects the amount of intrinsic jitter and wander that will be present in the DS3
signal, once it is ultimately de-mapped from SONET.
9.2.2.1
The Ideal Case for Mapping DS3 data into an STS-1 Signal (e.g., with no Frequency
Offsets)
Let us assume that we are mapping a DS3 signal, which has a bit rate of exactly 44.736Mbps (with no
frequency offset) into SONET. Further, let us assume that the SONET circuitry within the PTE is clocked at
exactly 51.84MHz (also with no frequency offset), as depicted below.
FIGURE 38. A SIMPLE ILLUSTRATION OF A DS3 DATA-STREAM BEING MAPPED INTO AN STS-1 SPE, VIA A PTE
DS3_Data_In
STS-1_Data_Out
51.84MHz + 0ppm
PTE
44.736MHz + 0ppm
Given the above-mentioned assumptions, we can state the following.
• The DS3 data-stream has a bit-rate of exactly 44.736Mbps
• The PTE will create 8000 STS-1 SPE’s per second
• In order to properly map a DS3 data-stream into an STS-1 data-stream, then each STS-1 SPE must carry
(44.736Mbps/8000 =) 5592 DS3 data bits.
Is there a Problem?
According to Figure 37, each STS-1 SPE only contains 5589 bits that are specifically designated for "DS3 data
bits". In this case, each STS-1 SPE appears to be three bits "short".
No there is a Simple Solution
No, earlier we mentioned that each STS-1 SPE consists of nine (9) "Stuff Opportunity" bits. Therefore, these
three additional bits (for DS3 data) are obtained by using three of these "Stuff Opportunity" bits. As a
consequence, three (3) of these nine (9) "Stuff Opportunity" bits, within each STS-1 SPE, will carry DS3 data-
bits. The remaining six (6) "Stuff Opportunity" bits will typically function as "stuff" bits.
In summary, for the "Ideal Case"; where there is no frequency offset between the DS3 and the STS-1 bit-rates,
once this DS3 data-stream has been mapped into the STS-1 data-stream, then each and every STS-1 SPE will
have the following "Stuff Opportunity" bit utilization.
3 "Stuff Opportunity" bits will carry DS3 data bits.
6 "Stuff Opportunity" bits will function as "stuff" bits
In this case, this DS3 signal (which has now been mapped into STS-1) will be transported across the SONET
network. As this STS-1 signal arrives at the "Destination PTE", this PTE will extract (or de-map) this DS3 data-
stream from each incoming STS-1 SPE. Now since each and every STS-1 SPE contains exactly 5592 DS3
data bits; then the bit rate of this DS3 signal will be exactly 44.736Mbps (such as it was when it was mapped
into SONET, at the "Source" PTE).
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As a consequence, no "Mapping/De-Mapping" Jitter or Wander is induced in the "Ideal Case".
9.2.2.2 The 44.736Mbps + 1ppm Case
The "above example" was a very ideal case. In reality, there are going to be frequency offsets in both the DS3
and STS-1 signals. For instance Bellcore GR-499-CORE mandates that a DS3 signal have a bit rate of
44.736Mbps ± 20ppm. Hence, the bit-rate of a "Bellcore" compliant DS3 signal can vary from the exact correct
frequency for DS3 by as much of 20ppm in either direction. Similarly, many SONET applications mandate that
SONET equipment use at least a "Stratum 3" level clock as its timing source. This requirement mandates that
an STS-1 signal must have a bit rate that is in the range of 51.84 ± 4.6ppm. To make matters worse, there are
also provisions for SONET equipment to use (what is referred to as) a "SONET Minimum Clock" (SMC) as its
timing source. In this case, an STS-1 signal can have a bit-rate in the range of 51.84Mbps ± 20ppm.
In order to convey the impact that frequency offsets (in either the DS3 or STS-1 signal) will impose on the bit-
stuffing behavior, and the resulting bit-rate, intrinsic jitter and wander within the DS3 signal that is being
transported across the SONET network; let us assume that a DS3 signal, with a bit-rate of 44.736Mbps +
1ppm is being mapped into an STS-1 signal with a bit-rate of 51.84Mbps + 0ppm. In this case, the following
things will occur.
• In general, most of the STS-1 SPE's will each transport 5592 DS3 data bits.
• However, within a "one-second" period, a DS3 signal that has a bit-rate of 44.736Mbps + 1 ppm will deliver
approximately 44.7 additional bits (over and above that of a DS3 signal with a bit-rate of 44.736Mbps + 0
ppm). This means that this particular signal will need to "negative-stuff" or map in an additional DS3 data bit
every (1/44.736 =) 22.35ms. In other words, this additional DS3 data bit will need to be mapped into about
one in every (22.35ms · 8000 =) 178.8 STS-1 SPEs in order to avoid dropping any DS3 data-bits.
What does this mean at the "Source" PTE?
All of this means that as the "Source" PTE maps this DS3 signal, with a data rate of 44.736Mbps + 1ppm into
an STS-1 signal, most of the resulting "outbound" STS-1 SPEs will transport 5592 DS3 data bits (e.g., 3 Stuff
Opportunity bits will be carrying DS3 data bits, the remaining 6 Stuff Opportunity bits are "stuff" bits, as in the
"Ideal" case). However, in approximately one out of 178.8 "outbound" STS-1 SPEs, there will be a need to
insert an additional DS3 data bit within this STS-1 SPE. Whenever this occurs, then (for these particular STS-
1 SPEs) the SPE will be carrying 5593 DS3 data bits (e.g., 4 Stuff Opportunity bits will be carrying DS3 data
bits, the remaining 5 Stuff Opportunity bits are "stuff" bits).
Figure 39 presents an illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, during
this condition.
FIGURE 39. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE "SOURCE" PTE,
WHEN MAPPING IN A DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS + 1PPM, INTO AN STS-1 SIGNAL
Extra DS3 Data
Bit Stuffed Here
SPE # N+177
SPE # N+179
SPE # N
SPE # N+1
5592
5592
5592
5593
5592
DS3 Data
DS3 Data
DS3 Data
DS3 Data
DS3 Data
Source
Bits
Bits
Bits
Bits
Bits
PTE
SPE # N+178
44.736Mbps + 1ppm
STS-1 SPE Data Stream
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What does this mean at the "Destination" PTE?
In this case, this DS3 signal (which has now been mapped into an STS-1 data-stream) will be transported
across the SONET network. As this STS-1 signal arrives at the "Destination" PTE, this PTE will extract (or de-
map) this DS3 data from each incoming STS-1 SPE. Now, in this case most (e.g., 177/178.8) of the incoming
STS-1 SPEs will contain 5592 DS3 data-bits. Therefore, the nominal data rate of the DS3 signal being de-
mapped from SONET will be 44.736Mbps. However, in approximately 1 out of every 178 incoming STS-1
SPEs, the SPE will carry 5593 DS3 data-bits. This means that (during these times) the data rate of the de-
mapped DS3 signal will have an instantaneous frequency that is greater than 44.736Mbps. These "excursion"
of the de-mapped DS3 data-rate, from the nominal DS3 frequency can be viewed as occurrences of "mapping/
de-mapping" jitter. Since each of these "bit-stuffing" events involve the insertion of one DS3 data bit, we can
say that the amplitude of this "mapping/de-mapping" jitter is approximately 1UI-pp. From this point on, we will
be referring to this type of jitter (e.g., that which is induced by the mapping and de-mapping process) as "de-
mapping" jitter.
Since this occurrence of "de-mapping" jitter is periodic and occurs once every 22.35ms, we can state that this
jitter has a frequency of 44.7Hz.
9.2.2.3
The 44.736Mbps - 1ppm Case
In this case, let us assume that a DS3 signal, with a bit-rate of 44.736Mbps - 1ppm is being mapped into an
STS-1 signal with a bit-rate of 51.84Mbps + 0ppm. In this case, the following this will occur.
• In general, most of the STS-1 SPEs will each transport 5592 DS3 data bits.
• However, within a "one-second" period a DS3 signal that has a bit-rate of 44.736Mbps - 1ppm will deliver
approximately 45 too few bits below that of a DS3 signal with a bit-rate of 44.736Mbps + 0ppm. This means
that this particular signal will need to "positive-stuff" or exclude a DS3 data bit from mapping every (1/44.736)
= 22.35ms. In other words, we will need to avoid mapping this DS3 data-bit about one in every
(22.35ms*8000) = 178.8 STS-1 SPEs.
What does this mean at the "Source" PTE?
All of this means that as the "Source" PTE maps this DS3 signal, with a data rate of 44.736Mbps - 1ppm into
an STS-1 signal, most of the resulting "outbound" STS-1 SPEs will transport 5592 DS3 data bits (e.g., 3 Stuff
Opportunity bits will be carrying DS3 data bits, the remaining 6 Stuff Opportunity bits are "stuff" bits). However,
in approximately one out of 178.8 "outbound" STS-1 SPEs, there will be a need for a "positive-stuffing" event.
Whenever these "positive-stuffing" events occur then (for these particular STS-1 SPEs) the SPE will carry only
5591 DS3 data bits (e.g., in this case, only 2 Stuff Opportunity bits will be carrying DS3 data-bits, and the
remaining 7 Stuff Opportunity bits are "stuff" bits).
Figure 40 presents an illustration of the STS-1 SPE traffic that will be generated by the "Source" PTE, during
this condition.
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FIGURE 40. AN ILLUSTRATION OF THE STS-1 SPE TRAFFIC THAT WILL BE GENERATED BY THE SOURCE PTE, WHEN
MAPPING A DS3 SIGNAL THAT HAS A BIT RATE OF 44.736MBPS - 1PPM, INTO AN STS-1 SIGNAL
DS3 Data
Bit Excluded Here
SPE # N+177
SPE # N+179
SPE # N
SPE # N+1
5592
5592
5592
5591
5592
DS3 Data
DS3 Data
DS3 Data
DS3 Data
DS3 Data
Source
Bits
Bits
Bits
Bits
Bits
PTE
SPE # N+178
44.736Mbps - 1ppm
STS-1 SPE Data Stream
What does this mean at the Destination PTE?
In this case, this DS3 signal (which has now been mapped into an STS-1 data-stream) will be transported
across the SONET network. As this STS-1 signal arrives at the "Destination" PTE, this PTE will extract (or de-
map) this DS3 data from each incoming STS-1 SPE. Now, in this case, most (e.g., 177/178.8) of the incoming
STS-1 SPEs will contain 5592 DS3 data-bits. Therefore, the nominal data rate of the DS3 signal being de-
mapped from SONET will be 44.736Mbps. However, in approximately 1 out of every 178 incoming STS-1
SPEs, the SPE will carry only 5591 DS3 data bits. This means that (during these times) the data rate of the de-
mapped DS3 signal will have an instantaneous frequency that is less than 44.736Mbps. These "excursions" of
the de-mapped DS3 data-rate, from the nominal DS3 frequency can be viewed as occurrences of mapping/de-
mapping jitter with an amplitude of approximately 1UI-pp.
Since this occurrence of "de-mapping" jitter is periodic and occurs once every 22.35ms, we can state that this
jitter has a frequency of 44.7Hz.
We talked about De-Mapping Jitter, What about De-Mapping Wander?
The Telcordia and Bellcore specifications define "Wander" as "Jitter with a frequency of less than 10Hz".
Based upon this definition, the DS3 signal (that is being transported by SONET) will cease to contain jitter and
will now contain "Wander", whenever the frequency offset of the DS3 signal being mapped into SONET is less
than 0.2ppm.
9.3
Jitter/Wander due to Pointer Adjustments
In the previous section, we described how a DS3 signal is asynchronously-mapped into SONET, and we also
defined "Mapping/De-mapping" jitter. In this section, we will describe how occurrences within the SONET
network will induce jitter/wander within the DS3 signal that is being transported across the SONET network.
In order to accomplish this, we will discuss the following topics in detail.
• The concept of an STS-1 SPE pointer
• The concept of Pointer Adjustments
• The causes of Pointer Adjustments
• How Pointer Adjustments induce jitter/wander within a DS3 signal being transported by that SONET network.
9.3.1
The Concept of an STS-1 SPE Pointer
As mentioned earlier, the STS-1 SPE is not aligned to the STS-1 frame boundaries and is permitted to "float"
within the Envelope Capacity. As a consequence, the STS-1 SPE will often times "straddle" across two
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consecutive STS-1 frames. Figure 41 presents an illustration of an STS-1 SPE straddling across two
consecutive STS-1 frames.
FIGURE 41. AN ILLUSTRATION OF AN STS-1 SPE STRADDLING ACROSS TWO CONSECUTIVE STS-1 FRAMES
TOH
STS-1 FRAME N + 1
STS-1 FRAME N
H1, H2
Bytes
J1 Byte (1st byte of next SPE)
J1 Byte (1st byte of SPE)
SPE can straddle across two STS-1 frames
A PTE that is receiving and terminating an STS-1 data-stream will perform the following tasks.
• It will acquire and maintain STS-1 frame synchronization with the incoming STS-1 data-stream.
• Once the PTE has acquired STS-1 frame synchronization, then it will locate the J1 byte (e.g., the very byte
within the very next STS-1 SPE) within the Envelope Capacity by reading out the contents of the H1 and H2
bytes.
The H1 and H2 bytes are referred to (in the SONET standards) as the SPE Pointer Bytes. When these two
bytes are concatenated together in order to form a 16-bit word (with the H1 byte functioning as the "Most
Significant Byte") then the contents of the "lower" 10 bit-fields (within this 16-bit word) reflects the location of
the J1 byte within the Envelope Capacity of the incoming STS-1 data-stream. Figure 42 presents an
illustration of the bit format of the H1 and H2 bytes, and indicates which bit-fields are used to reflect the
location of the J1 byte.
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FIGURE 42. THE BIT-FORMAT OF THE 16-BIT WORD (CONSISTING OF THE H1 AND H2 BYTES) WITH THE 10 BITS,
REFLECTING THE LOCATION OF THE J1 BYTE, DESIGNATED
H1 Byte
H2 Byte
MSB
LSB
N N N N S S X X X X X X X X X X
10 Bit Pointer Expression
Figure 43 relates the contents within these 10 bits (within the H1 and H2 bytes) to the location of the J1 byte
(e.g., the very first byte of the STS-1 SPE) within the Envelope Capacity.
FIGURE 43. THE RELATIONSHIP BETWEEN THE CONTENTS OF THE "POINTER BITS" (E.G., THE 10-BIT EXPRESSION
WITHIN THE H1 AND H2 BYTES) AND THE LOCATION OF THE J1 BYTE WITHIN THE ENVELOPE CAPACITY OF AN STS-
1 FRAME
TOH
The Pointer Value “0” is immediately
After the H3 byte
A1
B1
D1
H1
B2
D4
D7
D10
S1
A2
E1
C1/J0 522
523 * * * * * * * * 607
608
* *
F1
D3
H3
K2
D6
D9
D12
E2
609
696
0
610 * * * * * * * * 694
* *
697 * * * * * * * * 781
695
782
86
D2
H2
K1
D5
D8
D11
M0
* *
1
* * * * * * * *
85
* *
87
88
* * * * * * * * 172
173
260
347
434
521
* *
174
261
348
435
175 * * * * * * * * 259
* *
262 * * * * * * * * 346
* *
349 * * * * * * * * 433
* *
436 * * * * * * * * 520
* *
NOTES:
1. If the content of the "Pointer Bits" is "0x00" then the J1 byte is located immediately after the H3 byte, within the
Envelope Capacity.
2. If the contents of the 10-bit expression exceed the value of 0x30F (or 782, in decimal format) then it does not
contain a valid pointer value.
9.3.2
Pointer Adjustments within the SONET Network
The word SONET stands for "Synchronous Optical NETwork. This name implies that the entire SONET
network is synchronized to a single clock source. However, because the SONET (and SDH) Networks can
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span thousands of miles, traverse many different pieces of equipments, and even cross International
boundaries; in practice, the SONET/SDH network is NOT synchronized to a single clock source.
In practice, the SONET/SDH network can be thought of as being divided into numerous "Synchronization
Islands". Each of these "Synchronization Islands" will consist of numerous pieces of SONET Terminal
Equipment. Each of these pieces of SONET Terminal Equipment will all be synchronized to a single Stratum-1
clock source which is the most accurate clock source within the Synchronization Island. Typically a
"Synchronization Island" will consist of a single "Timing Master" equipment along with multiple "Timing Slave"
pieces of equipment. This "Timing Master" equipment will be directly connected to the Stratum-1 clock source
and will have the responsibility of distributing a very accurate clock signal (that has been derived from the
Stratum 1 clock source) to each of the "Timing Slave" pieces of equipment within the "Synchronization Island".
The purpose of this is to permit each of the "Timing Slave" pieces of equipment to be "synchronized" with the
"Timing Master" equipment, as well as the Stratum 1 Clock source. Typically this "clock distribution" is
performed in the form of a BITS (Building Integrated Timing Supply) clock, in which a very precise clock signal
is provided to the other pieces of equipment via a T1 or E1 line signal.
Many of these "Synchronization Islands" will use a Stratum-1" clock source that is derived from GPS pulses
that are received from Satellites that operate at Geo-synchronous orbit. Other "Synchronization Islands" will
use a Stratum-1" clock source that is derived from a very precise local atomic clock. As a consequence,
different "Synchronization Islands" will use different Stratum 1 clock sources. The up-shot of having these
"Synchronization Islands" that use different "Stratum-1 clock" sources, is that the Stratum 1 Clock frequencies,
between these "Synchronization Islands" are likely to be slightly different from each other. These "frequency-
differences" within Stratum 1 clock sources will result in "clock-domain changes" as a SONET signal (that is
traversing the SONET network) passes from one "Synchronization Island" to another.
The following section will describe how these "frequency differences" will cause a phenomenon called "pointer
adjustments" to occur in the SONET Network.
9.3.3
Causes of Pointer Adjustments
The best way to discuss how pointer adjustment events occur is to consider an STS-1 signal, which is driven
by a timing reference of frequency f1; and that this STS-1 signal is being routed to a network equipment (that
resides within a different "Synchronization Island") and processes STS-1 data at a frequency of f2.
NOTE: Clearly, both frequencies f1 and f2 are at the STS-1 rate (e.g., 51.84MHz). However, these two frequencies are
likely to be slightly different from each other.
Now, since the STS-1 signal (which is of frequency f1) is being routed to the network element (which is
operating at frequency f2), the typical design approach for handling "clock-domain" differences is to route this
STS-1 signal through a "Slip Buffer" as illustrated below.
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FIGURE 44. AN ILLUSTRATION OF AN STS-1 SIGNAL BEING PROCESSED VIA A SLIP BUFFER
Clock Domain operating
At frequency f1
STS-1 Data_IN
STS-1 Data_OUT
STS-1 Clock_f2
SLIP BUFFER
STS-1 Clock_f1
Clock Domain operating
At Frequency f2.
In the "Slip Buffer, the "input" STS-1 data (labeled "STS-1 Data_IN") is latched into the FIFO, upon a given
edge of the corresponding "STS-1 Clock_f1" input clock signal. The STS-1 Data (labeled "STS-1 Data_OUT")
is clocked out of the Slip Buffer upon a given edge of the "STS-1 Clock_f2" input clock signal.
The behavior of the data, passing through the "Slip Buffer" is now described for each possible relationship
between frequencies f1 and f2.
If f1 = f2
If both frequencies, f1 and f2 are exactly equal, then the STS-1 data will be "clocked" into the "Slip Buffer" at
exactly the same rate that it is "clocked out". In this case, the "Slip Buffer" will neither fill-up nor become
depleted. As a consequence, no pointer-adjustments will occur in this STS-1 data stream. In other words, the
STS-1 SPE will remain at a constant location (or offset) within each STS-1 envelope capacity for the duration
that this STS-1 signal is supporting this particular service.
If f1 < f2
If frequency f1 is less than f2, then this means that the STS-1 data is being "clocked out" of the "Slip Buffer" at
a faster rate than it is being clocked in. In this case, the "Slip Buffer" will eventually become depleted.
Whenever this occurs, a typical strategy is to "stuff" (or insert) a "dummy byte" into the data stream. The
purpose of stuffing this "dummy byte" is to compensate for the frequency differences between f1 and f2, and
attempt to keep the "Slip Buffer, at a somewhat constant fill level.
NOTE: This "dummy byte" does not carry any valuable information (not for the user, nor for the system).
Since this "dummy byte" carries no useful information, it is important that the "Receiving PTE" be notified
anytime this "dummy byte" stuffing occurs. This way, the Receiving Terminal can "know" not to treat this
"dummy byte" as user data.
Byte-Stuffing and Pointer Incrementing in a SONET Network
Whenever this "byte-stuffing" occurs then the following other things occur within the STS-1 data stream.
During the STS-1 frame that contains the "Byte-Stuffing" event
a. The "stuff-byte" will be inserted into the byte position immediately after the H3 byte. This insertion of the
"dummy byte" immediately after the H3 byte position will cause the J1 byte (and in-turn, the rest of the
SPE) to be "byte-shifted" away from the H3 byte. As a consequence, the offset between the H3 byte posi-
tion and the STS-1 SPE will now have been increased by 1 byte.
b. The "Transmitting" Network Equipment will notify the remote terminal of this byte-stuffing event, by invert-
ing certain bits within the "pointer word" (within the H1 and H2 bytes) that are referred to as "I" bits.
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Figure 45 presents an illustration of the bit-format within the 16-bit word (consist of the H1 and H2 bytes) with
the "I" bits designated.
FIGURE 45. AN ILLUSTRATION OF THE BIT FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2
BYTES) WITH THE "I" BITS DESIGNATED
H1 Byte
H2 Byte
MSB
LSB
N N N N S S I D I D I D I D I D
10 Bit Pointer Expression
NOTE: At this time the "I" bits are inverted in order to denote that an "incrementing" pointer adjustment event is currently
occurring.
During the STS-1 frame that follows the "Byte-Stuffing" event
The "I" bits (within the "pointer-word") will be set back to their normal value; and the contents of the H1 and H2
bytes will be incremented by "1".
If f1 > f2
If frequency f1 is greater than f2, then this means that the STS-1 data is being clocked into the "Slip Buffer" at
a faster rate than is being clocked out. In this case, the "Slip Buffer" will start to fill up. Whenever this occurs,
a typical strategy is to delete (e.g., negative-stuff) a byte from the Slip Buffer. The purpose of this "negative-
stuffing" is to compensate for the frequency differences between f1 and f2; and to attempt to keep the "Slip
Buffer" at a somewhat constant fill-level.
NOTE: This byte, which is being "un-stuffed" does carry valuable information for the user (e.g., this byte is typically a
payload byte). Therefore, whenever this negative stuffing occurs, two things must happen.
a. The "negative-stuffed" byte must not be simply discarded. In other words, it must somehow also be
transmitted to the remote PTE with the remainder of the SPE data.
b. The remote PTE must be notified of the occurrence of these "negative-stuffing" events. Further, the
remote PTE must know where to obtain this "negative-stuffed" byte.
Negative-Stuffing and Pointer-Decrementing in a SONET Network
Whenever this "byte negative-stuffing" occurs then the following other things occur within the STS-1 data-
stream.
During the STS-1 frame that contains the "Negative Byte-Stuffing" Event
a. The "Negative-Stuffed" byte will be inserted into the H3 byte position. Whenever an SPE data byte is
inserted into the H3 byte position (which is ordinarily an unused byte), the number of bytes that will exist
between the H3 byte and the J1 byte within the very next SPE will be reduced by 1 byte. As a
consequence, in this case, the J1 byte (and in-turn, the rest of the SPE) will now be "byte-shifted"
towards the H3 byte position.
b. The "Transmitting" Network Element will notify the remote terminal of this "negative-stuff" event by
inverting certain bits within the "pointer word" (within the H1 and H2 bytes) that are referred to as "D"
bits.
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Figure 46 presents an illustration of the bit format within the 16-bit word (consisting of the H1 and H2 bytes)
with the "D" bits designated.
FIGURE 46. AN ILLUSTRATION OF THE BIT-FORMAT WITHIN THE 16-BIT WORD (CONSISTING OF THE H1 AND H2
BYTES) WITH THE "D" BITS DESIGNATED
H1 Byte
H2 Byte
MSB
LSB
N N N N S S I D I D I D I D I D
10 Bit Pointer Expression
NOTE: At this time the "D" bits are inverted in order to denote that a "decrementing" pointer adjustment event is currently
occurring.
During the STS-1 frame that follows the "Negative Byte-Stuffing" Event
The "D" bits (within the pointer-word) will be set back to their normal value; and the contents of the H1 and H2
bytes will be decremented by one.
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9.3.4
Why are we talking about Pointer Adjustments?
The overall SONET network consists of numerous "Synchronization Islands". As a consequence, whenever a
SONET signal is being transmitted from one "Synchronization Island" to another; that SONET signal will
undergo a "clock domain" change as it traverses the network. This clock domain change will result in periodic
pointer-adjustments occurring within this SONET signal. Depending upon the direction of this "clock-domain"
shift that the SONET signal experiences, there will either be periodic "incrementing" pointer-adjustment events
or periodic "decrementing" pointer-adjustment events within this SONET signal.
Regardless of whether a given SONET signal is experiencing incrementing or decrementing pointer
adjustment events, each pointer adjustment event will result in an abrupt 8-bit shift in the position of the SPE
within the STS-1 data-stream. If this STS-1 signal is transporting an "asynchronously-mapped" DS3 signal;
then this 8-bit shift in the location of the SPE (within the STS-1 signal) will result in approximately 8UIpp of jitter
within the asynchronously-mapped DS3 signal, as it is de-mapped from SONET. In “Section 9.5, A Review of
the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications” on page 68
we will discuss the "Category I Intrinsic Jitter Requirements (for DS3 Applications) per Telcordia GR-253-
CORE. However, for now we will simply state that this 8UIpp of intrinsic jitter far exceeds these "intrinsic jitter"
requirements.
In summary, pointer-adjustments events are a "fact of life" within the SONET/SDH network. Further, pointer-
adjustment events, within a SONET signal that is transporting an asynchronously-mapped DS3 signal, will
impose a significant impact on the Intrinsic Jitter and Wander within that DS3 signal as it is de-mapped from
SONET.
9.4
Clock Gapping Jitter
In most applications (in which the LIU will be used in a SONET De-Sync Application) the user will typically
interface the LIU to a Mapper Device in the manner as presented below in Figure 47.
FIGURE 47. ILLUSTRATION OF THE TYPICAL APPLICATIONS FOR THE LIU IN A SONET DE-SYNC APPLICATION
De-Mapped (Gapped)
DS3 Data and Clock
TPDATA_n input pin
DS3 to STS-N
Mapper/
Demapper
IC
LIU
STS-N Signal
TCLK_n input
In this application, the Mapper IC will have the responsibility of receiving an STS-N signal (from the SONET
Network) and performing all of the following operations on this STS-N signal.
• Byte-de-interleaving this incoming STS-N signal into N STS-1 signals
• Terminating each of these STS-1 signals
• Extracting (or de-mapping) the DS3 signal(s) from the SPEs within each of these terminated STS-1 signals.
In this application, these Mapper devices can be thought of as multi-channel devices. For example, an STS-3
Mapper can be viewed as a 3-Channel DS3/STS-1 to STS-3 Mapper IC. Similarly, an STS-12 Mapper can be
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viewed as a 12-Channel DS3/STS-1 to STS-12 Mapper IC. Continuing on with this line of thought, if a Mapper
IC is configured to receive an STS-N signal, and (from this STS-N signal) de-map and output N DS3 signals
(towards the DS3 facility), then it will typically do so in the following manner.
• In many cases, the Mapper IC will output this DS3 signal, using both a "Data-Signal" and a "Clock-Signal".
In many cases, the Mapper IC will output the contents of an entire STS-1 data-stream via the Data-Signal.
• However, as the Mapper IC output this STS-1 data-stream, it will typically supply clock pulses (via the Clock-
Signal output) coincident to whenever a DS3 bit is being output via the Data-Signal. In this case, the Mapper
IC will NOT supply a clock pulse coincident to when a TOH, POH, or any "non-DS3 data-bit" is being output
via the "Data-Signal".
Now, since the Mapper IC will output the entire STS-1 data stream (via the Data-Signal), the output Clock-
Signal will be of the form such that it has a period of 19.3ns (e.g., a 51.84MHz clock signal). However, the
Mapper IC will still generate approximately 44,736,000 clock pulses during any given one second period.
Hence, the clock signal that is output from the Mapper IC will be a horribly gapped 44.736MHz clock signal.
One can view such a clock signal as being a very-jittery 44.736MHz clock signal. This jitter that exists within
the "Clock-Signal" is referred to as "Clock-Gapping" Jitter. A more detailed discussion on how the user must
handle this type of jitter is presented in “Section 9.8.2, Recommendations on Pre-Processing the Gapped
Clocks (from the Mapper/ASIC Device) prior to routing this DS3 Clock and Data-Signals to the Transmit Inputs
of the LIU” on page 79.
9.5
A Review of the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3
applications
The "Category I Intrinsic Jitter Requirements" per Telcordia GR-253-CORE (for DS3 applications) mandates
that the user perform a large series of tests against certain specified "Scenarios". These "Scenarios" and their
corresponding requirements is summarized in Table 18, below.
TABLE 18: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3
APPLICATIONS
TELCORDIA GR-253-CORE
CATEGORY I INTRINSIC
SCENARIO
SCENARIO
NUMBER
COMMENTS
DESCRIPTION
JITTER REQUIREMENTS
DS3 De-Mapping
Jitter
0.4UI-pp
Includes effects of De-Mapping and Clock Gapping Jitter
Single Pointer
Adjustment
A1
0.3UI-pp + Ao
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.NOTE: Ao is the amount
of intrinsic jitter that was measured during the "DS3 De-
Mapping Jitter" phase of the Test.
Pointer Bursts
Phase Transients
87-3 Pattern
A2
A3
A4
A5
A5
A4
1.3UI-pp
1.2UI-pp
1.0UI-pp
1.3UI-pp
1.3UI-pp
1.0UI-pp
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
87-3 Add
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
87-3 Cancel
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
Continuous Pattern
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
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TABLE 18: SUMMARY OF "CATEGORY I INTRINSIC JITTER REQUIREMENT PER TELCORDIA GR-253-CORE, FOR DS3
APPLICATIONS
TELCORDIA GR-253-CORE
CATEGORY I INTRINSIC
SCENARIO
SCENARIO
NUMBER
COMMENTS
DESCRIPTION
JITTER REQUIREMENTS
Continuous Add
A5
A5
1.3UI-pp
1.3UI-pp
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
Continuous Cancel
Includes effects of Jitter from Clock-Gapping, De-Map-
ping and Pointer Adjustments.
NOTE: All of these intrinsic jitter measurements are to be performed using a band-pass filter of 10Hz to 400kHz.
Each of the scenarios presented in Table 18, are briefly described below.
9.5.1
DS3 De-Mapping Jitter
DS3 De-Mapping Jitter is the amount of Intrinsic Jitter that will be measured within the "Line" or "Facility-side"
DS3 signal, (after it has been de-mapped from a SONET signal) without the occurrence of "Pointer
Adjustments" within the SONET signal.
Telcordia GR-253-CORE requires that the "DS3 De-Mapping" Jitter be less than 0.4UI-pp, when measured
over all possible combinations of DS3 and STS-1 frequency offsets.
9.5.2
Single Pointer Adjustment
Telcordia GR-253-CORE states that if each pointer adjustment (within a continuous stream of pointer
adjustments) is separated from each other by a period of 30 seconds, or more; then they are sufficiently
isolated to be considered "Single-Pointer Adjustments".
Figure 48 presents an illustration of the "Single Pointer Adjustment" Scenario.
FIGURE 48. ILLUSTRATION OF SINGLE POINTER ADJUSTMENT SCENARIO
Pointer Adjustment Events
>30s
Initialization
Cool Down
Measurement Period
Telcordia GR-253-CORE states that the Intrinsic Jitter that is measured (within the DS3 signal) that is
ultimately de-mapped from a SONET signal that is experiencing "Single-Pointer Adjustment" events, must
NOT exceed the value 0.3UI-pp + Ao.
NOTES:
1. Ao is the amount of Intrinsic Jitter that was measured during the "De-Mapping" Jitter portion of this test.
2. Testing must be performed for both Incrementing and Decrementing Pointer Adjustments.
9.5.3
Pointer Burst
Figure 49 presents an illustration of the "Pointer Burst" Pointer Adjustment Scenario per Telcordia GR-253-
CORE.
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FIGURE 49. ILLUSTRATION OF BURST OF POINTER ADJUSTMENT SCENARIO
Pointer Adjustment Events
Pointer Adjustment Burst Train
t
0.5ms
0.5ms
>30s
Initialization
Cool Down
Measurement Period
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a
SONET signal, which is experiencing the "Burst of Pointer Adjustment" scenario, must NOT exceed 1.3UI-pp.
9.5.4
Phase Transients
Figure 50 presents an illustration of the "Phase Transients" Pointer Adjustment Scenario per Telcordia GR-
253-CORE.
FIGURE 50. ILLUSTRATION OF "PHASE-TRANSIENT" POINTER ADJUSTMENT SCENARIO
Pointer Adjustment Events
Pointer Adjustment Burst Train
0.5s
0.25s
0.25s
t
>30s
Initialization
Cool Down
Measurement Period
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a
SONET signal, which is experiencing the "Phase Transient - Pointer Adjustment" scenario must NOT exceed
1.2UI-pp.
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9.5.5
87-3 Pattern
Figure 51 presents an illustration of the "87-3 Continuous Pattern" Pointer Adjustment Scenario per Telcordia
GR-253-CORE.
FIGURE 51. AN ILLUSTRATION OF THE 87-3 CONTINUOUS POINTER ADJUSTMENT PATTERN
Repeating 87-3 Pattern (see below)
Pointer Adjustment Events
Initialization
Measurement Period
87-3 Pattern
No Pointer
Adjustments
87 Pointer Adjustment Events
NOTE: T ranges from 34ms to 10s (Req)
T ranges from 7.5ms to 34ms (Obj)
T
Telcordia GR-253-CORE defines an "87-3 Continuous" Pointer Adjustment pattern, as a repeating sequence of
90 pointer adjustment events. Within this 90 pointer adjustment event, 87 pointer adjustments are actually
executed. The remaining 3 pointer adjustments are never executed. The spacing between individual pointer
adjustment events (within this scenario) can range from 7.5ms to 10seconds.
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a
SONET signal, which is experiencing the "87-3 Continuous" pattern of Pointer Adjustments, must not exceed
1.0UI-pp.
9.5.6
87-3 Add
Figure 52 presents an illustration of the "87-3 Add Pattern" Pointer Adjustment Scenario per Telcordia GR-253-
CORE.
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FIGURE 52. ILLUSTRATION OF THE 87-3 ADD POINTER ADJUSTMENT PATTERN
Added Pointer Adjustment
No Pointer
Adjustments
43 Pointer Adjustments
43 Pointer Adjustments
T
t
Telcordia GR-253-CORE defines an "87-3 Add" Pointer Adjustment, as the "87-3 Continuous" Pointer
Adjustment pattern, with an additional pointer adjustment inserted, as shown above in Figure 52.
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a
SONET signal, which is experiencing the "87-3 Add" pattern of Pointer Adjustments, must not exceed 1.3UI-
pp.
9.5.7
87-3 Cancel
Figure 53 presents an illustration of the 87-3 Cancel Pattern Pointer Adjustment Scenario per Telcordia GR-
253-CORE.
FIGURE 53. ILLUSTRATION OF 87-3 CANCEL POINTER ADJUSTMENT SCENARIO
No Pointer
Adjustments
86 or 87 Pointer Adjustments
T
Cancelled
Pointer Adjustment
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Telcordia GR-253-CORE defines an "87-3 Cancel" Pointer Adjustment, as the "87-3 Continuous" Pointer
Adjustment pattern, with an additional pointer adjustment cancelled (or not executed), as shown above in
Figure 53.
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a
SONET signal, which is experiencing the "87-3 Cancel" pattern of Pointer Adjustments, must not exceed
1.3UI-pp.
9.5.8
Continuous Pattern
Figure 54 presents an illustration of the "Continuous" Pointer Adjustment Scenario per Telcordia GR-253-
CORE.
FIGURE 54. ILLUSTRATION OF CONTINUOUS PERIODIC POINTER ADJUSTMENT SCENARIO
Repeating Continuous Pattern (see below)
Pointer Adjustment Events
Initialization
Measurement Period
T
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a
SONET signal, which is experiencing the "Continuous" pattern of Pointer Adjustments, must not exceed 1.0UI-
pp. The spacing between individual pointer adjustments (within this scenario) can range from 7.5ms to 10s.
9.5.9
Continuous Add
Figure 55 presents an illustration of the "Continuous Add Pattern" Pointer Adjustment Scenario per Telcordia
GR-253-CORE.
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FIGURE 55. ILLUSTRATION OF CONTINUOUS-ADD POINTER ADJUSTMENT SCENARIO
Added Pointer Adjustment
Continuous Pointer Adjustments
Continuous Pointer Adjustments
T
t
Telcordia GR-253-CORE defines an "Continuous Add" Pointer Adjustment, as the "Continuous" Pointer
Adjustment pattern, with an additional pointer adjustment inserted, as shown above in Figure 55.
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a
SONET signal, which is experiencing the "Continuous Add" pattern of Pointer Adjustments, must not exceed
1.3UI-pp.
9.5.10 Continuous Cancel
Figure 56 presents an illustration of the "Continuous Cancel Pattern" Pointer Adjustment Scenario per
Telcordia GR-253-CORE.
FIGURE 56. ILLUSTRATION OF CONTINUOUS-CANCEL POINTER ADJUSTMENT SCENARIO
Continuous Pointer Adjustments
T
Cancelled
Pointer Adjustment
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Telcordia GR-253-CORE defines a "Continuous Cancel" Pointer Adjustment, as the "Continuous" Pointer
Adjustment pattern, with an additional pointer adjustment cancelled (or not executed), as shown above in
Figure 56.
Telcordia GR-253-CORE mandates that the Intrinsic Jitter, within the DS3 signal that is de-mapped from a
SONET signal, which is experiencing the "Continuous Cancel" pattern of Pointer Adjustments, must not
exceed 1.3UI-pp.
9.6
A Review of the DS3 Wander Requirements per ANSI T1.105.03b-1997.
To be provided in the next revision of this data sheet.
9.7
A Review of the Intrinsic Jitter and Wander Capabilities of the LIU in a typical system
application
The Intrinsic Jitter and Wander Test results are summarized in this section.
9.7.1 Intrinsic Jitter Test results
The Intrinsic Jitter Test results for the LIU in DS3 being de-mapped from SONET is summarized below in Table
2.
TABLE 19: SUMMARY OF "CATEGORY I INTRINSIC JITTER TEST RESULTS" FOR SONET/DS3 APPLICATIONS
SCENARIO
SCENARIO
NUMBER
LIU
TELCORDIA GR-253-CORE CATEGORY I
INTRINSIC JITTER REQUIREMENTS
DESCRIPTION
INTRINSIC JITTER TEST RESULTS
DS3 De-Mapping
Jitter
0.13UI-pp
0.4UI-pp
Single Pointer
Adjustment
A1
0.201UI-pp
0.43UI-pp (e.g. 0.13UI-pp + 0.3UI-pp)
Pointer Bursts
Phase Transients
87-3 Pattern
87-3 Add
A2
A3
A4
A5
A5
A4
0.582UI-pp
0.526UI-pp
0.790UI-pp
0.926UI-pp
0.885UI-pp
0.497UI-pp
1.3UI-pp
1.2UI-pp
1.0UI-pp
1.3UI-pp
1.3UI-pp
1.0UI-pp
87-3 Cancel
Continuous
Pattern
Continuous Add
A5
A5
0.598UI-pp
0.589UI-pp
1.3UI-pp
1.3UI-pp
Continuous
Cancel
NOTES:
1. A detailed test report on our Test Procedures and Test Results is available and can be obtained by contacting your
Exar Sales Representative.
2. These test results were obtained via the LIUs mounted on our XRT94L43 12-Channel DS3/E3/STS-1 Mapper
Evaluation Board.
3. These same results apply to SDH/AU-3 Mapping applications.
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9.7.2
Wander Measurement Test Results
Wander Measurement test results will be provided in the next revision of the LIU Data Sheet.
9.8 Designing with the LIU
In this section, we will discuss the following topics.
• How to design with and configure the LIU to permit a system to meet the above-mentioned Intrinsic Jitter and
Wander requirements.
• How is the LIU able to meet the above-mentioned requirements?
• How does the LIU permits the user to comply with the SONET APS Recovery Time requirements of 50ms
(per Telcordia GR-253-CORE)?
• How should one configure the LIU, if one needs to support "Daisy-Chain" Testing at the end Customer’s site?
9.8.1
How to design and configure the LIU to permit a system to meet the above-mentioned
Intrinsic Jitter and Wander requirements
As mentioned earlier, in most application (in which the LIU will be used in a SONET De-Sync Application) the
user will typically interface the LIU to a Mapper device in the manner as presented below in Figure 57.
In this application, the Mapper has the responsibility of receiving a SONET STS-N/OC-N signal and extracting
as many as N DS3 signals from this signal. As a given channel within the Mapper IC extracts out a given DS3
signal (from SONET) it will typically be applying a Clock and Data signal to the "Transmit Input" of the LIU IC.
Figure 57 presents a simple illustration as to how one channel, within the LIU should be connected to the
Mapper IC.
FIGURE 57. ILLUSTRATION OF THE LIU BEING CONNECTED TO A MAPPER IC FOR SONET DE-SYNC APPLICATIONS
De-Mapped (Gapped)
DS3 Data and Clock
TPDATA_n input pin
DS3 to STS-N
Mapper/
Demapper
IC
LIU
STS-N Signal
TCLK n input
As mentioned above, the Mapper IC will typically output a Clock and Data signal to the LIU. In many cases,
the Mapper IC will output the contents of an entire STS-1 data-stream via the Data Signal to the LIU. However,
the Mapper IC typically only supplies a clock pulse via the Clock Signal to the LIU coincident to whenever a
DS3 bit is being output via the Data Signal. In this case, the Mapper IC would not supply a clock edge
coincident to when a TOH, POH or any non-DS3 data-bit is being output via the Data-Signal.
Figure 57 indicates that the Data Signal from the Mapper device should be connected to the TPDATA_n input
pin of the LIU IC and that the Clock Signal from the Mapper device should be connected to the TCLK_n input
pin of the LIU IC.
In this application, the LIU has the following responsibilities.
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• Using a particular clock edge within the "gapped" clock signal (from the Mapper IC) to sample and latch the
value of each DS3 data-bit that is output from the Mapper IC.
• To (through the user of the Jitter Attenuator block) attenuate the jitter within this "DS3 data" and "clock signal"
that is output from the Mapper IC.
• To convert this "smoothed" DS3 data and clock into industry-compliant DS3 pulses, and to output these
pulses onto the line.
To configure the LIU to operate in the correct mode for this application, the user must execute the following
configuration steps.
a. Configure the LIU to operate in the DS3 Mode
The user can configure a given channel (within the LIU) to operate in the DS3 Mode, by executing either of the
following steps.
• If the LIU has been configured to operate in the Host Mode
The user can accomplish this by setting both Bits 2 (E3_n) and Bits 1 (STS-1/DS3*_n), within each of the
"Channel Control Registers" to "0" as depicted below.
CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06
CHANNEL 1 ADDRESS LOCATION = 0X0E
CHANNEL 2 ADDRESS LOCATION = 0X16
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
PRBS Enable
Ch_n
RLB_n
LLB_n
E3_n
STS-1/DS3_n
SR/DR_n
R/O
0
R/O
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• If the LIU has been configured to operate in the Hardware Mode
The user can accomplish this by pulling all of the following input pins "Low".
Pin 76 - E3_0
Pin 94 - E3_1
Pin 85 - E3_2
Pin 72 - STS-1/DS3_0
Pin 98 - STS-1/DS3_1
Pin 81 - STS-1/DS3_2
b. Configure the LIU to operate in the Single-Rail Mode
Since the Mapper IC will typically output a single "Data Line" and a "Clock Line" for each DS3 signal that it
demaps from the incoming STS-N signal, it is imperative to configure each channel within the LIU to operate in
the Single Rail Mode.
The user can accomplish this by executing either of the following steps.
• If the LIU has been configured to operate in the Host Mode
The user can accomplish this by setting Bit 0 (SR/DR*), within the each of the "Channel Control" Registers to
1, as illustrated below.
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CHANNEL CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X06
CHANNEL 1 ADDRESS LOCATION = 0X0E
CHANNEL 2 ADDRESS LOCATION = 0X16
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
PRBS Enable
Ch_n
RLB_n
LLB_n
E3_n
STS-1/
DS3_n
SR/DR_n
R/O
0
R/O
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
• If the LIU has been configured to operate in the Hardware Mode
Then the user should tie the (SR/DR*) pin to "High".
c. Configure each of the channels within the LIU to operate in the SONET De-Sync Mode
The user can accomplish this by executing either of the following steps.
• If the LIU has been configured to operate in the Host Mode.
Then the user should set Bit D2 (JA0) to "0" and Bit D0 (JA1) to "1", within the Jitter Attenuator Control
Register, as depicted below.
JITTER ATTENUATOR CONTROL REGISTER - (CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
SONET APS JA RESET
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
Recovery
Time
Ch_n
DisableCh_n
R/O
0
R/O
0
R/O
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
• If the LIU has been configured to operate in the Hardware Mode
Then the user should tie pin 44 (JA0) to a logic "HIGH" and pin 42 (JA1) to a logic "LOW".
Once the user accomplishes either of these steps, then the Jitter Attenuator (within the LIU) will be configured
to operate with a very narrow bandwidth.
d. Configure the Jitter Attenuator (within each of the channels) to operate in the Transmit Direction.
The user can accomplish this by executing either the following steps.
• If the LIU has been configured to operate in the Host Mode.
Then the user should be Bit D1 (JATx/JARx*) to "1", within the Jitter Attenuator Control Register, as depicted
below.
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JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
SONET APS JA RESET
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
Recovery
Time
Ch_n
DisableCh_n
R/O
0
R/O
0
R/O
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
1
• If the LIU has been configured to operate in the Hardware Mode.
Then the user should tie pin 43 (JATx/JARx*) to "1".
e. Enable the "SONET APS Recovery Time" Mode
Finally, if the user intends to use the LIU in an Application that is required to reacquire proper SONET and DS3
traffic, prior within 50ms of an APS (Automatic Protection Switching) event (per Telcordia GR-253-CORE), then
the user should set Bit 4 (SONET APS Recovery Time Disable), within the "Jitter Attenuator Control" Register,
to "0" as depicted below.
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
SONET APS JA RESET
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
Recovery
Time
Ch_n
DisableCh_n
R/O
0
R/O
0
R/O
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
NOTES:
1. The ability to disable the "SONET APS Recovery Time" mode is only available if the LIU is operating in the Host
Mode. If the LIU is operating in the "Hardware" Mode, then this "SONET APS Recovery Time Mode" feature will
always be enabled.
2. The "SONET APS Recovery Time" mode will be discussed in greater detail in “Section 9.8.3, How does the LIU
permit the user to comply with the SONET APS Recovery Time requirements of 50ms (per Telcordia GR-253-
CORE)?” on page 83.
9.8.2
Recommendations on Pre-Processing the Gapped Clocks (from the Mapper/ASIC Device)
prior to routing this DS3 Clock and Data-Signals to the Transmit Inputs of the LIU
In order to minimize the effects of "Clock-Gapping" Jitter within the DS3 signal that is ultimately transmitted to
the DS3 Line (or facility), we recommend that some "pre-processing" of the "Data-Signals" and "Clock-Signals"
(which are output from the Mapper device) be implemented prior to routing these signals to the "Transmit
Inputs" of the LIU.
9.8.2.1
SOME NOTES PRIOR TO STARTING THIS DISCUSSION:
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Our simulation results indicate that Jitter Attenuator PLL (within the LIU LIU IC) will have no problem handling
and processing the "Data-Signal" and "Clock-Signal" from a Mapper IC/ASIC if no pre-processing has been
performed on these signals. In order words, our simulation results indicate that the Jitter Attenuator PLL
(within the LIU IC) will have no problem handling the "worst-case" of 59 consecutive bits of no clock pulses in
the "Clock-Signal (due to the Mapper IC processing the TOH bytes, an Incrementing Pointer-Adjustment-
induced "stuffed-byte", the POH byte, and the two fixed-stuff bytes within the STS-1 SPE, etc), immediately
followed be processing clusters of DS3 data-bits (as shown in Figure 37) and still comply with the "Category I
Intrinsic Jitter Requirements per Telcordia GR-253-CORE for DS3 applications.
NOTE: If this sort of "pre-processing" is already supported by the Mapper device that you are using, then no further action
is required by the user.
9.8.2.2
OUR PRE-PROCESSING RECOMMENDATIONS
For the time-being, we recommend that the customer implement the "pre-processing" of the DS3 "Data-Signal"
and "Clock-Signal" as described below. Currently we are aware that some of the Mapper products on the
Market do implement this exact "pre-processing" algorithm. However, if the customer is implementing their
Mapper Design in an ASIC or FPGA solution, then we strongly recommend that the user implement the
necessary logic design to realize the following recommendations.
Some time ago, we spent some time, studying (and then later testing our solution with) the PM5342 OC-3 to
DS3 Mapper IC from PMC-Sierra. In particular, we wanted to understand the type of "DS3 Clock" and "Data"
signal that this DS3 to OC-3 Mapper IC outputs.
During this effort, we learned the following.
1. This "DS3 Clock" and "Data" signal, which is output from the Mapper IC consists of two major "repeating"
patterns (which we will refer to as "MAJOR PATTERN A" and "MAJOR PATTERN B". The behavior of
each of these patterns is presented below.
MAJOR PATTERN A
MAJOR PATTERN A consists of two "sub" or minor-patterns, (which we will refer to as "MINOR PATTERN P1
and P2).
MINOR PATTERN P1 consists of a string of seven (7) clock pulses, followed by a single gap (no clock pulse).
An illustration of MINOR PATTERN P1 is presented below in Figure 58.
FIGURE 58. ILLUSTRATION OF MINOR PATTERN P1
Missing Clock Pulse
1
2
3
4
5
6
7
It should be noted that each of these clock pulses has a period of approximately 19.3ns (or has an
"instantaneously frequency of 51.84MHz).
MINOR Pattern P2 consists of string of five (5) clock pulses, which is also followed by a single gap (no clock
pulse). An illustration of Pattern P2 is presented below in Figure 59.
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FIGURE 59. ILLUSTRATION OF MINOR PATTERN P2
Missing Clock Pulse
1
2
3
4
5
HOW MAJOR PATTERN A IS SYNTHESIZED
MAJOR PATTERN A is created (by the Mapper IC) by:
• Repeating MINOR PATTERN P1 (e.g., 7 clock pulses, followed by a gap) 63 times.
• Upon completion of the 63rd transmission of MINOR PATTERN P1, MINOR PATTERN P2 is transmitted
repeatedly 36 times.
Figure 60 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN A
FIGURE 60. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE MAJOR PATTERN A
Repeats 63 Times
Repeats 36 Times
MINOR PATTERN P1
MINOR PATTERN P2
Hence, MAJOR PATTERN A consists of "(63 x 7) + (36 x 5)" = 621 clock pulses. These 621 clock pulses were
delivered over a period of "(63 x 8) + (36 x 6)" = 720 STS-1 (or 51.84MHz) clock periods.
MAJOR PATTERN B
MAJOR PATTERN B consists of three sub or minor-patterns (which we will refer to as "MINOR PATTERNS P1,
P2 and P3).
MINOR PATTERN P1, which is used to partially synthesize MAJOR PATTERN B, is exactly the same "MINOR
PATTERN P1" as was presented above in Figure 30. Similarly, the MINOR PATTERN P2, which is also used
to partially synthesize MAJOR PATTERN B, is exactly the same "MINOR PATTERN P2" as was presented in
Figure 31.
MINOR PATTERN P3 (which has yet to be defined) consists of a string of six (6) clock pulses, which contains
no gaps. An illustration of MINOR PATTERN P3 is presented below in Figure 61.
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FIGURE 61. ILLUSTRATION OF MINOR PATTERN P3
1
2
3
4
5
6
HOW MAJOR PATTERN B IS SYNTHESIZED
MAJOR PATTERN B is created (by the Mapper IC) by:
• Repeating MINOR PATTERN P1 (e.g., 7 clock pulses, followed by a gap) 63 times.
• Upon completion of the 63rd transmission of MINOR PATTERN P1, MINOR PATTERN P2 is transmitted
repeatedly 36 times.
• pon completion of the 35th transmission of MINOR PATTERN P2, MINOR PATTERN P3 is transmitted once.
Figure 62 presents an illustration which depicts the procedure that is used to synthesize MAJOR PATTERN B.
FIGURE 62. ILLUSTRATION OF PROCEDURE WHICH IS USED TO SYNTHESIZE PATTERN B
Transmitted 1 Time
Repeats 63 Times
PATTERN P1
Repeats 35 Times
PATTERN P2
PATTERN P3
Hence, MAJOR PATTERN B consists of "(63 x 7) + (35 x 5)" + 6 = 622 clock pulses.
These 622 clock pulses were delivered over a period of "(63 x 8) + (35 x 6) + 6 = 720 STS-1 (or 51.84MHz)
clock periods.
PUTTING THE PATTERNS TOGETHER
Finally, the DS3 to OC-N Mapper IC clock output is reproduced by doing the following.
• MAJOR PATTERN A is transmitted two times (repeatedly).
• After the second transmission of MAJOR PATTERN A, MAJOR PATTERN B is transmitted once.
• Then the whole process repeats.
Throughout the remainder of this document, we will refer to this particular pattern as the "SUPER PATTERN".
Figure 63 presents an illustration of this "SUPER PATTERN" which is output via the Mapper IC.
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FIGURE 63. ILLUSTRATION OF THE SUPER PATTERN WHICH IS OUTPUT VIA THE "OC-N TO DS3" MAPPER IC
PATTERN A
PATTERN A
PATTERN B
CROSS-CHECKING OUR DATA
• Each SUPER PATTERN consists of (621 + 621 + 622) = 1864 clock pulses.
• The total amount of time, which is required for the "DS3 to OC-N Mapper" IC to transmit this SUPER
PATTERN is (720 + 720 + 720) = 2160 "STS-1" clock periods.
• This amount to a period of (2160/51.84MHz) = 41,667ns.
• In a period of 41, 667ns, the LIU (when configured to operate in the DS3 Mode), will output a total (41,667ns
x 44,736,000) = 1864 uniformly spaced DS3 clock pulses.
• Hence, the number of clock pulses match.
APPLYING THE SUPER PATTERN TO THE LIU
Whenever the LIU is configured to operate in a "SONET De-Sync" application, the device will accept a
continuous string of the above-defined SUPER PATTERN, via the TCLK input pin (along with the
corresponding data). The channel within the LIU (which will be configured to operate in the "DS3" Mode) will
output a DS3 line signal (to the DS3 facility) that complies with the "Category I Intrinsic Jitter Requirements -
per Telcordia GR-253-CORE (for DS3 applications). This scheme is illustrated below in Figure 64.
FIGURE 64. SIMPLE ILLUSTRATION OF THE LIU BEING USED IN A SONET DE-SYNCHRONIZER" APPLICATION
De-Mapped (Gapped)
DS3 Data and Clock
TPDATA_n input pin
DS3 to STS-N
Mapper/
Demapper
IC
LIU
STS-N Signal
TCLK_n input
9.8.3
How does the LIU permit the user to comply with the SONET APS Recovery Time
requirements of 50ms (per Telcordia GR-253-CORE)?
Telcordia GR-253-CORE, Section 5.3.3.3 mandates that the "APS Completion" (or Recovery) time be 50ms or
less. Many of our customers interpret this particular requirement as follows.
"From the instant that an APS is initiated on a high-speed SONET signal, all lower-speed SONET traffic (which
is being transported via this "high-speed" SONET signal) must be fully restored within 50ms. Similarly, if the
"high-speed" SONET signal is transporting some PDH signals (such as DS1 or DS3, etc.), then those entities
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that are responsible for acquiring and maintaining DS1 or DS3 frame synchronization (with these DS1 or DS3
data-streams that have been de-mapped from SONET) must have re-acquired DS1 or DS3 frame
synchronization within 50ms" after APS has been initiated."
The LIU was designed such that the DS3 signals that it receives from a SONET Mapper device and processes
will comply with the Category I Intrinsic Jitter requirements per Telcordia GR-253-CORE.
Reference 1 documents some APS Recovery Time testing, which was performed to verify that the Jitter
Attenuator blocks (within the LIU) device that permit it to comply with the Category I Intrinsic Jitter
Requirements (for DS3 Applications) per Telcordia GR-253-CORE, do not cause it to fail to comply with the
"APS Completion Time" requirements per Section 5.3.3.3 of Telcordia GR-253-CORE. However, Table 3
presents a summary of some APS Recovery Time requirements that were documented within this test report.
Table 3,
TABLE 20: MEASURED APS RECOVERY TIME AS A FUNCTION OF DS3 PPM OFFSET
DS3 PPM OFFSET (PER W&G ANT-20SE)
MEASURED APS RECOVERY TIME (PER LOGIC ANALYZER)
-99 ppm
-40ppm
-30 ppm
-20 ppm
-10 ppm
0 ppm
1.25ms
1.54ms
1.34ms
1.49ms
1.30ms
1.89ms
1.21ms
1.64ms
1.32ms
1.25ms
1.35ms
+10 ppm
+20 ppm
+30 ppm
+40 ppm
+99 ppm
NOTE: The APS Completion (or Recovery) time requirement is 50ms.
Configuring the LIU to be able to comply with the SONET APS Recovery Time Requirements of 50ms
Quite simply, the user can configure a given Jitter Attenuator block (associated with a given channel) to (1)
comply with the "APS Completion Time" requirements per Telcordia GR-253-CORE, and (2) also comply with
the "Category I Intrinsic Jitter Requirements per Telcordia GR-253-CORE (for DS3 applications) by making
sure that Bit 4 (SONET APS Recovery Time Disable Ch_n), within the Jitter Attenuator Control Register is set
to "0" as depicted below.
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
SONET APS JA RESET
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
Recovery
Time Disable
Ch_n
Ch_n
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JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
R/O
0
BIT 6
R/O
0
BIT 5
R/O
0
BIT 4
R/W
0
BIT 3
R/W
0
BIT 2
R/W
0
BIT 1
R/W
1
BIT 0
R/W
1
NOTE: The user can only disable the "SONET APS Recovery Time Mode" if the LIU is operating in the Host Mode. If the
user is operating the LIU in the Hardware Mode, then the user will have NO ability to disable the "SONET APS
Recovery Time Mode" feature.
9.8.4
How should one configure the LIU, if one needs to support "Daisy-Chain" Testing at the end
Customer’s site?
Daisy-Chain testing is emerging as a new requirements that many of our customers are imposing on our
SONET Mapper and LIU products. Many System Designer/Manufacturers are finding out that whenever their
end-customers that are evaluating and testing out their systems (in order to determine if they wish to move
forward and start purchasing this equipment in volume) are routinely demanding that they be able to test out
these systems with a single piece of test equipment. This means that the end-customer would like to take a
single piece of DS3 or STS-1 test equipment and (with this test equipment) snake the DS3 or STS-1 traffic
(that this test equipment will generate) through many or (preferably all) channels within the system. For
example, we have had request from our customers that (on a system that supports OC-192) our silicon be able
to support this DS3 or STS-1 traffic snaking through the 192 DS3 or STS-1 ports within this system.
After extensive testing, we have determined that the best approach to complying with test "Daisy-Chain"
Testing requirements, is to configure the Jitter Attenuator blocks (within each of the Channels within the LIU)
into the "32-Bit" Mode. The user can configure the Jitter Attenuator block (within a given channel of the LIU) to
operate in this mode by settings in the table below.
JITTER ATTENUATOR CONTROL REGISTER - CHANNEL 0 ADDRESS LOCATION = 0X07
CHANNEL 1 ADDRESS LOCATION = 0X0F
CHANNEL 2 ADDRESS LOCATION = 0X17
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
Unused
SONET APS JA RESET
JA1 Ch_n
JA in Tx Path
Ch_n
JA0 Ch_n
Recovery
Time Disable
Ch_n
Ch_n
R/O
0
R/O
0
R/O
0
R/W
0
R/W
0
R/W
1
R/W
1
R/W
0
REFERENCES
1. TEST REPORT - AUTOMATIC PROTECTION SWITCHING (APS) RECOVERY TIME TESTING WITH
THE XRT94L43 DS3/E3/STS-1 TO STS-12 MAPPER IC - Revision C Silicon
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ORDERING INFORMATION
PART NO.
PACKAGE
OPERATING TEMPERATURE RANGE
XRT75VL00DIV
52 Pin TQFP (10mm x 10mm)
-40°C to +85°C
PACKAGE DIMENSIONS
D
D1
39
27
40
26
D1
D
52
14
1
13
B
e
A2
C
A
α
Seating Plane
A1
L
Note: The control dimension is the millimeter column
INCHES MILLIMETERS
MAX
SYMBOL
MIN
MIN
MAX
1.60
0.15
1.45
0.38
0.20
12.20
10.10
A
A1
A2
B
0.055
0.002
0.053
0.009
0.004
0.465
0.390
0.063
0.006
0.057
0.015
0.008
0.480
0.398
1.40
0.05
1.35
0.22
0.09
11.80
9.90
C
D
D1
e
0.0256 BSC
0.65 BSC
L
0.018
0.030
0.45
0.75
α
0°
7°
0°
7°
β
7° typ
7° typ
aaa
-
0.003
-
0.08
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REVISION HISTORY
1.0.1 Changed ICC and PDD in the electrical characteristics. Added a detailed section on the De-Sync feature.
Removed evaluation schematic. Changed the MTIP/MRING configuration in Figure 16 (Transmit Driver
Monitor Setup).
1.0.2 Changed ICC and PDD in the electrical characteristics.
1.0.3 Incorrect Pin Number references in De-Sync functional description. Added 128-bit FIFO information for
the De-Sync function. Changed the device ID to reflect the correct value.
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any
circuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration
purposes and may vary depending upon a user’s specific application. While the information in this publication
has been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to
significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 2004 EXAR Corporation
Datasheet February 2004.
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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