XRT82D20IW_技术文档

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XRT82D20

SINGLE CHANNEL E1 LINE INTERFACE UNIT

APRIL 2001

REV. 1.0.7

• Clock Recovery and Selectable Crystal-less Jitter

attenuator

GENERAL DESCRIPTION

The XRT82D20 is a fully integrated, single channel,

Line Interface Unit (Transceiver) for 75 Ω or 120 Ω E1

(2.048 Mbps) applications. The LIU consists of a

receiver with adaptive data slicer for accurate data

and clock recovery and a transmitter which accepts

either single or dual-rail digital inputs for signal

transmission to the line using a low- impedance

differential line driver. The LIU also includes a crystal-

less jitter attenuator for clock and data smoothing

which, depending on system requirements, can be

selected in either the transmit or receive path.

• Compliant with ETS300166 Return Loss

• Compliant with the ITU-T G.823 Jitter Tolerance

Requirements

• Remote, Local and Digital Loop backs

• Declares and Clears LOS per ITU-T G.775

• Logic Inputs accept either 3.3V or 5.0V levels

• - 40⁰C to 85⁰C Temperature Range

• Low Power Dissipation; 145mW with 120 Ω or

160mW with 75 Ω typical

Coupling the XRT82D20 to the line requires trans-

formers on both the Receiver and Transmitter sides,

and supports both 120 Ω balanced and 75 Ω unbal-

anced interfaces. The receiver can be capacitive

coupled to for cost reduction

• +3.3V or +5V Supply Operation

• Pin Compatible with the XRT7288

APPLICATIONS

• PDH Multiplexers

FEATURES

• SDH Multiplexers

• Complete E1 (CEPT) line interface unit

• Digital Cross-Connect Systems

• Generates transmit output pulses that are compli-

ant with the ITU-T G.703 Pulse Template for

2.048Mbps (E1) rates

• DECT (Digital European Cordless Telephone) Base

Stations

• CSU/DSU Equipment

• Test Equipment

• On-Chip Pulse Shaping for both 75 Ω and 120 Ω

Line Drivers

FIGURE 1. BLOCK DIAGRAM OF THE XRT82D20

TTIP

TClk

TPOS

TNEG

HDB3

Encoder

Tx Pulse

Shaper

Line

Driver

MUX

TRing

Jitter Attenuator

Local

Loopback

Digital

Remote

Loopback

LOS

RLOS

Detect

Data &

Timing

Recovery

RClk

RPOS

RNEG

HDB3

Decoder

Data

Peak

RTIP

MUX

Slicer

Detector

RRing

Timing

Generator

MClk

Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com

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SINGLE CHANNEL E1 LINE INTERFACE UNIT

XRT82D20

REV. 1.0.7

FIGURE 2. PINOUT OF THE XRT82D20

1

2

28

27

26

25

24

23

22

21

20

19

18

17

16

15

RTIP

RLOS

ClkLOS

TNEG/CODE

RNEG/LCV

RClk

RRing

MuteRx

AGND

AVDD

TxLEV

TTIP

3

4

5

6

RPOS/RData

TClk

7

TVDD

TRing

TGND

JAEN

DIGI

8

TPOS/TData

LLoop

9

10

11

12

13

14

RLoop

DLoop

ATM

JATx/Rx

MClk

RAOS

TAOS

ORDERING INFORMATION

PART #

PACKAGE

OPERATING TEMPERATURE RANGE

-40^oC to + 85^oC

XRT82D20IW

28 Lead 300 Mil Jedec SOJ

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XRT82D20 SINGLE CHANNEL E1 LINE INTERFACE UNIT

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TABLE OF CONTENTS

GENERAL DESCRIPTION ................................................................................................. 1

FEATURES ................................................................................................................................................ 1

APPLICATIONS ......................................................................................................................................... 1

Figure 1. Block Diagram of the XRT82D20 .................................................................................................. 1

Figure 2. Pinout of the XRT82D20 ................................................................................................................ 2

ORDERING INFORMATION .............................................................................................................................. 2

PIN DESCRIPTIONS .......................................................................................................... 3

Figure 3. Interface Timing Diagram in Both Single-Rail and Dual-Rail Mode, with DIGI (Pin 17) = “0” . 5

Figure 4. Interface Timing Diagram in Dual-Rail Mode only, with DIGI (Pin 17) = “1” ............................. 6

ELECTRICAL CHARACTERISTICS .................................................................................. 7

TABLE 1: RECEIVER CHARACTERISTICS .............................................................................................................. 7

TABLE 2: TRANSMITTER CHARACTERISTICS ........................................................................................................ 7

TABLE 3: 3.3V POWER CONSUMPTION INCLUDING LINE POWER DISSIPATION, TRANSMISSION AND RECEIVE PATHS

ALL ACTIVE ........................................................................................................................................................ 7

TABLE 4: 5V POWER CONSUMPTION INCLUDING LINE POWER DISSIPATION, TRANSMISSION AND RECEIVE PATHS ALL

ACTIVE ............................................................................................................................................................... 8

TABLE 5: AC ELECTRICAL CHARACTERISTICS ................................................................................................... 8

TABLE 6: DC ELECTRICAL CHARACTERISTICS .................................................................................................... 9

ABSOLUTE MAXIMUM RATINGS .......................................................................................................... 9

Figure 5. Receiver Maximum Jitter Tolerance, Test Conditions: Test Pattern 2¹⁵-1, (-6dB) Cable Loss ..

10

Figure 6. Receiver Jitter Transfer Function (Jitter Attenuator Disabled), Test Conditions: Test Pattern

2¹⁵-1, Input Jitter 0.5UIp-p ............................................................................................................................ 11

Figure 7. Receiver Jitter Transfer Function (Jitter Attenuator enabled) Test Conditions: Test Pattern 2¹⁵-

1, Input Jitter 75% of Maximum Jitter Tolerance ........................................................................................ 11

SYSTEM DESCRIPTION .................................................................................................. 12

1.0 THE Receive Section ........................................................................................................................ 12

1.1 JITTER ATTENUATOR .................................................................................................................................. 12

1.2 THE TRANSMIT SECTION ............................................................................................................................ 12

Figure 8. Illustration on how the XRT82D20 Samples the data on the TPOS and TNEG input pins .... 12

1.3 THE PULSE SHAPING CIRCUIT ........................................................................................................................... 12

Figure 9. Illustration of the ITU-T G.703 Pulse Template for E1 Application .......................................... 13

1.4 INTERFACING THE TRANSMIT SECTION OF THE XRT82D20 TO THE LINE ............................................................. 14

Figure 10. Illustration of how to interface the XRT82D20 to the Line for 75 Ω Applications and 3.3V op-

eration only .................................................................................................................................................... 14

Figure 11. Illustration of how to interface the XRT82D20 to the Line for 120 Ω Applications and 3.3V op-

eration only .................................................................................................................................................... 15

1.5 INTERFACING THE RECEIVE SECTION TO THE LINE ............................................................................................. 15

Figure 12. Recommended Schematic for Transformer-Coupling the XRT82D20 to the Line for 75 Ω Ap-

plications and 5 V operation only ................................................................................................................ 16

Figure 13. Recommended Schematic for Transformer-Coupling the XRT82D20 to the Line for 120 Ω Ap-

plications and 5 V operation only ................................................................................................................ 17

1.6 CAPACITIVELY-COUPLING THE RECEIVE SECTION(S) OF THE XRT82D20 TO THE LINE ......................................... 18

Figure 14. Capacitively-coupling the Receive Section for 75 Ω Application and 3.3V supply ............. 18

Figure 15. Capacitively-coupling the Receive Section for 120 Ω Application and 3.3V supply ........... 19

Figure 16. Capacitively-coupling the Receive Section for 75 Ω Application and 5V supply ................ 20

Figure 17. Capacitively-coupling the Receive Section for 120 Ω Application and 5V supply .............. 21

2.0 Diagnostic Features ......................................................................................................................... 22

2.1 THE LOCAL LOOP-BACK MODE ......................................................................................................................... 22

Figure 18. Illustration of the Analog Local Loop-Back within the XRT82D20 ........................................ 22

2.2 THE REMOTE LOOP BACK MODE ....................................................................................................................... 23

Figure 19. Illustration of the Remote Loop-Back path, within the XRT82D20 ........................................ 23

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SINGLE CHANNEL E1 LINE INTERFACE UNIT

XRT82D20

REV. 1.0.7

PACKAGE OUTLINE DRAWING ...................................................................................... 24

REVISION HISTORY ..................................................................................................................................... 25

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XRT82D20 SINGLE CHANNEL E1 LINE INTERFACE UNIT

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PIN DESCRIPTIONS

PIN #

SYMBOL

TYPE

DESCRIPTION

1

Receiver Loss of Signal: This pin toggles Low to indicate the loss of

signal at the receive inputs.

RLOS

O

Receiver Loss of Clock: With MuteRx=1, this pin will toggle low to indi-

cate a loss of clock has occurred when the receive signal is lost

(RLOS=0). When RLOS=0, no transitions occur on RClk, RPOS/RData

and RNEG outputs.

2

3

ClkLOS

O

I

Transmitter Negative Data Input/Coding Select: With Jitter Attenuator

enabled (pin 18=1), input activity on this pin determines whether the

device is configured to operate in single-rail or dual-rail mode. With n-rail

transmit data applied to this pin, the device is automatically configured to

operate in dual-rail mode for both transmit input and receive output.

If this pin is tied high for more than 16 clock cycles, the device is config-

ured to operate in single-rail mode with HDB3 encoding and decoding

functions enabled.

TNEG/CODE

If this pin is tied low for more than 16 clock cycles, the device is config-

ured to operate in single-rail mode with AMI encoding and decoding

functions enabled. (internal pull-down).

Receive Negative Data/Line Code Violation Output:

If the device is configured in Dual-rail mode with n-rail data applied to pin

3, then the receive negative data will be output through this pin.

If the device is configured in Single-rail mode and operate with HDB3

coding enabled, HDB3 code violation will be detected and cause this pin

to go high.

4

RNEG/LCV

O

If the device is configured in Single-rail mode and with AMI coding

selected, every bipolar violation will be reported at this pin.

Receive Clock:

Output receive clock signal to the terminal equipment.

5

6

RClk

O

Receive Positive/ Data Output:

RPOS/RData

In Dual-rail mode, this signal is the p-rail receive output data. In Single-

rail mode, this signal is the receive output data.

Transmitter Clock Input:

Input clock signal (2.048 MHz ± 50ppm)

7

8

TClk

I

Transmit Positive / Data Input:

TPOS/TData

In Dual-rail mode, this signal is the p-rail transmit input data. In Single-rail

mode, this signal is the transmit input data.

Local Loop back enable (active low):

9

LLoop

I

Tie this pin low to enable analog Local Loop-back.In local loop-back

mode, transmit output data is looped back to the input of the

receiver.Input signal at RTIP and RRing are ignored. Local Loop-back

has priority over Remote and Digital Loop-back mode. See Section 2.2

for more details. (internal pull-down).

Remote Loop Back Enable (active low):

10

11

RLoop

DLoop

I

Connect this pin to ground to enable Remote Loop-back. In Remote

Loop-back mode, transmit data at TPOS/TData and TNEG are ignored.

See Section 2.2 for more details. (internal pull-down).

Digital Loop Back enable (active low):

Connect this pin to ground to enable Digital Local Loop-back.In Digital

loop-back mode, transmit input data after the encoder is looped back to

the jitter attenuator (if selected) and to the receive decoder. Input data at

RTIP and RRing are ignored in this mode. (internal pull-up). In this

mode, the XRT82D20 can operate only as a jitter attenuator.

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SINGLE CHANNEL E1 LINE INTERFACE UNIT

XRT82D20

REV. 1.0.7

PIN #

SYMBOL

TYPE

DESCRIPTION

Alarm Test Mode (Active-Low):

12

ATM

I

Connect this pin to ground to force ClkLOS, RLOS = 0 and LCV = 1 for

testing without affecting data transmission. (internal pull-up)

Receive All Ones:

13

RAOS

I

With this pin tied to High, an all “1’s” signal is inserted to the receiver out-

put at RPOS and RNEG/RData using MCLK as timing reference. This

control has priority over Digital Loop-back if both are enabled. (internal

pull-down).

Transmit All Ones:

14

15

TAOS

MClk

I

With this pin tied High, an AMI encoded all “1’s” signal is sent to the

transmit output using MCLK as timing reference. This control has priority

over Remote Loop-back if both are enabled. (internal pull-down).

Master Clock Input:

This signal is an independent 2.048 MHz clock with accuracy better than

+ 50 ppM and duty cycle within 40% to 60%. The function of MClk is to

provide timing source for the PLL clock recovery circuit, reference clock

to insert all “1’s” data in the transmit as well as receive paths. This signal

must be available for the device to operate.

Jitter Attenuator Path Select:

16

JATx/Rx

(DR/SR)

I

With the jitter attenuator enabled, (pin 18 =”1”), tie this pin “High” to

select the jitter attenuator in the transmit path and tie it “Low” to select in

the receive path. Data input/output format is then controlled automati-

cally by the status of the TNEG input. If TNEG data is present the device

operates in Dual-rail data mode.

Dual-Rail/Single-Rail Select:

With the jitter attenuator disabled, (pin 18 =”0”), tie this pin “High” to

select Dual-Rail data format and tie it “Low” to select Single-Rail data for-

mat. (internal pull-down)

Digital Interface:

17

DIGI

I

With this pin tied Low, input data at TPOS/TData and TNEG/CODE is

active-high and will be sampled by TClk on the falling edge, while active-

high RPOS/RData and RNEG output data are updated on the falling

edge of RClk. See Figure 3 and 4 for details.

With his pin tied high and in Dual-rail mode, transmit input accepts

active-low TPOS/TData and TNEG/CODE data and will be sampled by

TClk on the falling edge, while RPOS/RData and RNEG/LCV are active-

low, data is updated on the rising edge of RClk. (internal pull-down).

Jitter Attenuator Enable (active high):

18

JAEN

I

Connect this pin high to enable the jitter attenuation function. Jitter Atten-

uator Path select is determined by the pin 16 setting. (internal pull-down)

Transmitter Supply Ground

19

20

TGND

TRing

-

Transmitter Ring Output:

Negative bipolar data output to the line.

O

Transmit Positive Supply:

5.0 V + 5% or 3.3 V + 5%

21

22

23

TVDD

TTIP

-

O

I

Transmitter TIP Output:

Positive bipolar data output to the line.

Transmit Level:

TxLEV

Tie this pin high for 120 Ω twisted pair cable operation and tie it low for 75

Ω coaxial cable operation (internal pull-down). This pin is only active for

5.0V operation.

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PIN #

SYMBOL

TYPE

DESCRIPTION

Analog Positive Supply

5.0 V + 5% or 3.3 V+ 5%

24

AVDD

-

Analog Supply Ground

25

26

AGND

-

I

Mute Receive Output:

MuteRx

With this pin tied high, a loss of receive input signal (RLOS=0) will cause

ClkLOS to go low and generate the following.

Dual-rail mode operation:

With DIGI = 0, RClk = 1, RPOS and RNEG/RData = 0

fWith DIGI = 1, RClk =0, RPOS and RNEG/RData = 1

Single-rail mode:

RClk = 1 and RData=0

(internal pull-down)

Receive Bipolar Negative Input:

Bipolar line signal input to the receiver.

27

28

RRing

RTIP

I

Receiver Bipolar Positive Input:

Bipolar line signal input to the receiver.

FIGURE 3. INTERFACE TIMING DIAGRAM IN BOTH SINGLE-RAIL AND DUAL-RAIL MODE, WITH DIGI (PIN 17) = “0”

TClk

t_r

t_f

TClk

TPOS/TData

or

Active High

TNEG/CODE

t_TSU

t_THO

t_RCD

t_r

t_f

RClk

t_RSU

RPOS/RData

or

Active High

RNEG/LCV

t_RHO

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SINGLE CHANNEL E1 LINE INTERFACE UNIT

XRT82D20

REV. 1.0.7

FIGURE 4. INTERFACE TIMING DIAGRAM IN DUAL-RAIL MODE ONLY, WITH DIGI (PIN 17) = “1”

TClk

t_r

t_f

TClk

TPOS/TData

Active Low

t_TSU

t_THO

t_RCD

t_r

t_f

RClk

t_RSU

RPOS/RData

Active Low

t_RHO

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XRT82D20 SINGLE CHANNEL E1 LINE INTERFACE UNIT

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ELECTRICAL CHARACTERISTICS

TABLE 1: RECEIVER CHARACTERISTICS

TA = 25°C, VDD = 3.3V± 5% or 5V± 5% Unless otherwise specified

PARAMETER

MIN.

TYP.

MAX

UNIT

Receiver Sensitivity

0.7

-18

0.9

4.2

Vp

dB

kΩ

Interference Margin with -6db Cable Loss

-14

2.0

-

Input Impedance measured between RTIP or RRing to ground

Recovered Clock Jitter Transfer Corner Frequency

Peaking Amplitude

-

18

0.1

36

0.5

kHz

dB

Jitter Attenuator Corner Frequency (-3dB curve)

-

20

40

Hz

Return Loss

51kHz-102kHz

102kHz-2048kHz

2048kHz-3072kHz

12

18

14

25

35

25

-

dB

TABLE 2: TRANSMITTER CHARACTERISTICS

TA = 25°C, VDD = 3.3V± 5% or 5V± 5% Unless otherwise specified

PARAMETER

MIN.

TYP.

MAX

UNIT

AMI Output Pulse Amplitude

75 Ω Application

120 Ω Application

2.14

2.70

2.37

3.00

2.60

3.30

V

Output Pulse Width

224

0.9

-

244

1.0

264

1.1

ns

Output Pulse Amplitude Ratio

Jitter Added by the Transmitter Output

0.025

0.050

UIpp

Output Return Loss:

51kHz -102kHz

102kHz-2048kHz

2048kHz-3072kHz

-

20

25

20

-

dB

TABLE 3: 3.3V POWER CONSUMPTION INCLUDING LINE POWER DISSIPATION, TRANSMISSION AND RECEIVE PATHS

ALL ACTIVE

TA = -40° to 85°C, VDD = 3.3V± 5% Unless otherwise specified

SYMBOL

PARAMETER

MIN.

TYP.

MAX

UNIT

CONDITIONS

PC

Power Consumption

-

100

92

140

130

190

160

mW

75Ω load, operating at 50% Mark Density

120Ω load, operating at 50% Mark Density

75Ω load, operating at 100% Mark Density

120Ω load, operating at 100% Mark Density

150

125

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SINGLE CHANNEL E1 LINE INTERFACE UNIT

XRT82D20

REV. 1.0.7

TABLE 4: 5V POWER CONSUMPTION INCLUDING LINE POWER DISSIPATION, TRANSMISSION AND RECEIVE PATHS ALL

ACTIVE

(TA = -40° to 85°C, VDD = 5V ± 5% Unless otherwise specified)

SYMBOL

PARAMETER

MIN.

TYP.

MAX

UNIT

CONDITIONS

PC

Power Consumption

-

160

145

200

180

210

195

260

240

mW

75Ω load, operating at 50% Mark Density

120Ω load, operating at 50% Mark Density

75Ω load, operating at 100% Mark Density

120Ω load, operating at 100% Mark Density

TABLE 5: AC ELECTRICAL CHARACTERISTICS

TA = -40 to +85 °C, VDD = 3.3V± 5% or 5V ± 5% Unless otherwise specified

PARAMETER

SYMBOL

MIN.

TYP

MAX

UNITS

Clock Frequency

MClk

TClk

-50 ppm

2.048

50

+50ppm MHz

Clock Duty Cycle

Clock Period

40

-

60

-

%

ns

%

ns

244

50

TClk Duty Cycle

TCDU

t_TSU

30

40

70

-

Transmit Data Setup Time

-

Transmit Data Hold Time

TClk Rise Time (10% /90%)

TClk Fall Time (90% / 10%)

RClk Duty Cycle

tTHO

tr

40

-

ns

%

40

55

-

tf

-

RCDU

t_RSU

45

150

50

244

Receive Data Setup Time

ns

-

Receive Data Hold Time

RClk to Data Delay

t_RHO

t_RCD

t_r

150

244

ns

-

40

RClk Rise Time (10%/90%)

RClk Fall Time (90%/10%)

t_f

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XRT82D20 SINGLE CHANNEL E1 LINE INTERFACE UNIT

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TABLE 6: DC ELECTRICAL CHARACTERISTICS

Ta = 25°C, Vdd=3.3V ± 5% or 5V ± 5% unless otherwise specified

PARAMETER

SYMBOL

V_IH

MIN

2.0

0.5

TYP

MAX

5.5

UNIT

Input High Voltage

Input Low Voltage

3.3 or 5.0

V

V_IL

0

-

0.8

Output High Voltage @IOH=5mA (See Note)

VDD=3.3V

VDD=5.0v

V_OH

2.4

VDD

Output Low Voltage @ IOL=5mA (See Note)

-

V

VDD=3.3V

VDD=5.0v

V_OL

I_L

0

0.4

Input Leakage Current (except input pins with pull-up

resistors)

-

0

10

uA

Input Capacitance

C_I

-

5

-

20

pF

Output Load Capacitance

C_O

NOTE: All Digital output pins except pin 1 and pin 2, which

typically source 20µA at VOH and sink -4mA at VOL

ABSOLUTE MAXIMUM RATINGS

Storage Temperature

Operating Temperature

Supply Voltage

-65 to 150°C

-40 to 85°C

-0.5V to +5.5V

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SINGLE CHANNEL E1 LINE INTERFACE UNIT

XRT82D20

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FIGURE 5. RECEIVER MAXIMUM JITTER TOLERANCE, TEST CONDITIONS: TEST PATTERN 2¹⁵-1, (-6dB) CABLE LOSS

10³

JAT Disabled

10²

JAT Enabled

10¹

ITU-T G.823 M ask

10⁰

10⁻¹

10⁰

10¹

10²

10³

10⁴

10⁵

(Freq.(MHz))

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FIGURE 6. RECEIVER JITTER TRANSFER FUNCTION (JITTER ATTENUATOR DISABLED), TEST CONDITIONS: TEST PAT-

TERN 2¹⁵-1, INPUT JITTER 0.5UIP-P

2

G.735-G739 Specification

0

−2

−4

T82D20 Perform ance

−6

−8

−10

−12

−14

10²

10³

10⁴

10⁵

(Freq.(MHz))

FIGURE 7. RECEIVER JITTER TRANSFER FUNCTION (JITTER ATTENUATOR ENABLED) TEST CONDITIONS: TEST PAT-

TERN 2¹⁵-1, INPUT JITTER 75% OF MAXIMUM JITTER TOLERANCE

10

ITU.G.736 M ask

0

−10

−20

−30

T82D20 Performance

−40

−50

−60

10⁰

10¹

10²

10³

10⁴

10⁵

(Freq.(MHz))

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SINGLE CHANNEL LINE INTERFACE UNIT

XRT82D20

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coming line signal) to the Receive Terminal Equip-

ment via the RPOS and RNEG output pins.

SYSTEM DESCRIPTION

The XRT82D20 is a single channel E1 transceiver

that provides an electrical interface for 2.048Mbps ap-

plications. XRT82D20 includes a receive circuit that

converts an ITU-T G.703 compliant bipolar signal into

a TTL compatible logic levels. The receiver also in-

cludes an LOS (Loss of Signal) detection circuit.

Similarly, in the Transmit Direction, the Transmitter

converts TTL compatible logic levels into a G.703

compatible bipolar signal.

If the Receive Section of the XRT82D20 has received

a Positive-Polarity pulse, via the RTIP and

RRing input pins, then the Receive Output Interface

will output a pulse at the RPOS output pin.

Similarly, if the Receive Section of the XRT82D20 has

received a Negative-Polarity pulse, via the RTIP and

RRing input pins, then the Receive Output Interface

will output a pulse at the RNEG output pin.

The XRT82D20 consists of both a Receive Section,

Jitter Attenuator and Transmit Section; each of these

sections will be discussed below.

1.1 JITTER ATTENUATOR

To reduce frequency jitter in the transmit clock or re-

ceive clock, a crystal-less jitter attenuator is provided.

The jitter attenuator can be selected either in the

transmit or receive path or it can be disabled.

1.0 THE RECEIVE SECTION

At the receiver input, cable attenuated AMI signal can

be coupled to the receiver using a capacitor or trans-

former. The receive data first goes through the peak

detector and data slicer for accurate data recov-

ery.The digital representation of the AMI signals go to

the clock recovery circuit for timing recovery and sub-

sequently to the decoder (if selected) for HDB3 de-

coding before being output to the RPOS/RData and

RNEG/LCV pins. The digital data output can be in

NRZ or RZ format depending the mode of operation

selected and with the option to be in dual-rail or single

rail mode. Clock timing recovery of the line interface

is accomplished by means of a digital PLL scheme

which has high input jitter tolerance.

1.2 THE TRANSMIT SECTION

In general, the purpose of the Transmit Section (with-

in the XRT82D20) is to accept TTL/CMOS level digital

data (from the Terminal Equipment), and to encode it

into a format such that it can:

1. Be efficiently transmitted over coaxial- or twisted

pair cable at the E1 data rate; and

2. Be reliably received by the Remote Terminal

Equipment at the other end of the E1 data link.

3. Comply with the ITU-T G.703 pulse template

requirements, for E1 applications

A 2.048 MHz clock is applied to the TClk input pin

and NRZ data at the TPOS and TNEG input pins.

The Transmit Input Interface circuit will sample the

data, at the TPOS and TNEG input pins, upon the fall-

ing edge of TClk, as illustrated in Figure 8 below.

The purpose of the Receive Output Interface block is

to interface directly with the Receiving Terminal

Equipment. The Receive Output Interface block out-

puts the data (which has been recovered from the in-

FIGURE 8. ILLUSTRATION ON HOW THE XRT82D20 SAMPLES THE DATA ON THE TPOS AND TNEG INPUT PINS

tHO

tSU

TPOS

TNEG

TClk

In general, if the XRT82D20 samples a “1” on the

TPOS input pin, then the Transmit Section will ulti-

mately generate a positive polarity pulse via the TTIP

and TRing output pins (across a 1:2 transformer).

Conversely, if the XRT82D20 samples a “1” on the

TNEG input pin, then the Transmit Section of the de-

vice will ultimately generate a negative polarity pulse

via the TTIP and TRing output pins (across a 1:2

transformer).

1.3 THE PULSE SHAPING CIRCUIT

The purpose of the Transmit Pulse Shaping circuit is

to generate Transmit Output pulses that comply with

12

XRT82D20 SINGLE CHANNEL LINE INTERFACE UNIT

áç

REV. 1.0.7

the ITU-T G.703 Pulse Template Requirements for E1

Applications.

Transmit Input Interface block, and will generate a

pulse that complies with the pulse template, present-

ed in Figure 9 (when measured on the secondary

side of the Transmit Output Transformer).

An illustration of the ITU-T G.703 Pulse Template Re-

quirements is presented below in Figure 9.

With input signal as described above, the XRT82D20

will take each mark (which is provided to it via the

FIGURE 9. ILLUSTRATION OF THE ITU-T G.703 PULSE TEMPLATE FOR E1 APPLICATION

269 ns

(244 + 25)

V = 100%

194 ns

(244 – 50)

Nominal pulse

50%

244 ns

219 ns

(244 – 25)

0%

488 ns

(244 + 244)

Note

– V corresponds to the nominal peak value.

13

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SINGLE CHANNEL LINE INTERFACE UNIT

XRT82D20

REV. 1.0.7

1.4 INTERFACING THE TRANSMIT SECTION OF THE

XRT82D20 TO THE LINE

ITU-T G.703 specifies that the E1 line signal can be

transmitted over coaxial cable and terminated with

75Ω or transmitted over twisted-pair and terminated

with 120Ω.

In both applications (e.g., 75Ω or 120Ω, the user is ad-

vised to interface the Transmitter to the Line, in the

manner as depicted in Figure 10 and Figure 11, re-

spectively.

FIGURE 10. ILLUSTRATION OF HOW TO INTERFACE THE XRT82D20 TO THE LINE FOR 75 Ω APPLICATIONS AND 3.3V

OPERATION ONLY

75 Ω Coax

RPOS/RData

1 : 2

RTIP

RNEG/LCV

270 Ω

RClk

75 Ω

Signal

Source

Rxx Input

TVDD

AVDD

+3.3 V

RRING

10µF

0.1 µF

TxLEV

TGND

AGND

75 Ω Coax

2 : 1

TTIP

9.1 Ω

R Load

75 Ω

Tx Output

TNEG/CODE

TPOS/TData

TClk

9.1 Ω

TRING

14

XRT82D20 SINGLE CHANNEL LINE INTERFACE UNIT

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REV. 1.0.7

FIGURE 11. ILLUSTRATION OF HOW TO INTERFACE THE XRT82D20 TO THE LINE FOR 120 Ω APPLICATIONS AND

3.3V OPERATION ONLY

Ω

120 Twisted Pair

RPOS/RData

RNEG/LCV

RClk

1 : 2

RTIP

Ω

866

Ω

120

Rx Input

RRING

Signal

Source

Ω

TVDD

AVDD

+3.3 V

µ

F

10

F

0.1

TxLEV

TGND

AGND

Ω

120 Twisted Pair

2 : 1

TTIP

Ω

9.1

R Load

Tx Output

TRING

Ω

120

TNEG/CODE

TPOS/TData

TClk

Ω

9.1

NOTES:

1.5 INTERFACING THE RECEIVE SECTION TO THE LINE

The design of the XRT82D20 permits the user to

transformer-couple the Receive Section to the line.

As mentioned earlier, the specifications for E1 require

75Ω termination loads, when transmitting over coaxial

cable, and 120Ω loads, when transmitting over twist-

ed-pair. Figure 12 and Figure 13 present the various

methods that the user can employ to interface the Re-

ceiver of the XRT82D20 to the line.

1. Figure 10 and Figure 11indicate that for 3.3 V oper-

ation, both 75 Ω and 120 Ω applications, the user

should connect a 9.1Ω resistor in series between

the TTIP/TRing outputs and the transformer.

2. Figure 10 and Figure 11indicate that the user

should use a 2 : 1 STEP-UP Transformer.

15

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SINGLE CHANNEL LINE INTERFACE UNIT

XRT82D20

REV. 1.0.7

FIGURE 12. RECOMMENDED SCHEMATIC FOR TRANSFORMER-COUPLING THE XRT82D20 TO THE LINE FOR 75 Ω

APPLICATIONS AND 5 V OPERATION ONLY

75 Ω Coax

RPOS/RData

RNEG/LCV

RClk

1 : 2

RTIP

270 Ω

75 Ω

Signal

Source

Rx Input

TVDD

AVDD

+5 V

RRING

10 µF

0.11 µF

TxLEV

TGND

AGND

75 Ω Coax

1.36 : 1

TTIP

15.4 Ω

R Load

75 Ω

Tx Output

TRING

TNEG/CODE

TPOS/TData

TClk

15.4 Ω

16

XRT82D20 SINGLE CHANNEL LINE INTERFACE UNIT

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REV. 1.0.7

FIGURE 13. RECOMMENDED SCHEMATIC FOR TRANSFORMER-COUPLING THE XRT82D20 TO THE LINE FOR 120 Ω

APPLICATIONS AND 5 V OPERATION ONLY

Ω

120 Twisted Pair

RPOS/RData

RNEG/LCV

RClk

1 : 2

RTIP

Ω

866

Ω

Signal

Source

120

Rx Input

RRING

Ω

866

TVDD

AVDD

+5 V

µ

F

µ

F

10

0.1

TxLEV

TGND

AGND

Ω

120 Twisted Pair

1.36 : 1

TTIP

Ω

26.1

R Load

120

Tx Output

Ω

TNEG/CODE

TPOS/TData

TClk

Ω

TRING

NOTE: Figure 12 and Figure 13indicate that the user should

use a 1.36 :1 STEP-UP transformer, when interfacing the

receiver to the line.

17

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SINGLE CHANNEL LINE INTERFACE UNIT

XRT82D20

REV. 1.0.7

1.6 CAPACITIVELY-COUPLING THE RECEIVE SEC-

TION(S) OF THE XRT82D20 TO THE LINE

Applications that are not sensitive to these issues can

benefit from the lower cost approach of using capaci-

tor coupling on the receive input.

Capacitive coupling provides a lower cost interface to

the line. It must be noted that the line isolation is lim-

ited to the breakdown voltage of the capactior versus

the typical transformer isolation of 1,500 to 3,000

volts. With a capacitor there is also no DC isolation to

ground as there is with with a transformer.

See Figure 14, Figure 15, Figure 16 and Figure 17 for

the recommended schematics for capacitively cou-

pling the receiver to the line.

FIGURE 14. CAPACITIVELY-COUPLING THE RECEIVE SECTION FOR 75 Ω APPLICATION AND 3.3V SUPPLY

75 Ω Coax

RPOS/RData

RTIP

RNEG/LCV

37.4 Ω

0.1 µF

RClk

75 Ω

Signal

Source

Rx Input

37.4 Ω

TVDD

0.1 µF

AVDD

RRING

+3.3 V

10µF

0.1µF

TxLEV

75 Ω Coax

2:1

TGND

AGND

TTIP

9.1 Ω

Tx Output

R Load

75 Ω

TNEG/CODE

TPOS/TData

TClk

9.1 Ω

TRING

NOTE: Resistive divider attenuates the input signal by one-

half for both 75 Ω and 120 Ω applications.

18

XRT82D20 SINGLE CHANNEL LINE INTERFACE UNIT

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REV. 1.0.7

FIGURE 15. CAPACITIVELY-COUPLING THE RECEIVE SECTION FOR 120 Ω APPLICATION AND 3.3V SUPPLY

Ω

120 Twisted Pair

RPOS/RData

RNEG/LCV

RClk

RTIP

Ω

30.1

µ

0.1

F

Ω

Rx Input

120

Ω

60.4

Signal

Source

TVDD

AVDD

Ω

30.1

+3.3 V

RRING

µ

F

µ

0.1 F

10

TxLEV

TGND

AGND

Ω

120 Twisted Pair

2:1

TTIP

Ω

9.1

Tx Output

R Load

120

Ω

TNEG/CODE

TPOS/TData

TClk

Ω

TRING

NOTE: Resistive divider attenuates the input signal by one-

half for both 75 Ω and 120 Ω applications.

19

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SINGLE CHANNEL LINE INTERFACE UNIT

XRT82D20

REV. 1.0.7

FIGURE 16. CAPACITIVELY-COUPLING THE RECEIVE SECTION FOR 75 Ω APPLICATION AND 5V SUPPLY

Ω

75 Coax

RPOS/RData

RNEG/LCV

RClk

RTIP

µ

0.1

F

Ω

75

Rx Input

Signal

Source

Ω

37.4

TVDD

AVDD

+5 V

RRING

µ

F

10

F

0.1

TxLEV

TGND

AGND

Ω

75 Coax

1.36:1

TTIP

Ω

15.4

Tx Output

R Load

Ω

75

TNEG/CODE

TPOS/TData

TClk

Ω

TRING

NOTE: Resistive divider attenuates the input signal by one-

half for both 75 Ω and 120 Ω applications.

20

XRT82D20 SINGLE CHANNEL LINE INTERFACE UNIT

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REV. 1.0.7

FIGURE 17. CAPACITIVELY-COUPLING THE RECEIVE SECTION FOR 120 Ω APPLICATION AND 5V SUPPLY

Ω

120 Twisted Pair

RPOS/RData

RNEG/LCV

RClk

RTIP

Ω

30.1

µ

0.1

F

Ω

Rx Input

120

Ω

60.4

Signal

Source

TVDD

AVDD

Ω

30.1

+5 V

RRING

µ

F

10

F

0.1

TxLEV

TGND

AGND

Ω

120 Twisted Pair

1.36:1

TTIP

Ω

26.1

Tx Output

R Load

Ω

120

TNEG/CODE

TPOS/TData

TClk

Ω

26.1

TRING

NOTE: Resistive divider attenuates the input signal by one-

half for both 75 Ω and 120 Ω applications.

21

áç

SINGLE CHANNEL LINE INTERFACE UNIT

XRT82D20

REV. 1.0.7

2.0 DIAGNOSTIC FEATURES

Shaping circuit. Finally, this data will be output to the

line via the TTIP and TRing output pins. Additionally,

this data (which is being output via the TTIP and

TRing output pins) will be looped back into the Re-

ceiver block. As a consequence, this data will also be

processed through the entire Receive Section of the

XRT82D20. After this post-loop-back data has been

processed through the Receive Section it will output,

to the Near-End Receiving Terminal Equipment via

the RPOS and RNEG output pins.

In order to support diagnostic operations, the

XRT82D20 supports the following loop-back modes:

• Local Loopback

• Remote Loopback

• Digital Loopback

Each of these loop-back modes will be discussed be-

low.

2.1 THE LOCAL LOOP-BACK MODE

Figure 18, illustrates the path that the data takes

(within the XRT82D20), when the chip is configured

to operate in the Local Loop-Back Mode.

When the XRT82D20 is configured to operate in the

Local Loop-Back Mode, the XRT82D20 will ignore

any signals that are input to the RTIP and RRing input

pins. The Transmitting Terminal Equipment will trans-

mit data into the XRT82D20 via the TPOS, TNEG and

TClk input pins. This data will be processed through

the Transmit Terminal Input Interface and the Pulse

The user can configure the XRT82D20 to operate in

the Local Loop-Back Mode, by pulling the LLoop input

pin (pin 9) to GND.

FIGURE 18. ILLUSTRATION OF THE ANALOG LOCAL LOOP-BACK WITHIN THE XRT82D20

TTIP

TClk

TPOS

TNEG

HDB3

Encoder

Tx Pulse

Shaper

Line

Driver

MUX

TRing

Jitter Attenuator

Local

Loopback

LOS

Detect

RLOS

Data &

Timing

Recovery

RClk

RPOS

RNEG

HDB3

Decoder

Data

Peak

RTIP

MUX

Slicer

Detector

RRing

Timing

Generator

MClk

22

XRT82D20 SINGLE CHANNEL LINE INTERFACE UNIT

áç

REV. 1.0.7

2.2 THE REMOTE LOOP BACK MODE

block within the Transmit Section. At this point, this

data will be routed through the remainder of the

Transmit Section of the XRT82D20 and will be trans-

mitted out onto the line via the TTIP and TRing output

pins.

When the XRT82D20 is configured to operate in the

Remote Loop-Back Mode, the XRT82D20 will ignore

any signals that are input to the TPOS and TNEG in-

put pins. The XRT82D20 will receive the incoming

line signals, via the RTIP and RRing input pins. This

data will be processed through the entire Receive

Section (within the XRT82D20) and will output to the

Receive Terminal Equipment via the RPOS and

RNEG output pins. Additionally, this data will also be

internally looped back to the Transmit Input Interface

Figure 19, illustrates the path that the data takes

(within the XRT82D20) when the chip is configured to

operate in the Remote Loop-Back Mode.

FIGURE 19. ILLUSTRATION OF THE REMOTE LOOP-BACK PATH, WITHIN THE XRT82D20

TTIP

TClk

TPOS

TNEG

HDB3

Encoder

Tx Pulse

Shaper

Line

Driver

MUX

TRing

Jitter Attenuator

Remote

Loopback

LOS

RLOS

Detect

Data &

Timing

Recovery

RClk

RPOS

RNEG

HDB3

Decoder

Data

Slicer

Peak

Detector

RTIP

RRing

MUX

Timing

Generator

MClk

NOTE: During Remote Loop-Back operation, any data

which is input via the RTIP and RRING input pins, will also

be output to the Terminal Equipment, via the RPOS and

RNEG output pins.

23

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SINGLE CHANNEL LINE INTERFACE UNIT

XRT82D20

REV. 1.0.7

PACKAGE OUTLINE DRAWING

24

áç

XRT82D20

SINGLE CHANNEL LINE INTERFACE UNIT

REV. 1.0.7

REVISION HISTORY

Rev. 1.0.6 corrections to figures, remove values from pull-up/down resistors, correct formating of ±.

Rev. 1.0.7 Minor edits of figures and text. Added 4 new figures 14, 15, 16 and 17, showing capacitive cou-

pling of the receiver to the line.

NOTICE

EXAR Corporation reserves the right to make changes to the products contained in this publication in order

to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of

any circuits described herein, conveys no license under any patent or other right, and makes no represen-

tation that the circuits are free of patent infringement. Charts and schedules contained here in are only for

illustration purposes and may vary depending upon a user’s specific application. While the information in

this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies.

EXAR Corporation does not recommend the use of any of its products in life support applications where

the failure or malfunction of the product can reasonably be expected to cause failure of the life support sys-

tem or to significantly affect its safety or effectiveness. Products are not authorized for use in such applica-

tions unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury

or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corpo-

ration is adequately protected under the circumstances.

Datasheet April 2001

Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.

25


型号：	XRT82D20IW
厂家：	EXAR CORPORATION
描述：	SINGLE CHANNEL E1 LINE INTERFACE UNIT 单路E1线路接口单元
文件：	总27页 (文件大小：207K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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