XRT84V24IV-208 [EXAR]
Framer, PQFP208, 28 X 28 MM, PLASTIC, QFP-208;
| 型号： | XRT84V24IV-208 |
| 厂家： | 
EXAR CORPORATION |
| 描述： | Framer, PQFP208, 28 X 28 MM, PLASTIC, QFP-208 电信 电信集成电路 |
| 文件： | 总6页 (文件大小：70K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
QUAD E1 FRAMER IC
XRT84V24
PRELIMINARY
REV. 1.0.1
• Contains Microprocessor Interface for popular
types of Microprocessors and supports Pro-
grammed I/O, Burst and DMA modes of Read/Write
access
GENERAL DESCRIPTION
The XRT84V24 Quad E1 Framer IC contains four in-
dependent E1 Framer blocks. Each E1 Framer block
contains its ownTransmit and Receive E1 Framin
function, Transmit HDLC Controller (which encapsu-
lates contentsof Transmit HDLC Buffers into LAPD
Message frames) and Receiver HDLC Controller
(which extracts payload content of “Receive LAPD
Message” frames from the incoming E1 data stream
and writes it into the Receive HDLC Buffer). Each
framer also contains aTransmit and Overhead Input
port, which permits “Data Link” Terminal equipment
direct access to the outbound E1 frames and a Re-
ceive Overhead Output port, which permits “Data
Link” Terminal equipment direct access to the “Data
Link” bits within the inbound E1 frames.
• Each framer block can encode or decode the E
Frame data into/from the Single-Rail or Dual-Rail
(AMI or HDB3 encoded) formats
• Detects and forces RAI and AIS Alarms
• Detects LOF, COFA and LOS conditions
• Each Framer Contains a 512 bit Elastic Store Buffer
• Uses a Single +3.3VPower Supply
• Available in either a 160 pin PQFP and 208 pin
PQFP package
APPLICATIONS
• SDH terminal or add/drop multiplexers supporting
FEATURES
E1 framing
• E1 multiplexers
• Four independent, ITU-T G.704 compliant Trans-
ceiver E1 Framers
• Channel Service Units (CSUs)
• LAN routers with integrated E1 interfaces
• E1 Frame Relay Interface
• ISDN Primary Rate Interfaces
• Test Equipment
• Supports Channel Associated Signalin
• Supports Common-Channel and Primary Rate
ISDN Signalin
• SupportsFAS, CRC-Multiframe and CAS Multi-
frame framing stuctures
• Contains two 96 byteTransmit HDLC Buffers and
two 96 byte Receive HDLC buffers for each channel
FIGURE 1. BLOCK DIAGRAM OF THE XRT84V24
Transmit E1
Overhead Input
Interface
TxOH_0
TxOHClk_0
Transmit E1
Serial Input
Interface
TxPOS_0
TxNEG_0
TxLineClk_0
TxSER_0
Transmit E1
Framer
Transmit E1
LIU Interface
TxSERClk_0
GPO_6_CS_L_3
TxLAPD
Buffer
PCS_L
PWR_L
PRD_L
PD[7:0]
PA[5:0]
GPO_5_CS_L_2
GPO_4_CS_L_1
GPO_3_CS_L_0
GPO_2_SClK_L
GPO_1_SDI
LIU
Controller
Block
HDLC
Controller
Microprosser
Interface Block
Rx LAPD
Buffer
GPO_0_SDO
RxPOS_0
RxNEG_0
RxLineClk_0
Receive E1
Serial Output
Interface
RxSER_0
Receive E1
LIU Interface
Receive E1
Framer
RxSERClk_0
Receive E1
Overhead Output
Interface
RxOH_0
RxOHClk_0
Framer Block 0
Framer Block 1
Framer Block 2
Framer Block 3
1
XRT84V24 QUAD E1 FRAMER IC
PRELIMINARY
REV. 1.0.1
FIGURE 2. PIN OUT OF THE XRT84V24 IN THE 160 PIN PQFP PACKAGE
TxChClk_3
1
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
TxChClk_0
TxOHClk_0
TxOH_0
TxMSync_0
TxSync_0
G N D
TxSerClk_0
TxSER_0
RxLOS_0
RxOHClk_0
RxOH_0
RxCHClk_0
RxCASMSync_0
VDD
RxCRCMSync_0
RxSync_0
RxSerClk_0
RxSer_0
TxOHClk_3
2
TxOH_3
3
TxMSync_3
4
TxSync_3
5
G N D
6
TxSerClk_3
7
TxSer_3
8
RxLOS_3
9
RxOHClk_3
10
RxOH_3
11
RxCHClk_3
12
RxCASMSync_3
13
VDD
14
RxCRCMSync_3
15
RxSync_3
16
RxSerClk_3
17
RxSer_3
18
TCK
19
OSCClk
TMS
TDI
RESET_L
8kHzREF
TESTMODE
G N D
20
21
160 Lead PQFP
TDO
22
G N D
23
TxSer_2
24
TxSer_1
TxSerClk_2
25
TxSerClk_1
TxSync_1
TxMSync_1
TxOH_1
TxOHClk_1
RxSer_1
TxChClk_1
RxSerClk_1
VDD
RxSync_1
RxCRCMSync_1
RxCASMSync_1
RxCHClk_1
RxOH_1
TxSync_2
26
TxMSync_2
27
TxOH_2
28
TxOHClk_2
29
RxSer_2
30
TxChClk_2
31
RxSerClk_2
32
VDD
33
RxSync_2
34
RxCRCMSync2
35
RxCASMSync_2
36
RxChClk_2
37
RxOH_2
38
RxOHClk_2
82
81
RxOHClk_1
RxLOS_1
39
RxLOS_2
40
2
QUAD E1 FRAMER IC
XRT84V24
PRELIMINARY
REV. 1.0.1
FIGURE 3. PIN OUT OF THE XRT84V24 IN THE 20 PIN PQFP PACKAGE
NC
TxChClk_3
TxOHClk_3
RxCHN3_0
TxOH_3
RxCHN3_1
TxMSync_3
RxCHN_3_2
TxSync_3
RxCHN_3_3
VSS
TxSerClk_3
RxCHN_3_4
TxSer_3
RxLOS_3
RxOHClk_3
RxOH_3
RxCHClk_3
RxCASMSync_3
VDD
RxCRCMSync_3
RxSync_3
RxSerClk_3
RxSer_3
1
2
3
4
5
6
7
8
156
NC
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
TxChClk_0
TxOHClk_0
RxCHN_0_0
TxOH_0
RxCHN_0_1
TxMSync_0
RxCHN_0_2
TxSync_0
RxCHN_0_3
GND
TxSerClk_0
RxCHN_0_4
TxSER_0
RxLOS_0
RxOHClk_0
RxOH_0
RxCHClk_0
RxCASMSync_0
VDD
RxCRCMSync_0
RxSync_0
RxSerClk_0
RxSer_0
OSCClk
RESET_L
8kHzREF
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
208 Lead PQFP
TCK
TMS
TDI
TDO
GND
TxSer_2
TxSerClk_2
TxSync_2
TxMSync_2
TxOH_2
TxOHClk_2
RxSer_2
TxChClk_2
RxSerClk_2
VDD
TESTMODE
GND
TxSer_1
TxSerClk_1
TxSync_1
TxMSync_1
TxOH_1
TxOHClk_1
RxSer_1
TxChClk_1
RxSerClk_1
VDD
RxSync_2
TxCHN_2_4
RxCRCMSync2
TxCHN_2_3
RxCASMSync_2
RxChClk_2
TxCHN_2_2
RxOH_2
TxCHN_2_1
GND
RxOHClk_2
TxCHN_2_0
RxLOS_2
RxSync_1
TxCHN_1_4
RxCRCMSync_1
TxCHN_1_3
RxCASMSync_1
RxCHClk_1
TxCHN_1_2
RxOH_1
TxCHN_1_1
GND
RxOHClk_1
TxCHN_1_0
RxLOS_1
ORDERING INFORMATION
PART NUMBER
XRT84V24IV-208
XRT84V24IV-160
PACKAGE
OPERATING TEMPERATURE RANGE
-40°C to +85°C
208 Lead PQFP
160 Lead PQFP
-40°C to +85°C
3
XRT84V24 QUAD E1 FRAMER IC
PRELIMINARY
REV. 1.0.1
PACKAGE DIMENSIONS
4
QUAD E1 FRAMER IC
XRT84V24
PRELIMINARY
REV. 1.0.1
5
XRT84V24 QUAD E1 FRAMER IC
PRELIMINARY
REV. 1.0.1
REVISION HISTORY
NOTICE
EXAR Corporation reserves the right to make changes to the products contained in this publication in order to
improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any cir-
cuits described herein, conveys no license under any patent or other right, and makes no representation that
the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration pur-
poses and may vary depending upon a user’s specific application. While the information in this publication has
been carefully checked; no responsibility, however, is assumed for inaccuracies.
EXAR Corporation does not recommend the use of any of its products in life support applications where the
failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to
significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless
EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has
been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately
protected under the circumstances.
Copyright 1999 EXAR Corporation
Datasheet October 1999
Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
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