74ABT16652 [FAIRCHILD]
16-Bit Transceivers and Registers with 3-STATE Outputs; 16位收发器和寄存器与3态输出
| 型号： | 74ABT16652 |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | 16-Bit Transceivers and Registers with 3-STATE Outputs |
| 文件： | 总9页 (文件大小：94K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 1993
Revised January 1999
74ABT16652
16-Bit Transceivers and Registers with 3-STATE Outputs
General Description
Features
■ Independent registers for A and B buses
■ Multiplexed real-time and stored data
■ Separate control logic for each byte
The ABT16652 consists of sixteen bus transceiver circuits
with D-type flip-flops, and control circuitry arranged for mul-
tiplexed transmission of data directly from the input bus or
from the internal registers. Each byte has separate control
inputs which can be shorted together for full 16-bit opera-
tion. Data on the A or B bus will be clocked into the regis-
ters as the appropriate clock pin goes to HIGH logic level.
Output Enable pins (OEAB, OEBA) are provided to control
the transceiver function.
■ A and B output sink capability of 64 mA, source
capability of 32 mA
■ Guaranteed output skew
■ High impedance glitch free bus loading during entire
power up and power down cycle
■ Nondestructive hot insertion capability
Ordering Code:
Order Number
74ABT16652CSSC
74ABT16652CMTD
Package Number
MS56A
Package Description
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
MTD56
Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.
Pin Descriptions
Connection Diagram
Pin Names
Descriptions
A0–A16
B0–B16
Data Register A Inputs/
3-STATE Outputs
Data Register B Inputs/
3-STATE Outputs
CPABn, CPBAn
SABn, SBAn
Clock Pulse Inputs
Select Inputs
OEABn, OEBAn
Output Enable Inputs
© 1999 Fairchild Semiconductor Corporation
DS011599.prf
www.fairchildsemi.com
Functional Description
In the transceiver mode, data present at the HIGH imped-
ance port may be stored in either the A or B register or
both.
Data on the A or B data bus, or both can be stored in the
internal D flip-flop by LOW to HIGH transitions at the
appropriate Clock Inputs (CPABn, CPBAn) regardless of
the Select or Output Enable Inputs. When SAB and SBA
are in the real time transfer mode, it is also possible to
store data without using the internal D flip-flops by simulta-
neously enabling OEABn and OEBAn. In this configuration
The select (SABn, SBAn) controls can multiplex stored and
real-time.
The examples in Figure 1 demonstrate the four fundamen-
tal bus-management functions that can be performed with
the ABT16652.
each Output reinforces its Input. Thus when all other data
sources to the two sets of bus lines are in a HIGH imped-
ance state, each set of bus lines will remain at its last state.
Note A: Real-Time
Note C: Storage
Transfer Bus B to Bus A
OEAB OEBA CPAB CPBA SAB SBA
OEAB OEBA CPAB CPBA SAB SBA
1
1
1
1
1
1
1
1
1
1
1
1
X
H
X
X
X
L
L
X
X
X
L
L
L
X
H
X
X
X
X
X
Note B: Real-Time
Transfer Bus A to Bus B
Note D: Transfer Storage
Data to A or B
OEAB OEBA CPAB CPBA SAB SBA
1
1
1
1
1
1
OEAB OEBA CPAB1 CPBA SAB SBA
H
H
X
X
L
X
1
1
1
1
1
H
L
H or L H or L
H
H
FIGURE 1.
www.fairchildsemi.com
2
Function Table
Inputs
Inputs/Outputs (Note 1)
B0 thru B7
Input
Operating Mode
OEAB1 OEBA1 CPAB1 CPBA1 SAB1 SBA1 A0 thru A7
L
L
H
H
H
H
X
L
H or L H or L
H or L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
Input
Isolation
Store A and B Data
Not Specified Store A, Hold B
Output Store A in Both Registers
X
H
L
Input
Input
H or L
Not Specified Input
Hold A, Store B
L
Output
Output
Input
Input
Store B in Both Registers
Real-Time B Data to A Bus
Store B Data to A Bus
Real-Time A Data to B Bus
Stored A Data to B Bus
Stored A Data to B Bus and
Stored B Data to A Bus
L
L
X
X
X
H or L
X
L
L
H
X
X
H
H
H
H
H
H
L
X
Input
Output
Output
H or L
X
H
H
H or L H or L
Output
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW to HIGH Clock Transition
Note 1: The data output functions may be enabled or disabled by various signals at OEAB or OEBA inputs. Data input functions are always enabled, i.e.,
data at the bus pins will be stored on every LOW to HIGH transition on the clock inputs. This also applies to data I/O (A and B: 8–15) and #2 control pins.
Logic Diagrams
Please note that these diagrams are provided only for the understanding of logic operations and should not be used to estimate propagation delays.
3
www.fairchildsemi.com
Over Voltage Latchup (I/O)
10V
Absolute Maximum Ratings(Note 2)
Storage Temperature
−65°C to +150°C
Recommended Operating
Conditions
Ambient Temperature under Bias
Junction Temperature under Bias
VCC Pin Potential to
−55°C to +125°C
−55°C to +150°C
Free Air Ambient Temperature
Supply Voltage
−40°C to +85°C
+4.5V to +5.5V
Ground Pin
−0.5V to +7.0V
−0.5V to +7.0V
Minimum Input Edge Rate (∆V/∆t)
Data Input
Input Voltage (Note 3)
50 mV/ns
20 mV/ns
100 mV/ns
Input Current (Note 3)
−30 mA to +5.0 mA
Enable Input
Voltage Applied to Any Output
in the Disable or Power-Off State
in the HIGH State
Clock Input
−0.5V to +5.5V
−0.5V to VCC
Note 2: Absolute maximum ratings are values beyond which the device
may be damaged or have its useful life impaired. Functional operation
under these conditions is not implied.
Current Applied to Output
in LOW State (Max)
Note 3: Either voltage limit or current limit is sufficient to protect inputs.
twice the rated IOL (mA)
DC Latchup Source Current
−500 mA
DC Electrical Characteristics
Symbol
Parameter
Min
Typ
Max
Units
V
Conditions
CC
V
Input HIGH Voltage
V
V
V
V
Recognized HIGH Signal
Recognized LOW Signal
IH
V
V
V
Input LOW Voltage
Input Clamp Diode Voltage
Output HIGH
0.8
IL
−1.2
Min
Min
I
I
I
I
I
= −18 mA (Non I/O Pins)
CD
OH
IN
2.5
2.0
= −3 mA, (A , B )
n n
OH
OH
OL
Voltage
= −32 mA, (A , B )
n n
V
V
Output LOW Voltage
Input Leakage Test
0.55
V
V
Min
0.0
= 64 mA, (A , B )
n n
OL
ID
= 1.9 µA, (Non-I/O Pins)
ID
All Other Pins Grounded
I
I
I
I
I
Input HIGH Current
1
1
7
µA
µA
µA
µA
µA
Max
Max
V
V
V
= 2.7V (Non-I/O Pins) (Note 4)
IH
IN
IN
IN
= V (Non-I/O Pins)
CC
Input HIGH Current
Breakdown Test
= 7.0V (Non-I/O Pins)
BVI
BVIT
IL
Input HIGH Current
Breakdown Test (I/O)
Input LOW Current
100
Max
V
= 5.5V (A , B )
n n
IN
−1
−1
10
Max
V
V
V
= 0.5V (Non-I/O Pins) (Note 4)
= 0.0V (Non-I/O Pins)
IN
IN
+ I
Output Leakage Current
0V–5.5V
= 2.7V (A , B );
OUT n n
IH
IL
OZH
OEAB = GND and OEBA = 2.0V
n
n
I
+ I
Output Leakage Current
−10
µA
0V–5.5V
V
= 0.5V (A , B );
OZL
OUT n n
OEAB = GND and OEBA = 2.0V
n
n
I
I
I
I
I
I
Output Short-Circuit Current
Output HIGH Leakage Current
Bus Drainage Test
−275
50
mA
µA
Max
Max
0.0V
Max
Max
Max
V
V
V
= 0V (A , B )
n n
OS
OUT
OUT
OUT
= V (A , B )
CEX
ZZ
CC
n
n
100
1.0
60
µA
= 5.5V (A , B ); All Others GND
n n
Power Supply Current
Power Supply Current
Power Supply Current
mA
mA
mA
All Outputs HIGH
All Outputs LOW
Outputs 3-STATE;
CCH
CCL
CCZ
1.0
All Others at V or GND
CC
I
Additional I /Input
2.5
mA
Max
Max
V = V − 2.1V
I CC
CCT
CC
All Others at V or GND
CC
I
Dynamic I
(Note 4)
No Load
0.23
mA/MHz
Outputs Open
CCD
CC
OEAB , OEBA and SEL = GND
n
n
Non-I/O = GND or V
CC
One bit toggling, 50% duty cycle
Note 4: Guaranteed but not tested.
www.fairchildsemi.com
4
DC Electrical Characteristics
(SSOP Package)
Conditions
= 50 pF, R = 500Ω
V
Symbol
Parameter
Min
Typ
Max
Units
CC
C
L
L
V
Quiet Output Maximum Dynamic V
0.7
−1.0
3.0
1.2
V
V
V
V
V
5.0
5.0
5.0
5.0
5.0
T
T
T
T
T
= 25°C (Note 5)
= 25°C (Note 5)
= 25° (Note 6)
= 25°C (Note 7)
= 25°C (Note 7)
OLP
OLV
OHV
IHD
ILD
OL
A
A
A
A
A
V
V
V
V
Quiet Output Minimum Dynamic V
−1.4
2.5
OL
Minimum HIGH Level Dynamic Output Voltage
Minimum HIGH Level Dynamic Input Voltage
Maximum LOW Level Dynamic Input Voltage
2.0
1.6
1.2
0.8
Note 5: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output at LOW. Guaranteed, but not tested.
Note 6: Max number of outputs defined as (n). n − 1 data inputs are driven 0V to 3V. One output HIGH. Guaranteed, but not tested.
Note 7: Max number of data inputs (n) switching. n − 1 inputs switching 0V to 3V. Input-under-test switching: 3V to threshold (V ), 0V to threshold (V ).
ILD
IHD
Guaranteed, but not tested.
AC Electrical Characteristics
(SSOP Package)
T
= +25°C
T
= −40°C to +85°C
A
A
V
= +5.0V
= 50 pF
V
= 4.5V–5.5V
CC
CC
Symbol
Parameter
Units
C
C = 50 pF
L
L
Min
1.5
1.5
1.5
1.5
1.5
1.5
Typ
3.0
3.4
2.6
3.0
2.9
3.2
Max
4.9
4.9
4.5
4.5
5.0
5.0
Min
1.5
1.5
1.5
1.5
1.5
1.5
Max
t
t
t
t
t
t
Propagation Delay
4.9
4.9
4.5
4.5
5.0
5.0
ns
ns
ns
PLH
Clock to Bus
PHL
PLH
PHL
PLH
PHL
Propagation Delay
Bus to Bus
Propagation Delay
SBA or SAB
n
n
to A to B
n
n
t
t
Enable Time
OEBA or OEAB
1.5
1.5
2.8
3.0
5.5
5.5
1.5
1.5
5.5
5.5
ns
ns
PZH
PZL
n
n
to A or B
n
n
t
t
Disable Time
1.5
1.5
3.9
3.3
5.9
5.9
1.5
1.5
5.9
5.9
PHZ
PLZ
OEBA or OEAB
n
n
to A or B
n
n
AC Operating Requirements
T
V
= +25°C
T = −40°C to +85°C
A
A
= +5.0V
= 50 pF
V
= 4.5V–5.5V
CC
CC
Symbol
Parameter
Units
C
C = 50 pF
L
L
Min
2.0
1.0
3.0
Typ
Max
Min
2.0
1.0
3.0
Max
f
Max Clock Frequency
200
MHz
ns
max
t (H)
Setup Time, HIGH
or LOW Bus to Clock
Hold Time, HIGH
or LOW Bus to Clock
Pulse Width,
S
t (L)
S
t
t
t
t
(H)
(L)
ns
ns
H
H
(H)
(L)
W
W
HIGH or LOW
5
www.fairchildsemi.com
Extended AC Electrical Characteristics
(SSOP Package)
T
= −40°C to +85°C
T
= −40°C to +85°C
T = −40°C to +85°C
A
A
A
V
= 4.5V–5.5V
V
= 4.5V–5.5V
V
= 4.5V–5.5V
CC
CC
CC
C
= 50 pF
C
= 250 pF
C
= 250 pF
L
L
L
Symbol
Parameter
Units
16 Outputs Switching
(Note 8)
1 Output Switching
(Note 9)
16 Outputs Switching
(Note 10)
Min
1.5
1.5
1.5
1.5
1.5
1.5
Max
5.8
5.8
6.5
6.5
6.0
6.0
Min
2.0
2.0
2.0
2.0
2.0
2.0
Max
7.5
7.5
7.0
7.0
7.5
7.5
Min
2.5
2.5
2.5
2.5
2.5
2.5
Max
10.0
10.0
9.5
t
t
t
t
t
t
Progagation Delay
ns
ns
PLH
Clock to Bus
PHL
PLH
PHL
PLH
PHL
Progagation Delay
Bus to Bus
9.5
Progagation Delay
SBA or SAB to
10.0
10.0
ns
ns
A
or B
n
n
t
t
Output Enable Time
OEBA or OEAB to
1.5
1.5
6.0
6.0
2.0
2.0
8.0
8.0
2.5
2.5
10.5
10.5
PZH
PZL
n
n
A
or B
n
n
t
t
Output Disable Time
OEBA or OEAB to
1.5
1.5
6.0
6.0
PHZ
PLZ
(Note 11)
(Note 11)
ns
A
or B
n
n
Note 8: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 9: This specification is guaranteed but not tested. The limits represent propagation delay with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load. This specification pertains to single output switching only.
Note 10: This specification is guaranteed but not tested. The limits represent propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.) with 250 pF load capacitors in place of the 50 pF load capacitors in the standard AC load.
Note 11: The 3-STATE delay times are dominated by the RC network (500Ω, 250 pF) on the output and has been excluded from the datasheet.
Skew (Note 12)
(SSOP Package)
T
= −40°C to +85°C
T = −40°C to +85°C
A
A
V
= 4.5V–5.5V
V
= 4.5V–5.5V
CC
CC
C
= 50 pF
C = 250 pF
L
L
Symbol
Parameter
Units
16 Outputs Switching
16 Outputs Switching
(Note 12)
Max
(Note 13)
Max
t
Pin to Pin Skew
2.0
2.5
ns
ns
OSHL
(Note 14)
HL Transitions
t
Pin to Pin Skew
LH Transitions
2.0
2.0
2.8
3.5
2.5
2.5
3.0
4.0
OSLH
(Note 14)
t
Duty Cycle
PS
(Note 15)
LH–HL Skew
t
Pin to Pin Skew
LH/HL Transitions
Device to Device Skew
LH/HL Transitions
ns
ns
OST
(Note 14)
t
PV
(Note 16)
Note 12: This specification is guaranteed but not tested. The limits apply to propagation delays for all paths described switching in phase
(i.e., all LOW-to-HIGH, HIGH-to-LOW, etc.).
Note 13: This specification is guaranteed but not tested. The limits represent propagation delays with 250 pF load capacitors in place of the 50 pF load
capacitors in the standard AC load.
Note 14: Skew is defined as the absolute value of the difference between the actual propagation delays for any two separate outputs of the same device.
The specification applies to any outputs switching HIGH to LOW (t
), LOW to HIGH (t
), or any combination switching LOW to HIGH and/or HIGH to
OSLH
OSHL
LOW (t
). This specification is guaranteed but not tested.
OST
Note 15: This describes the difference between the delay of the LOW-to-HIGH and the HIGH-to-LOW transition on the same pin. It is measured across all
the outputs (drivers) on the same chip, the worst (largest delta) number is the guaranteed specification. This specification is guaranteed but not tested.
Note 16: Propagation delay variation for a given set of conditions (i.e., temperature and V ) from device to device. This specification is guaranteed but not
CC
tested.
www.fairchildsemi.com
6
Capacitance
Conditions
(T = 25°C)
Symbol
Parameter
Typ
Units
A
C
C
Input Capacitance
I/O Capacitance
5.0
pF
pF
V
V
= 0V (non I/O pins)
IN
CC
CC
(Note 17)
11.0
= 5.0V (A , B )
n n
I/O
Note 17: C is measured at frequency, f = 1 MHz, per MIL-STD-883, Method 3012.
I/O
AC Loading
*Includes jig and probe capacitance
FIGURE 3. Test Input Signal Levels
Input Pulse Requirement
FIGURE 2. Standard AC Test Load
Amplitude Rep. Rate
3.0V 1 MHz
tW
tr
tf
500 ns
2.5 ns
2.5 ns
FIGURE 4. Test input Signal Requirements
AC Waveforms
FIGURE 5. Propagation Delay Waveforms for Inverting
and Non-Inverting Functions
FIGURE 7. 3-STATE Output HIGH
and LOW Enable and Disable Times
FIGURE 8. Setup Time, Hold Time
and Recovery Time Waveforms
FIGURE 6. Propagation Delay,
Pulse Width Waveforms
7
www.fairchildsemi.com
Physical Dimensions inches (millimeters) unless otherwise noted
56-Lead Shrink Small Outline Package (SSOP), JEDEC MO-118, 0.300” Wide
Package Number MS56A
www.fairchildsemi.com
8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Package Number MTD56
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
www.fairchildsemi.com
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications.
相关型号：
74ABT16652DG
IC ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.10 MM, PLASTIC, MO-153, SOT-364-1, TSSOP2-56, Bus Driver/Transceiver
NXP
74ABT16652DG-T
IC ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, Bus Driver/Transceiver
NXP
74ABT16652DGT
IC ABT SERIES, DUAL 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO56, 6.10 MM, PLASTIC, MO-153, SOT-364-1, TSSOP2-56, Bus Driver/Transceiver
NXP
©2020 ICPDF网 联系我们和版权申明