74ABT2240CSCX [FAIRCHILD]

Dual 4-Bit Inverting Buffer/Driver ; 双4位缓冲器/驱动器\n


型号：	74ABT2240CSCX
厂家：	FAIRCHILD SEMICONDUCTOR
描述：	Dual 4-Bit Inverting Buffer/Driver 双4位缓冲器/驱动器\n 总线驱动器总线收发器逻辑集成电路光电二极管输出元件信息通信管理
文件：	总8页 (文件大小：94K)
中文：	中文翻译
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March 1994

Revised November 1999

74ABT2240

Octal Buffer/Line Driver with

25Ω Series Resistors in the Outputs

General Description

Features

■ Guaranteed latchup protection

The ABT2240 is an inverting octal buffer and line driver

designed to drive the capacitive inputs of MOS memory

drivers, address drivers, clock drivers, and bus-oriented

transmitters/receivers.

■ High impedance glitch-free bus loading during entire

power up and power down cycle

■ Nondestructive hot insertion capability

The 25Ω series resistors in the outputs reduce ringing and

eliminate the need for external resistors.

Ordering Code:

Order Number

74ABT2240CSC

74ABT2240CSJ

74ABT2240CMSA

74ABT2240CMTC

Package Number

M20B

Package Description

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

M20D

MSA20

MTC20

Devices also available in Tape and Reel. Specify by appending letter suffix “X” to the ordering code.

Connection Diagram

Pin Descriptions

Pin Names

Descriptions

OE₁, OE₂

D₀–D₇

Output Enable Input (Active LOW)

Data Inputs

O₀–O₇

Outputs

Schematic of Each Output

Truth Table

OE₁

I_0–3

O_0–3

OE₂

I_4–7

O_4–7

H = HIGH Voltage Level

L = LOW Voltage Level

X = Immaterial

Z = High Impedance

DS011665

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Absolute Maximum Ratings(Note 1)

Recommended Operating

Conditions

−65°C to +150°C

Storage Temperature

Ambient Temperature under Bias

Junction Temperature under Bias

−55°C to +125°C

−55°C to +150°C

−0.5V to +7.0V

Free Air Ambient Temperature

Supply Voltage

−40°C to +85°C

+4.5V to +5.5V

_CCPin Potential to Ground Pin

Minimum Input Edge Rate (∆V/∆t)

Data Input

Input Voltage (Note 2)

Input Current (Note 2)

Voltage Applied to Any Output

in the Disabled or

−0.5V to +7.0V

50 mV/ns

20 mV/ns

−30 mA to +5.0 mA

Enable Input

Power-off State

−0.5V to 5.5V

−0.5V to V_CC

in the HIGH State

Current Applied to Output

in LOW State (Max)

Note 1: Absolute maximum ratings are values beyond which the device

may be damaged or have its useful life impaired. Functional operation

under these conditions is not implied.

twice the rated I_OL(mA)

DC Latchup Source Current

(Across Comm Operating Range)

Over Voltage Latchup (I/O)

Note 2: Either voltage limit or current limit is sufficient to protect inputs.

−300 mA

10V

DC Electrical Characteristics

V_CC

Symbol

V_IH

Parameter

Input HIGH Voltage

Min

Typ

Max

Units

Conditions

2.0

Recognized HIGH Signal

Recognized LOW Signal

V_IL

Input LOW Voltage

Input Clamp Diode Voltage

Output HIGH

0.8

V_CD

V_OH

−1.2

Min

_IN= −18 mA

_OH= −3 mA

_OH= −32 mA

_OL= 15 mA

2.5

2.0

Voltage

V_OL

I_IH

Output LOW Voltage

Input HIGH Current

0.8

_IN= 2.7V (Note 3)

_IN= V _CC

µA

Max

0.0

I_BVI

I _IL

Input HIGH Current Breakdown Test

Input LOW Current

_IN= 7.0V

−1

_IN= 0.5V (Note 3)

_IN= 0.0V

V_ID

Input Leakage Test

_ID= 1.9 µA

All Other Pins Grounded

I_OZH

I_OZL

Output Leakage Current

µA

0 − 5.5V

_OUT= 2.7V; OEn = 2.0V

−10

_OUT= 0.5V; OEn = 2.0V

_OUT= 0.0V

I_OS

Output Short-Circuit Current

Output HIGH Leakage Current

Bus Drainage Test

−275

µA

Max

0.0

I_CEX

I_ZZ

I_CCH

I_CCL

I_CCZ

_OUT= V _CC

100

_OUT= 5.5V; All Others GND

Power Supply Current

Max

All Outputs HIGH

All Outputs LOW

Power Supply Current

µA

Max

OEn = V _CC

All Others at V_CCor GND

V_I= V _CC− 2.1V

I_CCT

Additional

I_CC/Input

Outputs Enabled

Outputs 3-STATE

1.5

µA

Max

Enable Input V_I= V_CC− 2.1V

Data Input V_I= V_CC− 2.1V

All Others at V_CCor GND

Outputs OPEN

I_CCD

Dynamic I_CC

(Note 3)

No Load

mA/

Max

0.1

MHz

OEn = GND (Note 4)

One Bit Toggling, 50% Duty Cycle

Note 3: Guaranteed, but not tested.

Note 4: For 8 bits toggling, I_CCD< 0.8 mA/MHz.

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AC Electrical Characteristics

_A= +25°C

_A= −40°C to +85°C

_CC= 4.5V–5.5V

_L= 50 pF

Max

_CC= +5V

_L= 50 pF

Typ

Symbol

Parameter

Units

Min

1.0

1.5

2.7

1.9

Max

4.9

5.3

6.6

6.9

6.4

Min

1.0

1.5

2.7

1.9

t_PLH

Propagation

4.9

5.3

6.6

6.9

6.4

t_PHL

t_PZH

t_PZL

t_PHZ

t_PLZ

Delay Data to Outputs

Output Enable

Time

Output Disable

Time

Capacitance

Conditions

Symbol

Parameter

Typ

Units

_A= 25°C

C_IN

Input Capacitance

Output Capacitance

5.0

9.0

_CC= 0V

C_OUT(Note 5)

_CC= 5.0V

Note 5: C_OUTis measured at frequency f = 1 MHz, per MIL-STD-883, Method 3012.

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AC Loading

*Includes jig and probe capacitance

FIGURE 2. Propagation Delay,

Pulse Width Waveforms

FIGURE 1. Standard AC Test Load

Amplitude Rep. Rate

3.0V 1 MHz

t_W

t_r

2.5 ns

t_f

500 ns

2.5 ns

FIGURE 3. Test Input Signal Requirements

AC Waveforms

FIGURE 4. Propagation Delay Waveforms for

Inverting and Non-Inverting Functions

FIGURE 6. Test Input Signal Levels

FIGURE 5. 3-STATE Output HIGH

and LOW Enable and Disable Times

FIGURE 7. Setup Time, Hold Time

and Recovery Time Waveforms

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Physical Dimensions inches (millimeters) unless otherwise noted

20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300” Wide Body

Package Number M20B

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide

Package Number M20D

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide

Package Number MSA20

www.fairchildsemi.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide

Package Number MTC20

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and

Fairchild reserves the right at any time without notice to change said circuitry and specifications.

LIFE SUPPORT POLICY

FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT

DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD

SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the

body, or (b) support or sustain life, and (c) whose failure

to perform when properly used in accordance with

instructions for use provided in the labeling, can be rea-

sonably expected to result in a significant injury to the

user.

2. A critical component in any component of a life support

device or system whose failure to perform can be rea-

sonably expected to cause the failure of the life support

device or system, or to affect its safety or effectiveness.

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