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74AC169 [FAIRCHILD]

4-Stage Synchronous Bidirectional Counter; 4级同步双向计数器
74AC169
型号： 74AC169
厂家： FAIRCHILD SEMICONDUCTOR    FAIRCHILD SEMICONDUCTOR
描述：

4-Stage Synchronous Bidirectional Counter
4级同步双向计数器

计数器
文件： 总8页 (文件大小：106K)
中文：  中文翻译
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November 1988  
Revised November 1999  
74AC169  
4-Stage Synchronous Bidirectional Counter  
General Description  
Features  
The AC169 is fully synchronous 4-stage up/down counter.  
The AC169 is a modulo-16 binary counter. It features a  
preset capability for programmable operation, carry looka-  
head for easy cascading and a U/D input to control the  
direction of counting. All state changes, whether in count-  
ing or parallel loading, are initiated by the LOW-to-HIGH  
transition of the Clock.  
■ ICC reduced by 50%  
■ Synchronous counting and loading  
■ Built-In lookahead carry capability  
■ Presettable for programmable operation  
■ Outputs source/sink 24 mA  
Ordering Code:  
Order Number Package Number  
Package Description  
74AC169SC  
74AC169SJ  
74AC169MTC  
74AC169PC  
M16A  
M16D  
MTC16  
N16E  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150” Narrow Body  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.  
Logic Symbols  
Connection Diagram  
IEEE/IEC  
Pin Descriptions  
Pin Names  
Description  
CEP  
CET  
CP  
Count Enable Parallel Input  
Count Enable Trickle Input  
Clock Pulse Input  
P0–P3  
PE  
Parallel Data Inputs  
Parallel Enable Input  
Up-Down Count Control Input  
Flip-Flop Outputs  
U/D  
Q0–Q3  
TC  
Terminal Count Output  
FACT is a trademark of Fairchild Semiconductor Corporation.  
© 1999 Fairchild Semiconductor Corporation  
DS009934  
www.fairchildsemi.com  
Functional Description  
Mode Select Table  
The AC169 uses edge-triggered J-K-type flip-flops and  
have no constraints on changing the control or data input  
signals in either state of the Clock. The only requirement is  
that the various inputs attain the desired state at least a  
setup time before the rising edge of the clock and remain  
valid for the recommended hold time thereafter. The paral-  
lel load operation takes precedence over the other opera-  
tions, as indicated in the Mode Select Table. When PE is  
LOW, the data on the P0–P3 inputs enters the flip-flops on  
Action on Rising  
Clock Edge  
PE  
CEP CET  
U/D  
L
H
H
H
H
X
L
X
L
X
H
L
Load (Pn to Qn)  
Count Up (Increment)  
Count Down (Decrement)  
No Change (Hold)  
L
L
H
X
X
H
X
X
the next rising edge of the Clock. In order for counting to  
occur, both CEP and CET must be LOW and PE must be  
HIGH; the U/D input then determines the direction of count-  
ing. The Terminal Count (TC) output is normally HIGH and  
goes LOW, provided that CET is LOW, when a counter  
reaches zero in the Count Down mode or reaches 15 in the  
Count Up mode. The TC output state is not a function of  
the Count Enable Parallel (CEP) input level. If an illegal  
state occurs, the AC169 will return to the legitimate  
sequence within two counts. Since the TC signal is derived  
by decoding the flip-flop states, there exists the possibility  
of decoding spikes on TC. For this reason the use of TC as  
a clock signal is not recommended (see logic equations  
below).  
No Change (Hold)  
H = HIGH Voltage Level  
L = LOW Voltage Level  
X = Immaterial  
State Diagram  
1. Count Enable = CEP •CET • PE  
2. Up: TC = Q0•Q1•Q 2Q3•(Up)•CET  
3. Down: TC = Q0• Q1•Q2•Q3 •(Down)•CET  
Logic Diagram  
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.  
www.fairchildsemi.com  
2
Absolute Maximum Ratings(Note 1)  
Recommended Operating  
Conditions  
Supply Voltage (VCC  
)
−0.5V to +7.0V  
DC Input Diode Current (IIK  
VI = −0.5V  
)
Supply Voltage (VCC  
)
2.0V to 6.0V  
0V to VCC  
−20 mA  
+20 mA  
Input Voltage (VI)  
VI = VCC + 0.5V  
Output Voltage (VO)  
0V to VCC  
DC Input Voltage (VI)  
−0.5V to VCC + 0.5V  
Operating Temperature (TA)  
−40°C to +85°C  
DC Output Diode Current (IOK  
)
Minimum Input Edge Rate (∆V/∆t)  
V
V
O = −0.5V  
−20 mA  
+20 mA  
V
IN from 30% to 70% of VCC  
O = VCC + 0.5V  
VCC @ 3.3V, 4.5V, 5.5V  
125 mV/ns  
DC Output Voltage (VO)  
DC Output Source  
−0.5V to VCC + 0.5V  
or Sink Current (IO)  
±50 mA  
DC VCC or Ground Current  
per Output Pin (ICC or IGND  
)
±50 mA  
Note 1: Absolute maximum ratings are those values beyond which damage  
to the device may occur. The databook specifications should be met, with-  
out exception, to ensure that the system design is reliable over its power  
supply, temperature, and output/input loading variables. Fairchild does not  
recommend operation of FACT circuits outside databook specifications.  
Storage Temperature (TSTG  
Junction Temperature (TJ)  
PDIP  
)
−65°C to +150°C  
140°C  
DC Electrical Characteristics  
T
A = +25°C  
TA = −40°C to +85°C  
VCC  
(V)  
Symbol  
VIH  
Parameter  
Units  
Conditions  
Typ  
1.5  
Guaranteed Limits  
Minimum HIGH Level  
Input Voltage  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
2.1  
2.1  
3.15  
3.85  
0.9  
V
OUT = 0.1V  
2.25  
2.75  
1.5  
3.15  
3.85  
0.9  
V
or VCC − 0.1V  
VIL  
Maximum LOW Level  
Input Voltage  
V
OUT = 0.1V  
2.25  
2.75  
2.99  
4.49  
5.49  
1.35  
1.65  
2.9  
1.35  
1.65  
2.9  
V
V
or VCC − 0.1V  
VOH  
Minimum HIGH Level  
Output Voltage  
4.4  
4.4  
IOUT = −50 µA  
5.4  
5.4  
V
IN = VIL or VIH  
3.0  
4.5  
5.5  
3.0  
4.5  
5.5  
2.56  
3.86  
4.86  
0.1  
2.46  
3.76  
4.76  
0.1  
I
I
I
OH = −12 mA  
V
V
OH = −24 mA  
OH = −24 mA (Note 2)  
VOL  
Maximum LOW Level  
Output Voltage  
0.002  
0.001  
0.001  
0.1  
0.1  
I
OUT = 50 µA  
0.1  
0.1  
V
IN = VIL or VIH  
3.0  
4.5  
5.5  
0.36  
0.36  
0.36  
0.44  
0.44  
0.44  
I
I
I
OL = 12 mA  
V
OL = 24 mA  
OL = 24 mA (Note 2)  
IIN  
Maximum Input  
5.5  
±0.1  
±1.0  
µA  
VI = VCC, GND  
(Note 4)  
IOLD  
Leakage Current  
Minimum Dynamic  
Output Current (Note 3)  
Maximum Quiescent  
Supply Current  
5.5  
5.5  
75  
mA  
mA  
V
V
V
OLD = 1.65V Max  
OHD = 3.85V Min  
IN = VCC  
IOHD  
−75  
ICC  
5.5  
4.0  
40.0  
µA  
(Note 4)  
or GND  
Note 2: All outputs loaded; thresholds on input associated with output under test.  
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.  
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC  
.
3
www.fairchildsemi.com  
AC Electrical Characteristics  
VCC (V)  
T
A = +25°C, CL = 50 pF  
TA = −40°C to +85°C, CL = 50 pF  
Symbol  
Parameter  
(Note 5)  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
Min  
75  
Typ  
118  
154  
9.5  
Max  
Min  
65  
Max  
Units  
MHz  
fMAX  
Maximum Clock  
Frequency  
100  
2.5  
1.5  
2.5  
1.5  
4.5  
3.0  
3.5  
2.5  
3.5  
3.0  
3.0  
2.0  
3.5  
2.5  
2.5  
1.5  
90  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
tPLH  
tPHL  
Propagation Delay  
CP to Qn (PE HIGH or LOW)  
Propagation Delay  
CP to Qn (PE HIGH or LOW)  
Propagation Delay  
CP to TC  
13.0  
10.0  
14.5  
11.0  
18.0  
13.0  
18.0  
13.0  
15.0  
10.5  
12.5  
9.0  
2.0  
1.5  
2.0  
1.5  
3.5  
2.0  
3.0  
2.0  
3.0  
2.5  
2.5  
1.5  
3.0  
2.0  
2.0  
1.5  
14.5  
11.0  
16.0  
12.0  
22.0  
14.0  
20.5  
14.5  
16.5  
12.0  
14.5  
10.0  
17.0  
12.0  
15.5  
10.5  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
7.0  
10.5  
7.5  
13.5  
9.5  
Propagation Delay  
CP to TC  
13.5  
9.5  
Propagation Delay  
CET to TC  
11.0  
8.0  
Propagation Delay  
CET to TC  
9.5  
7.0  
Propagation Delay  
U/D to TC  
11.0  
8.0  
15.0  
10.5  
13.5  
9.5  
Propagation Delay  
U/D to TC  
10.0  
7.0  
Note 5: Voltage Range 3.3 is 3.3V ± 0.3V Voltage Range 5.0 is 5.0V ± 0.5V  
AC Operating Requirements  
VCC (V)  
T
A = +25°C, CL = 50 pF  
TA = −40°C to +85°C, CL = 50 pF  
Symbol  
tS  
Parameter  
Units  
ns  
(Note 6)  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
3.3  
5.0  
Typ  
Guaranteed Minimum  
Setup Time, HIGH or LOW  
Pn to CP  
3.0  
1.5  
4.5  
2.5  
0.5  
1.5  
10.5  
7.0  
0
5.0  
2.5  
0.5  
1.5  
12.5  
8.0  
0
tH  
Hold Time, HIGH or LOW  
−1.5  
−0.5  
7.5  
ns  
Pn to CP  
tS  
Setup Time, HIGH or LOW  
CEP to CP  
ns  
4.5  
tH  
Hold Time, HIGH or LOW  
CEP to CP  
−4.5  
−2.0  
7.0  
ns  
0.5  
10.0  
6.5  
0
1.0  
12.0  
8.0  
0
tS  
tH  
tS  
tH  
Setup Time, HIGH or LOW  
CET to CP  
ns  
4.0  
Hold Time, HIGH or LOW  
CET to CP  
−6.0  
−4.0  
3.5  
ns  
0.5  
5.5  
3.5  
0
1.0  
6.5  
4.0  
0
Setup Time, HIGH or LOW  
PE to CP  
ns  
2.0  
Hold Time, HIGH or LOW  
PE to CP  
−3.5  
−1.5  
7.0  
ns  
0.5  
10.0  
6.5  
0
0.5  
11.5  
7.5  
0
tS  
Setup Time, HIGH or LOW  
U/D to CP  
ns  
4.5  
tH  
Hold Time, HIGH or LOW  
U/D to CP  
−7.0  
−4.0  
2.0  
ns  
0.5  
3.0  
3.0  
0.5  
4.0  
3.0  
tW  
CP Pulse Width,  
HIGH or LOW  
ns  
2.0  
Note 6: Voltage Range 3.3 is 3.3V ± 0.3V  
Voltage Range 5.0 is 5.0V ± 0.5V  
Capacitance  
Symbol  
Parameter  
Input Capacitance  
Power Dissipation Capacitance  
Typ  
Units  
Conditions  
CIN  
4.5  
pF  
pF  
V
V
CC = OPEN  
CC = 5.0V  
CPD  
60.0  
www.fairchildsemi.com  
4
Physical Dimensions inches (millimeters) unless otherwise noted  
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 1.150” Narrow Body  
Package Number M16A  
5
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
16-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide  
Package Number M16D  
www.fairchildsemi.com  
6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
16-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide  
Package Number MTC16  
7
www.fairchildsemi.com  
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)  
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide  
Package Number N16E  
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and  
Fairchild reserves the right at any time without notice to change said circuitry and specifications.  
LIFE SUPPORT POLICY  
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT  
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD  
SEMICONDUCTOR CORPORATION. As used herein:  
1. Life support devices or systems are devices or systems  
which, (a) are intended for surgical implant into the  
body, or (b) support or sustain life, and (c) whose failure  
to perform when properly used in accordance with  
instructions for use provided in the labeling, can be rea-  
sonably expected to result in a significant injury to the  
user.  
2. A critical component in any component of a life support  
device or system whose failure to perform can be rea-  
sonably expected to cause the failure of the life support  
device or system, or to affect its safety or effectiveness.  
www.fairchildsemi.com  
www.fairchildsemi.com  
8

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