74AC74SJX [FAIRCHILD]
Dual D-Type Flip-Flop ; 双D型触发器\n
| 型号： | 74AC74SJX |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Dual D-Type Flip-Flop
|
| 文件： | 总9页 (文件大小：106K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
November 1988
Revised November 1999
74AC74 • 74ACT74
Dual D-Type Positive Edge-Triggered Flip-Flop
General Description
Features
The AC/ACT74 is a dual D-type flip-flop with Asynchronous
Clear and Set inputs and complementary (Q, Q) outputs.
Information at the input is transferred to the outputs on the
positive edge of the clock pulse. Clock triggering occurs at
a voltage level of the clock pulse and is not directly related
to the transition time of the positive-going pulse. After the
Clock Pulse input threshold voltage has been passed, the
Data input is locked out and information present will not be
transferred to the outputs until the next rising edge of the
Clock Pulse input.
■ ICC reduced by 50%
■ Output source/sink 24 mA
■ ACT74 has TTL-compatible inputs
Asynchronous Inputs:
LOW input to SD (Set) sets Q to HIGH level
LOW input to CD (Clear) sets Q to LOW level
Clear and Set are independent of clock
Simultaneous LOW on CD and SD makes both Q and Q
HIGH
Ordering Code:
Order Number Package Number
Package Description
74AC74SC
74AC74SJ
M14A
M14D
MTC14
N14A
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74AC74MTC
74AC74PC
74ACT74SC
74ACT74SJ
74ACT74MTC
74ACT74PC
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M14A
M14D
MTC14
N14A
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D1, D2
CP1, CP2
D1, CD2
Description
Data Inputs
Clock Pulse Inputs
Direct Clear Inputs
Direct Set Inputs
Outputs
C
SD1, SD2
Q1, Q1, Q2, Q2
FACT is a trademark of Fairchild Semiconductor Corporation.
© 1999 Fairchild Semiconductor Corporation
DS009920
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Logic Symbols
IEEE/IEC
Truth Table
(Each Half)
Inputs
Outputs
SD
CD
CP
D
Q
Q
L
H
L
H
L
X
X
X
X
X
X
H
L
H
L
L
H
L
H
H
L
H
H
H
H
H
H
H
L
H
L
X
Q0
Q0
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
= LOW-to-HIGH Clock Transition
Q
0 (Q0) = Previous Q (Q) before LOW-to-HIGH Transition of Clock
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
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2
Absolute Maximum Ratings(Note 1)
Recommended Operating
Conditions
Supply Voltage (VCC
)
−0.5V to +7.0V
DC Input Diode Current (IIK
VI = −0.5V
)
Supply Voltage (VCC
)
−20 mA
+20 mA
AC
2.0V to 6.0V
4.5V to 5.5V
0V to VCC
VI = VCC + 0.5V
ACT
DC Input Voltage (VI)
−0.5V to VCC + 0.5V
Input Voltage (VI)
Output Voltage (VO)
DC Output Diode Current (IOK
)
0V to VCC
V
V
O = −0.5V
−20 mA
+20 mA
Operating Temperature (TA)
Minimum Input Edge Rate (∆V/∆t)
AC Devices
−40°C to +85°C
O = VCC + 0.5V
DC Output Voltage (VO)
DC Output Source
−0.5V to VCC + 0.5V
V
IN from 30% to 70% of VCC
or Sink Current (IO)
±50 mA
VCC @ 3.3V, 4.5V, 5.5V
Minimum Input Edge Rate (∆V/∆t)
ACT Devices
125 mV/ns
125 mV/ns
DC VCC or Ground Current
per Output Pin (ICC or IGND
)
±50 mA
Storage Temperature (TSTG
Junction Temperature (TJ)
PDIP
)
−65°C to +150°C
V
IN from 0.8V to 2.0V
VCC @ 4.5V, 5.5V
140°C
Note 1: Absolute maximum ratings are those values beyond which damage
to the device may occur. The databook specifications should be met, with-
out exception, to ensure that the system design is reliable over its power
supply, temperature, and output/input loading variables. Fairchild does not
recommend operation of FACT circuits outside databook specifications.
DC Electrical Characteristics for AC
VCC
TA = −40°C to +85°C
T
A = +25°C
Symbol
VIH
Parameter
Units
Conditions
(V)
3.0
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
Typ
1.5
Guaranteed Limits
Minimum HIGH
2.1
3.15
3.85
0.9
2.1
3.15
3.85
0.9
V
OUT = 0.1V
Level Input
Voltage
2.25
2.75
1.5
V
or VCC − 0.1V
VIL
Maximum LOW
Level Input
Voltage
V
OUT = 0.1V
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
V
or VCC − 0.1V
VOH
Minimum HIGH
Level Output
Voltage
4.4
4.4
IOUT = −50 µA
5.4
5.4
V
IN = VIL or VIH
3.0
4.5
5.5
3.0
4.5
5.5
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
I
I
I
OH = −12 mA
V
V
OH = −24 m
OH = −24 m (Note 2)
VOL
Maximum LOW
Level Output
Voltage
0.002
0.001
0.001
0.1
0.1
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
3.0
4.5
5.5
5.5
5.5
5.5
0.36
0.36
0.36
± 0.1
0.44
0.44
0.44
± 1.0
75
I
I
I
OL = 12 mA
V
OL = 24 mA
OL = 24 mA (Note 2)
IIN (Note 4) Maximum InputLeakage Current
µA
mA
mA
VI = VCC, GND
IOLD
Minimum Dynamic
Output Current (Note 3)
Maximum Quiescent
Supply Current
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC
IOHD
−75
ICC
5.5
2.0
20.0
µA
(Note 4)
or GND
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC
.
3
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DC Electrical Characteristics for ACT
T
A = −40°C to +85°C
VCC
(V)
4.5
5.5
4.5
5.5
4.5
5.5
TA = +25°C
Symbol
VIH
Parameter
Units
Conditions
Typ
1.5
Guaranteed Limits
Minimum HIGH Level
Input Voltage
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
OUT = 0.1V
or VCC − 0.1V
OUT = 0.1V
or VCC − 0.1V
V
V
V
1.5
VIL
Maximum LOW Level
Output Voltage
1.5
V
1.5
VOH
Minimum HIGH Level
Output Voltage
4.49
5.49
I
OUT = −50 µA
IN = VIL or VIH
V
4.5
5.5
4.5
5.5
3.86
4.86
0.1
3.76
4.76
0.1
V
V
V
I
I
OH = −24 mA
OH = −24 mA (Note 5)
VOL
Maximum LOW Level
Output Voltage
0.001
0.001
I
OUT = 50 µA
0.1
0.1
V
IN = VIL or VIH
4.5
5.5
0.36
0.36
0.44
0.44
I
I
OL = 24 mA
OL = 24 mA (Note 5)
IIN
Maximum Input
Leakage Current
Maximum
5.5
5.5
±0.1
±1.0
µA
VI = VCC, GND
VI = VCC − 2.1V
ICCT
0.6
1.5
mA
ICC/Input
IOLD
IOHD
ICC
Minimum Dynamic
Output Current (Note 6)
Maximum Quiescent
Supply Current
5.5
5.5
75
mA
mA
V
V
V
OLD = 1.65V Max
OHD = 3.85V Min
IN = VCC
−75
5.5
2.0
20.0
µA
or GND
Note 5: All outputs loaded; thresholds on input associated with output under test.
Note 6: Maximum test duration 2.0 ms, one output loaded at a time.
AC Electrical Characteristics for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Max
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 7)
3.3
Units
Min
100
140
3.5
2.5
4.0
3.0
4.5
3.5
3.5
2.5
Typ
125
160
8.0
Max
Min
fMAX
Maximum Clock
Frequency
95
125
2.5
2.0
3.5
2.5
4.0
3.0
3.5
2.5
MHz
ns
5.0
tPLH
tPHL
tPLH
tPHL
Propagation Delay
Dn or SDn to Qn or Qn
Propagation Delay
Dn or SDn to Qn or Qn
3.3
12.0
9.0
13.0
10.0
13.5
10.5
16.0
10.5
14.5
10.5
C
5.0
6.0
3.3
10.5
8.0
12.0
9.5
ns
C
5.0
Propagation Delay
CPn to Qn or Qn
Propagation Delay
CPn to Qn or Qn
3.3
8.0
13.5
10.0
14.0
10.0
ns
5.0
6.0
3.3
8.0
ns
5.0
6.0
Note 7: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
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4
AC Operating Requirements for AC
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
Guaranteed Minimum
C
L = 50 pF
C
Symbol
Parameter
(V)
(Note 8)
3.3
Units
Typ
1.5
1.0
tS
Set-up Time, HIGH or LOW
4.0
4.5
3.0
0.5
0.5
ns
ns
ns
ns
Dn to CPn
5.0
3.0
0.5
0.5
tH
Hold Time, HIGH or LOW
Dn to CPn
3.3
−2.0
−1.5
5.0
tW
CPn or CDn or SDn
Pulse Width
3.3
5.0
3.3
5.0
3.0
2.5
5.5
4.5
0
7.0
5.0
0
trec
Recovery Time
CDn or SDn to CP
−2.5
−2.0
0
0
Note 8: Voltage Range 3.3 is 3.3V ± 0.3V
Voltage Range 5.0 is 5.0V ± 0.5V
AC Electrical Characteristics for ACT
VCC
T
A = +25°C
TA = −40°C to +85°C
CL = 50 pF
C
L = 50 pF
Symbol
Parameter
(V)
Units
(Note 9)
Min
Typ
Max
Min Max
fMAX
Maximum Clock
5.0
5.0
5.0
5.0
5.0
145
210
125
2.5
3.0
4.0
3.0
MHz
ns
Frequency
tPLH
tPHL
tPLH
tPHL
Propagation Delay
3.0
3.0
4.0
3.5
5.5
6.0
7.5
6.0
9.5
10.5
11.5
13.0.
11.5
C
Dn or SDn to Qn or Qn
Propagation Delay
Dn or SDn to Qn or Qn
10.0
11.0
10.0
ns
C
Propagation Delay
CPn to Qn or Qn
Propagation Delay
CPn to Qn or Qn
ns
ns
Note 9: Voltage Range 5.0 is 5.0V ± 0.5V
AC Operating Requirements for ACT
VCC
T
A = +25°C
T
A = −40°C to +85°C
L = 50 pF
C
L = 50 pF
C
Symbol
Parameter
(V)
Units
(Note 10)
Typ
Guaranteed Minimum
tS
Set-up Time, HIGH or LOW
Dn to CPn
5.0
5.0
1.0
3.0
1.0
3.5
ns
ns
tH
Hold Time, HIGH or LOW
−0.5
3.0
1.0
6.0
0
Dn to CPn
tW
CPn or CDn or SDn
Pulse Width
5.0
5.0
5.0
0
ns
ns
trec
Recovery Time
−2.5
CDn or SDn to CP
Note 10: Voltage Range 5.0 is 5.0V ± 0.5V
Capacitance
Symbol
Parameter
Typ
Units
Conditions
CIN
Input Capacitance
4.5
pF
pF
V
CC = OPEN
CC = 5.0V
CPD
Power Dissipation Capacitance
35.0
V
5
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Physical Dimensions inches (millimeters) unless otherwise noted
14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-120, 0.150” Narrow Body
Package Number M14A
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6
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D
7
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Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC14
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8
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300” Wide
Package Number N14A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and
Fairchild reserves the right at any time without notice to change said circuitry and specifications.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD
SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the
body, or (b) support or sustain life, and (c) whose failure
to perform when properly used in accordance with
instructions for use provided in the labeling, can be rea-
sonably expected to result in a significant injury to the
user.
2. A critical component in any component of a life support
device or system whose failure to perform can be rea-
sonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
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