74ACQ573SCX_NL [FAIRCHILD]
Bus Driver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, MS-013, SOIC-20;
| 型号： | 74ACQ573SCX_NL |
| 厂家： | 
FAIRCHILD SEMICONDUCTOR |
| 描述： | Bus Driver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 0.300 INCH, MS-013, SOIC-20 驱动 光电二极管 逻辑集成电路 |
| 文件： | 总13页 (文件大小：319K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
April 2007
74ACQ573, 74ACTQ573
tm
Quiet Series™ Octal Latch with 3-STATE Outputs
Features
General Description
■ I and I reduced by 50%
The ACQ/ACTQ573 is a high-speed octal latch with buff-
ered common Latch Enable (LE) and buffered common
Output Enable (OE) inputs. The ACQ/ACTQ573 is func-
tionally identical to the ACQ/ACTQ373 but with inputs
and outputs on opposite sides of the package. The ACQ/
ACTQ utilizes Fairchild's Quiet Series™ technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series™ features
GTO™ output control and undershoot corrector in addi-
tion to a split ground bus for superior performance.
CC
OZ
■ Guaranteed simultaneous switching noise level and
dynamic threshold performance
■ Guaranteed pin-to-pin skew AC performance
■ Improved latch-up immunity
■ Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
■ Outputs source/sink 24mA
Ordering Information
Package
Order Number
74ACQ573SC
74ACQ573SJ
Number
Package Description
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
M20D
74ACQ573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
74ACTQ573SC
74ACTQ573SJ
74ACTQ573QSC
74ACTQ573MTC
M20B
M20D
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
MQA20
MTC20
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
Device also available in Tape and Reel. Specify by appending suffix letter “X” to the ordering number.
Connection Diagram
Pin Descriptions
Pin Names
Description
D –D
Data Inputs
0
7
LE
Latch Enable Input
OE
3-STATE Output Enable Input
3-STATE Latch Outputs
O –O
0
7
FACT™, Quiet Series™, FACT Quiet Series™, and GTO™ are trademarks of Fairchild Semiconductor Corporation.
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
Logic Symbol
Functional Description
The ACQ/ACTQ573 contains eight D-type latches with
3-STATE output buffers. When the Latch Enable (LE)
input is HIGH, data on the D inputs enters the latches.
n
In this condition the latches are transparent, i.e., a latch
output will change state each time its D-type input
changes. When LE is LOW the latches store the informa-
tion that was present on the D-type inputs at setup time
preceding the HIGH-to-LOW transition of LE. The
3-STATE buffers are controlled by the Output Enable
(OE) input. When OE is LOW, the buffers are enabled.
When OE is HIGH the buffers are in the high impedance
mode but this does not interfere with entering new data
into the latches.
IEEE/IEC
Truth Table
Inputs
Outputs
OE
L
LE
H
D
H
L
O
n
H
L
H
L
L
L
X
X
O
0
H
X
Z
H = HIGH Voltage
L = LOW Voltage
Z = High Impedance
X = Immaterial
O = Previous O before HIGH-to-LOW transition of
0
0
Latch Enable
Logic Diagram
Please note that this diagram is provided only for the understanding of logic operations and should not be used to
estimate propagation delays.
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
2
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Symbol
Parameter
Rating
V
I
Supply Voltage
–0.5V to +7.0V
CC
IK
DC Input Diode Current
V = –0.5V
–20mA
+20mA
I
V = V + 0.5V
I
CC
V
DC Input Voltage
–0.5V to V + 0.5V
I
CC
I
DC Output Diode Current
OK
V
= –0.5V
–20mA
+20mA
O
V
= V + 0.5V
O
CC
V
DC Output Voltage
DC Output Source or Sink Current
–0.5V to V + 0.5V
O
CC
I
50mA
50mA
O
I
or I
DC V or Ground Current per Output Pin
CC
GND
STG
CC
T
Storage Temperature
–65°C to +150°C
300mA
DC Latch-Up Source or Sink Current
Junction Temperature
T
140°C
J
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to absolute maximum ratings.
Symbol
Parameter
Rating
V
Supply Voltage
ACQ
CC
2.0V to 6.0V
4.5V to 5.5V
ACTQ
V
Input Voltage
Output Voltage
Operating Temperature
0V to V
0V to V
I
CC
CC
V
O
T
–40°C to +85°C
125mV/ns
A
∆V / ∆t
Minimum Input Edge Rate, ACQ Devices:
from 30% to 70% of V , V @ 3.0V, 4.5V, 5.5V
V
IN
CC CC
∆V / ∆t
Minimum Input Edge Rate, ACTQ Devices:
from 0.8V to 2.0V, V @ 4.5V, 5.5V
125mV/ns
V
IN
CC
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
3
DC Electrical Characteristics for ACQ
T = +25°C T = –40°C to +85°C
A
A
Symbol
Parameter
V
(V)
Conditions
Typ.
Guaranteed Limits
Units
CC
V
Minimum HIGH Level
Input Voltage
3.0
V
V
= 0.1V or
OUT
CC
1.5
2.1
2.1
V
IH
– 0.1V
4.5
5.5
3.0
4.5
5.5
3.0
4.5
5.5
2.25
2.75
1.5
3.15
3.85
0.9
3.15
3.85
0.9
V
Maximum LOW Level
Input Voltage
V
V
= 0.1V or
OUT
V
V
IL
– 0.1V
CC
2.25
2.75
2.99
4.49
5.49
1.35
1.65
2.9
1.35
1.65
2.9
V
Minimum HIGH Level
Output Voltage
I
= –50µA
OUT
OH
4.4
4.4
5.4
5.4
V
I
= V or V :
IN
IL
IH
3.0
4.5
5.5
3.0
4.5
5.5
= –12mA
2.56
3.86
4.86
0.1
2.46
3.76
4.76
0.1
OH
OH
OH
I
I
= –24mA
= –24mA
(1)
V
Maximum LOW Level
Output Voltage
0.002
0.001
0.001
OL
I
= 50µA
0.1
0.1
V
OUT
0.1
0.1
V
I
= V or V :
IN
IL
IH
3.0
4.5
5.5
5.5
= 12mA
0.36
0.36
0.36
0.1
0.44
0.44
0.44
1.0
OL
OL
OL
I
I
= 24mA
= 24mA
(1)
(3)
I
Maximum Input
Leakage Current
V = V , GND
µA
IN
I
CC
I
Minimum Dynamic
Output Current
5.5
5.5
5.5
V
V
V
= 1.65 V
Max
75
mA
mA
µA
OLD
OLD
(2)
I
= 3.85 V
–75
40.0
OHD
(3)
OHD
Min
I
Maximum Quiescent
Supply Current
= V or GND
4.0
CC
IN
CC
I
Maximum 3-STATE
Leakage Current
5.5
V (OE) = V , V ;
0.25
2.5
µA
OZ
I
IL IH
V = V , GND;
I
CC
V
= V , GND
O
CC
(4)
V
Quiet Output Maximum
5.0
5.0
5.0
5.0
Figures 1 & 2
1.1
–0.6
3.1
1.5
–1.2
3.5
V
V
V
V
OLP
Dynamic V
OL
(4)
V
Quiet Output Minimum
Dynamic V
Figures 1 & 2
OLV
OL
(5)
V
Minimum HIGH Level
Dynamic Input Voltage
IHD
(5)
V
Maximum LOW Level
Dynamic Input Voltage
1.9
1.5
ILD
Notes:
1. All outputs loaded; thresholds on input associated with output under test.
2. Maximum test duration 2.0ms, one output loaded at a time.
3. I and I @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V V .
CC
IN
CC
4. Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
5. Max number of Data Inputs (n) switching. (n – 1) Inputs switching 0V to 5V (ACQ). Input-under-test switching:
5V to threshold (V ), 0V to threshold (V ), f = 1MHz.
ILD
IHD
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
4
DC Electrical Characteristics for ACTQ
T = +25°C T = –40°C to +85°C
A
A
Symbol
Parameter
V
(V)
Conditions
Typ.
Guaranteed Limits
Units
CC
V
Minimum HIGH Level
Input Voltage
4.5
V
V
= 0.1V or
OUT
CC
1.5
1.5
2.0
2.0
0.8
0.8
4.4
5.4
2.0
2.0
0.8
0.8
4.4
5.4
V
IH
– 0.1V
5.5
4.5
5.5
4.5
5.5
V
Maximum LOW Level
Input Voltage
V
V
= 0.1V or
OUT
1.5
V
V
IL
– 0.1V
CC
1.5
V
Minimum HIGH Level
Output Voltage
I
= –50µA
OUT
4.49
5.49
OH
V
I
= V or V :
IN
IL
IH
4.5
5.5
4.5
5.5
= –24mA
3.86
4.86
0.1
3.76
4.76
0.1
OH
OH
(6)
I
I
= –24mA
= 50µA
V
Maximum LOW Level
Output Voltage
0.001
0.001
V
OL
OUT
0.1
0.1
V
I
= V or V :
IN
IL
IH
4.5
5.5
5.5
= 24mA
0.36
0.36
0.1
0.44
0.44
1.0
OL
OL
(6)
I
= 24mA
I
Maximum Input Leakage
Current
V = V , GND
µA
µA
IN
I
CC
I
Maximum 3-STATE
Leakage Current
5.5
V = V , V ;
0.25
2.5
OZ
I
V
IL IH
= V , GND
O
CC
I
Maximum I /Input
5.5
5.5
5.5
5.5
V = V – 2.1V
0.6
1.5
75
mA
mA
mA
µA
CCT
CC
I
CC
I
Minimum Dynamic
V
V
V
= 1.65V Max.
OLD
OLD
OHD
(7)
Output Current
I
= 3.85V Min.
–75
40.0
OHD
I
Maximum Quiescent
Supply Current
= V or GND
4.0
1.5
CC
IN
CC
(8)
V
Quiet Output Maximum
5.0
5.0
5.0
5.0
Figures 1 & 2
1.1
–0.6
1.9
V
V
V
V
OLP
Dynamic V
OL
(8)
V
Quiet Output Minimum
Dynamic V
Figures 1 & 2
–1.2
2.2
OLV
OL
(9)
V
Minimum HIGH Level
Dynamic Input Voltage
IHD
(9)
V
Maximum LOW Level
Dynamic Input Voltage
1.2
0.8
ILD
Notes:
6. All outputs loaded; thresholds on input associated with output under test.
7. Maximum test duration 2.0ms, one output loaded at a time.
8. Max number of outputs defined as (n). Data Inputs are driven 0V to 3V. One output @ GND.
9. Max number of data inputs (n) switching. (n – 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching:
3V to threshold (V ), 0V to threshold (V ), f = 1MHz.
ILD
IHD
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
5
AC Electrical Characteristics for ACQ
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(10)
Symbol
Parameter
V
(V)
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
3.3
5.0
Min. Typ. Max.
Min.
2.5
1.5
2.5
2.0
2.5
1.5
1.0
1.0
Max.
11.0
7.5
Units
CC
t
, t
Propagation Delay,
2.5
1.5
2.5
2.0
2.5
1.5
1.0
1.0
8.5
5.5
8.5
6.0
8.5
6.0
9.0
6.0
1.0
0.5
10.5
7.0
ns
PHL PLH
D to O
n
n
t
, t
Propagation Delay,
LE to O
12.0
8.0
12.5
8.5
ns
ns
ns
ns
PLH PHL
n
t
t
, t
Output Enable Time
13.0
8.5
13.5
9.0
PZL PZH
, t
Output Disable Time
14.5
9.5
15.0
10.0
1.5
PHZ PLZ
t
, t
Output to Output Skew,
1.5
OSHL OSLH
(11)
D to O
n
n
1.0
1.0
Notes:
10. Voltage range 5.0 is 5.0V 0.5V. Voltage range 3.3 is 3.3V 0.3V.
11. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (t
) or LOW-to-HIGH (t
). Parameter guaranteed by design.
OSHL
OSLH
AC Operating Requirements for ACQ
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(12)
Symbol
Parameter
V
(V)
3.3
5.0
3.3
5.0
3.3
5.0
Typ.
Guaranteed Minimum
Units
CC
t
Setup Time, HIGH or LOW,
0
0
3.0
3.0
1.5
1.5
4.0
4.0
3.0
3.0
1.5
1.5
4.0
4.0
ns
S
D to LE
n
t
Hold Time, HIGH or LOW,
0
ns
ns
H
D to LE
n
0
t
LE Pulse Width, HIGH
2.0
2.0
W
Note:
12. Voltage range 5.0 is 5.0V 0.5V. Voltage range 3.3 is 3.3V 0.3V.
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
6
AC Electrical Characteristics for ACTQ
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(13)
Symbol
Parameter
V
(V)
Min.
Typ. Max.
Min.
Max.
Units
CC
t
, t
Propagation Delay,
5.0
2.0
6.5
7.5
2.0
8.0
ns
PHL PLH
D to O
n
n
t
, t
Propagation Delay,
LE to O
5.0
2.5
7.0
8.5
2.5
9.0
ns
PLH PHL
n
t
t
, t
Output Enable Time
Output Disable Time
5.0
5.0
5.0
2.0
1.0
7.0
8.0
0.5
9.0
10.0
1.0
2.0
1.0
9.5
10.5
1.0
ns
ns
ns
PZL PZH
, t
PHZ PLZ
t
, t
Output to Output Skew,
OSHL OSLH
(14)
D to O
n
n
Note:
13. Voltage range 5.0 is 5.0V 0.5V.
14. Skew is defined as the absolute value of the difference between the actual propagation delay for any two separate
outputs of the same device. The specification applies to any outputs switching in the same direction, either
HIGH-to-LOW (t
) or LOW-to-HIGH (t
). Parameter guaranteed by design.
OSHL
OSLH
AC Operating Requirements for ACTQ
T = +25°C,
T = –40°C to +85°C,
A
A
C = 50pF
C = 50pF
L
L
(15)
Symbol
Parameter
V
(V)
Typ.
Guaranteed Minimum
Units
CC
t
Setup Time, HIGH or LOW,
5.0
0
3.0
3.0
1.5
4.0
ns
S
D to LE
n
t
Hold Time, HIGH or LOW,
5.0
5.0
0
1.5
4.0
ns
ns
H
D to LE
n
t
LE Pulse Width, HIGH
2.0
W
Notes:
15. Voltage range 5.0 is 5.0V 0.5V.
Capacitance
Symbol
Parameter
Conditions
Typ.
4.5
Units
C
Input Capacitance
Power Dissipation Capacitance
V
= OPEN
pF
pF
IN
CC
C
V
= 5.0V
42.0
PD
CC
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
7
FACT Noise Characteristics
The setup of a noise characteristics measurement is
critical to the accuracy and repeatability of the tests. The
following is a brief description of the setup used to
measure the noise characteristics of FACT.
V
/V
and V
/V
:
OLP OLV
OHP OHV
■ Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually
be the furthest from the ground pin. Monitor the output
voltages using a 50Ω coaxial cable plugged into a
standard SMB type connector on the test fixture. Do
not use an active FET probe.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
■ Measure V
and V
on the quiet output during
OLP
OLV
the worst case transition for active and enable.
Measure V and V on the quiet output during
the worst case active and enable transition.
Tektronics Model 7854 Oscilloscope
OHP
OHV
Procedure:
1. Verify Test Fixture Loading: Standard Load 50pF,
■ Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
500Ω.
2. Deskew the HFS generator so that no two channels
have greater than 150ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
V
and V
:
ILD
IHD
■ Monitor one of the switching outputs using a 50Ω
coaxial cable plugged into a standard SMB type
connector on the test fixture. Do not use an active
FET probe.
3. Terminate all inputs and outputs to ensure proper
loading of the outputs and that the input levels are the
correct voltage.
■ First increase the input LOW voltage level, V , until
IL
the output begins to oscillate or steps out a min of 2ns.
Oscillation is defined as noise on the output LOW
4. Set the HFS generator to toggle all but one output at
a frequency of 1MHz. Greater frequencies will
increase DUT heating and affect the results of the
measurement.
level that exceeds V limits, or on output HIGH levels
IL
that exceed V limits. The input LOW voltage level at
IH
which oscillation occurs is defined as V
.
ILD
■ Next decrease the input HIGH voltage level, V , until
IH
5. Set the HFS generator input levels at 0V LOW and
3V HIGH for ACT devices and 0V LOW and 5V HIGH
for AC devices. Verify levels with an oscilloscope.
the output begins to oscillate or steps out a min of 2ns.
Oscillation is defined as noise on the output LOW
level that exceeds V limits, or on output HIGH levels
IL
that exceed V limits. The input HIGH voltage level at
IH
which oscillation occurs is defined as V
.
IHD
■ Verify that the GND reference recorded on the
oscilloscope has not drifted to ensure the accuracy
and repeatability of the measurements.
Notes:
16. V
and V
are measured with respect to ground
OHV
OLP
reference.
17. Input pulses have the following characteristics:
f = 1MHz, t = 3ns, t = 3ns, skew < 150ps.
r
f
Figure 1. Quiet Output Noise Voltage Waveforms
Figure 2. Simultaneous Switching Test Circuit
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
8
Physical Dimensions
Dimensions are in inches (millimeters) unless otherwise noted.
Figure 3. 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Package Number M20B
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
9
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 4. 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M20D
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
10
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 5. 20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150" Wide
Package Number MQA20
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
11
Physical Dimensions (Continued)
Dimensions are in millimeters unless otherwise noted.
Figure 6. 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Package Number MTC20
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
12
TRADEMARKS
The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an
exhaustive list of all such trademarks.
ACEx®
TinyLogic®
TINYOPTO¥
TinyPower¥
TinyWire¥
TruTranslation¥
PSerDes¥
UHC®
UniFET¥
VCX¥
Wire¥
HiSeC¥
i-Lo¥
Programmable Active Droop¥
QFET®
QS¥
QT Optoelectronics¥
Quiet Series¥
RapidConfigure¥
RapidConnect¥
ScalarPump¥
SMART START¥
SPM®
STEALTH™
SuperFET¥
SuperSOT¥-3
SuperSOT¥-6
SuperSOT¥-8
SyncFET™
Across the board. Around the world.¥
ActiveArray¥
Bottomless¥
Build it Now¥
CoolFET¥
ImpliedDisconnect¥
IntelliMAX¥
ISOPLANAR¥
MICROCOUPLER¥
MicroPak¥
MICROWIRE¥
MSX¥
CROSSVOLT¥
CTL™
Current Transfer Logic™
DOME¥
MSXPro¥
OCX¥
E2CMOS¥
EcoSPARK®
EnSigna¥
OCXPro¥
OPTOLOGIC®
OPTOPLANAR®
PACMAN¥
POP¥
FACT Quiet Series™
FACT®
FAST®
Power220®
Power247®
PowerEdge¥
PowerSaver¥
PowerTrench®
FASTr¥
TCM¥
The Power Franchise®
™
FPS¥
FRFET®
GlobalOptoisolator¥
GTO¥
TinyBoost¥
TinyBuck¥
DISCLAIMER
FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS
HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD’S
WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Definition
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Preliminary
First Production
Full Production
Not In Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Obsolete
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
©1990 Fairchild Semiconductor Corporation
74ACQ573, 74ACTQ573 Rev. 1.5
www.fairchildsemi.com
13
相关型号：
74ACQ573SMTCX
Bus Driver, AC Series, 1-Func, 8-Bit, True Output, CMOS, PDSO20, 4.40 MM, MO-153, TSSOP-20
FAIRCHILD
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